JP3357858B2 - Analog-to-digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-to-digital converter, and is an effective circuit built in, for example, a solid-state imaging device.

[0002]

2. Description of the Related Art As an analog-to-digital converter effective for a solid-state imaging device, there is a technique described in, for example, Japanese Patent Application Laid-Open No. 9-238286. However, the present inventor has noticed that the analog-to-digital conversion characteristics require further improvement.

[0003]

The above-described analog-to-digital converter samples a signal component multiplexed and output from a pixel into a DC component at two adjacent points in time, and converts the difference component of the sample component into a digital value. A single-slope analog-to-digital converter that compares a reference voltage waveform that changes accordingly and outputs the corresponding digital value when they match.

However, in this analog-to-digital converter,
There is a difference in sensitivity in conversion characteristics between when there is a very small input voltage and when there is an input voltage exceeding a predetermined voltage. If there is such a difference, the resolution will be different when the solid-state imaging device is used in a dark environment and in a bright environment.

Accordingly, an object of the present invention is to provide an analog-to-digital converter capable of obtaining stable analog-to-digital conversion characteristics.

[0006]

An analog according to the present invention is provided.
Digital converter , input to achieve the above purpose
Compare the signal voltage to the threshold voltage and respond to this comparison.
Inverting voltage comparator that inverts the output voltage
Generate digital values that increase or decrease linearly from values
Digital value generating means and the digital value generating means
A reference that generates a reference voltage corresponding to the digital value generated
The voltage generating means and the output voltage of the voltage comparator are inverted
A digital value generated by the digital value generating means at a point in time
Output as analog-to-digital conversion value
Force means, one end of which is connected to the input end and which is connected to said input end.
Selects the output signal multiplexed with the supplied DC component.
And a first switch element derived from
Connected between the other end of the element and the input end of the voltage comparator.
A first capacitor, one end of which is the first switch
A second capacitor connected to the other end of the element;
2 and the reference of the reference voltage generating means.
A first output terminal connected to the first output terminal and a second output terminal;
Selectively connect a series circuit with a capacitor to the reference voltage output terminal.
A second switch element to be connected and an input of the voltage comparator
A third switch element for selectively connecting between output terminals;
Digital value generation timing of the digital value generation means, before
The on / off timer of each of the first to third switch elements
And a timing control means for controlling the timing, the
The timing control means turns off the second switch element.
In the first state with the third switch element turned on,
By turning on the first switch element at the point,
A signal voltage at a first time point is taken in from the input terminal,
A first difference voltage between the first capacitor and the first capacitor;
And then turn on the first switch element.
State while the third switch element is turned off.
In this state, the second switch element is turned on at a second point in time.
Thus, the signal voltage at the second point in time is obtained from the input terminal.
And a second difference voltage from the reference voltage
And then turn on the second switch element.
The first switch element is turned off while maintaining the on state.
To connect the first and second capacitors in series.
The difference component between the first difference voltage and the second difference voltage
With obtaining the sum component between the reference voltage and the difference component
To the input of the voltage comparator, followed by the digital
Causes the value generator to start increasing or decreasing the digital value
This changes the reference voltage, thereby changing the voltage.
Invert the output of the pressure comparator from high to low
And the reference voltage generating means generates the digital value.
Before the operation of the means starts, an analog digital
While maintaining the monotonicity of the
And the sum of the reference voltage and the threshold voltage
The output voltage of the voltage comparator at the time of
Reference voltage sufficient to start from the high level
It is characterized by having a period for generating a pressure waveform .

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 1, a portion PB surrounded by a broken line is a pixel portion of the solid-state imaging device, and a cathode of the photoelectric conversion device PD is connected in series to a DC power supply 100 via a reset switch device RD and a read switch device RS. Have been.
The connection point between the switch elements RD and RS is connected to the gate of the current amplification element Q1. One electrode (drain) of the current amplifying element Q1 is connected to the DC power supply 100, and the other electrode (source) is grounded via the constant current source 11.

The electrode (source) is drawn out as a signal output node, and is led to an analog-to-digital (AD) converter 13. The AD converter 13 is a switch element
S1 is provided at the input node. The output node of the switch element S1 is connected to one electrode of each of the capacitors C1 and C2. The other electrode of the capacitor C2 is configured to be supplied with the reference voltage from the reference voltage generation circuit 14 via the switch element S2. The other electrode of the capacitor C2 is connected to a gate signal input terminal of the latch circuit 15 via a parallel circuit of the inverter A1 and the switch element S3.

The count data from the counter 16 is supplied to the latch circuit 15. The count data is also supplied to the reference voltage generation circuit 14.
The reference voltage generation circuit 14 outputs a voltage having an amplitude corresponding to the value of the count data. The timing circuit 17 is a circuit that outputs a timing pulse for turning on / off each switch element, a reset pulse of the counter 16, and a clock.

FIG. 2 shows waveforms for explaining the operation of the above circuit.

When the switch RS is turned on by a reset pulse (FIG. 2A), the gate of the current amplifying element Q1 is set to a high potential. Then, the output voltage Vsi of the current amplification element Q1
g becomes high potential, then the switching element RS is turned off, the switching element S1 is turned on, and the switching element S3 is turned on. Then, the potentials Va and Vth of the output voltage Vsig
The difference potential of 1 , that is, (Va- Vth1 ) is
Stored in 1. Vth1 is a threshold voltage of the inverter A1. Note that the threshold value of the inverter A1 is Vth1,
The threshold value of the switching circuit 15 is set to Vth2.

Next, the on state of the switch element S1 is maintained, and the switch element RD is turned on. That is, the signal charge stored in the photoelectric conversion element (photodiode) PD is transferred to the gate of the current amplification element Q1. Then, the output voltage Vsig of the current amplifying element Q1 becomes a voltage corresponding to the signal charge (the amount of photoelectric conversion). Here, the switch element S2 is turned on. Then, the difference voltage between the output voltage Vb and the reference voltage Vsaw at this time, that is, (Vb−V0) is stored in the capacitor C2.

Next, the switch element S1 is turned off, the on state of the switch element S2 is maintained, and the reference voltage Vsaw is varied based on the count value of the counter 16. As a result, the reference voltage Vsaw increases or decreases sequentially. After the switch element S1 is turned off, only the switch element S2 is kept on.

Here, the input voltage Vin of the inverter A1 is
Looking at, Vin = Vsaw + (Vb−V0) − (Vb−V
th1). By transforming this equation, Vin =Vth1+
(Vb-Va) + (Vsaw-V0). That is,
The input voltage Vin of the inverter A1 is a threshold voltageVth1
And the potential difference between the voltages sampled at two points in time
(Vb−Va) and the reference voltage change width (Vsaw−V).
0). Here, the reference voltage change width (Vsaw
−V0) and the potential difference (Vb−Va) become zero.
When Vin =Vth1(Threshold voltage)
The barter A1 can be inverted.

The reference voltage change width (Vsaw-V0);
The fact that the sum with the potential difference (Vb−Va) becomes zero means that (V
(saw−V0) + (Vb−Va) = 0, and (Vb−
Va) = − (Vsaw−V0). (G) of FIG.
Shows how the reference voltage Vsaw changes, and Vsaw-
The case where V0 = V1 has become equal to the threshold value Vth1 is shown. At this time, the output voltage Vout of the inverter A1 is
It changes from the high level VH to the low level VL.

At this time, the latch circuit 15 latches the count value of the counter 16. The digital output of the latch circuit 15 is an analog-to-digital conversion output.

The analog-to-digital converter has no sensitivity to a DC component (noise component) superimposed on a signal line on the output side of the current amplifying element Q1, and functions as a noise reduction circuit.

FIG. 3 is a diagram for explaining the conversion characteristics of the analog-to-digital converter. The ideal conversion characteristic should be a straight line as shown by the characteristic line 3A. However, in practice, as shown by the characteristic line 3B, in the range where the level of the input signal is low, the change characteristic change slope is larger than the other ranges. With such a characteristic indicated by the characteristic line 3B, when an image of a subject is taken in a dimly lit environment, the luminance change between the white part and the black part of the video becomes severe and unnatural. When a color camera is configured, RGB
Are different, and as a result, the non-linear state is different for each color, so that an achromatic subject is colored.

In order to improve such characteristics, the converter takes the following countermeasures against the waveform of the reference voltage.

First, considering the cause of the characteristic line 3B as described above, as shown in FIG. 4, the parasitic capacitance Cp is generated in parallel with the inverter A1.

Here, the change range (between VH and VL) of the output voltage of the inverter A1 is finite. While the output voltage of the inverter A1 is changing, the input capacitance of the inverter A1 increases due to the Miller effect.

[0023] Figure 5, variable threshold around (the output voltage of A1
Shows how the input capacitance is increased in the region) to reduction. FIG. 6D shows how the input voltage VM on the capacitor C1 changes between when there is no signal and when there is a signal. When there is no signal, VM and Vout
6 (d) and 6 (e) are shown as dotted lines, and the cross timing with respect to Vth2 coincides with the conversion start time of Vsaw. However, when the input signal Vb is present, the relationship between VM and Vout is as shown by a solid line, and as shown in FIG. 6D, VM drops to Vb. As a result, the cross timing of Vout with respect to Vth2 is delayed. Then, the analog-to-digital conversion characteristic shifts in the plus direction. FIG. 3 shows this shift.

Therefore, the present invention is devised so that the output digital value corresponding to the input signal has ideal conversion characteristics. In the present invention, as shown in FIG. 7, by controlling the waveform of the reference voltage Vsaw, the analog-to-digital conversion characteristics are shifted in the negative direction as a whole. This eliminates the use of a non-linear portion of the conversion characteristic, and obtains a linear conversion characteristic.

FIG. 8 shows the analog-digital conversion characteristics of the converter according to the present invention.

In order to obtain such characteristics, FIG.
The range indicated by the section T of Vsaw may be an amplitude outside the analog-to-digital conversion range. With such an amplitude characteristic, when the input signal Vb is present, the VM changes as shown by the solid line in FIG. The dashed line is the change in VM when there is no input signal. The change in the output Vout of the inverter A1 when there is no signal changes as indicated by the broken line in FIG. 7 ( i ), and after reaching the threshold value (Vth2) at time t1, the count value of the counter 16 is latched . The output Vout of the inverter A1 when there is a signal is shown in FIG.
After changing as indicated by the solid line in ( i ) and reaching the threshold value at time t2 , the count value of the counter 16 is latched .

That is, according to the present invention, the reference voltage is kept monotonic with the analog-to-digital conversion, and the voltage for comparing the input signal (difference component between the two sample voltages) with the reference voltage waveform. A signal period is provided for the output voltage of the comparator (inverter) to start from the same voltage regardless of the magnitude of the difference component.

[0028]

[0029]

In the above-described embodiment, the AD conversion characteristic is linearized by controlling the waveform of the reference voltage. However, the present invention is not limited to this, and other embodiments are possible. Inverter
It is also possible to take circuit measures to prevent the occurrence of the parasitic capacitance Cp between the input and output of A1.

FIG. 10 shows an example in which the influence of the parasitic capacitance Cp is eliminated by the circuit configuration to improve the analog-to-digital conversion characteristics. That is, the buffer amplifier A2 is connected in series to the input side of the inverter A1. Then, switches S3A and S3B are connected in series between the input side of the buffer amplifier A2 and the output side of the inverter A1. Further switch S
Switch S3 between the connection point of 3A and S3B and the earth line
Connect C.

With such a configuration, the switches S3A and S3B are turned on at the time of reset, and when the reference voltage Vsaw changes, the switch S3C is turned on so that the change of the output voltage does not reach the input side. Can be.

However, with this configuration, there is an increase in circuit scale and power consumption. Therefore, if the object is to be achieved without these increases, the above-described embodiment is preferable.

FIG. 11 is a diagram showing an example when the analog-to-digital converter of the present invention is specifically incorporated in a solid-state image sensor. This embodiment shows a case in which an imaging unit, a noise canceling circuit, and a control unit are configured as one solid-state imaging device.

The structure of one pixel block PB11 of the imaging section will be described as a representative. This pixel block PB11
There is a switch 101 and a light receiving element 102 connected in series between a power supply 100 and a ground potential, and a connection point between the switch 101 and the light receiving element 102 is connected to an input terminal of an amplifier 103. The output terminal is connected to a signal derivation line (vertical line) VL1 via a switch 104.

Although the pixel block PB11 has been described as a representative, other pixel blocks have the same configuration. Pixel blocks PB12 to PBnm (m horizontal pixel number, n
The same applies to the vertical pixel numbers. The pixel blocks PB11, PB12,... PB1m indicate pixel columns in the first horizontal line direction, and the pixel blocks PB21,.
PB2,... PB2m indicate pixel columns in the second horizontal line direction. Since each pixel block has the same configuration,
The same reference numerals are given. The columns in the vertical direction of each pixel block are signal derivation lines (vertical lines) VL1 to VL, respectively.
Lm.

Noise cancellation circuits NR1 to NRm are connected to the signal derivation lines VL1 to VLm, respectively.

Since each of the noise canceling circuits has the same configuration, only one will be described. Signal derivation line VL1
Are connected to the capacitors 3-1 and 4-1 via the switch 2-1.
Are connected to the connection point of one of the electrodes. The other electrode of the capacitor 3-1 is connected to the D / A via the switch 5-1.
It is connected to the output terminal of the converter 311.

The other electrode of the capacitor 4-1 is connected to the input terminal of the inverter 7-1 operating as a comparator and to the output terminal of the inverter 7-1 via the switch 8-1. Have been. This inverter 7
The output terminal of -1 is a latch circuit 11-
1 drive pulse input terminal G.

According to the noise cancel circuit NR2,
A latch circuit 11-2 is provided. The output of the inverter 7-1 of the noise cancel circuit NR2 is supplied to the drive pulse input terminal G of the latch circuit 11-2. As described above, the latch circuits 11-1 to 11-m are provided corresponding to the noise cancel circuits NR1 to NRm, and these latch circuits 11-1 to 11-m are connected to the inverters of the corresponding noise cancel circuits. When the output is inverted, the count value of the common counter 312 is latched. The output of the counter 312 is also input to the D / A converter 311.

The basic operation of each of the noise cancellation circuits NR1 to NRm is as described with reference to FIG. 1, and the D / A converter 311 is shared by the plurality of noise cancellation circuits NR1 to NRm. The counter 312 is reset at the beginning of the horizontal drive signal HD, and the clock CLOC
K is counted. The horizontal drive signal HD and the clock CLOCK are also supplied to the timing generator 313, and generate timing signals for various switch controls and the like.

According to the latch circuits 11-1 to 1-m,
Latch circuits 12-1 to 12-m are provided. These latch the digital values latched by the corresponding latch circuits 11-1 to 11-m all at once with the timing of the horizontal drive signal HD. Latch circuits 12-1 to 12-
Output terminals of m are connected to the scanning switches 13-1 to 13-m, respectively. These scanning switches 13-1
13-m turn on one after another in one horizontal period, and derive the digital value of the imaging signal for one scan to the output line 70.

FIGS. 12A to 12M are timing charts for explaining an example of the operation of the above-described image pickup device. FIG. 12A shows the horizontal drive signal (H
D), FIGS. 12B and 12C show the vertical line VL
1, Vl2 signal voltages Vin1 and Vin2. FIG.
2 (D) is a timing at which the switches 2-1 to 2-m are turned on / off, FIG. 12 (E) is a timing at which the switches 5-1 to 5-m are turned on / off, and FIG.
8-m is the timing of turning on and off. FIG. 12 (G)
Denotes a reference voltage Vref obtained from the D / A converter 311. FIGS. 12 (H) and 12 (I) show the input and output of the inverter 7-1, and FIGS.
(K) shows the input and output of the inverter 7-2. FIGS. 12 (L) and 12 (M) show the scanning switch 13.
-1 and 13-2 are shown.

[0044]

As described above, according to the present invention, stable analog-to-digital conversion characteristics can be obtained, which can contribute to obtaining good image pickup signals.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a waveform chart shown for explaining a basic operation of the circuit of FIG. 1;

FIG. 3 is a diagram illustrating a problem of analog-to-digital conversion characteristics.

FIG. 4 is a diagram illustrating a problem that occurs in a comparator.

FIG. 5 is a diagram illustrating the influence of the parasitic capacitance of the circuit of FIG. 4;

FIG. 6 is a diagram for explaining a problem in an analog-to-digital conversion operation by using a waveform.

FIG. 7 is a diagram showing waveforms in one embodiment of the present invention.

FIG. 8 is a diagram showing conversion characteristics when analog-to-digital conversion is performed according to an embodiment of the present invention.

FIG. 9 is a diagram showing another embodiment of the present invention.

FIG. 10 is an explanatory diagram of a solid-state imaging device to which the analog-to-digital converter of the present invention is applied.

FIG. 11 is a waveform chart shown for explaining the operation of the solid-state imaging device of FIG . 10 ;

[Explanation of symbols]

RS: reset switch element, RD: read switch element, PD: photoelectric conversion element, Q1: switch element, 13: analog-to-digital converter, 14: reference voltage converter, 15: latch circuit, 16: counter, 17: timing circuit , S
1, S2, S3: switch element, C1, C2: capacitor, A1: inverter.

Claims (3)

(57) [Claims] An input signal voltage is compared with a threshold voltage.
And inverts the output voltage according to the comparison result.
And a digital value that increases or decreases linearly from the initial value.
Digital value generating means for raw, corresponding to the digital values generated by the digital value generating means
A reference voltage generating means for generating a reference voltage to be applied, and the digital signal when the output voltage of the voltage comparator is inverted.
Digital value generated by the digital value generation means
Digital value output means for outputting as a digital conversion value, one end of which is connected to the input terminal, and a direct value supplied to the input terminal.
Selectively derive the output signal multiplexed with the stream component
A first switch element, and the other end of the first switch element and the input of the voltage comparator.
A first capacitor connected between the first switch element and a first end of the first switch element;
A second capacitor, the other end of the second capacitor and the reference voltage generating means
Between the first and second reference voltage output terminals.
A series circuit of capacitors is selected for the reference voltage output terminal.
A second switch element that is selectively connected and a third switch element that is selectively connected between the input and output terminals of the voltage comparator.
Switch element, digital value generation timing of the digital value generation means,
ON / OFF of each of the first to third switch elements
Timing control means for controlling timing, wherein the timing control means turns off the second switch element and turns off the third switch element.
With the switch turned on, the first switch element
The first time from the input terminal by turning the
And a first difference from the threshold voltage
Holding a voltage on the first capacitor, and subsequently maintaining the ON state of the first switch element;
With the third switch element turned off, the second
Said second switching element is turned on and the child at the point, the
The signal voltage at the second point in time is taken from the input terminal and
Holds the second difference voltage from the voltage to the second capacitor
Then, while maintaining the ON state of the second switch element,
By turning off the first switch element,
The first and second capacitors are connected in series to form the first capacitor.
Obtaining a difference component between the difference voltage and the second difference voltage;
The sum of the difference component and the reference voltage is calculated by the voltage comparator.
Input to the input of the digital value, and then, the digital value generating means receives
Or start the decrease to change the reference voltage.
This causes the output of the voltage comparator to rise from a high level.
The reference voltage generation means is configured to invert the reference voltage before starting operation of the digital value generation means.
When maintaining the monotonicity of the analog-to-digital conversion characteristics of the waveform
In both cases, the sum component of the difference component and the reference voltage is a threshold.
Output voltage of the voltage comparator when compared with the
Starting from the high level regardless of the voltage level of the differential component
Have a period to generate a reference voltage waveform sufficient for
An analog-to-digital converter characterized by the following. 2. The method according to claim 1, further comprising the step of:
2. The analog-to-digital converter according to claim 1, wherein the waveform generated during the period is obtained by extending the waveform of a portion for executing the analog-to-digital conversion. 3. The analog-to-digital converter according to claim 1, wherein the signal component supplied to the input terminal is a signal component read from a pixel of the solid-state imaging device.