JP2008054256A - Analog/digital converter and imaging circuit using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that the circuit area of a single slope type analog/digital converter can be reduced rather than flash type one but a conversion speed may tend to be decelerated. <P>SOLUTION: A reference signal generating circuit generates a reference signal of which a signal level sequentially changes in a step corresponding to a second resolution coarser than a first resolution dividing an input voltage range. A comparator circuit CP compares an analog signal with the reference signal generated by the reference signal generating circuit. A digital signal generating circuit generates a digital signal in accordance with a time until a result of the comparison due to the comparator circuit changes. When the result of the comparison due to the comparator circuit changes, the reference signal generating circuit supplies another reference signal to the comparator circuit in order to turn the resolution of the digital signal being held by the digital signal generating circuit into the first resolution or make it close to the first resolution. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an integral type analog-digital converter and an imaging circuit using the same.

  Digital still cameras and digital movie cameras have become widespread. The number of pixels has increased year by year, and it has become possible to easily capture high-definition images. In such a digital camera, it is necessary to convert an analog signal obtained by photoelectric conversion into a digital signal.

  As a method of converting an analog signal captured by a CMOS (Complementary Metal Oxide Semiconductor) image sensor into a digital signal, there is a method of converting it into a digital signal in parallel on a column basis using a single slope type analog-digital converter array. Proposed. In this method, since the same reference signal only needs to be supplied to a plurality of analog-digital converters arranged for each column, the circuit for generating the reference signal can be shared, and the circuit area can be reduced. .

The single slope type analog-digital converter has advantages such as high accuracy and low power consumption, in addition to the fact that the area can be easily reduced as compared with the flash type. Patent Document 1 discloses a configuration of a single slope type analog-digital converter.
Japanese Patent Laid-Open No. 7-86936

  However, unlike the flash type, the single slope type analog-digital converter has a lower conversion speed as the resolution increases. In recent years, high resolution has been demanded in various fields, and on the other hand, the demand for high-speed conversion has become increasingly strong. In the above-mentioned digital camera field, in addition to increasing the resolution, the number of pixels tends to increase, and further improvement in conversion speed is required.

  The present invention has been made in view of such a situation, and an object thereof is to provide an analog-digital converter capable of improving the conversion speed while suppressing an increase in circuit area and an imaging circuit using the same.

  In order to solve the above problems, an analog-digital converter according to an aspect of the present invention includes a step corresponding to a second resolution coarser than a first resolution obtained by dividing an input voltage range of an analog signal to be converted into a digital signal. A reference signal generation circuit that generates a reference signal whose level changes sequentially, a comparison circuit that compares an analog signal with a reference signal generated by the reference signal generation circuit, and a time until a comparison result by the comparison circuit changes And a digital signal generation circuit for generating a digital signal having the second resolution. When the comparison result of the comparison circuit changes, the reference signal generation circuit supplies another reference signal to the comparison circuit in order to bring the resolution of the digital signal held in the digital signal generation circuit close to the first resolution, thereby generating the digital signal. The circuit corrects the digital signal having the second resolution to the digital signal having the first resolution in accordance with a comparison result with another reference signal by the comparison circuit.

  The “reference signal generation circuit” may generate another reference signal for quantization with the first resolution. The “reference signal generation circuit” may sequentially generate other reference signals for gradually reducing the quantization width to the first resolution and sequentially supply them to the comparison circuit. For example, another reference signal for quantization with a resolution finer than the second resolution and coarser than the first resolution is generated and supplied to the comparison circuit, and then another reference signal for quantization with the first resolution is generated. Then, it may be supplied to the comparison circuit. The “digital signal generation circuit” may determine the value of the least significant bit according to a comparison result with another reference signal for quantization at the first resolution by the comparison circuit.

  According to this aspect, it is possible to improve the conversion speed as compared with the case of using the reference signal whose signal level sequentially changes in the step corresponding to the first resolution. Further, since there is no need to increase the number of comparison circuits, the increase in circuit area is also limited.

  The reference signal generation circuit receives a count value that is counted up or down, and generates a reference signal in which a signal level sequentially changes in steps corresponding to the second resolution, and a count up Or a second digital-to-analog converter circuit that receives a count value that is counted down and generates a signal that is shifted by a voltage corresponding to the quantization width of the first resolution as another reference signal with respect to the reference signal. But you can. According to this, a plurality of types of reference signals can be easily generated.

  The reference signal generation circuit receives a count value that is counted up or down, and generates a reference signal in which a signal level sequentially changes in steps corresponding to the second resolution, and a first digital-analog conversion circuit, A level shifter that shifts the level of the output signal of the digital-analog conversion circuit by a voltage corresponding to the quantization width of the first resolution to generate another reference signal may be included. According to this, it is possible to reduce the influence of characteristic variation caused by using a plurality of digital-analog conversion circuits.

  A plurality of comparison circuits may be provided to compare analog signals input in a plurality of systems in parallel, and the reference signal generation circuit may be shared by the plurality of comparison circuits provided. According to this, an increase in circuit area can be suppressed by sharing the reference signal generation circuit.

  Another aspect of the present invention is an analog-digital converter. The analog-to-digital converter includes a first reference signal whose signal level sequentially changes in steps corresponding to a second resolution coarser than the first resolution obtained by dividing the input voltage range of the analog signal to be converted into a digital signal, A reference signal generation circuit that generates a second reference signal for setting the resolution of a digital signal converted at two resolutions to the first resolution is compared with an analog signal and the first reference signal generated by the reference signal generation circuit. According to the first comparison circuit, the second comparison circuit that compares the analog signal and the second reference signal generated by the reference signal generation circuit, and the time until the comparison result by the first comparison circuit changes, the second comparison signal A digital signal generation circuit that generates a digital signal having a resolution and corrects the digital signal to a digital signal having the first resolution in accordance with a comparison result by the second comparison circuit.

  According to this aspect, while the second comparison circuit compares the analog signal to be converted with the second reference signal, the first comparison circuit can perform the next conversion operation, thereby further improving the conversion speed. Can be made.

  Yet another embodiment of the present invention is an imaging circuit. This imaging circuit includes an image sensor that converts light from a subject into an electrical signal, and the analog-digital converter of the above-described aspect that converts an analog signal output from the image sensor into a digital signal.

  According to this aspect, it is possible to realize an imaging circuit in which the circuit area is suppressed while high-speed conversion is possible.

  Note that any combination of the above-described constituent elements, and those in which the constituent elements and expressions of the present invention are mutually replaced between methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to the present invention, the conversion speed can be improved while suppressing an increase in circuit area.

(Embodiment 1)
FIG. 1 shows a configuration of an analog-digital converter (hereinafter referred to as an AD converter) 100 according to Embodiment 1 of the present invention. The AD converter 100 includes a comparison circuit CP, a first digital-analog conversion circuit 11 (denoted as DAC1 in the figure), a second digital-analog conversion circuit 12 (denoted as DAC2 in the figure), and a first switch SW1. , A second switch SW2, a first counter 20, a second counter 30, and a clock generator 40. A first digital-analog conversion circuit (hereinafter referred to as a DA conversion circuit) 11, a second DA conversion circuit 12, a first switch SW1, a second switch SW2, and a first counter 20 are used as reference signals supplied to the comparison circuit CP. It functions as a reference signal generation circuit to generate.

  The comparison circuit CP compares the voltage level of the input analog signal Vin to be converted into a digital signal with the voltage level of the reference signal supplied from the first DA conversion circuit 11 or the second DA conversion circuit 12. The comparison result is output to the second counter 30 as a control signal. The control signal is given as a binary signal. For example, the comparison circuit CP outputs a low level signal when the input analog signal Vin is less than the reference signal, and outputs a high level signal when the input analog signal Vin is greater than or equal to the reference signal.

  The clock generation unit 40 generates a clock signal having a predetermined speed and supplies it to the first counter 20 and the second counter 30. The first counter 20 counts up from zero in synchronization with the clock signal supplied from the clock generator 40. The first counter 20 supplies the count value to the first DA conversion circuit 11 and the second DA conversion circuit 12 as a digital signal.

  The first DA conversion circuit 11 converts the count value supplied from the first counter 20 into an analog signal, and supplies the analog signal as a first reference signal to the comparison circuit CP via the first switch SW1. The second DA conversion circuit 12 converts the count value supplied from the first counter 20 into an analog signal, and supplies the analog signal as a second reference signal to the comparison circuit CP via the second switch SW2. The first switch SW1 and the second switch SW2 are selectively turned on / off.

  The second counter 30 counts up from zero in synchronization with the clock signal supplied from the clock generator 40. The second counter 30 is controlled by the control signal from the comparison circuit CP, and uses the count value or the adjusted count value at the time pointed by the control signal as the output digital signal Vout of the AD converter 100. Therefore, the second counter 30 functions as a digital signal generation circuit that generates a converted digital value.

  Next, the operation of the AD converter 100 according to the first embodiment will be described. Hereinafter, an example in which the input analog signal Vin is converted into a 4-bit digital signal will be described. When converting to a 4-bit digital signal, it is necessary to divide the full scale range of the input analog signal Vin, that is, the entire input voltage range by 2 ^ 4 = 16. Therefore, the AD converter 100 has a resolution of 16 in order to convert it into a 4-bit digital signal. The resolution is also expressed as a quantum number or 1 LSB (Least Significant Bit). The 1LSB voltage refers to a minimum analog voltage that can be distinguished with a set resolution, that is, a voltage corresponding to a quantization width.

  FIGS. 2A to 2B are diagrams illustrating the first reference signal and the second reference signal in the first embodiment. FIG. 2A shows the output voltage of the first DA converter circuit 11, and FIG. 2B shows the output voltage of the second DA converter circuit 12. First, the AD conversion operation by the AD converter 100 starts when the first switch SW1 is on and the second switch SW2 is off. The first DA converter circuit 11 supplies, as a first reference signal, a signal whose voltage increases by 2LSB for each clock CLK to the comparison circuit CP. The first reference signal may be a ramp-like signal or a linear signal. Any waveform may be used as long as the reference voltage level is increased by 2LSB in synchronization with the clock CLK.

  In order to generate a signal that changes by 2 LSB every clock, the first counter 20 may be designed to count up by two each time the clock CLK is supplied from the clock generator 40. Further, when the first counter 20 counts up by one each time the clock CLK is supplied from the clock generation unit 40, the first DA converter circuit 11 outputs the input from the first counter 20 by doubling the input. That's fine.

  The comparison circuit CP compares the first reference signal supplied from the first DA conversion circuit 11 with the input analog signal Vin. While the voltage level of the input analog signal Vin is higher than the voltage level of the first reference signal, a low level signal is output. When the voltage level of the first reference signal is substantially equal to or exceeds the voltage level of the input analog signal Vin, the output signal is inverted and a low level signal is output. At this point, the input analog signal Vin is converted to a digital signal with half the resolution of the desired resolution.

  In synchronization with the inversion of the output of the comparison circuit CP, the first switch SW1 is turned off and the second switch SW2 is turned on. The second DA conversion circuit 12 also supplies a signal whose voltage increases by 2 LSB for each clock CLK, that is, a signal having the same waveform as the first reference signal, to the comparison circuit CP as the second reference signal.

  Compared with the first reference signal, the second reference signal has a voltage level lower by 1 LSB and draws a waveform delayed by one clock. In order to generate the second reference signal, the first counter 20 has a second DA conversion circuit at a timing obtained by delaying the value obtained by subtracting 1 from the count value that is incremented by 2 from the first DA conversion circuit 11 by one clock. 12 is supplied. The second DA converter circuit 12 can generate a signal having a voltage level lower by 1 LSB than the first DA converter circuit 11. Further, as will be described later, the output signal of the first DA converter circuit 11 may be generated by shifting the level by 1 LSB.

  The comparison circuit CP compares the input analog signal Vin with the second reference signal supplied from the second DA conversion circuit 12 at the next clock timing when the output is inverted. When the voltage level of the input analog signal Vin is higher than or substantially equal to the voltage level of the second reference signal, a high level signal is output. When the voltage level is lower than the voltage level of the second reference signal, a low level signal is output.

  The second counter 30 counts up by two in synchronization with the first counter 20 while the control signal from the comparison circuit CP is at low level, and stops counting up when the control signal changes to high level. . When the control signal input at the next clock is at a high level, the count value held as it is is output as the output digital signal Vout of the AD converter 100. When the control signal input at the next clock is at a low level, the count value held is 1 and the value obtained by subtraction is output as the output digital signal Vout. At this point, the input analog signal Vin is converted into a digital signal with a desired resolution.

The conversion time of the AD converter 100 in the first embodiment is expressed by the following formula 1.
Conversion time = T × number of steps (2 ⁿ⁻¹ +1) (Equation 1)
T indicates the time required for conversion of a unit step corresponding to 2-bit conversion, and generally depends on the speed of the comparison circuit CP. The last conversion step corresponds to 1-bit conversion. 2 ⁿ indicates the resolution. 2 ^n-1 indicates half of the desired resolution.

(Comparative example)
FIG. 3 shows a configuration of the AD converter 200 in the comparative example. The AD converter 200 in the comparative example is generally called a single scope type. The configuration of the AD converter 200 in the comparative example has the same parts as the configuration of the AD converter 100 in the first embodiment, and the same reference numerals as those in FIG. Hereinafter, differences from the AD converter 100 according to the first embodiment will be described.

  The AD converter 200 in the comparative example has one DA conversion circuit 10 included in the reference signal generation circuit, and only one type of reference signal supplied to the comparison circuit CP is generated. Therefore, the first switch SW1 and the second switch SW2 for switching a plurality of reference signals are not provided.

Next, the operation of the AD converter 200 in the comparative example will be described.
FIG. 4 is a diagram illustrating a reference signal in the comparative example. The DA conversion circuit 10 supplies a signal whose voltage increases by 1 LSB every clock CLK as a reference signal to the comparison circuit CP. In order to generate a signal that changes by 1 LSB for each clock, the first counter 20 may be designed to count up by 1 each time the clock CLK is supplied from the clock generator 40.

  The comparison circuit CP compares the reference signal supplied from the DA conversion circuit 10 with the input analog signal Vin. While the voltage level of the input analog signal Vin is higher than the voltage level of the reference signal, a low level signal is output. When the voltage level of the reference signal is substantially equal to or exceeds the voltage level of the input analog signal Vin, the output signal is inverted and a low level signal is output.

  The second counter 30 counts up by one in synchronization with the first counter 20 while the control signal from the comparison circuit CP is at low level, and stops counting up when the control signal changes to high level. . The count value held at that time is output as the output digital signal Vout of the AD converter 200. At this point, the input analog signal Vin is converted into a digital signal with a desired resolution.

The conversion time of the AD converter 200 in the comparative example is expressed by the following formula 2.
Conversion time = T × number of steps (2 ⁿ ) (Formula 2)
T indicates the time required for conversion of a unit step corresponding to conversion of 1 bit, and generally depends on the speed of the comparison circuit CP. 2 ⁿ indicates the resolution.

  As described above, according to the first embodiment, the conversion speed can be improved while suppressing an increase in circuit area. As can be seen from Equation 2, the single slope AD converter has a lower conversion speed and a longer conversion time as the resolution increases. In contrast, the AD converter 100 according to the first embodiment can halve the conversion time by about half compared to the AD converter 200 according to the comparative example. Moreover, it is not necessary to provide a large number of comparison circuits as in the flash type, and the increase in circuit area is limited even when compared with the AD converter 200 in the comparative example. In addition, when a large number of comparison circuits are used, conversion accuracy may decrease due to variations in characteristics between comparison circuits. In this regard, since the AD converter 100 according to the first embodiment performs conversion using a single comparison circuit, the conversion accuracy is high without being affected by variations in such characteristics.

(Embodiment 2)
FIG. 5 shows a configuration of the AD converter 300 according to the second embodiment of the present invention. The configuration of the AD converter 300 in the second embodiment has the same parts as the configuration of the AD converter 100 in the first embodiment, and the same reference numerals as those in FIG. Hereinafter, differences from the AD converter 100 according to the first embodiment will be described.

  The reference signal generation circuit of the AD converter 200 according to the second embodiment includes four DA conversion circuits including a first DA conversion circuit 11, a second DA conversion circuit 12, a third DA conversion circuit 13, and a fourth DA conversion circuit 14. Therefore, four types of reference signals supplied to the comparison circuit CP are generated. Correspondingly, switches for selecting any one of four types of reference signals and supplying them to the comparison circuit CP are the first switch SW1, the second switch SW2, the third switch SW3, and the fourth switch SW4. Four are provided.

Next, the operation of the AD converter 300 according to the second embodiment will be described.
FIGS. 6A to 6B are diagrams illustrating the first reference signal and the second reference signal in the second embodiment. FIG. 6A shows the output voltage of the first DA converter circuit 11, and FIG. 6B shows the output voltage of the second DA converter circuit 12. First, the AD conversion operation by the AD converter 100 starts from a state in which the first switch SW1 is on, the second switch SW2 is off, the third switch SW3 is off, and the fourth switch SW4 is off. The first DA converter circuit 11 supplies a signal whose voltage increases by 3 LSB for each clock CLK as a first reference signal to the comparator circuit CP.

  The comparison circuit CP compares the voltage level of the first reference signal supplied from the first DA conversion circuit 11 with the voltage level of the input analog signal Vin. While the voltage level of the input analog signal Vin is higher than the voltage level of the first reference signal, a low level signal is output. When the voltage level of the first reference signal is substantially equal to or exceeds the voltage level of the input analog signal Vin, the output signal is inverted and a low level signal is output. At this time, the input analog signal Vin is converted into a digital signal with a resolution of 1/4 with respect to the desired resolution.

  In synchronization with the inversion of the output of the comparison circuit CP, the first switch SW1 is turned off, the second switch SW2 is turned on, the third switch SW3 is turned off, and the fourth switch SW4 is turned off. The second DA conversion circuit 12 also supplies a signal whose voltage increases by 3 LSB for each clock CLK to the comparison circuit CP as a second reference signal.

  Compared with the first reference signal, the second reference signal has a low 2LSB voltage level and draws a waveform delayed by one clock. In order to generate the second reference signal, the first counter 20 has a second DA converter circuit at a timing obtained by delaying the value obtained by subtracting 2 from the count value incremented by 4 by one clock from the first DA converter circuit 11. 12 is supplied. The second DA converter circuit 12 can generate a signal having a voltage level lower by 2 LSB than the first DA converter circuit 11. Further, as will be described later, the output signal of the first DA converter circuit 11 may be generated by shifting the level by 2LSB.

  The comparison circuit CP compares the input analog signal Vin with the second reference signal supplied from the second DA conversion circuit 12 at the next clock timing when the output is inverted. When the voltage level of the input analog signal Vin is higher than or substantially equal to the voltage level of the second reference signal, a high level signal is output. When the voltage level is lower than the voltage level of the second reference signal, a low level signal is output.

  The second counter 30 counts up by four in synchronization with the first counter 20 while the control signal from the comparison circuit CP is at low level, and stops counting up when the control signal changes to high level. . When the control signal input at the next clock is at a high level, the count value is held as it is, and when it is at a low level, 2 is subtracted from the held count value. At this time, the input analog signal Vin is converted into a digital signal with half the resolution of the desired resolution.

  As described above, as a result of comparison between the input analog signal Vin by the comparison circuit CP and the second reference signal supplied from the second DA converter circuit 12, the voltage level of the input analog signal Vin is higher than the voltage level of the second reference signal. If they are substantially equal, a high level signal is output. In this case, the first switch SW1 is turned off, the second switch SW2 is turned off, the third switch SW3 is turned on, and the fourth switch SW4 is turned off corresponding to the output. On the other hand, if the voltage level of the input analog signal Vin is lower than the voltage level of the second reference signal as a result of the comparison, a low level signal is output. In this case, the first switch SW1 is turned off, the second switch SW2 is turned off, the third switch SW3 is turned off, and the fourth switch SW4 is turned on corresponding to the output.

  FIGS. 7A to 7B are diagrams illustrating the third reference signal and the fourth reference signal in the second embodiment. FIG. 7A shows the output voltage of the third DA converter circuit 13, and FIG. 7B shows the output voltage of the fourth DA converter circuit 14. When the voltage level of the input analog signal Vin is higher than or substantially equal to the voltage level of the second reference signal as a result of the comparison, the comparison circuit CP is supplied from the third DA conversion circuit 13 at the next clock timing. 3 The voltage level of the reference signal is compared with the voltage level of the input analog signal Vin. When the voltage level of the input analog signal Vin is higher than or substantially equal to the voltage level of the third reference signal, a high level signal is output. When the voltage level of the input analog signal Vin is lower than the voltage level of the third reference signal, a low level signal is output.

  The third reference signal has a voltage level lower by 1 LSB than the first reference signal, and draws a waveform delayed by two clocks. Compared with the second reference signal, the voltage level is higher by 1 LSB and a waveform delayed by one clock is drawn.

  When the voltage level of the input analog signal Vin is lower than the voltage level of the second reference signal as a result of the comparison between the voltage level of the input analog signal Vin and the voltage level of the second reference signal, the comparison circuit CP performs the next clock timing. The fourth reference signal supplied from the fourth DA conversion circuit 14 is compared with the input analog signal Vin. When the voltage level of the input analog signal Vin is higher than or substantially equal to the voltage level of the fourth reference signal, a high level signal is output. When the voltage level of the input analog signal Vin is lower than the voltage level of the fourth reference signal, a low level signal is output.

  The fourth reference signal has a 3LSB voltage level lower than the first reference signal and draws a waveform delayed by two clocks. Compared with the second reference signal, the voltage level is low by 1 LSB, and a waveform delayed by 1 clock is drawn.

  When the control signal from the comparison circuit CP is a high level signal when two clocks have elapsed after stopping the count-up, the second counter 30 outputs the held count value to the output digital signal of the AD converter 300. Output as Vout. When the control signal from the comparison circuit CP is a low level signal, 1 is subtracted from the held count value and output as the output digital signal Vout of the AD converter 300. At this point, the input analog signal Vin is converted into a digital signal with a desired resolution.

The conversion time of the AD converter 300 in the second embodiment is expressed by the following formula 3.
Conversion time = T × number of steps (2 ⁿ⁻² +2) (Equation 3)
T indicates the time required for conversion of a unit step corresponding to 3-bit conversion, and generally depends on the speed of the comparison circuit CP. Note that the last conversion step from the last corresponds to 2-bit conversion, and the last conversion step corresponds to 1-bit conversion. 2 ⁿ indicates the resolution. 2 ^n-2 indicates a resolution of 1/4 with respect to a desired resolution.

  As described above, according to the second embodiment, the conversion speed can be further improved as compared with the AD converter 100 according to the first embodiment. Compared to the AD converter 200 in the comparative example, the AD converter 300 in the second embodiment can reduce the conversion time to about ¼. However, it is necessary to make the area of the reference signal generation circuit larger than the configuration in the first embodiment. Thus, the conversion speed and circuit area are in a trade-off relationship, and can be selected by the designer according to the application to be applied. A configuration in which the conversion time is further shortened to about 1/8 is possible, and in this case, the area of the reference signal generation circuit increases.

(Embodiment 3)
FIG. 8 shows a configuration of the AD converter 400 according to the third embodiment of the present invention. The configuration of the AD converter 400 in the third embodiment is an example of converting a plurality of input analog signals into digital signals in parallel. Basically, a plurality of AD converters 100 according to the first embodiment are provided in an array and the reference signal generation circuit is shared.

  The AD converter 400 receives n analog signals. That is, the input analog signal Vin [0],..., The input analog signal Vin [n−1] and the input analog signal Vin [n] are input in parallel. A comparison circuit and a digital signal generation circuit are provided for each system. The input analog signal Vin [0] is input to one input terminal of the first comparison circuit CP1, and the output signal of the first DA conversion circuit 11 or the sixth switch is input to the other input terminal via the fifth switch SW11. The output signal of the second DA converter circuit 12 is selectively input via the SW12. The output signal of the first comparison circuit CP1 controls the third counter 31. Since these components operate in the same manner as the configuration of the AD converter 100 in the first embodiment, description thereof is omitted.

  Components including the second comparison circuit CP2, the seventh switch SW21, the first DA conversion circuit 11, the eighth switch SW22, the second DA conversion circuit 12 and the fourth counter 32, as well as the third comparison circuit CP3, the ninth switch SW31, Since the components including the 1DA conversion circuit 11, the tenth switch SW32, the second DA conversion circuit 12, and the fifth counter 33 also operate in the same manner as the configuration of the AD converter 100 in the first embodiment, description thereof is omitted.

  As described above, according to the third embodiment, when a plurality of analog signals are converted into digital signals in parallel, the DA converter circuit is compared with the case where a plurality of AD converters 100 described in the first embodiment are arranged. Since the reference signal generation circuit configured by the above can be shared, the circuit area can be reduced. As described above, the conversion speed and the circuit area are in a trade-off relationship. However, by sharing the reference signal generation circuit, the degree of increase in the circuit area can be reduced. In addition, variation in characteristics among a plurality of DA conversion circuits affects the conversion accuracy. However, by sharing, the influence can be reduced and the conversion accuracy can be increased.

(Embodiment 4)
FIG. 9 shows a configuration of an AD converter 500 according to Embodiment 4 of the present invention. The configuration of the AD converter 500 in the fourth embodiment has the same parts as the configuration of the AD converter 100 in the first embodiment, and the same reference numerals as those in FIG. Hereinafter, differences from the AD converter 100 according to the first embodiment will be described.

  The reference signal generation circuit of the AD converter 400 according to the fourth embodiment does not include a plurality of DA conversion circuits, but includes a single DA conversion circuit and a level shifter. In FIG. 9, a level shifter 15 is provided instead of the second DA conversion circuit 12. As described above, the reference signal generation circuit may generate the first reference signal and the second reference signal that is lower in voltage level by 1 LSB than the first reference signal and delayed by one clock. The first DA conversion circuit 11 generates a first reference signal, and the level shifter 15 receives the first reference signal from the first DA conversion circuit 11 and outputs a signal obtained by shifting the voltage level by 1 LSB in the low direction after one clock. 2 generated as a reference signal. The first counter 20 does not need to supply a count value to the level shifter 15.

  FIG. 10 shows a configuration example of the level shifter 15 in the AD converter 400 according to the fourth embodiment. The configuration example is an example in which the level shifter 15 is configured by a switched capacitor type subtracting amplifier circuit. The level shifter 15 includes an operational amplifier OP, an 1LSB voltage generator 16, an input capacitor C1, a feedback capacitor C2, an eleventh switch SW41, a twelfth switch SW42, and an auto zero switch SW43.

  An input capacitor C1 is connected to the inverting input terminal of the operational amplifier OP, the output signal of the first DA converter circuit 11 is input via the eleventh switch SW41, and the 1LSB voltage generator 16 is input via the twelfth switch SW42. Output signal is input. The non-inverting input terminal of the operational amplifier OP is connected to the auto-zero potential. The output terminal and the inverting input terminal of the operational amplifier OP are connected via a feedback capacitor C2. Further, an auto-zero switch SW43 is connected to the outside thereof, and the output terminal and the inverting input terminal of the operational amplifier OP can be short-circuited. The 1LSB voltage generator 16 generates an analog voltage corresponding to 1LSB.

FIG. 11 is a timing chart for explaining the operation of the level shifter 15. First, the auto-zero switch SW43 is turned on to set the auto-zero potential Vag. In this state, both the input side node N1 and the output side node N2 are at the auto-zero potential Vag. In order to sample the output signal VDAC1 of the first DA converter circuit 11, the eleventh switch SW41 is turned on and the twelfth switch SW42 is turned off. At this time, the charge QA of the input side node N1 is expressed by the following equation 4.
QA = C1 (VDAC1-Vag) (Formula 4)

Next, the auto-zero switch SW43 is turned off to amplify by virtual grounding. Thereafter, in order to subtract the output signal VLSB of the 1LSB voltage generator 16, the eleventh switch SW41 is turned off and the twelfth switch SW42 is turned on. At this time, the charge QB of the input side node N1 is expressed by the following formula 5.
QB = C1 (VLSB−Vag) + C2 (Vout−Vag) (Formula 5)

Since the input side node N1 does not have a path through which charges escape, QA = QB is obtained from the law of conservation of charge, and the following equation 6 is established.
Vout = C1 / C2 (VDAC1-VLSB) + Vag (Expression 6)

  Therefore, the switched-capacitor-type subtraction amplifier circuit calculates the difference between the output signal VDAC1 of the first DA converter circuit 11 and the output signal VLSB of the 1LSB voltage generator 16 when the auto-zero potential Vag is ideally the ground potential. Amplification is possible by the capacitance ratio of the input capacitor C1 and the feedback capacitor C2. If the capacitance ratio is the same, a signal obtained by subtracting the output signal VLSB of the 1LSB voltage generation unit 16 from the output signal VDAC1 of the first DA conversion circuit 11 can be generated.

  As described above, according to the fourth embodiment, it is possible to suppress a decrease in conversion accuracy due to characteristic variation caused by using a plurality of DA converter circuits. That is, even if the characteristics of the DA converter circuit are deteriorated and the first reference signal is deviated, the second reference signal is similarly deviated. Therefore, the relative relationship between the first reference signal and the second reference signal Then the characteristics do not deteriorate. Further, the control of the counter that supplies the count value to the DA converter circuit can be simplified.

(Embodiment 5)
FIG. 12 shows a configuration of an AD converter 600 according to the fifth embodiment of the present invention. The configuration of the AD converter 600 in the fifth embodiment has the same parts as the configuration of the AD converter 100 in the first embodiment, and the same reference numerals as those in FIG. Hereinafter, differences from the AD converter 100 according to the first embodiment will be described.

  The AD converter 600 according to the fifth embodiment includes a plurality of comparison circuits. In FIG. 12, two comparison circuits, that is, a fourth comparison circuit CP41 and a fifth comparison circuit CP42 are provided. The fourth comparison circuit CP41 compares the voltage level of the input analog signal Vin to be converted into a digital signal with the voltage level of the first reference signal supplied from the first DA conversion circuit 11. The comparison result is output to the control signal generator 35 as a control signal. The control signal is given as a binary signal. For example, the fourth comparison circuit CP41 outputs a low level signal when the voltage level of the input analog signal Vin is lower than the voltage level of the first reference signal, and the high level when it is equal to or higher than the voltage level of the first reference signal. Output a signal.

  The fifth comparison circuit CP42 compares the voltage level of the input analog signal Vin to be converted into a digital signal with the voltage level of the second reference signal supplied from the second DA conversion circuit 12. The comparison result is output to the control signal generator 35 as a control signal. The control signal is given as a binary signal. For example, the fifth comparison circuit CP42 outputs a low level signal when the voltage level of the input analog signal Vin is lower than the second reference signal, and outputs a high level signal when the voltage level is higher than the second reference signal.

  While the control signal from the fourth comparison circuit CP41 is at a low level, the control signal generator 35 generates a control signal instructing to count up by two in synchronization with the first counter 20, and to the second counter 30 Supply. When the control signal from the fourth comparison circuit CP41 changes to high level, the second counter 30 is instructed to stop counting up.

  When the control signal input from the fifth comparison circuit CP42 at the next clock is at a high level, the second counter 30 is instructed to output the held count value as the output digital signal Vout of the AD converter 600. When the control signal input from the fifth comparison circuit CP42 is at a low level, the second counter 30 is instructed to output a value obtained by subtracting 1 from the held count value as the output digital signal Vout. At this point, the input analog signal Vin is converted into a digital signal with a desired resolution.

The conversion time of the AD converter 600 according to the fifth embodiment is expressed by the following formula 7.
Conversion time = T × number of steps (2 ⁿ⁻¹ +1) (Expression 7)
T indicates the time required for the unit step conversion corresponding to the 2-bit conversion, and generally depends on the speeds of the fourth comparison circuit CP41 and the fifth comparison circuit CP42. The last conversion step corresponds to 1-bit conversion. 2 ⁿ indicates the resolution. 2 ^n-1 indicates half of the desired resolution.

  As described above, according to the fifth embodiment, the conversion time can be further reduced as compared with the AD converter 100 according to the first embodiment. That is, the fourth comparison circuit CP41 can start conversion of the next input analog signal Vin immediately after inverting its own output signal. This is because the operation of converting to the minimum resolution after the output signal of the fourth comparison circuit CP41 is inverted is performed by the fifth comparison circuit CP42. If an increase in circuit area is allowed, the conversion speed can be further improved by further increasing the number of comparison circuits. A reference signal generation circuit as described in Embodiment 4 may be provided.

(Sixth embodiment)
FIG. 13 shows a configuration of an imaging circuit 700 according to the sixth embodiment of the present invention. The imaging circuit 700 includes an image sensor 710, a CDS 720, a variable amplifier 730, and an AD converter 400, and may be configured to be integrated on a single semiconductor substrate. The image sensor 710 includes an image sensor such as a charge coupled device (CCD) image sensor or a complementary metal-oxide semiconductor (CMOS) image sensor, and takes in light from a subject and converts it into an electrical signal.

  A CDS (Correlated Double Sampling) 720 removes noise by subtracting the sampled signal period of the pixel signal from the image sensor 710 and the sampled reference period. The variable amplifier 730 amplifies the output signal of the CDS 720 according to the set gain. The AD converter 400 has the configuration according to the third embodiment described above, and converts the output analog signal of the variable amplifier 730 into a digital signal. The digital signal is output to a subsequent DSP (Digital Signal Processor) (not shown).

  The CDS 720 and the variable amplifier 730 are provided for each column of the two-dimensionally arranged CMOS image sensor, and pixel information is input in parallel for each column. The arrayed AD converter 400 converts pixel information, which is input for each column, transmitted as an analog signal into a digital signal in parallel. Of course, the CDS 720, the variable amplifier 730, and the AD converter 100 may have a single system configuration.

  As described above, according to the fifth embodiment, since the AD converter 400 according to the third embodiment is mounted on the imaging circuit 700, pixel information output from the CMOS image sensor or the CCD sensor is AD converted at high speed with high accuracy. can do. Further, since the reference signal generation circuit can be shared by a plurality of systems, an increase in circuit area can be suppressed.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and various modifications can be made to combinations of each component and each processing process. Those skilled in the art will appreciate that such modifications are also within the scope of the present invention. Hereinafter, modifications will be described.

  In the above-described embodiment, the example in which the second counter 30 is provided as the digital signal generation circuit has been described. In this regard, it may be configured by a buffer register capable of holding the count value of the first counter 20 supplied to the first DA conversion circuit 11 or the second DA conversion circuit 12.

  In the above-described embodiment, the first DA conversion circuit 11 and the second DA conversion circuit 12 receive the count value counted up from the first counter 20 and generate the reference signal. The comparison circuit CP receives the reference signal and compares the input analog signal Vin from the lower limit of the input voltage range. In this regard, the first DA conversion circuit 11 and the second DA conversion circuit 12 may receive the count value that is counted down from the first counter 20 and generate the reference signal. The comparison circuit CP receives the reference signal and compares the input analog signal Vin from the upper limit of the input voltage range.

  In addition, as the configuration of the level shifter 15 in the fourth embodiment, an example in which it is configured by a single-ended switched capacitor type subtraction amplifier circuit has been described. In this regard, a fully differential switched capacitor type subtracting amplifier circuit may be used. A voltage comparator such as a chopper comparator may be used.

It is a figure which shows the structure of the analog-digital converter in Embodiment 1 of this invention. FIGS. 2A to 2B are diagrams illustrating the first reference signal and the second reference signal in the first embodiment. It is a figure which shows the structure of the AD converter in a comparative example. It is a figure which shows the reference signal in a comparative example. It is a figure which shows the structure of the AD converter in Embodiment 2 of this invention. FIGS. 6A to 6B are diagrams illustrating the first reference signal and the second reference signal in the second embodiment. FIGS. 7A to 7B are diagrams illustrating the third reference signal and the fourth reference signal in the second embodiment. It is a figure which shows the structure of the AD converter in Embodiment 3 of this invention. It is a figure which shows the structure of the AD converter in Embodiment 4 of this invention. It is a figure which shows the structural example of the level shifter in the AD converter in Embodiment 4. It is a timing chart for demonstrating operation | movement of a level shifter. It is a figure which shows the structure of the AD converter in Embodiment 5 of this invention. It is a figure which shows the structure of the imaging circuit in Embodiment 6 of this invention.

Explanation of symbols

  SW1 first switch, SW2 second switch, 11 first DA conversion circuit, 12 second DA conversion circuit, CP comparison circuit, 20 first counter, second counter, 40 clock generation unit, 100 AD converter.

Claims (6)

A reference signal generation circuit that generates a reference signal whose signal level sequentially changes in steps corresponding to a second resolution coarser than the first resolution obtained by dividing the input voltage range of an analog signal to be converted into a digital signal;
A comparison circuit for comparing the analog signal and the reference signal generated by the reference signal generation circuit;
A digital signal generation circuit that generates a digital signal having the second resolution according to the time until the comparison result by the comparison circuit changes,
When the comparison result of the comparison circuit changes, the reference signal generation circuit supplies another reference signal to the comparison circuit so that the resolution of the digital signal held in the digital signal generation circuit approaches the first resolution. And
The digital signal generation circuit corrects a digital signal having the second resolution to a digital signal having the first resolution in accordance with a comparison result with the other reference signal by the comparison circuit. Digital converter. The reference signal generation circuit includes:
A first digital-analog conversion circuit that receives a count value that is counted up or down and generates a reference signal in which a signal level sequentially changes in steps corresponding to the second resolution;
Second digital-to-analog conversion that receives a count value that is counted up or down and generates a signal that is shifted from the reference signal by a voltage corresponding to the quantization width of the first resolution as the other reference signal Circuit,
The analog-digital converter according to claim 1, comprising: The reference signal generation circuit includes:
A first digital-analog conversion circuit that receives a count value that is counted up or down and generates a reference signal in which a signal level sequentially changes in steps corresponding to the second resolution;
A level shifter for shifting the output signal of the first digital-to-analog converter circuit by a voltage corresponding to the quantization width of the first resolution to generate the another reference signal;
The analog-digital converter according to claim 1, comprising: The comparison circuit is provided in a plurality, comparing analog signals input in a plurality of systems in parallel,
4. The analog-digital conversion circuit according to claim 1, wherein the reference signal generation circuit is shared by a plurality of the comparison circuits provided. A first reference signal whose signal level sequentially changes in a step corresponding to a second resolution coarser than the first resolution obtained by dividing the input voltage range of the analog signal to be converted into a digital signal, and converted by the second resolution A reference signal generation circuit for generating a second reference signal for setting the resolution of the digital signal to the first resolution;
A first comparison circuit for comparing the analog signal and the first reference signal generated by the reference signal generation circuit;
A second comparison circuit for comparing the analog signal and the second reference signal generated by the reference signal generation circuit;
The digital signal having the second resolution is generated according to the time until the comparison result by the first comparison circuit changes, and the digital signal having the first resolution is generated according to the comparison result by the second comparison circuit. A digital signal generation circuit for correcting to
An analog-digital converter characterized by that. An image sensor that converts light from the subject into an electrical signal;
The analog-digital converter according to any one of claims 1 to 5, which converts an analog signal output from the image sensor into a digital signal;
An imaging circuit comprising:

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