JP2017112605A - Image capturing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image capturing device capable of reducing a gain assigned to a PGA and thereby reducing a circuit area.SOLUTION: The image capturing device includes a pixel circuit, a programmable-gain amplifier, an analog-to-digital conversion circuit, and a control circuit. The pixel circuit outputs a photoreception signal. The programmable-gain amplifier amplifies the photoreception signal with a first gain. The analog-to-digital conversion circuit further amplifies the amplified signal that has been amplified by the programmable-gain amplifier, with a second gain by changing a circuit configuration by control, and digitally converts the resultant signal. The control circuit controls the analog-to-digital conversion circuit.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an imaging apparatus.

  One of image sensors for image input of electronic devices (for example, copiers and facsimiles) is a CMOS (Complementary MOS) image sensor. A CMOS image sensor amplifies a signal from a pixel with a programmable gain amplifier (PGA (Programmable-Gain Amplifier)), and the amplified signal is analog / digital converted with an analog / digital conversion circuit (ADC (Analog to Digital Converter)). (AD (Analog-to-Digital)) conversion and digital output. These PGAs and ADCs are required for units such as each pixel and column of the pixel array. Since the pixel pitch is as narrow as several μm, when these circuits are made on-chip, it is necessary to suppress the occupied area as much as possible within the pitch width. As one of such efforts, many ADCs using a lamp ADC or a cyclic ADC are used.

  There is a document that discloses an invention for obtaining a gain in a PGA of a CMOS image sensor. The document discloses a technique in which a CDS output signal is divided into a plurality of regions in accordance with the magnitude of the signal, and the divided signals are amplified by a PGA with a gain set for each region. (See Patent Document 1).

  However, in the conventional configuration, in order to increase the gain of the PGA, the element size ratio must be increased. Specifically, since the PGA does not fit in the pixel pitch (an integer multiple of the pixel pitch), it is necessary to increase the occupied area of the PGA in the vertical direction that is the orthogonal direction of the pixel pitch. Thus, there is a problem that an attempt to increase the gain of the PGA leads to an increase in circuit area.

  The present invention has been made in view of the above, and it is an object of the present invention to provide an imaging apparatus that can reduce a gain share in a PGA and reduce a circuit area.

  In order to solve the above-described problem, an imaging apparatus according to an embodiment of the present invention includes a pixel circuit that outputs a light reception signal, a programmable gain amplifier that amplifies the light reception signal with a first gain, and the programmable gain amplifier. An analog / digital conversion circuit that amplifies the amplified signal with a second gain by changing a circuit configuration by control and performs digital conversion, and a control circuit that controls the analog / digital conversion circuit. And

  According to the present invention, it is possible to reduce the gain share in the PGA and reduce the circuit area.

FIG. 1 is a block diagram illustrating an example of the configuration of an electronic apparatus including an imaging device according to an embodiment of the present invention. FIG. 2 is a diagram illustrating an example of a layout in the CMOS line sensor of each block included in the imaging apparatus illustrated in FIG. 1. FIG. 3 is a diagram illustrating an example of a PGA circuit. FIG. 4 is a diagram illustrating an example of a circuit of a cyclic ADC. FIG. 5A is a circuit diagram illustrating a connection state in the reset phase of the ADC. FIG. 5B is a circuit diagram showing a connection state in the data input phase of the ADC. FIG. 5C is a circuit diagram showing a connection state in the hold phase of the ADC. FIG. 5D is a circuit diagram illustrating a connection state in the ADC sample phase. FIG. 6 is a diagram illustrating an example of input / output characteristics of the comparator when AD conversion is performed with a redundant configuration of 1.5 bits per cycle. FIG. 7 is a diagram illustrating an example of ADC control timing and input / output states. FIG. 8 is a diagram illustrating an example of a change in output voltage in each operation phase when the ADC is operated as shown in FIG. FIG. 9 is a diagram illustrating an example of input / output characteristics of a comparator when AD conversion is performed with a redundant configuration of 2.5 bits per cycle. FIG. 10A is a circuit diagram illustrating a connection state in the reset phase of the ADC. FIG. 10B is a circuit diagram showing a connection state in the data input phase of the ADC. FIG. 10C is a circuit diagram illustrating a connection state in the signal amplification phase of the ADC. FIG. 10D is a circuit diagram showing a connection state in the amplified signal input phase of the ADC. FIG. 10E is a circuit diagram illustrating a connection state in the ADC hold phase. FIG. 10F is a circuit diagram illustrating a connection state in the ADC sample phase. FIG. 11 is a diagram illustrating an example of ADC control timing and input / output states including an amplifier mode. FIG. 12 is a diagram illustrating an example of a change in output voltage in each operation phase when the ADC is operated as illustrated in FIG. 11.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals.

  FIG. 1 is a block diagram illustrating an example of the configuration of an electronic apparatus including an imaging device according to an embodiment of the present invention. The electronic device shown in FIG. 1 is, for example, a multifunction machine, a facsimile machine, an image scanner device, or the like.

  As shown in FIG. 1, the electronic apparatus according to the present embodiment includes an imaging device 60, an image signal processing circuit 5, and a display unit 6. The imaging device 60 includes a pixel circuit 1 including photodiodes 1R, 1G, and 1B, an FPN (Fixed Pattern Noise) suppression circuit 2, a programmable gain amplifier (PGA (Programmable-Gain Amplifier)) 3, and an analog / digital conversion circuit. (ADC (Analog to Digital Converter)) 4.

  In FIG. 1, a pixel circuit 1 includes photodiodes 1R, 1G, and 1B that receive RGB three colors, and a charge signal that is proportional to the amount of light (light quantity) received by the photodiodes 1R, 1G, and 1B is supplied to a pixel amplifier (not shown). ) And is output to the FPN suppression circuit 2. In the present specification, each signal converted based on the charge signal until it is input to the PGA 3 corresponds to a “light reception signal”.

  The FPN suppression circuit 2 is configured by, for example, a sample hold circuit, and removes noise components due to transistor manufacturing variations from the signal voltages from the photodiodes 1R, 1G, and 1B of the pixel circuit 1.

  The PGA 3 amplifies the signal voltage (Vsig) output from the FPN suppression circuit 2 with a predetermined gain (first gain) and outputs the amplified signal voltage to the ADC 4.

  The ADC 4 converts the signal voltage (analog amplified signal) VPGAOUT output from the PGA 3 into digital data and outputs the digital data to the image signal processing circuit 5.

  The image signal processing circuit 5 includes a control circuit 50 (see FIG. 4) that controls the operation timing of the imaging device 60. The image signal processing circuit 5 includes an image signal processing unit that inputs digital data from the imaging device 60 and performs predetermined image signal processing such as edge enhancement processing, binarization processing, dither processing, and the like. An image obtained by signal processing is displayed on the display unit 6, for example.

  In the present embodiment, as an example, a method of using a cyclic ADC for the ADC 4 and obtaining a gain (second gain) in the ADC 4 will be described.

  FIG. 2 is a diagram illustrating an example of a layout in the CMOS line sensor of each block included in the imaging device 60 illustrated in FIG. 1. The CMOS line sensor is an example of the imaging device 60. On the substrate 10 of the CMOS line sensor 20 shown in FIG. 2, photodiodes 1R, 1G, and 1B are juxtaposed in two vertical columns, and each block such as PGA3 or ADC4 has a width W (twice the pixel pitch) W of the two columns. Is arranged. The signal processing circuit 7 is a circuit including a control circuit 50 (see FIG. 4) and the like.

  2 shows an example in which PGA3 and ADC4 are arranged in units of two sets of photodiodes 1R, 1G, and 1B, but the unit of the number of pixels in which PGA3 and ADC4 are arranged is arbitrary. It's okay. Further, here, a one-chip digital output configuration in which the ADC 4 and the signal processing circuit 7 are housed on the board is shown, but the ADC 4 and the signal processing circuit 7 may be off-board. In this case, the imaging device 60 is configured to include a chip having an analog output configuration and a set of ADCs 4 and a signal processing circuit 7.

  As shown in FIG. 2, in this example, PGA3, ADC4, etc. are provided in a narrow width (width W) of about several μm, which is twice the pixel pitch. In order to obtain a large gain with the PGA 3, the circuit area of the PGA 3 must be increased, and the occupied area of the PGA 3 needs to be increased in the vertical direction of the column 11. This leads to an increase in circuit area and an increase in chip size. In the present embodiment, a part of the gain share of the PGA 3 (second gain) is assigned to the ADC 4 so that the circuit area of the PGA 3 is as small as possible. Hereinafter, specific configurations of the PGA 3 and the ADC 4 according to the present embodiment will be described.

  FIG. 3 is a diagram illustrating an example of a circuit of the PGA 3 (see FIG. 2). In FIG. 3, PGA 3 is a capacitively coupled PGA with an offset correction function, and includes an operational amplifier 30 that is an operational amplifier, capacitors 31 and 32, and a switch 33. Here, the capacitor 31 is an input-side capacitor having a capacitance Cin1. The capacitor 32 has a capacitance Cout1 and is a feedback capacitor that connects the output terminal of the operational amplifier 30 and the non-inverting input terminal. The switch 33 is connected in parallel with the capacitor 32 and functions to reset the accumulated charge of the capacitor 32. The switch 33 is composed of, for example, a MOS transistor. VCOM_PGA is a reference voltage generated by a predetermined voltage generation circuit, and is applied to the inverting input terminal of the operational amplifier 30. The PGA 3 amplifies the signal voltage Vsig output from the FPN suppression circuit 2 with a set gain (first gain), and outputs the amplified signal voltage VPGAOUT.

  The gain of the PGA 3 configured as described above is determined by the capacitance ratio Cout1 / Cin1. Further, by turning on the switch 33 before amplifying the signal voltage Vsig, the output voltage VPGAOUT is offset to become the reference voltage VCOM_PGA. Accordingly, the output voltage VPGAOUT is obtained by multiplying the signal voltage Vsig of the FPN suppression circuit 2 by Cout1 / Cin1 with reference to the reference voltage VCOM_PGA. Thus, the PGA 3 can be configured by circuit elements that can keep the circuit area small. When a higher gain is required, the gain (first gain) obtained by the PGA 3 is insufficient, and therefore the insufficient gain (second gain) is obtained by the ADC 4 shown below.

  FIG. 4 is a diagram showing an example of a circuit of a cyclic ADC shown as an example of the ADC 4 (see FIG. 2). In FIG. 4, an ADC 4 includes an operational amplifier 40, which is an operational amplifier, capacitors 41 and 42, a comparator 43, switches 44a to 44e, a digital / analog converter circuit (DAC (Digital to Analog Converter)) 45, and a control circuit. 50.

  The capacitor 41 is an input-side capacitor and has a capacitance Cin2. The capacitor 42 is a feedback capacitor and has a capacitance Cout2. The switches 44a to 44e are composed of, for example, MOS transistors. The switches 44a to 44e are switched on and off based on control signals Sa to Sd from the control circuit 50, respectively. The control circuit 50 outputs control signals Sa to Sd corresponding to the switches 44a to 44e, and switches the operation phase of the ADC 4 by switching the switches 44a to 44e. In addition, the control circuit 50 outputs a control signal Sf to the DAC 45 and sets a fixed voltage in the DAC 45.

  The output voltage VPGAOUT from PGA3 is input to the non-inverting input terminal of the operational amplifier 40 via the switch 44a and the capacitor Cin2. The DAC 45 converts the digital signal from the comparator 43 into an analog signal and converts the analog signal output voltage (analog signal voltage) Vdac to the non-inverting input terminal of the operational amplifier 40 via the switch 44b and the capacitor 41. Is input. A predetermined reference voltage VCOM_ADC is applied to the inverting input terminal of the operational amplifier 40. The output terminal of the operational amplifier 40 is connected to the non-inverting input terminal via the switch 44e, and the output terminal of the operational amplifier 40 is connected to the non-inverting input terminal via the switch 44c and the capacitor 42. A connection point between the switch 44a and the capacitor 41 is connected to a connection point between the capacitor 42 and the switch 44c via the switch 44d. The comparator 43 is connected to a connection point between the switch 44c, the switch 44d, and the capacitor 42.

  The operational amplifier 40 subtracts the reference voltage VCOM_ADC from the signal voltage input to the non-inverting input terminal, and amplifies and outputs the voltage resulting from the subtraction. The comparator 43 compares the input signal voltage with a predetermined threshold value and outputs a digital signal. The digital signal output from the comparator 43 is looped back to the DAC 45. The digital signal output from the comparator 43 is input to the logic circuit of the signal processing circuit 7 (see FIG. 2), and is configured as a bit string after conversion of the output voltage VPGAOUT. The DAC 45 converts the digital signal fed back from the comparator 43 into an analog signal (analog signal voltage Vdac).

  Next, the operation of the ADC 4 will be described. First, referring to FIGS. 5 to 9, an analog / digital (AD (Analog-to-Digital)) conversion operation that cyclically performs a reset phase T1, a data input phase T2, a hold phase T3, and a sample phase T4. The phase will be described. After that description, an operation phase in the amplifier mode for obtaining a gain (second gain) in the ADC 4 will be described with reference to FIGS. In the following description, the switches 44a to 44e are turned on and off by the control circuit 50 outputting the control signals Sa to Se to the switches 44a to 44e.

  FIG. 5A is a circuit diagram showing a connection state of the ADC 4 in the reset phase T1. FIG. 5B is a circuit diagram showing a connection state in the data input phase T2 of the ADC 4. FIG. 5C is a circuit diagram showing a connection state of the ADC 4 during the hold phase T3. FIG. 5D is a circuit diagram illustrating a connection state of the ADC 4 in the sample phase T4.

(1) In the reset phase T1 (see FIG. 5A), the switches 44b, 44c, 44d, and 44e of the ADC 4 shown in FIG. 4 are turned on and the switch 44a is turned off. Thereby, the output of the operational amplifier 40 is offset to the reference voltage VCOM_ADC.

(2) In the data input phase T2 (see FIG. 5B), the switches 44a, 44c, and 44d are turned on, and the switches 44b and 44e are turned off. Then, the signal voltage VPGAOUT is input as the input voltage Vin. Thus, the analog value is sampled, and the comparator 43 compares the output voltage Vout at this time with a predetermined threshold value (reference voltage corresponding to the full scale of the ADC 4), and outputs a digital signal. This digital signal is output to a logic circuit and constitutes the MSB (Most Significant Bit) of the bit string.

(3) In the hold phase T3 (see FIG. 5C), the switches 44b and 44c are turned on and the switches 44a, 44d and 44e are turned off. As a result, the output voltage Vdac of the DAC 45 corresponding to the digital signal fed back from the comparator 43 is applied to the electrode of the capacitor 41 (input connected). At this time, the operational amplifier 40 amplifies the differential voltage between the input voltage Vin and the output voltage Vdac of the DAC 45 with an amplification factor determined by the capacitor 41 and the capacitor 42, and outputs the output voltage Vout to the comparator 43.

  When the output voltage Vout at this time is Vout (i + 1) and the output voltage Vout in the immediately preceding phase is Vout (i), the following relationship is established.

Vout (i + 1)
= Vout (i) + (Cout2 / Cin2) (Vout (i) -Vdac)
= (1+ (Cout2 / Cin2)) Vout (i)
-(Cout2 / Cin2) Vdac (1)

  Furthermore, the following expression (2) is obtained by making the capacitances Cin2 and Cout2 of the capacitors 41 and 42 the same.

Vout (i + 1) = 2 × Vout (i) −Vdac (2)

  That is, by the hold phase T3, the output voltage Vout is amplified by a factor of 2, and the predicted value Vdac predicted by the comparator 43 is subtracted.

(4) In the sample phase T4 (see FIG. 5D), the switches 44c and 44d are turned on and the switches 44a, 44b and 44e are turned off. Thereby, the comparator 43 compares the output voltage Vout (i + 1) with a predetermined threshold value (a reference voltage corresponding to the full scale of the ADC 4), and outputs a digital signal. This digital signal is output to the logic circuit and constitutes the lower bits following the MSB.

  FIG. 6 is a diagram illustrating an example of input / output characteristics of the comparator 43 when AD conversion is performed with a redundant configuration of 1.5 bits per cycle.

  Here, the input voltage range of the ADC 4 is assumed to be VREFN to VREFP as shown in FIG. The output voltage VPGAOUT of PGA3 is output with reference to the reference voltage VCOM_PGA. Therefore, if there is a difference between the reference voltage VREFP in the input voltage range of the ADC 4 and the reference voltage VCOM_PGA of the PGA 3, the corresponding amount becomes an offset. Therefore, the voltages VREFP and VCOM_PGA are ideally the same value, and are preferably set as such.

  Assuming that the voltage between the input voltage ranges is VREFN4 and VREFP4, VREFN4 and VREFP4 are expressed by the following equations when variation is ignored.

VREFN4 = (3/8) × (VREFP−VREFN) (3)
VREFP4 = (5/8) × (VREFP−VREFN) (4)

  In the redundant configuration of 1.5 bits, the comparator 43 (see FIG. 5) uses two comparators, and any of the digital signals whose input voltages are ternary (“−1”, “0”, “1”). And a 2-bit digital code (“00”, “01”, “10”, respectively) is output as a determination result. Specifically, the comparator 43 determines “−1” when the input voltage is in the range of the voltages VREFN to VREFN4. Further, the comparator 43 determines “0” when the input voltage is in the range of the voltages VREFN4 to VREFP4. Further, the comparator 43 determines “1” when the input voltage is in the range of the voltages VREP4 to VREFP. A signal obtained by encoding a digital signal is fed back from the comparator 43 to the DAC 45.

  The DAC 45 outputs a signal having a voltage VREFN when the input digital signal indicates “−1”. Further, the DAC 45 outputs a signal of voltage (VREFN + VREFP) / 2 when the input digital signal indicates “0”. Further, the DAC 45 outputs a signal of voltage VREFP when the input digital signal indicates “1”.

  Subsequently, the input / output state of the ADC 4 in each phase when the cycle of the hold phase T3 and the sample phase T4 is repeated a plurality of times after the data input phase T2 will be described.

  FIG. 7 is a diagram illustrating an example of control timing and input / output states of the ADC 4. FIG. 8 is a diagram illustrating an example of a change in the output voltage Vout. FIGS. 7 and 8 show a case where the cycle of the hold phase T3 and the sample phase T4 is performed six times after the reset phase T1 and the data input phase T2.

  The control signals Sa, Sb,..., Se in FIG. 7 indicate pulse input timings for switching on and off the switches 44a, 44b,. The corresponding switch is turned on at the rising edge of the pulse, and the corresponding switch is turned off at the falling edge of the pulse.

  In FIG. 7, the output signal waveform of the comparator 43 is shown. The comparator 43 outputs any one of the three values (“−1”, “0”, “1”) at the timing of the data input phase T2 and each sample phase T4.

  The DAC in FIG. 7 shows the output signal waveform of the DAC 45. The DAC 45 outputs an analog signal (analog voltage) of any one of three values (VREFN, (VREFN + VREFP) / 2, VREFP) at the timing of the hold phase T3.

  The DIG data in FIG. 7 shows the waveform of the bit string after the conversion of the output voltage VPGAOUT. As already described in Expression (2), in the hold phase T3, the output voltage Vout is amplified by a factor of two. Therefore, Formula (2) is satisfied whenever the cycle of the hold phase T3 and the sample phase T4 is repeated. The bit string after repeating the cycle shows higher resolution and approximates the output voltage VPGAOUT.

  Note that in the 1.5-bit redundant configuration of this example, when the operations of the hold phase T3 and the sample phase T4 are repeated N times, one corresponding to a resolution of N + 1 bits is generated.

  As shown as an example in FIG. 8, in the data input phase T2, a voltage value based on the signal voltage VPGAOUT from the PGA 3 appears in the output voltage Vout. In the subsequent hold phase T3, the output voltage Vout is held to be doubled with respect to the output voltage Vdac of the DAC 45. In the sample phase T4, the output voltage Vout is maintained to be held in the hold phase T3, and at this time, a digital signal is output from the comparator 43. Thereafter, the hold phase T3 and the sample phase T4 are cyclically repeated, and the output voltage Vout changes as shown in FIG.

  In the example shown in FIG. 8, the output voltage Vout is in the range of voltages VREFP4 to VREFP before switching to the first hold phase T3. Therefore, in this hold phase T3, the output voltage Vout is doubled with reference to the voltage VREFP. In FIG. 8, the direction and magnitude of the output voltage Vout from the reference voltage before and after being doubled are indicated by arrows X1 and X2, respectively. A pair of output voltages Vout before and after being doubled is indicated by an arrow Y.

  In the second hold phase T3, the output voltage Vout is in the range of voltages VREFN4 to VREFP4 before switching to the hold phase T3. Therefore, in this hold phase T3, the output voltage Vout is doubled with reference to the voltage (VREFN + VREFP) / 2. In the third hold phase T3, the output voltage Vout is in the range of voltages VREFN to VREFN4 before switching to the hold phase T3. Therefore, in this hold phase T3, the output voltage Vout is doubled with reference to the voltage VREFP. Since the fourth and subsequent times will be repeated, the description will be omitted.

  FIG. 9 is a diagram illustrating an example of input / output characteristics of the comparator 43 when AD conversion is performed with a redundant configuration of 2.5 bits per cycle. By changing the number of bits per cycle from 1.5 bits to 2.5 bits, the number of cycles can be reduced by the increase in the number of bits per cycle. In addition, the AD conversion processing time can be shortened. Here, by setting Cout2 / Cin2 = 3, the following equation (5) is obtained.

Vout (i + 1) = 4 × Vout (i) −3 × Vdac (5)

  Therefore, the output voltage Vout can be amplified four times.

  Here, the voltage VREFN to VREFP is divided by Va to Vf as shown in FIG. The voltages Va to Vf are expressed by the following formulas when the variations are ignored.

Va = (3/16) × (VREFP−VREFN) (6)
Vb = (5/16) × (VREFP−VREFN) (7)
Vc = (7/16) × (VREFP−VREFN) (8)
Vd = (9/16) × (VREFP−VREFN) (9)
Ve = (11/16) × (VREFP−VREFN) (10)
Vf = (13/16) × (VREFP−VREFN) (11)

  The bit output method of 1.5 bits and 2.5 bits is switched depending on the determination criteria (Va, Vb, Vc, Vd, Ve, Vf, etc.) of the comparator 43.

  Next, the operation including the amplifier mode in the ADC 4 will be described. In the present embodiment, in the AD conversion operation in which the reset phase T1, the data input phase T2, the hold phase T3, and the sample phase T4 are cyclically performed, the signal amplification phase T21 is between the data input phase T2 and the hold phase T3. The amplifier mode operation comprising the amplified signal input phase T22 is performed. The operation in the amplifier mode is an operation of amplifying the signal voltage output from the PGA 3 before AD conversion, and this operation enables a burden on the gain (second gain) in the ADC 4. Moreover, since each operation phase functions cyclically, the resolution can be maintained. A series of operations of the ADC 4 is as follows.

  FIG. 10A is a circuit diagram illustrating a connection state of the ADC 4 in the reset phase T1. FIG. 10B is a circuit diagram showing a connection state of the ADC 4 in the data input phase T2. FIG. 10C is a circuit diagram illustrating a connection state of the ADC 4 in the signal amplification phase T21. FIG. 10D is a circuit diagram showing a connection state of the ADC 4 in the amplified signal input phase T22. FIG. 10E is a circuit diagram illustrating a connection state of the ADC 4 during the hold phase T3. FIG. 10F is a circuit diagram illustrating a connection state of the ADC 4 in the sample phase T4.

A series of operations of the ADC 4 in this case is as follows.
(1) The reset phase T1 (see FIG. 10A) is the same as that in FIG. 5A, and the description will be repeated.

(2) The data input phase T2 (see FIG. 10B) is different in the following points from FIG. 5B. The digital signal output from the comparator 43 is not used for the bit string (MSB) after conversion of the output voltage VPGAOUT.

(3) In the signal amplification phase T21 (see FIG. 10C), the switches 44b and 44c in FIG. 4 are turned on and the switches 44a, 44d and 44e are turned off. Further, the output voltage Vdac of the DAC 45 is fixed to the reference voltage VREFP. Thereby, the reference voltage VREFP is applied from the DAC 45 to the electrode of the capacitor 41 (input connection). At this time, the output voltage Vout is amplified by a factor of 2 based on the reference voltage VREFP of the DAC 45, and a gain (second gain) is obtained.

(4) The amplified signal input phase T22 (see FIG. 10D) is substantially the same as FIG. 5D. In this case, the comparator 43 compares the voltage value twice the output voltage Vout in the phase before the amplification signal input phase T22 is switched with a predetermined threshold value (reference voltage corresponding to the full scale of the ADC 4). Output a digital signal. This digital signal is output to a logic circuit and configured as an MSB of a bit string.

(5) The hold phase T3 (see FIG. 10E) operates in the same manner as in FIG. 5C.

(6) The sample phase T4 (see FIG. 10F) operates in the same manner as in FIG. 5D.

  FIG. 11 is a diagram illustrating an example of control timing and input / output states of the ADC 4 including the amplifier mode. FIG. 12 is a diagram illustrating an example of a change in the output voltage Vout. FIGS. 11 and 12 include amplifier modes indicated by a signal amplification phase T21 and an amplification signal input phase T22 after the data input phase T2, as compared with FIGS. 7 and 8, respectively. Furthermore, the input timing of the pulse of the control signal Sf is included.

  As shown in the control signal Sf of FIG. 11, during the signal amplification phase T21, the control circuit 50 inputs a pulse to the DAC 45, thereby fixing the output voltage Vdac of the DAC 45 to the reference voltage VREFP. By this fixing, the signal is amplified, that is, gain (second gain) is obtained, and in the subsequent amplified signal input phase T22, the MSB bit is output as a bit string of DIG data. Except for the signal amplification phase T <b> 21, the control circuit 50 stops inputting pulses to the DAC 45, so that the DAC 45 operates to switch the output voltage Vdac according to the feedback signal from the comparator 43.

  As an example, FIG. 12 shows a change in the output voltage Vout when the signal voltage VPGAOUT is input from the PGA 3 at a level where the signal voltage from the VREFP is halved as shown in the data input phase T2 of FIG. ing. That is, an example in which the gain in the PGA 3 is reduced is shown.

  As shown in FIG. 12, in the data input phase T2, a voltage value based on the half signal voltage VPGAOUT from the PGA 3 appears in the output voltage Vout. In the subsequent signal amplification phase T21, the output voltage Vout is doubled and held based on the output voltage Vdac (here, fixed VREFP) of the DAC 45. That is, the half signal voltage VPGAOUT is amplified by a factor of 2, and the MSB of the bit string is generated at the stage of the subsequent amplified signal input phase T22 as in the data input phase T2 shown in FIG. Subsequent changes in the output voltage Vout based on the operations of the hold phase T3 and the sample phase T4 are the same as those in FIG.

  Thus, by including the amplifier mode, the gain share reduced by PGA 3 can be obtained in ADC 4.

  In the present embodiment, the amplification factor of the output voltage in the ADC 4 can be changed by changing the capacitance ratio of Cout2 / Cin2 and the setting of the output voltage Vdac of the DAC 45. Therefore, it is possible to quadruple the output voltage Vout only in the amplifier mode, and then double it, and it is also possible to double the output voltage Vout only in the amplifier mode and quadruple thereafter. The amplification factor for the output voltage Vout is not limited to 2 or 4. For the amplifier mode, the amplification factor may be a value exceeding 1.

  Further, by repeating the signal amplification phase T21 and the amplification signal input phase T22 not only once but a plurality of times, the output result voltage of the data input phase T2 can be further amplified by the ADC 4.

  Furthermore, since the operation of the signal amplification phase T21 is shorter than the operation of the hold phase T3 of the same operation, the time required for the amplifier mode can be shortened by executing it in a time shorter than the hold phase T3.

  In the above embodiment, the CMOS line sensor 20 is configured. However, the present invention is not limited to this, and a CCD line sensor may be configured.

  As described above, according to the imaging apparatus according to the present embodiment, the gain distribution of the PGA can be reduced, and the reduced gain can be given to the ADC. Further, according to the imaging apparatus according to the present embodiment, the ADC 4 can have a gain by changing the circuit configuration by controlling the connection without changing the circuit configuration of the ADC 4 itself. As a result, the area of the gain share in the PGA can be reduced, and the area occupied by the PGA can be reduced.

1 ... Pixel circuit,
1R, 1G, 1B ... photodiode,
2 ... FPN suppression circuit,
3. Programmable gain amplifier (PGA),
4 ... Analog / digital conversion circuit (ADC),
5. Image signal processing circuit,
6 ... display part,
7: Signal processing circuit,
10 ... substrate,
11 ... column,
20 ... CMOS line sensor,
30 ... operational amplifier,
31, 32 ... capacitors,
40. Operational amplifier,
41, 42 ... capacitors,
43 ... Comparator,
44a-44e ... switch,
45 ... Digital / analog conversion circuit (DAC),
50. Control circuit,
60: Imaging device.

JP 2010-41221 A

Claims (10)

A pixel circuit that outputs a light reception signal;
A programmable gain amplifier for amplifying the received light signal with a first gain;
An analog / digital conversion circuit for amplifying the amplified signal amplified by the programmable gain amplifier with a second gain by changing the circuit configuration under control and converting the digital signal;
A control circuit for controlling the analog / digital conversion circuit;
An imaging device comprising: The analog / digital conversion circuit is a cyclic analog / digital conversion circuit,
The control circuit amplifies the signal sampled by the analog / digital conversion circuit based on the amplified signal of the programmable gain amplifier with the second gain by changing the circuit configuration of the analog / digital conversion circuit under control. Let
The imaging apparatus according to claim 1. The analog / digital conversion circuit is:
A comparator that converts a signal voltage Vout (i) sampled based on the amplified signal into a digital signal;
A digital / analog conversion circuit that feeds back the digital signal output from the comparator and outputs an analog signal voltage Vdac;
A circuit configuration in which, when the output of the digital / analog conversion circuit is input-connected, a signal satisfying the amplified signal voltage Vout (i + 1) = 2 × Vout (i) −Vdac is output to the comparator;
Have
The control circuit fixes the analog signal voltage Vdac of the digital / analog conversion circuit to a constant value, and connects the output of the analog / digital conversion circuit by control.
The imaging apparatus according to claim 2. The control circuit includes:
A signal satisfying Vout (i + 1) = 2 × Vout (i) −Vdac by repeating the control of the input connection a plurality of times in a state where the fixation of the analog signal voltage Vdac to the digital / analog conversion circuit is released. The voltage Vout (i + 1) is repeatedly output.
The imaging apparatus according to claim 3. The programmable gain amplifier is a capacitively coupled programmable gain amplifier capable of offset correction.
The imaging apparatus according to any one of claims 1 to 4, wherein the imaging apparatus is characterized in that: The input voltage range of the analog / digital conversion circuit is set based on a reference voltage of the programmable gain amplifier.
The imaging apparatus according to any one of claims 1 to 4, wherein the imaging apparatus is characterized in that: The analog / digital conversion circuit performs 1.5-bit analog / digital conversion per cycle.
The imaging apparatus according to any one of claims 1 to 4, wherein the imaging apparatus is characterized in that: The analog / digital conversion circuit performs 2.5-bit analog / digital conversion per cycle.
The imaging apparatus according to any one of claims 1 to 4, wherein the imaging apparatus is characterized in that: The bit output method per cycle in the analog / digital conversion of the analog / digital conversion circuit is based on the setting of the determination criterion of the comparator.
The imaging apparatus according to claim 3 or 4, wherein   The image pickup apparatus according to any one of claims 1 to 9, wherein the image pickup apparatus is a CMOS line sensor.

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