JP2011091724A - Solid state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow a post-stage circuit to perform suitable signal processing by appropriately inputting a signal to the post-stage circuit even in the case where the post-stage circuit of an amplification circuit for amplifying a signal from a pixel or a signal corresponding thereto is configured to operate with a power supply voltage lower than a power supply voltage of a pixel part. <P>SOLUTION: A solid state imaging device 1 includes: a pixel 11 for performing photoelectric conversion on incident light; and an amplification circuit 16 to which a signal from the pixel 11 or a signal corresponding thereto is input, and which has a function for amplifying the input signal with a gain whose absolute value is smaller than 1. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device.

  Patent Document 1 below discloses a solid-state imaging device having an amplifier circuit (a so-called column amplifier) that amplifies a signal from a pixel for each column of a pixel array. The gain of the amplifier circuit is variable. In such a conventional solid-state imaging device, the gain of the amplifier circuit is set to be larger than 1.

  Further, Patent Document 2 below discloses a solid-state imaging device that is increased in speed by having an analog-digital converter (so-called column ADC) for each column of a pixel array.

  In order to further increase the S / N ratio of the solid-state imaging device, it is most effective to increase the photoelectric conversion efficiency and the electronic voltage conversion efficiency of the pixel to increase the signal amplitude from the pixel. In addition, the gain of the amplification circuit is made variable so that the gain is low when setting low sensitivity and high when setting high sensitivity, thereby expanding the dynamic range when low sensitivity and high S / N when sensitivity is high. I am trying.

JP 2008-34974 A Japanese Patent Laying-Open No. 2005-303648

  In the amplifier circuit as described above, it has been found that following the technical common sense that the gain is 1 or more may cause inconvenience as follows.

  By the way, it has been found that it is preferable to configure the subsequent circuit of the amplifier circuit to operate with a power supply voltage lower than the power supply voltage of the pixel portion. For example, when a column ADC is employed as a circuit subsequent to the amplifier circuit, it is preferable that the column ADC be operated at a power supply voltage lower than the power supply voltage of the pixel portion because the column ADC can be operated at high speed. However, in this case, the voltage amplitude that can be input to a subsequent circuit such as a column ADC is smaller than the voltage amplitude that can be output from the pixel portion having a high output amplitude. Therefore, if the gain of the amplifier circuit is set to be larger than 1, it becomes impossible to properly input a signal to a subsequent circuit such as a column ADC, and appropriate signal processing cannot be performed in the subsequent circuit. .

  The present invention has been made in view of such circumstances, and a circuit subsequent to an amplifier circuit that amplifies a signal from a pixel or a signal corresponding thereto operates with a power supply voltage lower than the power supply voltage of the pixel portion. An object of the present invention is to provide a solid-state imaging device that can appropriately input a signal to a subsequent circuit and allow the subsequent circuit to perform appropriate signal processing.

  The following aspects are presented as means for solving the problems. The solid-state imaging device according to the first aspect includes a pixel that photoelectrically converts incident light, a signal from the pixel, or a signal corresponding thereto, and a function of amplifying the absolute value with a gain smaller than 1. And. In the first aspect, a vertical signal line to which a signal output from the pixel is supplied is provided corresponding to each column of the plurality of pixels, and the amplifier circuit is provided corresponding to each column. Also good.

  In the solid-state imaging device according to the second aspect, in the first aspect, the gain of the amplifier circuit is a ratio of a change in the output signal of the amplifier circuit to a change in the input signal of the amplifier circuit. .

In the solid-state imaging device according to the third aspect, in the first or second aspect, the gain of the amplifier circuit is variable to a plurality of different gains, and the plurality of gains has an absolute value smaller than 1. In addition to the gain, one or more gains having an absolute value of 1 or more are included, n is an integer from 0 to m (m is an integer of 1 or more), and A is a predetermined gain whose absolute value is smaller than 1. The plurality of gains include (m + 1) gains represented by 2 ⁿ * A. In the first and second aspects, the gain of the amplifier circuit is variable to a plurality of different gains, and the plurality of gains has an absolute value of 1 in addition to a gain whose absolute value is smaller than 1. In the case where one or more of the above gains are included, the plurality of gains do not necessarily include (m + 1) gains represented by 2 ⁿ * A.

  In the solid-state imaging device according to the fourth aspect, in any one of the first to third aspects, the amplification circuit applies a signal input from the pixel or a signal input unit corresponding thereto and a first predetermined potential. The first and second voltage dividing capacitors connected in series in that order from the input section side, and the first input terminal and the second predetermined potential applied to the second predetermined potential at least temporarily An operational amplifier having an input terminal, an input capacitor connected at least temporarily between the first node between the first and second voltage dividing capacitors and the first input terminal, and the calculation A first that temporarily short-circuits between the output terminal of the amplifier and the first input terminal and temporarily forms a predetermined capacitance value between the output terminal of the operational amplifier and the first input terminal. And a feedback circuit.

  A solid-state imaging device according to a fifth aspect includes, in the fourth aspect, a switch connected between the first node and the first input terminal.

  A solid-state imaging device according to a sixth aspect includes, in the fourth aspect, first to fourth capacitors and first to fifth switches, wherein the first switch and the first capacitor are the input unit. From the side, the input unit and the first node are connected in series in that order, the second switch is connected between the input unit and the first node, and the third switch is A second node between the first switch and the first capacitor is connected between the first input terminal, and the third capacitor and the fourth switch are connected to the first node. The fifth switch is connected in series between the first node and the part in that order from the side, and the fifth switch is connected to the third node between the third capacitor and the fourth switch. And the second capacitor is connected to the first node and the front terminal. Connected to a first input terminal, the fourth capacitor is a capacitor between the first node and the part, the first voltage dividing capacitor is composed of the first capacitor, The second voltage dividing capacitor is composed of the fourth capacitor or a parallel combined capacitor of the third capacitor and the fourth capacitor, and the input capacitor is composed of the second capacitor or the It consists of a parallel combined capacity of a second capacity and the third capacity.

  The solid-state imaging device according to a seventh aspect is the second feedback circuit according to the fourth aspect, wherein the amplifier circuit at least temporarily forms a predetermined capacitance value between the output terminal and the first node. It is what has.

  In the solid-state imaging device according to the eighth aspect, in the seventh aspect, at least a part of the capacitance constituting the second feedback circuit is also used as at least a part of the capacitance constituting the first feedback circuit. It is a thing.

  A solid-state imaging device according to a ninth aspect includes the first to fifth capacitors and the first to seventh switches in the seventh or eighth aspect, wherein the first capacitor includes the input unit and the first capacitor. The first switch and the second capacitor are connected in series between the first node and the first input terminal in that order from the first node side. The second switch is connected between a second node between the first switch and the second capacitor and the input unit, and the seventh switch and the third capacitor are The third node is connected in series between the first node and the part, the third switch is connected between the first node and the first input terminal, and the first feedback circuit is connected to the fourth node. And a fifth capacitor and the fifth and sixth switches, and the fifth switch. H and the fourth capacitor are connected in series between the first input terminal and the output terminal in that order from the first input terminal side, and the sixth switch and the fifth capacitor are 1 is connected in series between the input terminal and the output terminal, and the fourth switch is between the third node and the first node between the fifth switch and the fourth capacitor. The first voltage dividing capacitor comprises the first capacitor, the second voltage dividing capacitor comprises the third capacitor, the input capacitor comprises the second capacitor, and the first capacitor. The second feedback circuit includes the fourth capacitor and the fourth switch.

  In the ninth aspect, the capacitance value of the first capacitor and the capacitance value of the second capacitor may be equal, and the capacitance value of the fourth capacitor and the capacitance value of the fifth capacitor may be equal. .

  In the solid-state imaging device according to the tenth aspect, in the first or second aspect, the amplifier circuit includes an operational amplifier having a first input terminal and a second input terminal to which a predetermined potential is applied. An input capacitance circuit connected between an input unit of a signal from the pixel or a signal corresponding thereto and the first input terminal and configured to change a capacitance value to a plurality of different values; A feedback circuit that temporarily short-circuits between the output terminal of the amplifier and the first input terminal and temporarily forms a predetermined capacitance value between the output terminal of the operational amplifier and the first input terminal. And.

  A solid-state imaging device according to an eleventh aspect includes a pixel that photoelectrically converts incident light, and an amplifier circuit that receives a signal from the pixel or a signal corresponding thereto. The amplifier circuit includes an operational amplifier having a first input terminal and a second input terminal to which a predetermined potential is applied, an input unit for a signal from the pixel or a signal corresponding thereto, and the first input terminal And an input capacitance circuit configured to change the capacitance value to a plurality of different values, and temporarily shorting between the output terminal of the operational amplifier and the first input terminal A feedback circuit that temporarily forms a predetermined capacitance value between the output terminal of the operational amplifier and the first input terminal.

  A solid-state imaging device according to a twelfth aspect is the solid-state imaging device according to the tenth or eleventh aspect, wherein the input capacitance circuit has a plurality of capacitors and one or more switches, and the plurality of capacitors and the one or more switches are The capacitance value of the input capacitance circuit is connected so that it can change to the plurality of different values depending on the on / off state of the one or more switches.

  According to the present invention, even if the subsequent circuit of the amplification circuit that amplifies the signal from the pixel or the signal corresponding thereto is configured to operate with a power supply voltage lower than the power supply voltage of the pixel unit, It is possible to provide a solid-state imaging device that can appropriately input a signal to a circuit and cause a subsequent circuit to perform appropriate signal processing.

1 is a circuit diagram showing a solid-state imaging device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing one amplifier circuit in FIG. 1. It is a circuit diagram which shows the amplifier circuit in the 2nd Embodiment of this invention. It is a circuit diagram which shows the amplifier circuit in the 3rd Embodiment of this invention. FIG. 5 is a diagram showing an operation state and gain in each mode of the amplifier circuit shown in FIG. 4. It is a circuit diagram which shows the amplifier circuit in the 4th Embodiment of this invention. It is a figure which shows the operation state and gain of each mode of the amplifier circuit shown in FIG. FIG. 7 is a diagram illustrating a design example of operation states and gains in respective modes of the amplifier circuit illustrated in FIG. 6. It is a circuit diagram which shows the solid-state image sensor by the 5th Embodiment of this invention. FIG. 10 is a circuit diagram showing one amplifier circuit in FIG. 9. 10 is a timing chart illustrating an example of a reading operation of the solid-state imaging device illustrated in FIG. 9. It is a circuit diagram which shows the amplifier circuit in the 6th Embodiment of this invention.

  Hereinafter, a solid-state imaging device according to the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a circuit diagram showing a solid-state imaging device 1 according to the first embodiment of the present invention. The solid-state imaging device 1 according to this embodiment includes a plurality of pixels 11 arranged in a two-dimensional manner, a vertical scanning circuit 12, a horizontal scanning circuit 13, and a corresponding column provided corresponding to each column of pixels 11. A vertical signal line 14 to which an output signal of the pixel 11 is supplied, a constant current source 15 connected to each vertical signal line 14, and a signal on the vertical signal line 14 provided corresponding to each vertical signal line 14 is input voltage. The amplifier circuit 16 receives the output voltage Vout as Vin, the AD converter 20 converts the output voltage Vout of each amplifier circuit 16 from analog to digital, and a horizontal output bus line 21. In FIG. 1, Vdd is the power supply potential of the pixel portion.

  Each pixel 11 outputs a signal corresponding to the photodiode PD as a photoelectric conversion unit, the floating diffusion FD as a charge-voltage conversion unit, and the potential of the floating diffusion FD, as in a general CMOS solid-state imaging device. An amplifying transistor AMP as an amplifying unit, a transfer transistor TX as a charge transferring unit that transfers charges from the photodiode PD to the floating diffusion FD, a reset transistor RES as a resetting unit that resets the potential of the floating diffusion FD, and the pixel 11 and a selection transistor SEL as a selection unit for selecting 11.

  The gates of the transfer transistor TX, the reset transistor RES, and the selection transistor SEL are connected in common to the pixels 11 arranged in the row direction, and drive signals φTX, φRES, and φSEL are supplied from the vertical scanning circuit 12 for each row. .

  FIG. 2 is a circuit diagram showing one amplifier circuit 16 in FIG. Each amplifier circuit 16 includes an input capacitor Ci, an operational amplifier OP, a feedback capacitor Cf, and a clamp control switch Sf that is turned on / off in response to a clamp control signal. The vertical signal line 14 is an input part of the amplifier circuit 16, and the output terminal of the operational amplifier OP is an output part of the amplifier circuit 16. The operational amplifier OP is configured using a differential amplifier circuit or the like. Vref in FIG. 2 is a constant potential. In the following description, the capacitance value of the input capacitance Ci is also denoted by the same reference symbol Ci. This also applies to the feedback capacitor Cf and each capacitor described later.

  The amplification circuit 16 is reset (amplifier reset) by turning on the switch Sf. As a result, the output terminal of the operational amplifier OP is clamped to the predetermined potential Vref. In the subsequent amplification operation, when the input voltage Vin changes by ΔVin from the voltage at the time of resetting the amplifier with the switch Sf turned off, if the output voltage Vout changes from the potential Vref by ΔVout, then Vout−Vref = ΔVout = − (Ci / Cf) * ΔVin. Here, ΔVin = Vsig−Vdark. Vdark is a so-called dark signal obtained on the vertical signal line 14 in accordance with the reset transistor of the pixel 11 being turned on at the time of amplifier reset. Vsig is a so-called optical signal obtained on the vertical signal line 14 when the signal from the photodiode PD is transferred to the floating diffusion FD after the amplifier reset. The point of ΔVin = Vsig−Vdark is the same for each embodiment described later.

  Therefore, the gain (ΔVout / ΔVin) of the amplifier circuit 16 is − (Ci / Cf). In the present embodiment, the absolute value of this gain is set smaller than 1. That is, (Ci / Cf) <1 is set. Thus, in the present embodiment, the amplifier circuit 16 has a function of amplifying with a gain whose absolute value is smaller than 1.

  Each AD converter 20 converts the output voltage Vout of the corresponding amplifier circuit 16 from analog to digital. As a specific configuration of the AD converter 20, various known configurations can be employed. Although not shown in the drawing, for example, each AD converter 20 includes a comparison unit that compares the ramp signal with an input (here, the output voltage Vout of the amplifier circuit 16), and an elapsed time from the start of the ramp signal. And a latch unit that latches the counter value of the counter that obtains the count value according to the comparison result by the comparison unit. At this time, a ramp signal generator and the like are provided in common to each AD converter 20.

  In the present embodiment, each AD converter 20 is configured to operate at a power supply voltage lower than the power supply voltage Vd of the pixel portion in order to advance the miniaturization and operate the AD converter 20 at high speed. Yes. Thereby, the voltage amplitude that can be input to the AD converter 20 is smaller than the voltage amplitude that can be output from the pixel 11 to the vertical signal line 14.

  The horizontal scanning circuit 13 outputs a horizontal scanning signal φH for each column and supplies the signal to each AD converter 20. As a result, the digital signals converted by the AD converters 20 are sequentially output to the horizontal output bus line 21 having a predetermined number of bits and output to the outside through the horizontal output bus line 21.

  According to the present embodiment, the amplifier circuit 16 has a function of amplifying with a gain whose absolute value is smaller than 1. Therefore, the voltage amplitude that can be received by the AD converter 20 that is a circuit subsequent to the amplifier circuit 16 is as follows. Even in the case where a large voltage level is output from the pixel 11 that is smaller than the voltage amplitude that can be output from the pixel 11, signal transmission to the AD converter 20 can be performed appropriately.

  In the present invention, a signal processing unit such as a buffer is interposed between the vertical signal line 14 and the input unit of the amplifier circuit 16, and the signal (from the pixel 11) of the vertical signal line 14 is input to the input unit of the amplifier circuit 16. A signal corresponding to the signal (1) may be input. This also applies to each embodiment described later.

[Second Embodiment]
In the first embodiment, since (Ci / Cf) <1 is set, the signal feedback amount of the operational amplifier OP is large, the phase margin of the amplifier is small, and it tends to be unstable. Therefore, the worst oscillation may occur depending on the design of the operational amplifier OP. Therefore, in the amplifier circuit 16, it is relatively difficult to design the operational amplifier OP in order to stabilize it. This inconvenience is solved in the second embodiment of the present invention.

  FIG. 3 is a circuit diagram showing an amplifier circuit 26 used in the solid-state imaging device according to the second embodiment of the present invention. The present embodiment is different from the first embodiment only in that each amplifier circuit 16 is replaced with an amplifier circuit 26.

  The amplifying circuit 26 includes a first component connected in series between the input unit to which the input voltage Vin is supplied and the part X to which the first predetermined potential is applied, in that order from the input unit side. It has a pressure capacity C1 and a second voltage dividing capacity Ca. In the present embodiment, the first predetermined potential is a ground potential, and a portion to which the first predetermined voltage is applied is a ground portion. However, the first predetermined potential is not necessarily limited to the ground potential. In the present embodiment, the first and second voltage dividing capacitors C1 and Ca are connected in series between the input unit and the ground unit.

  The amplifier circuit 26 includes an operational amplifier OP having a −input terminal and a + input terminal to which a second predetermined potential Vref is applied, a first node N1 between the voltage dividing capacitors C1 and Ca, and the operational amplifier OP. The input capacitor C2 connected at least temporarily between the input terminal and the output terminal of the operational amplifier OP and the input terminal are temporarily short-circuited, and the output terminal and the input terminal of the operational amplifier OP; And a first feedback circuit that temporarily forms a predetermined capacitance value. In the present embodiment, the input capacitor C2 is connected between the node N1 and the negative input terminal. In the present embodiment, the first feedback circuit includes a switch Sf and a capacitor Cf connected in parallel between the output terminal and the negative input terminal of the operational amplifier OP.

  Furthermore, the amplifier circuit 26 has a switch Sr connected between the node N1 and the negative input terminal of the operational amplifier OP. The switch Sr is connected in parallel with the input capacitor C2.

  The amplifier circuit 26 is reset (amplifier reset) by turning on both the switches Sr and Sf. During the subsequent amplification operation, when the input voltage Vin changes by ΔVin from the voltage at the time of amplifier reset with the switches Sr and Sf turned off, the voltage Va at the node N1 changes by ΔVa and the output voltage Vout changes from the potential Vref. It is assumed that it changes by ΔVout. Then, ΔVa is expressed by the following formula 1, and ΔVout is expressed by the following formula 2. By substituting Equation 1 into Equation 2, Equation 3 is obtained.

ΔVa = (C1 / (C1 + C2 + Ca)) * ΔVin Equation 1
ΔVout = − (C2 / Cf) * ΔVa Equation 2
ΔVout = − [(C1 * C2) / {Cf * (C1 + C2 + Ca)}] * ΔVin Equation 3
Therefore, the gain (ΔVout / ΔVin) of the amplifier circuit 26 is − [(C1 * C2) / {Cf * (C1 + C2 + Ca)}]. Here, C1 / (C1 + C2 + Ca) is always smaller than 1. Therefore, it is easy to set the signal feedback amount of the operational amplifier OP to be small by increasing the absolute value of (−C2 / Cf) to 1 or more while making the absolute value of the gain (ΔVout / ΔVin) smaller than 1. In this embodiment, it is set as such.

  In the present embodiment, the amplifier circuit 26 has a function of amplifying with a gain (ΔVout / ΔVin) whose absolute value is smaller than 1. Therefore, the same advantage as the first embodiment can be obtained. Moreover, in the present embodiment, since the absolute value of (−C2 / Cf) is increased to 1 or more to reduce the signal feedback amount of the operational amplifier OP, the operational amplifier for stabilizing the amplifier circuit 26 is obtained. The circuit design of the OP is simplified.

  Note that the switches Sr and Sf included in the amplifier circuit 26 are composed of transistors, for example, and the on / off states of the switches Sr and Sf can be controlled by supplying a control signal to the gates. This also applies to each switch included in an amplifier circuit according to each embodiment described later.

[Third Embodiment]
FIG. 4 is a circuit diagram showing an amplifier circuit 36 used in the solid-state imaging device according to the third embodiment of the present invention. The present embodiment is different from the second embodiment only in that each amplifier circuit 26 is replaced with an amplifier circuit 36. The amplifier circuit 36 is obtained by modifying the amplifier circuit 26 so as to have the configuration described below.

  The amplifier circuit 36 includes a first capacitor C1, a second capacitor C2, a third capacitor Ca, a fourth capacitor Cb, first to fifth switches S1 to S5, a negative input terminal, and a first input terminal. An operational amplifier OP having a + input terminal to which a predetermined potential Vref of 2 is applied, and the output terminal and − input terminal of the operational amplifier OP are temporarily short-circuited, and the output terminal and − input of the operational amplifier OP And a first feedback circuit that temporarily forms a predetermined capacitance value with the terminal. The vertical signal line 14 is an input part of the amplifier circuit 36, and the output terminal of the operational amplifier OP is an output part of the amplifier circuit 36.

  The first switch S1 and the first capacitor C1 are connected in series between the input unit and the first node N1 in that order from the input unit side. The second switch S2 is connected between the input unit and the first node N1. The fourth capacitor Cb is a parasitic capacitance that exists between the first node N1 and the ground part (a ground part as a part to which the ground potential as the first predetermined voltage is applied). The third switch S3 is connected between the second node N2 between the first switch S1 and the first capacitor C1 and the negative input terminal of the operational amplifier OP. The third capacitor Ca and the fourth switch S4 are connected in series between the first node N1 and the ground portion in that order from the first node N1 side. The fifth switch S5 is connected between the third node N3 between the third capacitor Ca and the fourth switch S4 and the negative input terminal of the operational amplifier OP. The second capacitor C2 is connected between the first node N1 and the negative input terminal of the operational amplifier OP.

  The first capacitor C1 constitutes a first voltage dividing capacitor that is temporarily connected between the input unit and the first node N1 by the switch S1. The fourth capacitor Cb constitutes a second voltage dividing capacitor that is temporarily connected between the first node N1 and the ground portion when the fourth switch S4 is turned off. Further, the parallel combined capacitance of the third capacitor Ca and the fourth capacitor Cb is that the fourth switch S4 is turned on and the fifth switch S5 is turned off, so that the first node N1 and the ground portion are connected. The second voltage dividing capacity is temporarily connected to the second voltage dividing capacity. Therefore, similarly to the amplifier circuit 26, the amplifier circuit 36 also includes the first voltage dividing capacitor and the first voltage dividing capacitor connected in series in that order from the input unit side between the input unit and the ground unit. The second voltage dividing capacity is provided.

  The second capacitor C2 constitutes an input capacitor that is temporarily connected between the first node N1 and the negative input terminal of the operational amplifier OP when the switch S5 is turned off. The parallel combined capacitor of the second capacitor C2 and the third capacitor Ca is temporarily connected between the first node N1 and the negative input terminal of the operational amplifier OP when the switch S5 is turned on. Configure the input capacity. Therefore, similarly to the amplifier circuit 26, the amplifier circuit 36 also has an input capacitor connected at least temporarily between the first node N1 and the negative input terminal of the operational amplifier OP.

  In the amplifier circuit 36, the first feedback circuit is composed of a switch Sf and k series circuits connected in parallel between the output terminal and the negative input terminal of the operational amplifier OP. Each series circuit is a series circuit including a switch S7-k and a capacitor Cf-k, where k is an integer from 1 to i (i is an integer of 2 or more). The capacitance value of the first feedback circuit is a variable capacitance value according to the on / off states of the switches S7-1 to S7-i when the switch Sf is off. In the following description and Table 5, the capacitance value of the first feedback circuit determined according to the on / off states of the switches S7-1 to S7-i is Cf.

  FIG. 5 shows the on / off states of the switches S1 to S5, S7-1 to S7-i, and Sf at the time of amplifier reset for each of the four modes (1) to (4) in which the amplifier circuit 36 can operate, The on / off states of the switches S1 to S5, S7-1 to S7-i, and Sf during the amplification operation and the gain ΔVout / ΔVin obtained are shown.

  In the amplifier circuit 36, the gain from the lowest absolute value of the mode (1) to the gain of the highest absolute value of the mode (4) can be obtained in order from the mode (1) to the mode (4) by setting each switch. it can. The state of mode (1) is substantially the same as that of the amplifier circuit 26. Therefore, in the mode (1) of the amplifier circuit 36, the absolute value of the gain (ΔVout / ΔVin) is made smaller than 1, and the absolute value of (−C2 / Cf) is made larger than 1, and the signal of the operational amplifier OP It is easy to set the feedback amount small, and in this embodiment, it is set as such.

  In the present embodiment, the absolute value of the gain (ΔVout / ΔVin) is set to be larger than 1 in the mode (4) of the amplifier circuit 36. It can be understood from FIG. 5 that such setting can be easily performed.

  As described above, according to the present embodiment, the same advantages as those of the second embodiment can be obtained, and in addition to a gain whose absolute value is smaller than 1, a gain whose absolute value is 1 or more is obtained. be able to. Therefore, for example, by increasing the gain when setting the low sensitivity and increasing the gain when setting the high sensitivity, it is possible to increase the dynamic range when the sensitivity is low and to increase the S / N ratio when the sensitivity is high.

[Fourth Embodiment]
In the amplifier circuit 36 used in the third embodiment, various advantages can be obtained as described above. However, the gain setting is complicated, and when the mode is changed and the gain is changed, each gain is changed. It is cumbersome and difficult to design the gain to a predetermined value while relating them.

  As a result of research, the inventor has found that a second capacitance value is formed at least temporarily between the output terminal of the operational amplifier OP and the first node N1 in a circuit such as the amplifier circuit 36 described above. It has been found that the circuit design related to the gain value can be simplified by providing the feedback circuit. The fourth embodiment of the present invention is based on such knowledge.

  FIG. 6 is a circuit diagram showing an amplifying circuit 46 used in the solid-state imaging device by the solid-state imaging device according to the fourth embodiment of the present invention. This embodiment is different from the third embodiment only in that each amplifier circuit 36 is replaced by an amplifier circuit 46.

  The amplifier circuit 46 includes a first capacitor C1, a second capacitor C2, a third capacitor Ca, a fourth capacitor Cf2, a fifth capacitor Cf1, and first to seventh switches S1 to S7. An operational amplifier OP having a negative input terminal and a positive input terminal to which a second predetermined potential Vref is applied, and a short circuit between the output terminal and the negative input terminal of the operational amplifier OP and the operational amplifier A first feedback circuit that temporarily forms a predetermined capacitance value between an output terminal of the OP and a negative input terminal; and a predetermined capacitance value that is at least temporarily formed between the output terminal and the first node. And a second feedback circuit. In the present embodiment, at least a part of the capacitors constituting the second feedback circuit is also used as at least a part of the capacitors constituting the first feedback circuit. The vertical signal line 14 is an input part of the amplifier circuit 46, and the output terminal of the operational amplifier OP is an output part of the amplifier circuit 46.

  The first capacitor C1 is connected between the input unit and the first node N1. The first switch S1 and the second capacitor C2 are connected in series between the first node N1 and the negative input terminal of the operational amplifier OP in that order from the first node N1 side. The second switch S2 is connected between the second node N2 between the first switch S1 and the second capacitor C2 and the input unit. The seventh switch S7 and the third capacitor Ca are connected in series between the first node N1 and the ground part (a ground part as a part to which the ground potential as the first predetermined voltage is applied). . The third switch S3 is connected between the first node N1 and the negative input terminal of the operational amplifier OP.

  The first feedback circuit includes a fourth capacitor Cf2, a fifth capacitor Cf1, fifth and sixth switches S5 and S6, and a switch Sf. The fifth switch S5 and the fourth capacitor Cf2 are connected in series between the first input terminal and the output terminal of the operational amplifier OP in that order from the negative input terminal side of the operational amplifier OP. The sixth switch S6 and the fifth capacitor Cf1 are connected in series between the negative input terminal and the output terminal of the operational amplifier OP. The switch Sf is connected in series between the negative input terminal and the output terminal of the operational amplifier OP.

The fourth switch S4 is connected between the third node N3 and the first node N1 between the fifth switch S and the fourth capacitor Cf2. The second feedback circuit includes a fourth capacitor Cf2 and a fourth switch S4. The fourth capacitor Cf2 is also used as the first and second feedback circuits. However, without using both, for example, the fourth switch S4 is connected between the first node N1 and the output terminal of the operational amplifier OP without connecting the fourth switch S4 to the third node N3. And a series circuit of a capacitor dedicated to the second feedback circuit may be connected.
The first capacitor C1 constitutes a first voltage dividing capacitor connected between the input unit and the first node N1. The third capacitor Ca constitutes a second voltage dividing capacitor that is temporarily connected between the first node N1 and the ground by the switch S7. The second capacitor C2 constitutes an input capacitor that is temporarily connected by the switch S1 between the first node N1 and the negative input terminal of the operational amplifier OP.

  FIG. 7 shows the on / off states of the switches S1 to S7 and Sf at the time of amplifier reset and the switches S1 to S1 at the subsequent amplification operation for each of the five modes (1) to (5) in which the amplifier circuit 46 can operate. The on / off states of S7 and Sf and the obtained gain ΔVout / ΔVin are shown.

  In the amplifier circuit 46, the gain from the lowest absolute value of the mode (1) to the gain of the highest absolute value of the mode (5) can be obtained in order from the mode (1) to the mode (5) by setting each switch. it can. The state of mode (1) is substantially the same as that of the amplifier circuit 26. Therefore, in the mode (1) of the amplifier circuit 36, the absolute value of the gain (ΔVout / ΔVin) is made smaller than 1, and the absolute value of (−C2 / Cf) is made larger than 1, and the signal of the operational amplifier OP It is easy to set the feedback amount small, and in this embodiment, it is set as such. Here, Cf is a parallel combined capacitance of the fourth and fifth capacitors Cf2 and Cf1.

  In mode (2), the absolute value of the gain (ΔVout / ΔVin) can be made smaller than 1 as shown in a design example (FIG. 8) described later. In mode (2), the closed loop gain of the feedback loop of the operational amplifier OP is (−C2 / Cf1) * {Cf2 / (C1 + C2 + Ca)}. If this closed loop gain is smaller than 1, the circuit design of the operational amplifier OP for preventing the oscillation and stabilizing the amplifier circuit 46 becomes simple. As shown in a design example described later, this closed loop gain can be made smaller than one. In the present embodiment, in the mode (2), the absolute value of the gain (ΔVout / ΔVin) is set smaller than 1, and the closed loop gain is set smaller than 1.

  In the present embodiment, as shown in a design example described later, the absolute value of the gain (ΔVout / ΔVin) is set to be larger than 1 in the modes (3) to (5) of the amplifier circuit 46. It can be understood from the design example described later that such setting can be easily performed.

  According to the present embodiment, the same advantages as those of the third embodiment described above can be obtained, and the gain of the amplifier circuit 46 can be designed with a simple expression, so that the circuit design relating to the gain value can be simplified. Become. This point will be clarified by explaining the following specific design example.

  In this design example, in the amplifier circuit 46 shown in FIG. 6, the design values of a and b are obtained with C1 = C2 = C0, Cf1 = Cf2 = a * C0, and Ca = b * C0.

  At this time, the gain of the mode (3) shown in FIG. 7 is −1 / (2 * a). It is assumed that the minimum gain Gmin (however, absolute value) determined from the signal amplitude of the output of the pixel 11 (signal of the vertical signal line 14) and the input range of the AD converter 20 is given. At this time, the gain of the mode (3) shown in FIG. 7 is set to −2 * Gmin. Therefore, -1 / (2 * a) =-2 * Gmin is established. Therefore, a = 1 / (4 * Gmin).

  Incidentally, in the mode (3) shown in FIG. 7, the state is substantially the same as that of the amplifier circuit 16 shown in FIG. Accordingly, in order to simplify the circuit design of the operational amplifier OP for reducing the signal feedback amount of the operational amplifier OP and stabilizing the amplifier circuit 46 in the mode (3) in the mode (3) shown in FIG. Needs to have an absolute value of 1 or more. For this reason, since the gain of the mode (3) shown in FIG. 7 is set to −2 * Gmin, it is necessary that Gmin ≧ 0.5. Further, as described above, since the gain in the mode (3) shown in FIG. 7 is −1 / (2 * a), it is necessary to satisfy a ≦ 0.5. Of course, 0 <a must be satisfied. Therefore, it is necessary that 0 <a ≦ 0.5. From the above, after all, Gmin ≧ 0.5 is the applicable range.

When C1 = C2 = C0, Cf1 = Cf2 = a * C0, and Ca = b * C0 are substituted for the gain of mode (2) shown in FIG. 7, the gain of mode (2) shown in FIG. (A ² + 3 * a + a * b). Now, it is assumed that the gain of the mode (2) shown in FIG. 7 is set to -Gmin. Here, since the absolute value of the gain in the mode (2) shown in FIG. 7 is smaller than 1, Gmin <1. As described above, since a = 1 / (4 * Gmin), −Gmin = −1 / (4 * a). Therefore, −1 / (a ² + 3 * a + a * b) = − 1 / (4 * a) is established. If this is solved for b, then b = 1−a. Substituting the above-mentioned a = 1 / (4 * Gmin) into this equation results in b = 1- {1 / (4 * Gmin)}. The gain of mode (2) shown in FIG. 7 includes Ca. The design value of Ca is used by estimating the amount of stray capacitance (parasitic capacitance) and subtracting that amount.

  As described above, the gain in mode (3) shown in FIG. 7 is set to −2 * Gmin, and the gain in mode (2) shown in FIG. 7 is set to −Gmin. Then, the gains of the modes (1), (4), and (5) shown in FIG. 7 are added to C1 = C2 = C0, Cf1 = Cf2 = a * C0, Ca = b * C0, and a, When b is substituted, these gains are as shown in FIG.

To summarize the above results, the gains of modes (1) to (5) shown in FIG. 7 are as shown in FIG. Modes (1) to (5) in FIG. 8 are the same as modes (1) to (5) in FIG. In the circuit shown in FIG. 6, at the time of design, Gmin is set from the signal amplitude of the output of the pixel 11 and the input range of the AD converter 20 under the condition of 0.5 ≦ Gmin <1, and C1 = C2 = C0, Cf1 = When Cf2 = a * C0 and Ca = b * C0 are set, and a = 1 / (4 * Gmin) and b = 1− {1 / (4 * Gmin)}, the mode (2) in FIG. It can be seen that -Gmin, -2 * Gmin, -4Gmin, and -8Gmin are obtained as gains (5) to (5). The absolute value of -Gmin is smaller than 1, and the absolute value of -2 * Gmin, the absolute value of -4Gmin, and the absolute value of -8Gmin are larger than 1. These four gains are -Gmin = A and n is an integer from 0 to m (here, m = 3), and (m + 1) gains represented by 2 ⁿ * A It has become. Such a gain of 2 times is very convenient when setting the sensitivity in the solid-state imaging device. In this case, the gain in the mode (1) in FIG. 8 is not necessarily used because it is not in a double relationship.

  As described above, in the mode (2) in FIGS. 7 and 8, the closed loop gain of the feedback loop of the operational amplifier OP is (−C2 / Cf1) * {Cf2 / (C1 + C2 + Ca)}. Substituting C1 = C2 = C0, Cf1 = Cf2 = a * C0, Ca = b * C0, and a and b obtained previously into this closed loop gain, this closed loop gain is obtained, and 0.5 ≦ Gmin <1 Therefore, the closed loop gain is smaller than 1. In mode (2) in FIGS. 7 and 8, the circuit design of the operational amplifier OP for preventing oscillation and stabilizing the amplifier circuit 46 is simplified.

  In order to obtain a gain larger than the gain in FIG. 8, for example, the capacitance Cf1 is divided according to a normal variable capacitance technique in the feedback circuit, and Cf1 = a * C0 * (1/2 + 1/4 + 1/8 + 1/8). ), Cf1 / 2, Cf1 / 4, etc. may be used.

[Fifth Embodiment]
FIG. 9 is a circuit diagram showing a solid-state imaging device 101 according to the fifth embodiment of the present invention. FIG. 10 is a circuit diagram showing one amplifier circuit 56 in FIG.

  The present embodiment is different from the first embodiment in that an amplifier circuit 56 is provided instead of the amplifier circuit 16, and that the sampling unit 17 is replaced with the AD converter 20 and the horizontal output bus line 21. , Only horizontal signal lines 18N and 18S, output amplifiers APN and APS, and transistors RTHN and RTHS are provided.

  In the amplifier circuit 16 shown in FIG. 2, the amplifier circuit 56 includes switches Sf1 to Sf4 and capacitors Cf1, Cf2, Cf31, Cf32, and Cf4 instead of the feedback capacitor Cf, and is configured to obtain a variable capacitance value. Yes. This amplifying circuit 56 amplifies with a gain whose absolute value is smaller than 1 and a gain whose absolute value is 1 or more by appropriately setting the capacitance values of the capacitors Ci, Cf1, Cf2, Cf31, Cf32, and Cf4. It has a function to do. For example, by setting Ci = Cf4 = 4 * C0, Cf1 = Cf2 = Cf31 = Cf32 = C0, Cf4 = 4 * C0, 0.5, 1, 2, and so on depending on the on / off state of the switches Sf1 to Sf4 A gain of 4 (ΔVout / ΔVin) can be obtained.

  Each sampling unit 17 has a first capacitor CS and a second capacitor CN. In the present embodiment, the first capacitor CS is a capacitor that stores optical signals. The second capacitor CN is a capacitor for accumulating a differential signal including a noise component to be subtracted from the optical signal. Each sampling unit 17 includes first and second input switches TVS and TVN, and first and second output switches THS and THN. Each sampling unit 17 samples and holds the output signal Vout of the corresponding amplifier circuit 56 according to the control signals φTVN and φTVS, and also holds the held signal according to the horizontal scanning signal φH from the horizontal scanning circuit 13. , 18S. The optical signal and the difference signal output to the horizontal signal lines 18N and 18S are amplified via output amplifiers APS and APN, respectively, and output to an external signal processing unit (not shown). Although not shown in the drawing, the external signal processing unit obtains a difference between outputs of the output amplifiers APS and APN by a differential amplifier or the like. Thereby, correlated double sampling is realized. The sampling unit 17 is provided to remove the offset of the amplifier circuit 56.

  FIG. 11 is a timing chart showing an example of the reading operation of the solid-state imaging device 101 according to the present embodiment. In the present embodiment, a mechanical shutter (not shown) is opened for a predetermined exposure period, and charges are accumulated in the charge accumulation layer of the photodiode PD of each pixel 11. The same operation is sequentially performed on the rows. When each signal in FIG. 11 is at a high level, the corresponding transistor (switch) is turned on. φSf is a control signal for the switch Sf of the amplifier circuit 56, and the high level period of φSf is the amplifier reset period.

  Although not shown in FIG. 11, it goes without saying that a control signal for setting on / off states of the switches Sf1 to Sf4 is supplied in accordance with a desired gain.

  According to this embodiment, the amplifier circuit 56 has a function of amplifying with a gain whose absolute value is smaller than 1. Therefore, a voltage that can be received by an external circuit (not shown) that is a circuit subsequent to the amplifier circuit 56. Even when the amplitude is smaller than the amplitude corresponding to the voltage amplitude that can be output from the pixel 11 and a large level of voltage is output from the pixel 11, signal transmission to the external circuit can be performed appropriately. it can.

  In the amplifier circuit 56 used in the present embodiment, a variable gain can be obtained, and in addition to a gain whose absolute value is smaller than 1, a gain whose absolute value is 1 or more can be obtained. For example, by increasing the gain when setting low sensitivity and increasing the gain when setting high sensitivity, it is possible to increase the dynamic range when the sensitivity is low and increase the S / N ratio when the sensitivity is high.

  However, in the amplifier circuit 56, as in the amplifier circuit 16, it is relatively difficult to design the operational amplifier OP in order to stabilize the amplifier circuit 56.

  In the present embodiment, any of the above-described amplifier circuits 16, 26, 36, and 46 may be provided in place of the amplifier circuit 56. In the first embodiment, either the amplifier circuit 56 or an amplifier circuit 66 described later may be provided instead of the amplifier circuit 16.

[Sixth Embodiment]
FIG. 12 is a circuit diagram showing an amplifier circuit 66 used in the solid-state imaging device according to the sixth embodiment of the present invention. The present embodiment is different from the fifth embodiment only in that each amplifier circuit 56 is replaced by an amplifier circuit 66.

  The only difference between the amplifier circuit 66 and the amplifier circuit 56 is that the switch Sf4 and the capacitor Cf4 are removed and that the capacitors Ci1 and Ci2 and the switch Si are provided instead of the input capacitor Ci. In the present embodiment, the capacitors Ci1 and Ci2 and the switch Si are connected between the input unit to which the input voltage Vin is applied and the negative input terminal of the operational amplifier OP so that the capacitance value can be changed to a plurality of different values. The configured input capacitance circuit is configured. In the present embodiment, the switches Sf1 to Sf3, Sf and the capacitors Cf1, Cf2, Cf31, Cf32 temporarily short-circuit between the output terminal and the −input terminal of the operational amplifier OP and the operational amplifier OP. A feedback circuit that temporarily forms a predetermined capacitance value between the output terminal and the negative input terminal is configured.

  The amplifier circuit 66 appropriately amplifies the capacitance values of the capacitors Ci1, Ci2, Cf1, Cf2, Cf31, and Cf32 so that the absolute value is amplified with a gain smaller than 1, and the absolute value is amplified with a gain of 1 or more. It has a function to do. For example, by setting Ci1 = Ci2 = 2 * C0 and Cf1 = Cf2 = Cf31 = Cf32 = C0, the gains (0.5, 1, 2, 4) according to the on / off states of the switches Si, Sf1 to Sf3 ( ΔVout / ΔVin) can be obtained.

  According to the present embodiment, in addition to the same advantages as those of the fifth embodiment, the area occupied by the amplifier circuit 66 can be reduced compared to the area occupied by the amplifier circuit 56 when obtaining the same gain. There are also benefits. This will be described below.

  In the amplifier circuit 56, since the input capacitance Ci is fixed, the capacitance value of the feedback circuit must be increased in order to obtain a relatively small gain value. Therefore, the area occupied by the amplifier circuit 56 increases. On the other hand, in the amplifier circuit 66, since the input capacitance circuit has a variable capacitance value, when a relatively small gain value is obtained, the capacitance value of the input capacitance circuit is compared without increasing the capacitance value of the feedback circuit. A small value may be used. Therefore, the area occupied by the amplifier circuit 66 can be reduced.

  For example, the capacitance setting example of the amplification circuit 56 for obtaining the gains 0.5, 1, 2, 4 and the capacitance setting of the amplification circuit 66 for obtaining the same gains 0.5, 1, 2, 4 are described. As compared with the example, since Cf4 = 4 * C0 of the amplifier circuit 56 is removed in the amplifier circuit 66, the occupied area can be reduced accordingly. When comparing the capacitance on the input side, the occupied area of Ci1 = 2 * C0 and Ci2 = 2 * C0 of the amplifier circuit 66 and the occupied area of Ci = 4 * C0 of the amplifier circuit 56 are substantially equal.

  By the way, in the present embodiment, as described above, the amplifier circuit 56 has a function of amplifying with a gain whose absolute value is smaller than 1 and a function of amplifying with a gain whose absolute value is 1 or more. A capacity value is set. However, in the present invention, in the present embodiment, the amplifier circuit 56 does not have a function of amplifying with a gain whose absolute value is smaller than 1, but has a function of amplifying with a gain of 1 or more in absolute value. A capacity value of each capacity may be set. In this case, for example, by setting Ci1 = Ci2 = 4 * C0 and Cf1 = Cf2 = Cf31 = Cf32 = C0, gains of 1, 2, 4, and 8 can be obtained. In this case, although the advantage associated with the function of performing amplification with a gain whose absolute value is smaller than 1 cannot be obtained, the advantage that the area occupied by the amplifier circuit 56 can be reduced when obtaining the same gain is obtained.

  Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments.

DESCRIPTION OF SYMBOLS 1,101 Solid-state image sensor 11 Pixel 14 Vertical signal line 16, 26, 36, 46, 56 Amplifier circuit 20 AD converter

Claims (12)

A pixel that photoelectrically converts incident light;
An amplification circuit having a function of amplifying with a gain whose absolute value is smaller than 1 by inputting a signal from the pixel or a signal corresponding thereto
A solid-state imaging device comprising:   2. The solid-state imaging device according to claim 1, wherein the gain of the amplifier circuit is a ratio of a change in the output signal of the amplifier circuit to a change in the input signal of the amplifier circuit. The gain of the amplifier circuit is variable to a plurality of different gains,
The plurality of gains include one or more gains having an absolute value of 1 or more in addition to a gain having an absolute value smaller than 1.
When n is an integer from 0 to m (m is an integer equal to or greater than 1) and A is a predetermined gain whose absolute value is smaller than 1, the plurality of gains are represented by 2 ⁿ * A ( including m + 1) gains,
The solid-state imaging device according to claim 1 or 2.   The amplifier circuit is connected in series at least temporarily between the input portion of the signal from the pixel or a signal corresponding thereto and the portion to which the first predetermined potential is applied in that order from the input portion side. An operational amplifier having first and second voltage dividing capacitors, a first input terminal and a second input terminal to which a second predetermined potential is applied, and a first amplifier between the first and second voltage dividing capacitors. An input capacitor connected at least temporarily between one node and the first input terminal, and temporarily shorting between the output terminal of the operational amplifier and the first input terminal, and 4. A first feedback circuit that temporarily forms a predetermined capacitance value between an output terminal of an operational amplifier and the first input terminal. 5. Solid-state image sensor.   The solid-state imaging device according to claim 4, further comprising a switch connected between the first node and the first input terminal. Comprising first through fourth capacitors and first through fifth switches;
The first switch and the first capacitor are connected in series between the input unit and the first node in that order from the input unit side,
The second switch is connected between the input unit and the first node,
The third switch is connected between a second node between the first switch and the first capacitor and the first input terminal;
The third capacitor and the fourth switch are connected in series between the first node and the part in that order from the first node side,
The fifth switch is connected between a third node between the third capacitor and the fourth switch and the first input terminal;
The second capacitor is connected between the first node and the first input terminal,
The fourth capacity is a capacity between the first node and the part,
The first voltage dividing capacity includes the first capacity,
The second voltage dividing capacity is composed of the fourth capacity or a parallel combined capacity of the third capacity and the fourth capacity,
The input capacitor is composed of the second capacitor or a parallel combined capacitor of the second capacitor and the third capacitor.
The solid-state imaging device according to claim 4.   The solid-state imaging device according to claim 4, wherein the amplifier circuit includes a second feedback circuit that forms a predetermined capacitance value between the output terminal and the first node at least temporarily.   8. The solid-state image pickup device according to claim 7, wherein at least a part of the capacitance constituting the second feedback circuit is also used as at least a part of the capacitance constituting the first feedback circuit. Comprising first to fifth capacitors and first to seventh switches;
The first capacitor is connected between the input unit and the first node;
The first switch and the second capacitor are connected in series between the first node and the first input terminal in that order from the first node side,
The second switch is connected between a second node between the first switch and the second capacitor and the input unit,
The seventh switch and the third capacitor are connected in series between the first node and the part,
The third switch is connected between the first node and the first input terminal;
The first feedback circuit includes the fourth and fifth capacitors and the fifth and sixth switches.
The fifth switch and the fourth capacitor are connected in series between the first input terminal and the output terminal in that order from the first input terminal side,
The sixth switch and the fifth capacitor are connected in series between the first input terminal and the output terminal,
The fourth switch is connected between a third node between the fifth switch and the fourth capacitor and the first node;
The first voltage dividing capacity includes the first capacity,
The second voltage dividing capacity includes the third capacity,
The input capacitance comprises the second capacitance;
The second feedback circuit includes the fourth capacitor and the fourth switch.
The solid-state imaging device according to claim 7 or 8, wherein The amplifier circuit includes an operational amplifier having a first input terminal and a second input terminal to which a predetermined potential is applied, an input unit for a signal from the pixel or a signal corresponding thereto, and the first input terminal And an input capacitance circuit configured to change the capacitance value to a plurality of different values, and temporarily shorting between the output terminal of the operational amplifier and the first input terminal A feedback circuit that temporarily forms a predetermined capacitance value between the output terminal of the operational amplifier and the first input terminal;
The solid-state imaging device according to claim 1 or 2. A pixel that photoelectrically converts incident light;
An amplifier circuit to which a signal from the pixel or a signal corresponding thereto is input;
With
The amplifier circuit includes an operational amplifier having a first input terminal and a second input terminal to which a predetermined potential is applied, an input unit for a signal from the pixel or a signal corresponding thereto, and the first input terminal And an input capacitance circuit configured to be capable of changing the capacitance value to a plurality of different values, and temporarily shorting between the output terminal of the operational amplifier and the first input terminal A feedback circuit that temporarily forms a predetermined capacitance value between the output terminal of the operational amplifier and the first input terminal;
A solid-state imaging device. The input capacitance circuit has a plurality of capacitors and one or more switches,
The plurality of capacitors and the one or more switches are connected such that a capacitance value of the input capacitance circuit can be changed to the plurality of different values according to an on / off state of the one or more switches.
The solid-state imaging device according to claim 10 or 11,

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