JP4366646B2 - AD conversion circuit and solid-state imaging device - Google Patents

Description

    The present invention relates to an AD conversion circuit and an imaging apparatus that accurately derive a signal component multiplexed with a varying DC component, such as an output signal from a solid-state imaging device.

    In recent years, CMOS image sensors have attracted attention as imaging devices. This is because the noise reduction circuit can be mounted on the same chip to achieve the same level of sensitivity as a CCD image sensor, with low voltage operation and low power consumption. It is attracting attention because of its ease. Among them, the mounting of an AD converter is significant and has received the most attention in that the design of an analog circuit having a high S / N ratio, which is difficult among camera design techniques, is no longer necessary for the camera designer.

     One of the AD converter mounting methods is a column parallel type. By having an AD converter for each pixel column, it is possible to extend the time required for signal detection and AD conversion from the pixel cycle to the row cycle. The noise bandwidth of the AD converter can be reduced and the signal S / N ratio can be improved. For example, in the case of an image sensor with 2 million pixels for high vision, the cycle of one pixel is 13.47 ns, and the row cycle is 26.94 μs, which is an increase of 2,200 times. Even if most of this row period is used for AD conversion and only 2% is used for signal detection from pixels, the white noise produced by the charge-voltage converter can be averaged and captured over a period of 44 pixels, and the amount of noise Is inversely proportional to the square root of the time to average the signal, so that the amount of noise can be greatly reduced to about 1/7 and the camera sensitivity can be improved.

     The column parallel type has a drawback that vertical line-shaped fixed pattern noise is generated when there is variation in the conversion characteristics of the AD converter for each pixel column. As a conventional technique for solving this drawback, as shown in FIG. 16, the threshold voltage variation of the amplifier 7 used for the voltage comparator of the AD converter and the low frequency noise included in the input signal VL are canceled by the self-clamping operation of the amplifier. In some cases, each input signal is compared with a common reference voltage waveform, and the digital value is determined at the timing when the output of the voltage comparator 7 is inverted. For this reason, even if there are variations in the threshold voltage and amplification factor of the voltage comparator 7, there is no variation in the conversion gain of the AD converter, and there is no vertical line-shaped fixed pattern noise. It becomes.

However, since the conventional AD converter sequentially compares the input signal component and the reference voltage one gradation at a time, voltage comparison of the number of gradations of the output digital value is required. That is, 2 ⁿ voltage comparisons are required to determine an n-bit digital value. For example, an 8-bit digital value can be determined by 256 voltage comparisons, but to obtain a 12-bit digital value 4,096 times and for a 16-bit digital value 65,536 times A voltage comparison is required. The number of comparisons for obtaining a digital value of 12 bits or more is larger than the ratio of the pixel period to the horizontal period, and not only a problem that requires a clock with a frequency higher than the frequency corresponding to the pixel period, but also a wideband inverting amplifier. As a result, there is a problem that noise increases because the noise bandwidth also increases.
Japanese Patent Laid-Open No. 9-247494

    The problem to be solved is that in order to achieve high resolution with a conventional AD converter, the number of comparisons between the input signal component and the reference signal must be increased, and therefore the time required for each comparison is shortened. A broadband analog system is required, and the amount of noise increases.

    In order to solve the above-described problem, in the AD converter circuit according to the present invention, the voltage comparator for comparing the input signal component and the reference signal has the above two voltages obtained by matching the voltages at a predetermined time by the first clamping means. A first differential amplifier for amplifying the signal voltage difference; an integrating means for selectively integrating the output signal of the first differential amplifier; and adding the output signal of the first differential amplifier and the output signal of the integrating means Adding means, first sample hold means for sample-holding the output signal of the adder means, and second difference for amplifying the potential difference between the output signal of the first differential amplifier and the output signal of the first sample-hold means Use a dynamic amplifier configuration.

    First, when no signal level is given to the input terminal, the first clamp means makes the input voltage of the first amplifier the same, resets the integrating means, and outputs the output signal of the adding means to the first sample hold means. Sample and hold. Thereafter, a signal level is given to the input terminal, and an n-step staircase waveform is given as a reference signal. When the level of the staircase waveform exceeds the input signal level, the second differential amplifier is inverted. The upper digital value is determined based on this timing, and the voltage corresponding to the reference signal exceeding the input signal level is amplified by the first differential amplifier and sample-held in the first sample-and-hold means.

    Next, as a reference signal, a signal having an amplitude reduced by ½ with respect to the step voltage of the staircase wave given at the time of determining the upper digital value is generated m times. Each time, the reference signal is amplified by the first differential amplifier and is compared by the second differential amplifier with the output signal of the first sample and hold means via the adding means. When the output of the second differential amplifier is not inverted, the output signal of the first differential amplifier is integrated by the integrating means, and the lower digital value is bit by bit from the upper order according to the output of the second differential amplifier. Determine the digital value. By synthesizing the upper and lower digital values obtained in this way, an AD-converted digital signal is obtained.

Since the staircase waveform when determining the upper digital value is n steps and the lower step is an m-bit digital value, an (n × 2 ^m ) gradation digital value can be obtained by (n + m) voltage comparisons. Amplifies the reference voltage when determining the lower digital value with the same amplifier that amplified the residual voltage when determining the higher digital value, so there is no effect even if the gain of the amplifier varies. There is a feature.

    Further, the integrating means and the adding means can be realized by a clamp means and a means for sampling and holding the output and feeding back as a clamp voltage.

    Furthermore, since the reference voltage only needs to always generate the same waveform regardless of the output digital value, the same reference voltage generating means can be shared by a plurality of AD converting means, and variations in conversion characteristics can be eliminated.

    As described above, according to the present invention, the number of times of voltage comparison of the AD converter having a noise removal function can be reduced, so that the comparison time per time can be increased and the bandwidth of the analog signal processing circuit is reduced. As a result, the amount of noise can be reduced. In addition, since the AD converter having a plurality of characteristics can be obtained by sharing the reference voltage generating means, the solid-state image pickup element that simultaneously AD-converts signals for one row and sequentially selects and outputs a digital scanning signal. Is particularly effective.

    In the present invention, the upper digital value is determined by comparing the input signal component with the reference step wave, the residual voltage information at that time is retained, the lower digital value is determined from the residual voltage information, and the upper and lower digital values are determined. The most important feature is to obtain an AD conversion value by synthesizing digital values.

    1 is a block diagram of an AD conversion circuit according to a first embodiment of the present invention, FIG. 2 is a detailed block diagram of the AD conversion control circuit 109 of FIG. 1, FIG. 3 is a timing diagram of AD conversion operation, and FIG. FIG. 5 is a block diagram of the voltage generation circuit, and FIG. 5 is an operation timing chart of the reference voltage generation circuit.

    A read signal (imaging signal) Vin from the solid-state imaging device is supplied to the input terminal 101. A signal input from the input terminal 101 is input to the differential amplifier 104 via the clamp circuit 102. The other input of the differential amplifier 104 is input with the output signal of the reference voltage generator 103, and a voltage Va1 obtained by amplifying the differential voltage is output from the differential amplifier 104. The output Va1 of the differential amplifier 104 is input to the adder 105 and the integrating circuit 106. The adding means 105 outputs the sum of the output Va1 of the differential amplifier 104 and the output Vsum of the integrating circuit 106 to the voltage comparator 108 and the sample hold circuit 107. The sample hold circuit 107 samples the SHP signal during the high level, and outputs the signal voltage Vsh holding the voltage to the voltage comparator 108 during the low level period. The voltage comparator 108 outputs a high level when the output Va2 of the adder 105 is higher than the sampled and held voltage Vsh, and outputs a low level when it is lower. The output of the voltage comparator 108 is input to an AD conversion control circuit 109, and an AD converted digital value is output from an output terminal 111. The timing generation circuit 110 generates various pulses necessary for the AD conversion operation and supplies them to each unit.

    Hereinafter, the AD conversion operation will be described with reference to the timing chart of FIG. 3, taking as an example the case where the input signal voltage Vsig is 5.4 times the step voltage Vstep of the staircase wave of the reference signal. Prior to AD conversion, various initializations are performed in the non-signal period PC. The input signal Vin from the image sensor is input with a reference level Vr that varies every time before the signal period. In order to remove this fluctuation component, a high level clamp pulse CP 1 is applied to the clamp circuit 102, and a signal Vin ′ having the same potential as the output signal Vref of the reference signal generator 103 is output to the differential amplifier 104. The accumulator 106 is supplied with the initialization signal RST, and 0 is output until the upper AD conversion is completed. The output Va2 of the adder 105 is sampled and held by the sample and hold circuit 107. The SR flip-flop 203 is reset by the ST pulse, and the SR flip-flops 205 and 211 are set.

    In the first AD conversion period AD1 for determining the upper digital value, the original signal output Vsig is superimposed on the reference level Vr. Since the output Vin ′ of the clamp circuit 102 is clamped in the period PC, the differential amplifier 104 amplifies the voltage change of the input signal generated after clamping, that is, the difference between the original signal output Vsig and the reference voltage Vref.

The reference voltage generator 103 is, for example, the circuit of the block diagram of FIG. 4 and generates the staircase reference voltage Vref as follows according to the timing of FIG. Since the gain of the operational amplifier 404 is very high, the potential Vis of the inverting input terminal is a virtual ground that is substantially zero. The capacitors 406 and 407 have the same capacitance value, and the switch 408 is closed when a staircase wave is generated. Prior to the initialization period PC, the switch 405 is closed and the capacitors 406 and 407 have already been discharged. When the switch 402 is connected to the terminal b, the capacitor 403 stores a charge of (capacitance of the capacitor 403) × (voltage of the constant voltage source 401). When the switch 402 is connected to the terminal “a”, all charges of the capacitor 403 are transferred to the capacitors 406 and 407. At this time, the capacitances of the capacitors 403, 406, and 407 and the voltage of the constant voltage source 401 are set so that the change in the output Vref of the operational amplifier 404 becomes Vstep. When the switching of the terminal b → a → b of the switch 402 is performed n times, an n-step staircase of the step voltage Vstep is output as a reference voltage.

    Since the signal output Vsig is exceeded at the sixth stage of the staircase wave, the output voltage Va2 of the adder 105 exceeds the output voltage Vsh of the sample hold circuit 107, and the voltage comparator 108 outputs a high level. When the high level output of the voltage comparator 108 is supplied to the AND circuit 202 via the OR circuit 201, the clock signal CK1 is supplied to the set input of the SR flip-flop 203, and the SR flip-flop 203 is set. The As a result, the clock signal CK2 is supplied to the reset input of the SR flip-flop 112 via the AND circuit 204, and the SR flip-flop 205 is reset in synchronization with the clock signal CK2. Therefore, the AND circuit 206 generates an upper digital value determination signal GH that becomes a high level at the timing from CK1 to CK2 immediately after the voltage change of the reference voltage Vref becomes equal to or higher than the signal voltage component Vsig.

    Based on this higher-order digital value determination signal GH, the digital value CNT synchronized with the staircase wave of the reference voltage generator 103 output from the timing generation circuit 110 is latched in the data latch 207 and the higher-order digital value 5 of AD conversion is determined. The Further, the upper digital value determination signal GH is given to the sample hold circuit 107 via the OR circuit 208, and the output Va2 of the adder 105 at this time is sampled and held. The voltage that is sampled and held (hereinafter referred to as the residual voltage) is a voltage obtained by amplifying the difference voltage between Vref and Vin ′ (6-5.4) × Vstep (hereinafter referred to as excess voltage) by the differential amplifier 104. It becomes.

    When the signal voltage Vsig is equal to or larger than the amplitude of the staircase wave generated by the reference voltage generator 103, the output of the voltage comparator 107 does not become high level, but in this case, the converted digital value becomes the maximum value. For this purpose, an OR circuit 201 is provided. The OR circuit 201 is supplied with a pulse HC that becomes a high level at the peak of the staircase wave of the reference voltage in the first AD conversion period AD1, thereby generating the upper digital value determination signal GH. At this time, the output Va1 of the differential amplifier 104 is lower than that at the time of clamping, and the sample hold circuit 106 holds this voltage, and memorizes that the signal voltage Vsig is not less than the AD conversion range. The relationship between the input signal Vsig and the output of the sample hold circuit 106 after the first AD conversion period AD1 is as shown in FIG. An input signal outside the AD conversion range may not be linear as shown by a solid line, and the amplification factor of the differential amplifier 104 can be set high, so that it can be hardly affected by noise generated in the sample hold circuit 106. .

    In this way, after the first AD conversion is performed, the voltage at the input terminal is set to the no-signal level Vr ′, and the second AD conversion for determining the lower digital value is started.

    In the second AD conversion period AD2, the reference signal generator 103 switches the square wave whose amplitude is reduced by 1/2 of Vstep by the timing shown in FIG. 5 in the circuit configuration of FIG. Occurs. With the switch 408 closed, the switch 405 is closed and the capacitors 406 and 407 are discharged. After the switch 405 is opened, the switch 402 is switched to the terminal a, and the capacitors 406 and 407 are charged to the voltage Vstep.

    After opening the switch 408 so that the voltage Vstr of the capacitor 407 is not affected, the switch 405 is closed and only the capacitor 406 is discharged. When switch 405 is opened and then switch 408 is closed, the charge is redistributed by capacitors 406 and 407. Since the capacitances of the capacitors 406 and 407 are the same, the charge is distributed by ½, and the charging voltage becomes (Vstep / 2). Accordingly, the operational amplifier 404 outputs a square-wave reference voltage output Vref having an amplitude of (Vstep / 2). Furthermore, by repeatedly opening and closing the switches 405 and 408, a square wave that decreases by a factor of 1/2 is output as the reference voltage output Vref.

    The square-wave-like reference voltage Vref in which the amplitude thus generated decreases by 1/2 times Vstep is amplified by the differential amplifier 104 and input to the voltage comparator 108 via the adder 105. Since the signal held in the sample hold circuit 107 is a voltage obtained by amplifying the excess voltage in the first AD conversion period AD1 by the differential amplifier 104 and passing through the adder 105, the result of comparing the excess voltage with the reference voltage is the voltage. It is output from the comparator 108.

    Since the reference voltage (Vstep / 2) is smaller than the excess voltage (0.6 × Vstep), a low level is output from the voltage comparator 108 and a high level GL signal is output from the NOT circuit 209 via the OR circuit 208. Then, the most significant bit determination pulse L1 of the lower digital value resets the SR flip-flop 211-1 via the AND circuit 210-1. The most significant bit D1 of the lower digital value becomes zero.

    The AND circuit 213 passes the SUP signal, the SR flip-flop 215 is set, the SUM signal becomes high level, and the integrator 106 integrates the output signal of the differential amplifier 104. Due to this integration operation, the output Vsum of the integrator approaches the output Vsh of the sample hold circuit 106. Even if the output of the adder 105 becomes larger than Vsh and the GL signal becomes low level, the output is held only by setting and reset inputs to the SR flip-flops 211 and 215 being low level. When the SUM signal becomes low level, the NOT circuit 214 resets the SR flip-flop 215, and the SUM signal becomes low level.

     Next, the reference voltage generator 103 generates a signal having an amplitude of Vstep / 4. Since the voltage obtained by amplifying Vstep / 2 by the amplifier 104 is held in the accumulator 106, the output of the adder 105 is (Vstep / 2 + Vstep / 4 = 0.75 × Vstep) amplified by the amplifier 104. It becomes the same voltage. Since the reference voltage (0.75 × Vstep) is larger than the excess voltage (0.6 × Vstep), a high level is output from the voltage comparator 108, and a low level GL signal is output from the NOT circuit 209 via the OR circuit 208. Is output, bit decision pulse L2 of the lower digital value is blocked by AND circuit 210-2, SR flip-flop 211-1 remains set, and the second most significant bit D1 of the lower digital value is set to 1. Become. Further, the AND circuit 213 blocks the SUP signal, the SUM signal is not output, and the signal held in the accumulator 106 is not changed.

    Further, by repeating the same operation for the lower bits, the converted values are sequentially determined in the SR flip-flop 211, and the signal held in the integrator 106 is changed to the signal held in the sample hold circuit 107. Approach from the side.

The upper and lower digital values thus determined are the gate signal ADCK.
Are taken into the data latch 212, and an AD conversion value with all the bit timings is output to the output terminal 111.

As described above, the digital value of (n × 2 ^m ) gradations is obtained by a total of (n + m) times of n times when the number of comparisons determines the upper digital value and m times when the lower digital value is determined. Obtainable. FIG. 3 shows the case of n = 8 and m = 6. However, for example, a combination of n = 16 and m = 12 may be used. In this case, 65,536 gradations, that is, 16 in only 28 voltage comparisons. Bit AD conversion can also be realized, and analog signal processing can be narrowed, so that low noise and high resolution AD conversion is possible.

    FIG. 7 is a block diagram of an AD conversion circuit according to the second embodiment of the present invention, and FIG. 9 is a timing chart for explaining the operation thereof. This corresponds to the circuit shown in FIG. 1, and the same reference numerals are assigned to the same blocks. The difference is that the adder 105 and the accumulator 106 are replaced with a clamp circuit 701 and a sample hold circuit 702 with an initialization function, and only this part will be described below.

    A detailed block diagram of the sample and hold circuit 702 with an initialization function is shown in FIG. In the no-signal period PC and the first AD conversion period AD1, the switch 803 is closed by the high level initialization signal RST, the capacitor 804 is initialized to the potential of the constant voltage source 806, and a constant voltage is output from the buffer amplifier 805. Is done. Also, the clamp pulse CP2 is given during the no-signal period PC, and the bias point is set to a predetermined voltage for the output of the clamp circuit 701. In the first AD conversion period AD1, the same voltage change as the output voltage of the differential amplifier 104 is generated in the output of the clamp circuit 701. Therefore, the output of the clamp circuit 701 is the same as the output of the adder 105 in FIG. The upper digital value is determined at the timing when the output of the voltage comparator 108 is inverted, and the sample hold circuit 106 is supplied with the voltage obtained by amplifying the reference signal excess by the differential amplifier 104 and the initialization voltage of the sample hold circuit 702. The sum is preserved.

    In the second AD conversion period AD2, the clamp pulse CP2 is given during the low level period of the square wave train in which the amplitude generated by the reference signal generator 103 is reduced by a factor of 1/2. Therefore, the output of the clamp circuit 701 is a signal obtained by adding the output voltage Vsum of the sample and hold circuit 702 and the output voltage change of the reference signal generator 103 amplified by the differential amplifier 104 during the high level period of the square wave. The voltage comparator 108 compares the voltage with the voltage held in the sample hold circuit 106. When the output of the clamp circuit 701 is lower than the output voltage of the sample hold circuit 106, the SUM signal is generated from the AD conversion control circuit 109, and the output of the clamp circuit 701 at this time is taken into the sample hold circuit 106. When the output of the clamp circuit 701 is higher than the output voltage of the sample and hold circuit 106, the SUM signal is low and the output of the sample and hold circuit 106 does not change. Therefore, the output voltage of the sample hold circuit 106 approaches the voltage held in the sample hold circuit 106 sequentially from the lower side, the lower digital value is determined, and the AD conversion value can be determined by combining with the upper digital value.

    FIG. 10 is a block diagram of a solid-state imaging device according to the third embodiment of the present invention, and FIG. 11 is a timing diagram for explaining the operation thereof. This is a so-called line sensor in which pixels are arranged in a line, and in the figure, only two pixels are shown as a representative.

    The pixel 1000 includes a photodiode 1001 having a photoelectric conversion function and a charge storage function, a switch 1002 for reading the signal charge, a capacitor 1004 for converting the read signal charge amount into a voltage, and signal reading Prior to this, a switch 1003 for resetting the capacitor 1004, a MOS transistor 1005 for obtaining a low-impedance voltage output, and a source follower circuit of a constant current source 1006 are formed. Note that the capacitor 1004 may not be provided with a capacitor element in order to obtain a high charge-voltage conversion gain, and may be configured only by the parasitic capacitance of the MOS transistor 1005 and the switches 1002 and 1003.

    Prior to reading a signal from the photodiode 1001, the switch 1003 is closed by the RS pulse to discharge the capacitor 1004. At this time, thermal noise due to the on-resistance of the switch 1003 is generated, so that voltage fluctuations occur in the outputs VA1, Va2,... Of the source follower circuit. The

    When the read pulse RD is given, the read switch 1002 is closed, the signal charge is transferred from the photodiode 1001 to the capacitor 1004, and is converted into a voltage change proportional to the signal charge amount. This voltage change is output as a voltage change to the outputs VA1, Va2,... Of the source follower circuit and input to the AD conversion unit 1007.

    The AD conversion unit 1007 performs the above-described AD conversion operation and determines the upper digital value by comparing the change voltage of the input signal, which is a true signal, with the step wave of the reference signal Vref in the first AD conversion period AD1. In the second AD conversion period AD2, the lower digital value is determined bit by bit from the upper bit using the reference signal Vref having an amplitude obtained by subtracting the step voltage of the staircase wave by ½.

    The digital value determined in this way is latched at the timing of the clock signal ADCK and is output sequentially from the output terminal 1011 via the scanning circuit 1009. Simultaneously with this scanning output, the next signal is read from the pixel and AD conversion is performed.

    The variation in the output voltage of the source follower circuit is canceled by the clamping operation of the AD converter 1007, and the reference signal Vref used for comparison with the input signal is supplied from one reference signal generator 1008 to all the AD converters 1007. There is no variation in conversion gain. Since the scan output time can be set to AD conversion time and the number of voltage comparisons necessary for AD conversion can be reduced, the signal bandwidth of the voltage comparator can be narrowed. Accordingly, it is possible to realize a digital output image sensor with low noise and high resolution.

    FIG. 12 is a block diagram of a solid-state imaging device according to the fourth embodiment of the present invention, and FIG. 13 is a timing diagram for explaining the operation thereof. This is a so-called area sensor in which pixels are arranged in a matrix. In the drawing, only two pixels in the vertical direction and the horizontal direction are shown as representatives, and components having the same functions as those in FIG.

    First, in order to read out the pixel signals of the first row, the row selection pulse LS1 is set to the high level and the column selection switches 1201-11, 1201-12,. ,... Are output to the signal lines VA1, Va2,. At this time, the reset pulse RS1 is also given, and the capacitors 1004-11, 1004-12,... Are discharged by the switches 1003-11, 1003-12,. The signal line voltages VA1, Va2,... Vary due to threshold voltage variations of the MOS transistor 1005 and thermal noise generated by the on-resistance of the switch 1003, but are canceled by the clamp operation of the AD conversion unit 1007.

    Next, when the read pulse RD1 of the first row is given and the switches 1002-11, 1002-12,... Are closed, the photodiodes 1001-11, 1002-12,. The signal charge is transferred, and a voltage change proportional to the signal charge amount occurs in the signal line voltages VA1, Va2,.

In the first AD conversion period AD 1-1, a staircase wave is output from the reference signal generator 1008, and voltage changes generated in the signal line voltages VA 1, Va 2,. .., 1007-2,... Are compared to determine the upper digital value, and the residual voltage is held in the AD converter.

    Next, when the row selection pulse LS1 is set to the low level and the FP pulse is set to the high level, the signal line voltages VA1, Va2,... Are grounded by the switches 1202-1, 1202-2,. This prevents the source follower noise from entering the AD conversion unit 1007 during the second AD conversion period AD2-1.

    In the second AD conversion period AD2, the lower digital value is determined bit by bit from the upper bit using the reference signal Vref having an amplitude obtained by subtracting the step voltage of the staircase wave by 1/2. The digital value determined in this way is latched at the timing of the clock signal ADCK and is output sequentially from the output terminal 1011 via the scanning circuit 1009. In the period during which the AD conversion values of the first row are scanned and output, signals are read from the pixels 1000-21, 1000-22,. Similarly, the output of the nth row and the AD conversion of the (n + 1) th row are executed simultaneously.

    The variation in the output voltage of the source follower circuit is canceled by the clamping operation of the AD converter 1007, and the reference signal Vref used for comparison with the input signal is supplied from one reference signal generator 1008 to all the AD converters 1007. There is no variation in conversion gain. Since the output time for one row can be set to AD conversion time and the number of voltage comparisons required for AD conversion can be reduced, the time required for voltage comparison can be increased and the signal bandwidth can be reduced. Accordingly, it is possible to realize a digital output image sensor with low noise and high resolution.

    FIG. 14 is a block diagram of a CCD solid-state imaging device according to a fifth embodiment of the present invention, and FIG. 15 is a timing diagram for explaining the operation thereof. In the drawing, only two pixels in the vertical direction and the horizontal direction are shown as representatives. Further, since the pixel 141 and the vertical transfer CCD 142 are interline CCDs which are general CCD solid-state imaging devices, the operation timing for reading the signal charges from the pixels and transferring them in the CCD charge transfer path 142 is omitted, and the AD conversion operation is performed. Only the timing is shown.

    The signal charge photoelectrically converted by the pixel 141 is read out to the CCD charge transfer path 142 and then transferred sequentially downward, and the signal charge is given when a low level is applied to the final transfer stage electrode 142L of the CCD charge transfer path. The charge is sent to the charge / voltage conversion circuit 144 via the output gate 143. Since the CCD image pickup device easily increases the transfer efficiency, electrons are used as signal charges. Therefore, the outputs VA1, Va2,... Of the charge voltage conversion circuit 144 are negative signals. For this reason, a negative signal is given as the reference voltage Vref, and the magnitude comparison in the AD converter 146 is also handled as a negative signal. Further, the negative reference voltage Vref can be generated, for example, by inverting the switching of the switch 402-1 in the reference voltage generation circuit of FIG. In addition, two AD conversion units 146 are provided for one charge-voltage conversion circuit 144 via a switch 145, so that a first AD conversion that requires a pixel signal and an unnecessary second first AD conversion can be executed simultaneously. I am doing so.

    In order to initialize the charge-voltage conversion circuit 144, a reset pulse RS is applied to turn on the MOS transistor switch 144a, the charge-voltage conversion capacitor 144b is set to the initialization voltage VRD, and the sources of the MOS transistor 144c and the low current source 144d Buffered and output by follower. By connecting the signal selection switch 145 to the a side, the signals are input to the AD conversion units 146-1a, 146-2a,. By providing the clamp pulse CPa, voltage fluctuations generated at the output of the charge-voltage conversion circuit 144 are canceled by the AD conversion units 146-1a, 146-2a,.

    By applying a low-level pulse to the final transfer stage electrode 142L, the signal charges of the pixels 141-11, 141-12,... For one row are transferred to the charge-voltage conversion circuit 144, and the voltage change that is the true signal voltage Vsig11, Vsig12,... Are input to the AD conversion units 146-1a, 146-2a,. In the first AD conversion period AD1, a negative step wave is output from the reference signal generator 148a, and the voltage changes Vsig11, Vsig12,... -1a, 146-2a,... To determine the upper digital value, and each residual voltage is held in the AD converter.

    Next, the signal selection switch 145 is connected to the b side. The DC bias voltage VB is input to the AD conversion units 146-1a, 146-2a,..., And the second AD conversion period AD2 is started. In the second AD conversion period AD2, the reference signals Vref having an amplitude obtained by reducing the step voltage of the staircase wave by a factor of 1/2 are held in the AD conversion units 146-1a, 146-2a,. By comparing with the residual voltage, the lower digital value is determined bit by bit from the upper bit. The digital value determined in this way is latched at the timing of the clock signal ADCKa and output from the AD conversion units 146-1a, 146-2a,. In the second AD conversion period AD2, the output of the charge voltage conversion circuit 144 is connected to the AD conversion units 146-1b, 146-2b,..., And is a negative step wave output from the reference signal generator 148a. The first AD conversion is performed at the same time, and the upper digital value for the signal in the second row is determined. .

The determined output digital values DV1a, DV2a,... Of the AD conversion units 146-1a, 146-2a,... Are sequentially selected by the scanning circuit 147, and the digital output signals P11, P12,. The During the scanning output period, the AD conversion units 146-1b, 146-2b,... Simultaneously execute lower-order AD conversion of the pixels 141-21, 141-22,. In 146-1a, 146-2a, ..., higher-order AD conversion of the pixel signals in the third row is simultaneously executed. From the next line onward, digital value output and upper and lower AD conversion are executed simultaneously.

    With this configuration, the output time for two rows can be converted to AD conversion time, and the number of voltage comparisons required for AD conversion is small, so that the time required for one voltage comparison can be further increased and the signal bandwidth can be narrowed. it can. Accordingly, it is possible to realize a digital output image sensor with low noise and high resolution.

Block diagram of AD conversion circuit (Example 1) Block diagram of AD conversion control circuit (first embodiment) AD conversion operation timing chart (Example 1) Block diagram of reference voltage generation circuit (Example 1) Operational Timing Diagram of Reference Voltage Generation Circuit (Example 1) A diagram for explaining a relationship with an input signal (Example 1) Block diagram of AD converter circuit (Example 2) Block diagram of sample hold circuit with initialization function (Example 2) AD conversion operation timing diagram (Example 2) Block diagram of solid-state image sensor (Example 3) Operation timing diagram of solid-state image sensor (Example 3) Block diagram of solid-state image sensor (Example 4) Operation timing diagram of solid-state image sensor (Example 4) Block diagram of a CCD solid-state image sensor (Example 5) Timing chart of operation of CCD solid-state image sensor (Example 5) Block diagram of CCD solid-state image sensor (conventional example)

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Input terminal 102,701 ... Clamp circuit 103,148,1008 ... Reference signal generator 104 ... Differential amplifier 105 ... Adder 106 ... Integration circuit 107,702 ... Sample hold circuit 108 ... Voltage comparator 109 ... AD conversion control Circuit 110 ... Timing generation circuits 111 and 1011 ... Output terminals 141 and 1000 ... Pixel 142 ... CCD charge transfer path 143 ... Output gate 144 ... Charge voltage conversion circuits 146 and 1007 ... AD converters 147 and 1009 ... Scan circuit 1006 ... Low current Sources 201, 208 ... OR circuits 202, 204, 206, 210, 213 ... AND circuits 203, 205, 211, 215 ... SR flip-flops 207, 212 ... Data latches 209, 214 ... NOT circuits 401, 806 ... Constant voltage source 145 , 402, 405, 408, 803 02,1002,1003,1201,1202 ... Switch 403,406,407,804,1004 ... capacitor 404 ... operational amplifier 801, 805 ... buffer amplifier 1001 ... photodiode 1005 ... MOS transistor

Claims (5)

A first differential amplifier to which an input signal and a reference voltage are respectively supplied to the input and a first differential amplifier provided in at least one of the supply paths so as to match the input voltages of the first differential amplifier at a predetermined time point 1 clamping means, integrating means for selectively integrating the output signal of the first differential amplifier, and adding means for adding the output signal of the first differential amplifier to the holding signal of the integrating means; First sample hold means for sample-holding the output signal of the adder means, and a second difference for amplifying a difference voltage between the output signal of the adder means and the output signal of the first sample hold means And a reference voltage generating means for generating the reference voltage. At a first time point of the input signal, the first clamping means is caused to perform a clamping operation and the first voltage is supplied. The sample hold means holds the sum signal of the output signal of the first differential amplifier and the output signal of the integrating means initialized, and a staircase waveform is given as the reference voltage at the second time point of the input signal. The upper digital value is determined according to the timing at which the output of the second differential amplifier is inverted, and the output voltage of the adding means is held by the first sample-and-hold means. At a third time point, A reference voltage having an amplitude reduced by a factor of ½ with respect to the step voltage of the step voltage of the reference voltage at the second time point is generated a plurality of times, and the lower digital value is increased depending on whether the output of the comparison means is inverted or not. And when the output of the comparison means does not invert, the output signal of the first differential amplifier is integrated in the integration means, and the first sample hold Output means for A / D converting the voltage held in the stage to determine a lower digital value, and combining and outputting the upper digital value and the lower digital value; and outputting the first time and the first 2. An AD conversion circuit characterized in that a digital value corresponding to a difference voltage of an input signal at time 2 is obtained. The input signal supply path has switching means for switching between the input signal and a predetermined voltage, and the input signal is selected by the switching means at the first and second time points of the input signal, and the input 2. The AD converter circuit according to claim 1, wherein the predetermined voltage is selected by the switching means at a third time point of the signal. The integration means for selectively integrating the output signal of the first differential amplifier includes a second clamp means for clamping the output signal of the first differential amplifier, and an output of the second clamp means. 3. The AD conversion circuit according to claim 1, further comprising: second sample and hold means for sample-holding and applying feedback to the second clamp means. A plurality of photoelectric conversion means, a plurality of signal detection means for converting a signal charge from the photoelectric conversion means into a signal voltage, and a plurality of signal conversion circuits provided corresponding to the signal detection means for converting the signal voltage into a digital value. The AD converter circuit according to any one of claims 1 to 3, and at least means for sequentially selecting and outputting digital value outputs of the plurality of AD converter circuits, wherein the reference voltage generating means of the AD converter circuit includes: A solid-state image pickup device shared by a plurality of AD conversion circuits. A plurality of photoelectric conversion means, a plurality of signal detection means for reading signal charges from the photoelectric conversion means and converting them into signal voltages, and the signal detection means operating at different phases for converting the signal voltages into digital values A plurality of AD converter circuits according to any one of claims 1 to 4 and means for sequentially selecting and outputting digital value outputs of the plurality of AD converter circuits; A solid-state imaging device characterized in that a reference voltage generating means is shared by a plurality of AD conversion circuits.

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