JP5641112B2 - Solid-state imaging device and camera system - Google Patents

Description

  The present invention relates to a solid-state imaging device represented by a CMOS image sensor and a camera system.

In recent years, CMOS image sensors have attracted attention as solid-state imaging devices (image sensors) that replace CCDs. This is due to the following reason.
A dedicated process is required for manufacturing a CCD pixel, and a plurality of power supply voltages are required for its operation, and a plurality of peripheral ICs need to be operated in combination.
On the other hand, the CMOS image sensor overcomes various problems such as a very complicated system in such a CCD.

The CMOS image sensor can be manufactured by using a manufacturing process similar to that of a general CMOS integrated circuit, can be driven by a single power source, and further, an analog circuit or a logic circuit using the CMOS process. Can be mixed in the same chip.
For this reason, it has a plurality of great merits such that the number of peripheral ICs can be reduced.

The output circuit of a CCD is mainly a 1-channel (ch) output using an FD amplifier having a floating diffusion layer (FD).
In contrast, a CMOS image sensor has an FD amplifier for each pixel, and its output is a column parallel output type in which one row in the pixel array is selected and read out in the column direction at the same time. Mainstream.
This is because it is difficult to obtain a sufficient driving capability with an FD amplifier arranged in a pixel, and therefore it is necessary to lower the data rate, and parallel processing is advantageous.

  Various signal output circuits of this column parallel output type CMOS image sensor have been proposed.

As a technique used for pixel signal readout of a CMOS image sensor, a signal charge, which is an optical signal generated by a photoelectric conversion element such as a photodiode, is temporarily sampled in a capacitor ahead through a MOS switch arranged in the vicinity thereof. There is a method of reading out.
In the sampling circuit, noise having an inverse correlation with the normal sampling capacitance value is carried.
In the pixel, when the signal charge is transferred to the sampling capacitor, the potential gradient is used to completely transfer the signal charge. Therefore, no noise is generated in this sampling process, but the voltage level of the previous capacitor is set to a certain reference value. Noise appears when resetting.

As a general technique for removing this, there is correlated double sampling (CDS). This is a method of removing noise by reading and storing signal charges in a state (reset level) immediately before sampling once, then reading the signal level after sampling and subtracting it.
There are various specific methods of CDS.

  Various pixel signal readout (output) circuits for column parallel output type CMOS image sensors have been proposed. Among them, one of the most advanced forms is a type that includes an analog-digital conversion device (hereinafter abbreviated as ADC (Analog digital converter)) for each column and extracts a pixel signal as a digital signal.

  A CMOS image sensor equipped with such a column-parallel ADC is disclosed in Non-Patent Document 1, Patent Documents 1, 2, and 3, for example.

JP-A-2005-278135 JP 2005-295346 A JP-A 63-209374

W. Yang et al. (W. Yang et. Al., “An Integrated 800x600 CMOS Image System,” ISSCC Digest of Technical Papers, pp. 304-305, Feb., 1999)

  As described above, in a column parallel ADC-mounted CMOS image sensor (column AD type CMOS image sensor), the comparator compares the RAMP wave from the DAC with the pixel signal, and performs AD conversion by performing digital CDS with the counter at the subsequent stage. I do.

  In general, the comparator has a two-stage amplifier configuration, which performs a low-speed signal comparison operation at the first stage, narrows the operating band, and increases the gain by the second-stage amplifier.

Incidentally, random noise is an important performance index of a solid-state imaging device.
It is known that there are a pixel and an AD converter as main random noise sources.

  Generally, as a random noise reduction method, flicker noise is reduced by increasing the transistor size, or a capacitor is added to the output of the first stage of the comparator, and the noise is filtered by CDS by reducing the bandwidth. A method of aiming at is known.

  However, each method has the disadvantage that the area increases, the inversion delay of the comparator deteriorates due to the increase in capacity, and the frame rate of the image sensor cannot be increased.

  In Patent Documents 2 and 3, a mirror capacitor is used to reduce reset noise within a pixel (before the vertical signal line), but there is a disadvantage that noise of the AD converter cannot be reduced.

  An object of the present invention is to provide a solid-state imaging device and a camera system capable of improving a frame rate while suppressing an increase in area and reducing noise of an AD converter.

  A solid-state imaging device according to a first aspect of the present invention includes a pixel unit in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix, and a pixel signal readout unit that reads out pixel signals from the pixel unit in units of a plurality of pixels. The pixel signal readout unit is arranged corresponding to the column arrangement of the pixels, and compares and determines the readout signal potential and the reference voltage, and corresponds to a plurality of comparators that output the determination signal. A plurality of counters for counting the comparison time of the comparator, each of the comparators receiving the reference voltage at the gate of one transistor and receiving the read signal at the gate of the other transistor, A first amplifier including a differential amplifier that performs a comparison operation between the voltage and the read signal potential; a second amplifier including an amplifier that increases the output of the first amplifier and outputs the same; and the second amplifier. Having a capacitor for expressing mirror effect that is connected between the input and output of the amplifier.

  A camera system according to a second aspect of the present invention includes a solid-state image sensor and an optical system that forms a subject image on the image sensor, and the solid-state image sensor includes a plurality of pixels that perform photoelectric conversion in a matrix. And a pixel signal readout unit that reads out a pixel signal from the pixel unit in units of a plurality of pixels, and the pixel signal readout unit is arranged corresponding to a column arrangement of pixels. Each of the comparators includes: a plurality of comparators that compare and determine the read signal potential and the reference voltage and output the determination signal; and a plurality of counters that count the comparison time of the corresponding comparator. A first amplifier including a differential amplifier that receives the reference voltage at the gate of one transistor and receives the read signal at the gate of the other transistor and performs a comparison operation between the reference voltage and the read signal potential; It said a second amplifier comprising an amplifier the output of the first amplifier and outputs the gain-up, a capacitor for expressing the connected Miller effect between the input and output of the second amplifier of the amplifier, the.

According to the present invention, the capacitor exhibits a mirror effect, which is equivalent to, for example, a gain-doubled capacitor connected to the source ground input.
The capacitance that appears at the output of the first amplifier is multiplied by the gain as {C * (1 + A _V2 )} where the gain of the amplifier is A _V2 and the capacitance of the capacitor is C. Therefore, the capacitance value of the capacitor is small. Good.

  According to the present invention, it is possible to improve the frame rate while suppressing an increase in area, and to reduce the noise of the AD converter.

It is a block diagram which shows the structural example of the solid-state image sensor (CMOS image sensor) mounted with column parallel ADC which concerns on embodiment of this invention. FIG. 3 is a block diagram showing more specifically an ADC group in the solid-state imaging device (CMOS image sensor) mounted with the column parallel ADC of FIG. 2. It is a figure which shows an example of the pixel of the CMOS image sensor comprised by four transistors which concern on this embodiment. It is a circuit diagram which shows the structural example of the comparator which concerns on this embodiment. It is a figure which shows the operation | movement flow of CDS. It is a figure which shows the formula of a CDS transfer function. It is a figure which shows a frequency vs. CDS gain characteristic. It is a figure which shows typically the filter process in CDS. It is a figure shown about the noise reduction by the filter effect of CDS. FIG. 5 is a diagram showing a comparator as a comparative example of the circuit of FIG. 4. It is a figure which shows the comparison result of the inversion delay with the circuit of FIG. 4 which concerns on embodiment of this invention using the mirror effect and the existing circuit of FIG. 10 set to the same cut-off frequency and does not use the mirror effect. 5 is a timing chart of the comparator in FIG. FIG. 11 is a diagram showing comparison of inversion delays of comparator outputs of the circuit of FIG. 4 and the circuit of FIG. It is a circuit diagram which shows the modification of the comparator which concerns on this embodiment. It is a figure which shows an example of a structure of the camera system with which the solid-state image sensor which concerns on embodiment of this invention is applied.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The description will be given in the following order.
1. 1. Overall configuration example of solid-state imaging device 2. Configuration example of comparator 3. Considerations for CDS 4. Operation of the comparator 5. Modification of comparator Configuration example of camera system

<1. Example of overall configuration of solid-state image sensor>
FIG. 1 is a block diagram illustrating a configuration example of a solid-state imaging device (CMOS image sensor) equipped with a column parallel ADC according to an embodiment of the present invention.
FIG. 2 is a block diagram showing more specifically the ADC group in the column-parallel ADC-mounted solid-state image sensor (CMOS image sensor) of FIG.

As shown in FIGS. 1 and 2, the solid-state imaging device 100 includes a pixel unit 110 as an imaging unit, a vertical scanning circuit 120, a horizontal transfer scanning circuit 130, a timing control circuit 140, and an ADC group as a pixel signal reading unit. 150.
The solid-state imaging device 100 includes a DAC and bias circuit 160 including a DAC (digital-analog converter) 161, an amplifier circuit (S / A) 170, a signal processing circuit 180, and a line memory 190.
Among these components, the pixel unit 110, the vertical scanning circuit 120, the horizontal transfer scanning circuit 130, the ADC group 150, the DAC and bias circuit 160, and the amplifier circuit (S / A) 170 are configured by analog circuits.
The timing control circuit 140, the signal processing circuit 180, and the line memory 190 are configured by digital circuits.

  In the pixel unit 110, for example, pixels as shown in FIG. 3 including photodiodes and in-pixel amplifiers are arranged in a matrix (matrix).

  FIG. 3 is a diagram illustrating an example of a pixel of a CMOS image sensor including four transistors according to the present embodiment.

The pixel circuit 110A includes, for example, a photodiode 111 as a photoelectric conversion element.
The pixel circuit 110A includes the photodiode 111 as the one photoelectric conversion element.
The pixel circuit 110 </ b> A has four transistors as active elements, that is, a transfer transistor 112 as a transfer element, a reset transistor 113 as a reset element, an amplification transistor 114, and a selection transistor 115 for one photodiode 111.

The photodiode 111 photoelectrically converts incident light into charges (here, electrons) in an amount corresponding to the amount of light.
The transfer transistor 112 is connected between the photodiode 111 and the floating diffusion FD as an output node.
The transfer transistor 112 transfers the electrons photoelectrically converted by the photoelectric conversion element 111 to the floating diffusion FD when a drive signal TG is given to its gate (transfer gate) through the transfer control line LTx.

The reset transistor 113 is connected between the power supply line LVDD and the floating diffusion FD.
The reset transistor 113 resets the potential of the floating diffusion FD to the potential of the power supply line LVDD when a reset RST is given to its gate through the reset control line LRST.

The gate of the amplification transistor 114 is connected to the floating diffusion FD. The amplification transistor 114 is connected to the vertical signal line 116 via the selection transistor 115, and constitutes a constant current source and a source follower outside the pixel portion.
Then, a control signal (address signal or select signal) SEL is applied to the gate of the selection transistor 115 through the selection control line LSEL, and the selection transistor 115 is turned on.
When the selection transistor 115 is turned on, the amplification transistor 114 amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the vertical signal line 116. The voltage output from each pixel through the vertical signal line 116 is output to the ADC group 150 serving as a pixel signal readout circuit.
These operations are performed simultaneously for each pixel for one row because, for example, the gates of the transfer transistor 112, the reset transistor 113, and the selection transistor 115 are connected in units of rows.

A reset control line LRST, a transfer control line LTx, and a selection control line LSEL wired to the pixel unit 110 are wired as a set for each row of the pixel array.
These reset control line LRST, transfer control line LTx, and selection control line LSEL are driven by a vertical scanning circuit 120 as a pixel driving unit.

  The solid-state imaging device 100 controls a timing control circuit 140 that generates an internal clock as a control circuit for sequentially reading signals from the pixel unit 110, a vertical scanning circuit 120 that controls row addresses and row scanning, and column addresses and column scanning. A horizontal transfer scanning circuit 130 is disposed.

The timing control circuit 140 is necessary for signal processing of the pixel unit 110, the vertical scanning circuit 120, the horizontal transfer scanning circuit 130, the ADC group (column ADC circuit) 150, the DAC and bias circuit 160, the signal processing circuit 180, and the line memory 190. A timing signal is generated.
The timing control circuit 140 is a control as an initialization signal applied to an initialization (auto zero: AZ) switch (hereinafter referred to as AZ switch) for determining an operation point for each column at the start of row operation of each comparator of the ADC group. Generate a pulse.

The pixel unit 110 photoelectrically converts an image and a screen image for each pixel row by photon accumulation and discharge using a line shutter, and outputs an analog signal VSL to the ADC group.
In the ADC group 150, the ADC block (each column unit) performs an APGA-compatible integral ADC using the ramp signal RAMP from the DAC 161 and digital CDS on the analog output of the pixel unit 110, and outputs a digital signal of several bits. To do.

In the ADC group 150, a plurality of ADCs are arranged.
Each ADC has a reference voltage Vslop, which is a ramp waveform (RAMP) obtained by changing the reference voltage generated by the DAC 161 in a stepped manner, and an analog signal (potential VSL) obtained from a pixel via a vertical signal line for each row line. The comparator (comparator) 151 is compared.
Further, each ADC includes a counter 152 that counts the comparison time and a latch 153 that holds the count result.
The ADC group 150 has an n-bit digital signal conversion function and is arranged for each vertical signal line (column line) to constitute a column parallel ADC block.
The output of each latch 153 is connected to a horizontal transfer line LTRF having a width of 2n bits, for example.
Then, 2n amplifier circuits 170 and signal processing circuits 180 corresponding to the horizontal transfer lines LTRF are arranged.
The specific configuration and function of the comparator 151 will be described in detail later.

In the ADC group 150, an analog signal (potential VSL) read out to the vertical signal line 116 is a reference voltage Vslop (a linearly changing slope with a certain slope) in a comparator 151 arranged for each column (each column). It is compared with the ramp signal RAMP) which is a waveform.
At this time, the counters 152 arranged for each column are operating similarly to the comparator 151, and the ramp signal RAMP (potential Vslop) having a ramp waveform and the counter value change while taking a one-to-one correspondence to each other. The potential VSL of the signal line is converted into a digital signal.
The ADC converts a change in the reference voltage Vslop (ramp signal RAMP) into a change in time, and converts the time into a digital value by counting the time in a certain period (clock).
Then, when the analog signal VSL and the ramp signal RAMP (reference voltage Vslop) intersect, the output of the comparator 151 is inverted, the input clock of the counter 152 is stopped, or the clock whose input has been stopped is input to the counter 152. Input and complete AD conversion.

  After the end of the above AD conversion period, the data held in the latch 153 is transferred to the horizontal transfer line LTRF by the horizontal transfer scanning circuit 130, input to the signal processing circuit 180 through the amplifier 170, and 2 by the predetermined signal processing. A dimensional image is generated.

The horizontal transfer scanning circuit 130 performs simultaneous parallel transfer of several channels in order to ensure the transfer speed.
In the timing control circuit 140, timing necessary for signal processing in each block such as the pixel unit 110 and the ADC group 150 is generated.
In the subsequent signal processing circuit 180, vertical line defects and point defects are corrected from the signals stored in the line memory 190, the signals are clamped, parallel-serial conversion, compression, encoding, addition, averaging, and intermittent operation. Digital signal processing is performed.
The line memory 190 stores a digital signal transmitted for each pixel row.
In the solid-state imaging device 100 of the present embodiment, the digital output of the signal processing circuit 180 is transmitted as an input of an ISP or a baseband LSI.

In the ADC group (pixel signal readout unit) 150 according to the present embodiment, the band is largely limited by using a mirror effect in an amplifier type comparator in order to reduce pixel noise and comparator noise.
The comparator 151 of the present embodiment is configured as follows.

<2. Example of comparator configuration>
Each comparator 151 arranged for each column has a first amplifier and a second amplifier connected in cascade.
A capacitor is connected between the input and output of the common source amplifier of the second amplifier in the second stage. This capacitance exhibits a Miller effect and is equivalent to a gain-multiple capacitance connected to the source ground input.
Thereby, the band of each comparator 151 is greatly narrowed with a small capacity.
Each comparator 151 has a function of performing initialization (auto-zero: AZ) and sampling in order to determine an operating point for each column at the start of a row operation.

Hereinafter, the configuration and function of the comparator 151 of the ADC group (pixel signal readout unit) 150 having the characteristic configuration of the present embodiment will be described in detail.
In the present embodiment, the first conductivity type is p channel or n channel, and the second conductivity type is n channel or p channel.
The following comparator will be described with reference numeral 200.

  FIG. 4 is a circuit diagram illustrating a configuration example of the comparator according to the present embodiment.

  As shown in FIG. 4, the comparator 200 includes a first amplifier 210 and a second amplifier 220 that are connected in cascade, and a capacitor C230 that exhibits a mirror effect.

  The first amplifier 210 includes p-channel MOS (PMOS) transistors PT211 to PT214, n-channel MOS (NMOS) transistors NT211 to NT213, and first and second capacitors C211 and C212 as AZ level sampling capacitors.

The source of the PMOS transistor PT211 and the source of the PMOS transistor PT212 are connected to the power supply potential source VDD.
The drain of the PMOS transistor PT211 is connected to the drain of the NMOS transistor NT211 and a node ND211 is formed by the connection point. Further, the drain and gate of the PMOS transistor PT211 are connected, and the connection point is connected to the gate of the PMOS transistor 212.
The drain of the PMOS transistor PT212 is connected to the drain of the NMOS transistor NT212, and an output node ND212 of the first amplifier 210 is formed by the connection point.
The sources of the NMOS transistor NT211 and the NMOS transistor NT212 are connected to each other, and the connection point is connected to the drain of the NMOS transistor NT213. The source of the NMOS transistor NT213 is connected to a reference potential source (for example, ground potential) GND.

The gate of the NMOS transistor NT211 is connected to the first electrode of the capacitor C211 and a node ND213 is formed by the connection point. The second electrode of the capacitor C211 is connected to the input terminal TRAMP for the ramp signal RAMP.
The gate of the NMOS transistor NT212 is connected to the first electrode of the capacitor C212, and a node ND214 is formed by the connection point. The second electrode of the capacitor C212 is connected to the input terminal TVSL for the analog signal VSL.
The gate of the NMOS transistor NT213 is connected to the input terminal TBIAS for the bias signal BIAS.
The source of the PMOS transistor PT213 is connected to the node ND211 and the drain is connected to the node ND213. The source of the PMOS transistor PT214 is connected to the node ND212, and the drain is connected to the node ND214.
The gates of the PMOS transistors PT213 and PT214 are commonly connected to the input terminal TPSEL of the first AZ signal PSEL which is active at a low level.

In the first amplifier 210 having such a configuration, a current mirror circuit is configured by the PMOS transistors PT211 and PT212, and a differential comparison unit using the NMOS transistor NT213 as a current source is configured by the NMOS transistors NT211 and NT212.
The PMOS transistors PT213 and PT214 function as AZ switches, and the capacitors C211 and C212 function as AZ level sampling capacitors.
The output signal 1stcomp of the first amplifier 210 is output from the output node ND212 to the second amplifier 220.

  The second amplifier 220 includes a PMOS transistor PT221, NMOS transistors NT221 and NT222, and a third capacitor C221 as an AZ level sampling capacitor.

The source of the PMOS transistor PT221 is connected to the power supply potential VDD, and the gate is connected to the output node ND212 of the first amplifier 210.
The drain of the PMOS transistor PT221 is connected to the drain of the NMOS transistor NT221, and an output node ND221 is formed by the connection point.
The source of the NMOS transistor NT221 is connected to the ground potential GND, the gate is connected to the first electrode of the capacitor C221, and a node ND222 is formed by the connection point. A second electrode of the capacitor C221 is connected to the ground potential GND.
The drain of the NMOS transistor NT222 is connected to the node ND221, and the source is connected to the node ND222.
The gate of the NMOS transistor NT222 is connected to the input terminal TNSEL of the second AZ signal NSEL which is active at a high level.
The second AZ signal NSEL takes a level complementary to the first AZ signal PSEL supplied to the first amplifier 210.

In the second amplifier 220 having such a configuration, an input and amplifier circuit is configured by the PMOS transistor PT221.
The NMOS transistor NT222 functions as an AZ switch, and the capacitor C221 functions as an AZ level sampling capacitor.
The output node ND221 of the second amplifier 220 is connected to the output terminal TOUT of the comparator 200.

The capacitor C230 has a first electrode connected to the gate (input) of the PMOS transistor PT221 as a common source amplifier, and a second electrode connected to the drain (output) of the PMOS transistor PT221.
This capacitor C230 exhibits a Miller effect, and is equivalent to a capacitor having a gain multiplied by the source ground input.
Capacity visible in the output of the first amplifier 210, the gain of the PMOS transistor PT221 and _{A V2,} and the capacitance of the capacitor C230 is C, the capacitor C230 from being gain-multiplied as _{{C * (1 + A V2} )} The capacitance value may be small.
As a result, the bandwidth of the comparator 200 is greatly narrowed with a small capacity.

<3. Considerations for CDS>
Next, a CDS (correlated double sampling) using an ADC including the comparator 200 (151) having the above configuration will be considered.

  FIG. 5 is a diagram showing an operation flow of the CDS.

  In the CDS, as shown in FIG. 5, first, AD conversion of the reset level of the pixel is performed (ST1), then AD conversion of the actual signal is performed (ST2), and the difference becomes final data (ST3).

6 and 7 are diagrams showing a CDS transfer function. FIG. 6 shows an expression of the CDS transfer function, and FIG. 7 is a diagram showing frequency vs. CDS gain characteristics.
FIG. 8 is a diagram schematically showing filter processing in CDS.

As shown in FIGS. 6 and 7, the CDS shows band-pass transfer characteristics.
Then, as shown in FIG. 8, pixel noise and noise of the comparator itself are filtered by CDS.
That is, as the cutoff frequency ω _C of the comparator is lowered due to the mirror effect, the noise of the entire solid-state imaging device is reduced due to the transfer characteristic of the CDS.

9A to 9C are diagrams illustrating noise reduction due to the CDS filter effect.
FIG. 9A shows input conversion noise before CDS, FIG. 9B shows CDS gain, and FIG. 9C shows input conversion noise after CDS.
9B and 9C, a curve A shows the characteristics of the circuit according to the embodiment of the present invention, and a curve B shows the characteristics of the existing circuit.

The noise spectrum after CDS is obtained by multiplying the noise of the pixel + ADC (AD converter) by the CDS transfer characteristic.
It can be seen that the level of the noise spectrum is lowered due to the comparator band limitation due to the mirror effect.

  FIG. 10 shows a comparator as a comparative example of the circuit of FIG.

In the comparator 200C of FIG. 10, a capacitor (capacitance) C240 is connected to the output of the first amplifier (differential amplifier) 210 in the first stage without using the Miller effect, so that the band can be limited.
However, in the comparator 200C, when the band is largely limited, there is a problem that the capacity increases and the charge / discharge time for the capacity increases, so that the slew rate deteriorates and the inversion delay of the comparator itself increases.

  FIG. 11 is a diagram showing a comparison result of inversion delay between the existing circuit of FIG. 10 that does not use the mirror effect and the circuit of FIG. 4 according to the embodiment of the present invention that uses the mirror effect, set to the same cutoff frequency. .

As shown in FIG. 11, the circuit of the present invention has a smaller inversion delay amount than the existing circuit.
When the inversion delay of the comparator increases, the AD conversion time must be extended, and as a result, the frame rate must be reduced.

Thus, in the comparator 200 of this embodiment, random noise can be reduced without reducing the frame rate by limiting the band using the mirror effect.
Furthermore, since mounting with a small capacity is sufficient, it is advantageous in terms of area and cost.

<4. Operation of comparator>
Next, the operation of the comparator 200 according to the present embodiment will be described with reference to the timing chart of FIG.
In FIG. 12, only the second AZ signal NSEL supplied to the second amplifier 220 is shown as the AZ signal. As described above, the first AZ signal PSEL takes a level complementary to the second AZ signal NSEL. That is, when the second AZ signal NSEL is at a high level, the first AZ signal PSEL is at a low level, and when the second AZ signal NSEL is at a low level, the first AZ signal PSEL is at a high level.

In the comparator 200, during the AZ period, the first AZ signal PSEL is supplied at a low level and the second AZ signal NSEL is supplied at a high level. As a result, the PMOS transistors PT213 and PT214 as the AZ switch of the first amplifier 210 are turned on. Similarly, the NMOS transistor NT222 as the AZ switch of the second amplifier 220 is turned on.
As described above, the ADC group 150 uses the comparator 200 to sample the DAC offset level, the pixel reset level, and the AZ level for each column, and charge the capacitors C211, C212, and C221 that are AZ level sampling capacitors. Store.

Next, when the AZ period ends, the first AZ signal PSEL is switched to the high level and the second AZ signal NSEL is switched to the low level. As a result, the PMOS transistors PT213 and PT214 as the AZ switch of the first amplifier 210 are turned off. Similarly, the NMOS transistor NT222 as the AZ switch of the second amplifier 220 is turned off.
Thereby, the integration type AD conversion (hereinafter referred to as P phase) at the pixel reset level is started.

In the first amplifier 210 of the comparator 200, in the P-phase, the gate-side nodes ND213 and ND214 of the NMOS transistors NT211 and NT212 of the capacitors C211 and C212, which are sampling capacitors accumulated at the time of AZ, are in a high impedance (HiZ).
For this reason, the gate inputs of the NMOS transistors NT211 and NT212 constituting the differential transistor change following the change of the ramp wave of the ramp signal RAMP by the DAC 161, and the comparison with the VSL level as the pixel signal is started.
Then, after the intersection of the ramp signal RAMP and the pixel signal, the output signal 1stcomp of the first amplifier 210 changes sharply.
As a result, the PMOS transistor PT221 of the second amplifier 220 is turned on, the current I1 begins to flow, and the output 2ndOUT of the second amplifier 220 changes from the low level (L) to the high level (H).

  Also in the D phase, the comparator 200 performs the same operation as that of the P phase for each column, so that kTC noise and pixel reset noise can be canceled as a result of digital CDS (timing chart of FIG. 12: D phase period). .

FIGS. 13A and 13B are diagrams comparing the inversion delays of the comparator outputs of the circuit of FIG. 4 and the circuit of FIG. 10 according to the embodiment of the present invention.
FIG. 13A shows the comparator output of the existing circuit, and FIG. 13B shows the comparator output of the circuit according to the embodiment of the present invention.

FIG. 13A shows a timing chart when the band is limited by an existing method.
As shown in FIG. 13A, when the inversion delay is large, it is necessary to extend the P phase / D phase period, and as a result, the frame rate is lowered.

FIG. 13B shows a case where the band is limited by the circuit of FIG. 4 according to the embodiment.
In the case of FIG. 13B, since the P-phase / D-phase period is reduced as compared with FIG. 13A, the 1H timing can be reduced, and as a result, the frame rate can be increased.

<5. Modified Example of Comparator>
FIG. 14 is a circuit diagram showing a modification of the comparator according to the present embodiment.

The comparator 200A of FIG. 14 is configured with the polarity of the transistor of the comparator 200 of FIG. For this reason, the power supply potential to be connected and the ground potential are also reversed in the circuit.
In FIG. 14, the same reference numerals as those in FIG. 5 are assigned to the nodes and capacitors for easy understanding.

In the first amplifier 210A, a differential comparison unit and a current source are configured using PMOS transistors PT215 to PT217 instead of the NMOS transistors NT211 to NT213 in FIG. The source of the PMOS transistor PT217 as a current source is connected to the power supply potential VDD.
Further, instead of the PMOS transistors PT211 and PT212 of FIG. 4, NMOS transistors NT214 and NT215 are used to form a current mirror circuit, and the sources of the NMOS transistors NT214 and NT215 are connected to the ground potential GND.
Further, an AZ switch is configured using NMOS transistors NT216 and NT217 instead of the PMOS transistors PT213 and PT214 of FIG. In this case, the second amplifier AZ is supplied with the second AZ signal NSEL to the gates of the NMOS transistors NT216 and NT217.

In the second amplifier 220A, an input and amplifier circuit is configured using an NMOS transistor NT223 instead of the PMOS transistor PT221 of FIG. The source of the NMOS transistor NT223 is connected to the ground potential GND.
Instead of the NMOS transistor NT221 of FIG. 4, a PMOS transistor PT222 is used to form a transistor that forms a mirror circuit. The source of the PMOS transistor PT222 is connected to the power supply potential VDD. The first electrode of the capacitor C221 is connected to the node ND222 connected to the gate of the PMOS transistor PT222, and the second electrode is connected to the power supply potential VDD.
Further, an AZ switch is configured using a PMOS transistor PT223 instead of the NMOS transistor NT222 of FIG. In this case, the first amplifier AZ is supplied with the first AZ signal PSEL to the gate of the PMOS transistor PT223.

The capacitor C230A has a first electrode connected to the gate (input) of the NMOS transistor NT223 as a common source amplifier, and a second electrode connected to the drain (output) of the NMOS transistor NT223.
This capacitor C230A exhibits a Miller effect, and is equivalent to a capacitor having a gain multiplied by the source ground input.
Capacity visible in the output of the first amplifier 210A has a gain of the NMOS transistors NT223 and _{A V2,} and the capacitance of capacitor C230A and _{C, {C * (1 +} A V2)} from being gain multiple capacitors C230A as The capacitance value may be small.
Thereby, the bandwidth of the comparator 200A is greatly narrowed with a small capacity.

The comparator 200A of FIG. 14 having such a configuration basically operates in the same manner as the comparator 200 of FIG. However, the waveforms of RAMP, 1st comp, and 2nd Amp in the timing chart of FIG.
Then, according to the comparator 200A of FIG. 14, the same effects as those of the comparator 200 of FIG. 4 can be obtained.

As described above, according to this embodiment, the pixel unit 110 in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix, and the pixel signal reading unit (ADC) that reads data from the pixel unit 110 in units of rows. Group) 150.
The ADC group 150 is arranged corresponding to the column arrangement of pixels, compares and determines the readout signal potential and the reference voltage, and counts the comparison time of the corresponding comparators that output the determination signal. And a plurality of counters 152.
Each comparator 151 is connected between the input and output of the first amplifier 210, the second amplifier 220 cascaded to the first amplifier 210 and increasing the output of the first amplifier 210, and the source grounded amplifier of the second amplifier. And a capacitor C230 for expressing the mirror effect.
Therefore, according to the present embodiment, the following effects can be obtained.

In other words, pixel noise and comparator noise can be reduced by greatly reducing the bandwidth of the comparator due to the mirror effect of the capacitor.
Since the mirror effect is used to reduce the bandwidth of the comparator, noise can be reduced while the inversion delay of the comparator is small. Since the inversion delay does not deteriorate, the frame rate is not lowered.
Since the mirror effect is used to reduce the bandwidth of the comparator, the bandwidth can be greatly reduced with a small capacity. In order to achieve the same noise reduction effect, the area and cost can be reduced compared to the existing methods.

  A solid-state imaging device having such an effect can be applied as an imaging device for a digital camera or a video camera.

<6. Configuration example of camera system>
FIG. 15 is a diagram illustrating an example of a configuration of a camera system to which the solid-state imaging device according to the embodiment of the present invention is applied.

As shown in FIG. 15, the camera system 300 includes an imaging device 310 to which the CMOS image sensor (solid-state imaging device) 100 according to the present embodiment can be applied.
The camera system 300 includes an optical system that guides incident light (images a subject image) to a pixel region of the imaging device 310, for example, a lens 320 that forms incident light (image light) on an imaging surface.
The camera system 300 includes a drive circuit (DRV) 330 that drives the imaging device 310 and a signal processing circuit (PRC) 340 that processes an output signal of the imaging device 310.

  The drive circuit 330 includes a timing generator (not shown) that generates various timing signals including a start pulse and a clock pulse that drive a circuit in the imaging device 310, and drives the imaging device 310 with a predetermined timing signal. .

Further, the signal processing circuit 340 performs predetermined signal processing on the output signal of the imaging device 310.
The image signal processed by the signal processing circuit 340 is recorded on a recording medium such as a memory. The image information recorded on the recording medium is hard copied by a printer or the like. The image signal processed by the signal processing circuit 340 is displayed as a moving image on a monitor including a liquid crystal display.

  As described above, a high-precision camera can be realized by mounting the above-described solid-state imaging device 100 as the imaging device 310 in an imaging apparatus such as a digital still camera.

  DESCRIPTION OF SYMBOLS 100 ... Solid-state image sensor, 110 ... Pixel part, 120 ... Vertical scanning circuit, 130 ... Horizontal transfer scanning circuit, 140 ... Timing control circuit, 150 ... ADC group, 151 ... Comparator, 152 ... Counter, 153 ... Latch, 160 ... DAC, 170 ... Amplifier circuit, 180 ... Signal processing circuit, 190 ... Line memory, LTRF ... Horizontal transfer Line, 200, 200A ... Comparator, 210, 210A ... First amplifier, 220, 220A ... Second amplifier, C230, C230A ... Capacitor, 300 ... Camera system, 310 ... Imaging device, 320 ... lens, 330 ... drive circuit, 340 ... signal processing circuit.

Claims (9)

A pixel unit in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix;
A pixel signal readout unit that reads out pixel signals from the pixel unit in units of a plurality of pixels,
The pixel signal readout unit is
A plurality of comparators that are arranged corresponding to the column arrangement of pixels, compare and determine a read signal potential and a reference voltage, and output a determination signal;
A plurality of counters for counting the comparison time of the corresponding comparators,
Each of the above comparators
Non-feedback type,
The reference voltage is received at the gate of one transistor, the read signal is received at the gate of the other transistor, and the reference voltage and the read signal potential are compared, and the reference voltage and the read signal potential are equal. A first amplifier including a differential amplifier that inverts the output level when the level is reached;
A second amplifier including an amplifier that inverts the level of the inverted output of the first amplifier in response to the inverted output and increases the gain;
A solid-state imaging device comprising: a capacitor connected between the input and output of the amplifier of the second amplifier for expressing a mirror effect and limiting the bandwidth of the comparator . The pixel signal readout unit is
An analog-to-digital (AD) conversion function for converting a pixel signal read from the pixel by the corresponding comparator and the counter from an analog signal to a digital signal;
A first AD conversion for AD conversion of the pixel signal at the reset level of the pixel and a second AD conversion for AD conversion of the pixel signal that is an actual signal of the pixel are performed, and the data and the second AD conversion by the first AD conversion are performed. anda correlated double sampling (CDS) function of the final data the difference between the Ru good data,
The capacitor is
The solid-state imaging device according to claim 1, having a function of lowering a cutoff frequency of the comparator.

The capacitor connected between the input and output of the second amplifier is {C * (1 + A _V2 )} when viewed from the output of the first amplifier, where A _V2 is the gain of the amplifier and C is the capacitance of the capacitor. The solid-state imaging device according to claim 1 or 2, wherein the gain is multiplied as follows. The amplifier of the second amplifier is formed of a source-grounded field effect transistor whose gate is supplied with the output of the first amplifier,
The solid-state imaging device according to any one of claims 1 to 3, wherein the capacitor is connected between a gate and a drain of the common-source field-effect transistor. The first amplifier is
The differential transistor that receives the reference voltage at the gate of one transistor and the read signal at the gate of the other transistor and performs a comparison operation between the reference voltage and the read signal potential;
An initialization switch for determining an operating point for each column at the start of row operation connected between the gate and drain of the differential transistor;
5. The solid-state imaging device according to claim 1, further comprising: a first capacitor and a second capacitor for sampling connected to each gate of the differential transistor. The second amplifier is
An initialization switch to determine the operating point for each column at the start of row operation;
The solid-state imaging device according to claim 5, further comprising: a third capacitor for sampling at initialization. The second amplifier is
A first conductivity type field effect transistor in which an output of the first amplifier is input to a gate;
A second conductivity type field effect transistor connected in series with the first conductivity type field effect transistor, wherein the initialization switch is disposed between the gate and the drain, and the gate is connected to the third capacitor. And
An output node is formed by a connection point of the first conductivity type field effect transistor and the second conductivity type field effect transistor,
The solid-state imaging device according to claim 6, wherein the capacitor for expressing the mirror effect is connected between a gate and a drain of the first conductivity type field effect transistor. A solid-state image sensor;
An optical system for forming a subject image on the image sensor,
The solid-state imaging device is
A pixel unit in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix;
A pixel signal readout unit that reads out pixel signals from the pixel unit in units of a plurality of pixels,
The pixel signal readout unit is
A plurality of comparators that are arranged corresponding to the column arrangement of pixels, compare and determine a read signal potential and a reference voltage, and output a determination signal;
A plurality of counters for counting the comparison time of the corresponding comparators,
Each of the above comparators
Non-feedback type,
The reference voltage is received at the gate of one transistor, the read signal is received at the gate of the other transistor, and the reference voltage and the read signal potential are compared, and the reference voltage and the read signal potential are equal. A first amplifier including a differential amplifier that inverts the output level when the level is reached;
A second amplifier including an amplifier that inverts the level of the inverted output of the first amplifier in response to the inverted output and increases the gain;
And a capacitor for limiting the bandwidth of the comparator by developing a mirror effect connected between the input and output of the amplifier of the second amplifier. The pixel signal readout unit is
An analog-to-digital (AD) conversion function for converting a pixel signal read from the pixel by the corresponding comparator and the counter from an analog signal to a digital signal;
A first AD conversion for AD conversion of the pixel signal at the reset level of the pixel and a second AD conversion for AD conversion of the pixel signal that is an actual signal of the pixel are performed, and the data and the second AD conversion by the first AD conversion are performed. anda correlated double sampling (CDS) function of the final data the difference between the Ru good data,
The capacitor is
The camera system according to claim 8, having a function of reducing a cutoff frequency of the comparator.

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