JP3064703B2 - Sample hold circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit, and more particularly to a sample and hold circuit for reducing low frequency 1 / f noise and reset pulse noise of an image signal obtained from a CCD image sensor.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional sample-hold circuit corresponding to a CCD image sensor constituted by connecting a feed-through clamp circuit and a video signal sample-hold circuit in series.

As shown in FIG. 4, a conventional sample-and-hold circuit 41 includes a CCD image sensor 70, a capacitor 71, a comparator 73, and a differential amplifier 7.
2, a sample holder 42 including buffer amplifiers 44, 47, a feed-through clamp capacitor 45, a sample-hold capacitor 49, a feed-through clamp switch 46, and a sample-hold switch 48; Amplifiers 54 and 57, feed-through capacitor 55, sample-and-hold capacitor 59, and feed-through clamp switch 5
6, a sample holder 43 including a sample hold switch 58, a feed-through clamp reference voltage source 61, and a feedback clamp control voltage source 60.
And terminals 62 to 66.

FIG. 3 shows the CCD of FIG.
FIG. 7 is an operation waveform diagram of an image output signal output from the image sensor 70.

An image output signal for each pixel output from the CCD image sensor 70 is, as shown in FIG.
A reset noise period t1 and a feed-through period t that occur because a reset pulse applied to clear the charge of the previous pixel during charge transfer inside the CCD leaks to the output.
2, and a video signal period t3.
The signal required as the level of the video signal is a difference voltage A between the voltage of the feedthrough period t2 and the voltage of the video signal period t3.
It is expressed as Of these, the reset noise has nothing to do with the video signal level, and when the video signal level is low, the signal is buried in the reset noise and the S / N ratio is degraded.

[0006] Also, low frequency 1 / f noise is usually superimposed on the image output signal output from the CCD image sensor 70, and if the low frequency 1 / f noise is not removed, it is necessary to remove the low frequency 1 / f noise. Since the brightness changes, the image quality deteriorates.

[0007] These reset noise and low frequency 1 / f
In order to remove noise, a sample-and-hold circuit 41 for a CCD image sensor output signal shown in FIG. 4 has been proposed.

An image output signal from the CCD image sensor 70 input from the input terminal 62 is input to the sample holder 42, and is supplied to a feed-through clamp capacitor 45 via a buffer amplifier 44 in the sample holder 42. With the through clamp switch 46, the voltage of the image input signal during the feedthrough period t2 is clamped for each pixel through a feedthrough / calamp action for adjusting the voltage to the clamp reference voltage VR,
Low frequency 1 / f noise is removed. Here, the clamp reference voltage VR is a voltage set by the feedthrough / clamp control voltage source 61.

Next, the signal voltage of the maximum amplitude level during the video signal period is sampled and held by the buffer amplifier 47, the sampling switch 48, and the holding capacitor 48, and output via the output terminal 64.
The image signal output from the output terminal 64 is a video signal based on a feed-through voltage from which low frequency 1 / f noise has been removed and reset noise and feed-through periods t1 and t2 have been removed.

In order to remove the fluctuation component of the clamp reference voltage VR and the sampling noise at the time of sampling and holding, a buffer amplifier 54, a capacitor 55 for a feed-through clamp, a switch 56 for a feed-through clamp, and a buffer amplifier. A non-signal-side sample holder 43 including a sampling switch 58 and a holding capacitor 59 is provided in parallel with the same circuit configuration as the signal-side sample holder 42.
Output signals of output terminals 64 and 65 corresponding to these sample holders 42 and 43 are input in a differential manner to a differential amplifier 72 using a constant current source having an excellent common mode rejection rate, and output of a clamp reference voltage VR. A fluctuating voltage component and sampling noise are removed, and an image signal having an excellent S / N ratio is output.

Further, even if the clamp reference voltage VR is common to the signal side sample holder 42 and the non-signal side sample holder 43, the corresponding feed-through clamp switches 46 and 56 and the buffer amplifiers 47 and 57 respectively. , Sampling switch 4
Offset voltages often occur in the DC voltages obtained at the output terminals 64 and 65 due to variations at 8 and 48 and the like.

When the differential amplifier 72 connected to the output terminals 64 and 65 also has a function as an AGC (automatic gain control amplifier) for amplifying a signal level at low illuminance, its maximum The gain is 40 dB (1
In this case, the DC voltage offset at the output terminals 64 and 65 is amplified by the gain, so that the output DC voltage of the differential amplifier 72 is reduced. In some cases, it may change greatly, preventing normal operation. Corresponding to this case, as shown in FIG. 4, a comparator 73 is provided so that the DC voltages at the output terminals 64 and 65 of the sample holders 42 and 43 have the same potential. Are compared by a comparator 73, and the comparison output voltage is input to a feedback clamp control voltage source 60 via a terminal 66 to perform feedback clamp control such that the clamp control voltage VC on the non-signal side is varied. Has become. As shown in FIG. 4, the circuit for varying the clamp reference voltage varies the voltage on the signal-side clamp switch 46, not on the side connected to the no-signal-side clamp switch 56. However, there is no problem in characteristics.

[0013]

In the above-described conventional sample and hold circuit 41, the image output signal W output from the CCD image sensor 70 every one horizontal period is provided.
As shown in FIG. 2, reference numeral 1 denotes a signal period and the first of optical black (hereinafter, referred to as OB) which outputs an ideal black signal by covering a photodiode on a CCD image sensor with aluminum. OB, a vacant transfer section T2 in which an indefinite signal is output without a photodiode or a CCD transfer section, and a third period T3 of OB, which is used for the conventional CCD image sensor 70 described above. In the sample-and-hold circuit 41, the period during which the feedback clamp for absorbing the offset of the DC voltage of the output terminals 64 and 65 is applied is only the OB period of the image output signal W1 from the CCD image sensor 70. is there. In FIG. 4, the signal applied to the next-stage amplifier is given by the differential form of output terminals 64 and 65, the DC voltage output from output terminal 65 on the non-signal side is black level, It is necessary to compare and match with the DC voltage in the OB period output from the output terminal 64.

However, the OB period signal once used in the feedback clamp is damaged by the clamp, and if the signal is used more than once at the same timing due to the clamp, there is a possibility that the clamp is displaced. .

Further, the OB period of a general CCD image sensor is about 3 μsec in a portion corresponding to the first OB period T1 shown in FIG. 2, and about 0.2 μsec in the second OB period T2. Accordingly, in the OB period T1, the feedback clamp can be applied twice with the timing shifted, but in the OB period T2, it is difficult to apply the feedback clamp because the period is extremely short. For convenience, only two feedback clamps can be used in one horizontal period. However, in the image signal processing corresponding to the CCD image sensor, it is necessary to perform at least the black level adjustment in the γ amplification section and, at the time of blanking, further feedback clamp in the color separation output section. A minimum of two or three feedback clamps are performed. For this reason, the current CCD image sensor has a disadvantage that the OB period is short, and it is difficult to clamp the OB period in the next stage. In particular, the feedback clamp in the conventional sample and hold circuit 41 shown in FIG. 4 is preferably performed in a period other than the OB period in consideration of the clamp in the OB period in the subsequent signal processing, but cannot be performed in the conventional example.

An object of the present invention is to solve the above-mentioned drawbacks,
An object of the present invention is to provide a sample-and-hold circuit capable of performing a B-period clamp.

[0017]

A first configuration of a sample and hold circuit according to the present invention comprises a first buffer amplifier to which an image output signal of a CCD image sensor is input and a clamp of the output of the first buffer amplifier. A first sampler that samples and holds the output of the first clamper and outputs the same; a second buffer amplifier whose input is AC grounded to low impedance; and A second clamp circuit that clamps the output of the second buffer amplifier, and a second sample holder that samples and holds the output of the second clamp circuit and outputs the result. The operation of the first and second buffer amplifiers is stopped during the period so that feedback is applied even during periods other than the optical black period in the image output signal. And characterized in that a means for operating said first, second clamp circuit.

According to a second configuration of the present invention, there is provided a first buffer amplifier which receives an image output signal of a CCD image sensor from a first signal input terminal and stops operation by a predetermined output offset voltage absorption operation control signal. And a first clamping circuit for clamping the voltage level of the output of the first buffer amplifier to a predetermined reference clamping voltage with a predetermined clamping operation control signal and the predetermined output offset voltage absorbing operation control signal and outputting the clamped voltage.
And a first clamp circuit, which receives an output signal of the first clamp circuit, samples and holds a voltage level of the output signal with a predetermined sampling operation control signal, and outputs the sampled voltage level to a first signal output terminal. Sample holder and second
Is connected to the input of a second buffer amplifier that is grounded with an AC low impedance and stops operating with a predetermined output offset voltage absorption operation control signal, and outputs the output voltage of the second buffer amplifier. A second clamp circuit that clamps and outputs the clamp operation signal and the predetermined output offset voltage absorption operation signal to a clamp voltage supplied by predetermined voltage varying means, and an output signal of the second clamp circuit; A second sample holder that samples and holds the voltage level of the output signal with a sampling operation control signal similar to that of the first sample holder and outputs the same to a second signal output terminal. The clamp voltage in the clamp circuit changes the output voltage level at the first and second signal output terminals to the predetermined output offset. By comparing the output voltage levels of the first and second signal output terminals so as to have the same potential by comparing in the absorption operation control signal period, the first and second outputs are provided. The output signal at the terminal is output in a reverse phase relationship.

[0019]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a sample and hold circuit according to one embodiment of the present invention.

As shown in FIG. 1, the sample and hold circuit 1 of this embodiment comprises a CCD image sensor 30, a capacitor 31, a comparator 33 and a differential amplifier 32.
In response to the above, the buffer amplifier 4 and the feed-through clamp capacitor 5 which stop the operation at the time of the feedback clamp, the feed-through clamp switch 6 and the buffer amplifier 7 which are closed at the time of the feed-through clamp and the feedback clamp, and A sample holder 2 including a sampling switch 8 and a holding capacitor 9 which are closed during sampling;
The buffer amplifier 14 which stops the operation at the time of clamping, the capacitor 15 for the feed-through clamp, the switch 16 for the feed-through clamp which is closed at the time of the feed-through clamp and the feedback clamp, the buffer amplifier 17, and the switch for the sampling which is closed at the time of sampling. A sample holder 3 including a capacitor 18 and a holder capacitor 19, a feedback clamp control voltage source 20, and a feed-through clamp reference voltage source 2.
1 and is configured.

In FIG. 1, the capacitor 5 and the switch 6 and the capacitor 15 and the switch 16
A clamp circuit that operates through the same clamp operation control signal is formed, and the switch 8, the capacitor 9, the switch 18, and the capacitor 19 are connected to the sample circuit that operates through the same sampling operation control signal. An AND hold circuit is formed.

This embodiment is different from the above-mentioned conventional example in that:
The operation of the buffer amplifiers 4 and 14 is stopped during the feeder back clamp operation, and the feedback clamp operation signal is input from the terminal 28, and the signals from the input terminals 22 and 23 are not transmitted to the feed-through capacitors 5 and 15. That is, in the feed-through clamp switches 6 and 16, when the feedback clamp operation signal input from the terminal 28 is applied during the feedback clamp, the feed-through clamp operation signal input from the terminal 27 is applied. It is always closed regardless.

The image output signal W1 for each pixel output from the CCD image sensor 30 is, as described above,
Reset noise caused by a reset pulse leaking to the output, feedthrough, and three periods t of the video signal
The signal required as the level of the video signal, which is divided into 1, t2, and t3, is represented as a difference voltage A between the voltage in the feedthrough period and the voltage in the video signal period (see FIG. 3).
This video output signal W1 is input to the sample holder 2 via the terminal 22.

In the sample holder 2, the voltage of the image input signal during the feed-through period t2 is changed to the clamp reference voltage by the feed-through clamp capacitor 5 and the feed-through clamp switch 6 via the buffer amplifier 4. The signal voltage at the maximum amplitude level in the video signal period is sampled and held by the buffer amplifier 7, the sampling switch 8, and the holding capacitor 9, and output via the output terminal 24. The image signal output from the output terminal 24 has the low frequency 1 / f noise removed, the reset noise and the feedthrough period t1, t2 removed, as in the above-described conventional example. It is output as a voltage-based video signal.

The input terminal 23 on the non-signal side is connected to a capacitor 2 to prevent a disturbance signal such as noise from entering.
The buffer amplifier 14 is connected to the ground via the reference 3 and has a low impedance in an AC manner. The buffer amplifier 14 is similar to the sample holder 2 on the signal side. The signal is input to a sample / hold 3 comprising a sampling switch 18, a sampling switch 18 and a holding capacitor 19, and its output is output via an output terminal 25 on the non-signal side. Needless to say, the sample holder 2 on the signal side and the sample holder 3 on the non-signal side are constituted by similar circuits.

The feed-through clamp reference voltage source 21 is connected to the feed-through clamp switch 6 on the signal side.
Feed-through reference voltage VR is supplied by
Switch 16 for feedthrough clamp on non-signal side
The feedthrough reference voltage VR from the feedthrough reference voltage source 21 and the feedthrough clamp VR
Control voltage source 2 for feedback clamp superimposed on
A control voltage VC of 0 is supplied. The control voltage VC is compared between the output of the signal side output terminal 24 and the output of the non-signal side output terminal 25 by the comparator 33 during the feedback clamp period.
6, a control voltage source 20 for feedback clamp
Is a control voltage that is fed back to the output terminals 24 and 25 by this feedback action.
Are controlled to be the same. Also, by making the feedthrough / clamp operation control signals applied to the feedthrough / clamp switches 6 and 16 the same and the sampling operation signals applied to the sampling switches 8 and 18 to be the same, the sampling noise and the clamp Since the fluctuation component of the reference voltage VR is output from the output terminals 24 and 25 in the same phase, by configuring the differential amplifier 32 with a differential amplifier having an excellent common mode rejection rate and using a constant current source,
Characteristics higher than those of the conventional example shown in FIG. 4 are obtained.

During the video signal period of the image output signal output from the CCD image sensor 30, a feedback clamp stop signal is supplied to the feedback clamp operation signal input terminal 28, and the buffer amplifiers 4 and 14 In operation, the feed-through clamp switches 6 and 16 and the sampling switches 8 and 18 perform clamping and sampling for each pixel, respectively, and the comparator 33 is set to an off state. . Therefore, the control voltage VC by the feedback clamp control signal applied during the feedback clamp period is maintained at the same level.

Next, during the feedback clamp period, the feedback clamp operation signal is supplied to the feedback clamp operation signal input terminal 28, and the buffer amplifiers 4 and 14 stop operating.
The signals from input terminals 22 and 23 are fed-through
The voltage is not applied to the capacitors 5 and 15 for clamping, and the switches 6 and 1 for feed-through clamping are not applied.
6 is closed and switches 8 and 1 for sampling
At 8, sampling is performed at the timing of each pixel.

For this reason, the signals output to the output terminals 24 and 25 are only DC potentials including no AC signal regardless of the output from the CCD image sensor 30. Only the DC voltage components output to 24 and 25 are compared and a comparison result is output. As described above, since the signal component from the CCD image sensor can be ignored, it is possible to perform the feedback clamp even in the idle transfer section other than the OB period. If feedback clamping can be performed in this empty transfer section, CCD
The fear of damaging the OB period due to the feedback clamp in the sample and hold circuit for the image sensor is eliminated, and the entire OB period can be used in the signal processing unit after the sample and hold.

In the idle transfer section T2 shown in FIG. 2, there are cases where the potential during the OB period and the DC offset voltage exist. In such a case, all of the idle transfer section T2 is clamped by the feedback clamp. In the case of the period, only the DC potential is output to the output terminals 24 and 25, the offset voltage component of the idle transfer portion is not output to the differential amplifier 32, and the potential in the OB period is output instead.

Therefore, even when the differential amplifier 32 has a high gain, if the idle transfer portion has an offset voltage in the direction opposite to the signal side, the inversion component is not generated in the conventional sample and hold circuit. Even in a state where the problem is large and circuit saturation or the like becomes a problem, the present embodiment eliminates any problem.

In this embodiment, the buffer amplifiers 4 and 1
If the switch 4 is not operating during the feedback clamp period, its output voltage becomes indefinite, so that the switches 6 and 16 for the feed-through clamp must be closed.

If the output impedance of buffer amplifiers 4 and 14 is sufficiently larger than the impedance of the voltage supplied from feed-through clamp switches 6 and 16, the signals output from buffer amplifiers 4 and 14 are used. Since the voltages input to the buffer amplifiers 7 and 17 are determined by the feed-through clamp reference voltage VR and the feedback clamp control voltage VC, it is not necessary to stop the operation of the buffer amplifiers 4 and 14 during the feedback clamp. In this case, there is no need to provide an operation stopping mechanism for the buffer amplifiers 4 and 14, and the circuit can be simplified.

In the above embodiment, the feedback clamp control voltage VC is supplied to the feed-through clamp switch 16 on the non-signal side, but the input phase or output phase of the comparator 33 is inverted.
Even if the voltage is applied to the feed-through / clamp switch 6 on the signal side, there is no change in characteristics. The details of the operation of the sample holders 2 and 3 are the same as in the above-described conventional example.

[0035]

As described above, the present invention provides a CCD
In response to the image output signal output from the image sensor, the operation of the input buffer amplifier is stopped during the feedback clamp period, and the feed-through clamp circuit is operated, so that the feedback clamp can be performed even during periods other than the OB period. It is possible to avoid clamping scratches of the OB, and therefore, even if the OB period is used in the subsequent clamping operation in the signal processing section, there is an effect that the displacement of the clamp can be extremely reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a sample and hold circuit according to one embodiment of the present invention.

FIG. 2 is a waveform diagram showing an output voltage of a CCD image sensor during one horizontal period.

FIG. 3 is a waveform diagram showing an output voltage in one pixel period of the CCD image sensor.

FIG. 4 is a block diagram showing a conventional sample and hold circuit.

[Explanation of symbols]

1,41 sample hold circuit 4,7,14,17,44,47,54,57 buffer amplifier 6,8,16,18,46,48,56,58 switch 2,3,42,43 sample holder 5, 9, 15, 19, 31, 45, 49, 55, 59,
71 Capacitor 21, 61 Feed-through clamp reference voltage source 20, 60 Feedback clamp control voltage source 30, 70 CCD image sensor 33, 73 Comparator 32, 72 Differential amplifier

Claims (2)

(57) [Claims] A first buffer amplifier for inputting an image output signal of a CCD image sensor; and a first clamp circuit for clamping an output of the first buffer amplifier, wherein the first clamp circuit is provided. A first sample holder that samples and holds the output of the second buffer amplifier, outputs a second buffer amplifier whose input is AC grounded to low impedance, and a second clamp circuit that clamps the output of the second buffer amplifier. Having a second sample holder that samples and holds the output of the second clamp circuit and outputs the same, so that feedback is applied even during periods other than the optical black period in the image output signal. Means are provided for stopping the operations of the first and second buffer amplifiers and operating the first and second clamp circuits during the period. A sample-and-hold circuit characterized in that: A first signal input terminal receiving an image output signal of the CCD image sensor and stopping the operation by a predetermined output offset voltage absorption operation control signal;
And a first buffer amplifier that clamps the voltage level of the output of the first buffer amplifier to a predetermined reference clamp voltage with a predetermined clamp operation control signal and the predetermined output offset voltage absorption operation control signal, and outputs the same. A first sampling circuit which receives an output signal of the clamp circuit and the first clamp circuit, samples and holds a voltage level of the output signal with a predetermined sampling operation control signal, and outputs the sampled signal to a first signal output terminal The holder and the second input terminal are connected to an input of a second buffer amplifier which is grounded with an AC low impedance and is stopped by a predetermined output offset voltage absorbing operation control signal, and is connected to an input of the second buffer amplifier. The output voltage is changed to a clamp voltage supplied by a predetermined voltage varying means by the clamp operation signal and the predetermined output offset voltage absorption operation signal. And a second clamp circuit for clamping and outputting an output signal of the second clamp circuit, and sampling a voltage level of the output signal with a sampling operation control signal similar to that of the first sample holder. And a second sample holder for holding and outputting to a second signal output terminal, wherein the clamp voltage in the second clamp circuit changes the output voltage level at the first and second signal output terminals to the predetermined output. By comparing in the offset absorption operation control signal period, the output voltage levels of the first and second signal output terminals are provided by the voltage varying means for adjusting the output voltage levels to the same potential. A sample-and-hold circuit, wherein an output signal at an output terminal is output in an out-of-phase relationship.