JP4763367B2 - Video signal input circuit - Google Patents

Video signal input circuit Download PDF

Info

Publication number
JP4763367B2
JP4763367B2 JP2005200573A JP2005200573A JP4763367B2 JP 4763367 B2 JP4763367 B2 JP 4763367B2 JP 2005200573 A JP2005200573 A JP 2005200573A JP 2005200573 A JP2005200573 A JP 2005200573A JP 4763367 B2 JP4763367 B2 JP 4763367B2
Authority
JP
Japan
Prior art keywords
video signal
gnd
circuit
signal
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2005200573A
Other languages
Japanese (ja)
Other versions
JP2007019983A (en
Inventor
貴弘 鳥越
祥正 稗田
敦 北島
堅次 武渕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
New Japan Radio Co Ltd
Original Assignee
New Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New Japan Radio Co Ltd filed Critical New Japan Radio Co Ltd
Priority to JP2005200573A priority Critical patent/JP4763367B2/en
Publication of JP2007019983A publication Critical patent/JP2007019983A/en
Application granted granted Critical
Publication of JP4763367B2 publication Critical patent/JP4763367B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Picture Signal Circuits (AREA)

Description

本発明は、映像信号に含まれるＧＮＤノイズを除去する機能を有する映像信号入力回路に関するものである。   The present invention relates to a video signal input circuit having a function of removing GND noise contained in a video signal.

独立したＧＮＤをもつ外部機器から出力される映像信号を入力して所定の映像処理を行うとき、その外部機器内でＧＮＤノイズが発生していると、そのＧＮＤノイズが入力映像信号に重畳されてくるので、適切な映像処理を行うことができない。   When a predetermined video processing is performed by inputting a video signal output from an external device having an independent GND, if the GND noise is generated in the external device, the GND noise is superimposed on the input video signal. Therefore, appropriate video processing cannot be performed.

特に、アナログの映像信号をデジタルの映像信号に変換するときは、そのレファレンス電圧をＧＮＤを基準に作成するので、そのレファレンス電圧にＧＮＤノイズが重畳していると適正なＡ／Ｄ変換を行うことができない。   In particular, when an analog video signal is converted into a digital video signal, the reference voltage is created based on GND, so that appropriate A / D conversion is performed if GND noise is superimposed on the reference voltage. I can't.

このような場合に従来では、図９に示すように、映像信号とＧＮＤ信号を別々のＡ／Ｄ変換器２８，２９でデジタル信号に変換してから、そのデジタル信号の差分を演算回路３０でとってＧＮＤノイズを除去することが行われている（例えば、特許文献１参照）。図９において、２４は映像信号取出用のエミッタホロワトランジスタ、２５は抵抗、２６はマッチング用のコモンチョークである。
特開２００４−２１４９１８号公報 Conventionally, in this case, as shown in FIG. 9, the video signal and the GND signal are converted into digital signals by separate A / D converters 28 and 29, and then the difference between the digital signals is calculated by the arithmetic circuit 30. Thus, GND noise is removed (for example, see Patent Document 1). In FIG. 9, 24 is an emitter-follower transistor for extracting video signals, 25 is a resistor, and 26 is a common choke for matching.
JP 2004-214918 A

しかし、図９の回路では、入力側の映像信号ラインのエミッタホロワトランジスタ２４のエミッタとＧＮＤ信号ラインが抵抗２５で接続され、そのエミッタから映像信号を取り出しているため、そのトランジスタ２４のエミッタ抵抗と抵抗２５により分圧された信号が映像信号となるので、映像信号に重畳されるＧＮＤノイズと、ＧＮＤラインのＧＮＤノイズのレベルが異なることになる。よって、Ａ／Ｄ変換を行わない場合では、映像信号に重畳するＧＮＤノイズとＧＮＤ信号に重畳するＧＮＤノイズのレベルが異なり、映像信号からＧＮＤノイズを除去することが困難になるという問題がある。   However, in the circuit of FIG. 9, since the emitter of the emitter follower transistor 24 in the video signal line on the input side and the GND signal line are connected by the resistor 25 and the video signal is taken out from the emitter, the emitter resistance of the transistor 24 Since the signal divided by the resistor 25 becomes a video signal, the level of the GND noise superimposed on the video signal is different from that of the GND line. Therefore, when A / D conversion is not performed, there is a problem in that it is difficult to remove the GND noise from the video signal because the level of the GND noise superimposed on the video signal is different from the level of the GND noise superimposed on the GND signal.

本発明の目的は、映像信号に重畳したＧＮＤノイズが簡単な構成で除去できるようにした映像信号入力回路を提供することである。   An object of the present invention is to provide a video signal input circuit capable of removing GND noise superimposed on a video signal with a simple configuration.

上記目的を達成するために請求項１にかかる発明は、独立したＧＮＤをもち、ＧＮＤノイズが重畳したＧＮＤ信号を出力するとともに前記ＧＮＤノイズが重畳した映像信号を出力し、且つ前記ＧＮＤ信号に重畳したＧＮＤノイズと前記映像信号に重畳したＧＮＤノイズの瞬時値が同一である映像信号出力用外部機器と、前記映像信号出力用外部機器から出力する前記映像信号と前記ＧＮＤ信号を入力して前記映像信号から前記ＧＮＤ信号を減算する減算手段を有する映像信号用同相信号除去回路と、を具備し、前記映像信号出力用外部機器の前記映像信号の出力部と前記映像信号用同相信号除去回路の前記映像信号の入力部との間に第１の容量を接続し、前記映像信号出力用外部機器の前記ＧＮＤ信号の出力部と前記映像信号用同相信号除去回路の前記ＧＮＤ信号の入力部との間に第２の容量を接続し、前記映像信号用同相信号除去回路の前記映像信号の入力部に、映像信号のＡＰＬの中心レベルをバイアスするバイアス回路を接続したことを特徴とする。
請求項２にかかる発明は、請求項１に記載の映像信号入力回路において、前記第１の容量に第１の抵抗を直列接続すると共に前記第２の容量に第２の抵抗を直列接続し、前記映像信号用同相信号除去回路の前記減算手段を差動増幅器で構成して、該差動増幅器の非反転入力側にゲイン設定用の第１の抵抗群を接続すると共に反転入力側に前記第１の抵抗群で設定されるゲインと同程度のゲインを設定する第２の抵抗群を接続し、且つ前記映像信号の入力部と前記第１の抵抗群の間に第１のバッファ回路を接続すると共に前記ＧＮＤ信号の入力部と前記第２の抵抗群の間に第２のバッファ回路を接続した、ことを特徴とする。
請求項３にかかる発明は、請求項２に記載の映像信号入力回路において、前記バイアス回路を、前記映像信号の入力部と前記第１のバッファ回路の入力側との間に接続したことを特徴とする。 In order to achieve the above object, the invention according to claim 1 has an independent GND, outputs a GND signal on which GND noise is superimposed, outputs a video signal on which the GND noise is superimposed, and superimposes on the GND signal. A video signal output external device having the same instantaneous value of the GND noise superimposed on the video signal and the video signal output from the video signal output external device and the GND signal. A video signal common-mode signal removal circuit having subtracting means for subtracting the GND signal from the signal, and the video signal output unit of the video signal output external device and the video signal common-mode signal removal circuit A first capacitor is connected between the video signal input unit and the GND signal output unit of the video signal output external device and the video signal in-phase signal removal A bias circuit that connects a second capacitor to the input portion of the GND signal of the path and biases the center level of the APL of the video signal to the input portion of the video signal of the common-mode signal removal circuit for the video signal Is connected .
The invention according to claim 2 is the video signal input circuit according to claim 1, wherein a first resistor is connected in series to the first capacitor and a second resistor is connected in series to the second capacitor. The subtracting means of the video signal in-phase signal removal circuit is configured by a differential amplifier, and a first resistor group for gain setting is connected to the non-inverting input side of the differential amplifier and the inverting input side is A second resistor group that sets a gain comparable to that set by the first resistor group is connected, and a first buffer circuit is connected between the video signal input section and the first resistor group. And a second buffer circuit is connected between the GND signal input section and the second resistor group .
According to a third aspect of the present invention, in the video signal input circuit according to the second aspect, the bias circuit is connected between the input portion of the video signal and the input side of the first buffer circuit. Features.

請求項１の発明によれば、バイアスされたＧＮＤノイズ重畳映像信号から、ＧＮＤノイズ成分のみが減算処理され、除去される。これにより、映像信号出力用外部機器内で発生し映像信号に重畳してしまっていたＧＮＤノイズを取り除き、映像信号のみを出力することが出来る。 According to the present invention, the bias has been GND noise superimposed video signal, only the G ND noise component is subtracted, is removed. As a result, the GND noise generated in the video signal output external device and superimposed on the video signal can be removed, and only the video signal can be output.

請求項２及び請求項３の発明によれば請求項１の発明の利点に加え、映像信号用同相信号除去回路の静電耐圧を向上させる利点がある。 According to the invention of claim 2 and claim 3 in addition to the advantages of the invention of claim 1, it has the advantage of improving the electrostatic breakdown voltage of the common-mode rejection circuit for movies image signal.

本発明では、映像信号出力用外部機器から出力する映像信号に重畳されるＧＮＤノイズとＧＮＤ信号に重畳されるＧＮＤノイズが瞬時値において同じとなるようにして、ＧＮＤノイズの除去を行う。以下、本発明を実施例によって図を参照しながら説明する。   In the present invention, the GND noise is removed such that the GND noise superimposed on the video signal output from the video signal output external device and the GND noise superimposed on the GND signal have the same instantaneous value. Hereinafter, the present invention will be described by way of examples with reference to the drawings.

図１は本発明の実施例１の映像信号入力回路の構成を示すブロック図であり、映像信号用同相信号除去回路１００Ａおよび映像信号出力用外部機器２００からなる。１０１は同相信号除去回路１００Ａの映像信号入力端子、１０２はＧＮＤ信号入力端子、１０３は映像信号出力端子、１０４は減算回路である。２０１は外部機器２００の映像信号出力端子、２０２はＧＮＤ信号出力端子（接地端子）である。   FIG. 1 is a block diagram showing a configuration of a video signal input circuit according to a first embodiment of the present invention, which includes a video signal common-mode signal removal circuit 100A and a video signal output external device 200. 101 is a video signal input terminal of the in-phase signal removal circuit 100A, 102 is a GND signal input terminal, 103 is a video signal output terminal, and 104 is a subtraction circuit. Reference numeral 201 denotes a video signal output terminal of the external device 200, and 202 denotes a GND signal output terminal (ground terminal).

映像信号出力用外部機器２００内でノイズが発生してＧＮＤに重畳すると、このＧＮＤに重畳したノイズにて影響された映像信号、すなわちＧＮＤノイズを重畳した映像信号が映像信号出力端子２０１から出力され、映像信号用同相信号除去回路１００Ａ内の映像信号入力端子１０１に入力される。   When noise is generated in the video signal output external device 200 and superimposed on the GND, a video signal affected by the noise superimposed on the GND, that is, a video signal on which the GND noise is superimposed is output from the video signal output terminal 201. Are input to the video signal input terminal 101 in the video signal in-phase signal removal circuit 100A.

また、映像信号出力用外部機器２００内で発生したノイズの重畳したＧＮＤ信号もＧＮＤ信号出力端子２０２に出力され、映像信号用同相信号除去回路１００Ａ内のＧＮＤ信号入力端子４に入力される。このＧＮＤ信号に重畳されたＧＮＤノイズは映像信号に重畳したＧＮＤノイズと瞬時値が同じである。   In addition, a GND signal on which noise generated in the video signal output external device 200 is superimposed is also output to the GND signal output terminal 202 and input to the GND signal input terminal 4 in the video signal in-phase signal removal circuit 100A. The GND noise superimposed on the GND signal has the same instantaneous value as the GND noise superimposed on the video signal.

映像信号用同相信号除去回路１００Ａでは、映像信号入力端子１０１から入力されたＧＮＤノイズ重畳の映像信号Ｓ１とＧＮＤ信号入力端子１０２から入力されたＧＮＤノイズ信号Ｓ２が減算回路１０４に入力して、前者から後者が減算され、ＧＮＤノイズ成分が除去された映像信号Ｓ３が映像出力端子１０３より出力される。   In the video signal in-phase signal removal circuit 100A, the GND noise superimposed video signal S1 input from the video signal input terminal 101 and the GND noise signal S2 input from the GND signal input terminal 102 are input to the subtraction circuit 104, The video signal S3 from which the latter is subtracted from the former and the GND noise component is removed is output from the video output terminal 103.

本実施例１では、入力する映像信号に重畳したＧＮＤノイズとＧＮＤ信号に重畳したＧＮＤノイズが同じ瞬時値で映像信号用同相信号除去回路１００Ａに取り込まれて減算回路１０４に入力されるので、そのＧＮＤノイズはそのまま相殺されることになり、簡単に映像信号からＧＮＤノイズ成分を除去することができる。   In the first embodiment, the GND noise superimposed on the input video signal and the GND noise superimposed on the GND signal are taken into the video signal common-mode signal removal circuit 100A with the same instantaneous value and input to the subtraction circuit 104. The GND noise is canceled as it is, and the GND noise component can be easily removed from the video signal.

図２は本発明の実施例２の映像信号入力回路の構成を示すブロック図である。ここでは、映像信号入力端子１０２と減算回路１０４の間にクランプ回路１０５を設けた映像信号用同相信号除去回路１００Ｂを用いる。また、直流成分除去のため、映像信号出力用外部機器２００の映像出力端子２０１と映像信号用同相信号除去回路１００Ｂの映像信号入力端子１０１との間に容量Ｃ１を接続し、さらに映像信号出力用外部機器２００のＧＮＤ信号出力端子２０２と映像信号用同相信号除去回路１００ＢのＧＮＤ信号入力端子１０２との間に容量Ｃ２を接続する。容量値はＣ１＝Ｃ２である。   FIG. 2 is a block diagram showing the configuration of the video signal input circuit according to the second embodiment of the present invention. Here, an in-phase signal removal circuit 100B for video signals in which a clamp circuit 105 is provided between the video signal input terminal 102 and the subtraction circuit 104 is used. Further, in order to remove the direct current component, a capacitor C1 is connected between the video output terminal 201 of the video signal output external device 200 and the video signal input terminal 101 of the video signal common-mode signal removal circuit 100B to further output the video signal. The capacitor C2 is connected between the GND signal output terminal 202 of the external device for video 200 and the GND signal input terminal 102 of the video signal common-mode signal removal circuit 100B. The capacitance value is C1 = C2.

よって、容量Ｃ１を介して映像信号入力端子１０１に入力されたＧＮＤノイズが重畳された映像信号は、クランプ回路１０５により入力映像信号のシンクチップ又はペデスタルが所望の電圧にクランプされる。クランプされた信号は、減算回路１０４において、容量Ｃ２を介してＧＮＤ信号入力端子１０２に入力されたＧＮＤノイズ重畳のＧＮＤ信号と減算処理され、ＧＮＤノイズ成分が除去された映像信号が映像出力端子１０３より出力される。   Therefore, in the video signal on which the GND noise input to the video signal input terminal 101 via the capacitor C1 is superimposed, the sync chip or pedestal of the input video signal is clamped to a desired voltage by the clamp circuit 105. The clamped signal is subtracted from the GND signal superimposed GND signal input to the GND signal input terminal 102 via the capacitor C2 in the subtraction circuit 104, and the video signal from which the GND noise component is removed is the video output terminal 103. Is output.

図３は本発明の実施例３の映像信号入力回路の構成を示すブロック図である。ここでは、映像信号入力端子１０２と減算回路１０３の間にバイアス回路１０６を設けた映像信号用同相信号除去回路１００Ｃを用いる。バイアス回路１０６は、入力映像信号のＡＰＬ（平均映像信号レベル）の中心となる電位を与える回路である。   FIG. 3 is a block diagram showing the configuration of the video signal input circuit according to the third embodiment of the present invention. Here, an in-phase signal removal circuit for video signal 100 </ b> C in which a bias circuit 106 is provided between the video signal input terminal 102 and the subtraction circuit 103 is used. The bias circuit 106 is a circuit that applies a potential that is the center of the APL (average video signal level) of the input video signal.

よって、容量Ｃ１を介して映像信号入力端子１０１に入力されたＧＮＤノイズが重畳された映像信号は、バイアス回路１０６により入力映像信号のＡＰＬ中心が所定の電圧にバイアスされて、減算回路１０４において、容量Ｃ２を介してＧＮＤ信号入力端子１０２に入力されたＧＮＤノイズ重畳のＧＮＤ信号と減算処理され、ＧＮＤノイズ成分が除去された映像信号が映像出力端子１０３より出力される。   Therefore, the video signal on which the GND noise input to the video signal input terminal 101 via the capacitor C1 is superimposed has the APL center of the input video signal biased to a predetermined voltage by the bias circuit 106, and the subtraction circuit 104 A video signal from which the GND noise component is subtracted from the GND noise superimposed GND signal input to the GND signal input terminal 102 via the capacitor C 2 and from which the GND noise component is removed is output from the video output terminal 103.

図４は本発明の実施例４の映像信号入力回路の構成を示すブロック図である。ここでは、映像信号用同相信号除去回路１００Ｄを用い、その映像信号入力端子１０１とＧＮＤ信号入力端子１０２の静電耐圧向上のために、それらと映像信号出力用外部機器２００の映像出力端子２０１、ＧＮＤ信号出力端子２０２との間に、抵抗Ｒａ，Ｒｂを挿入する。抵抗値はＲａ＝Ｒｂであり、数十乃至数百Ωである。   FIG. 4 is a block diagram showing the configuration of the video signal input circuit according to the fourth embodiment of the present invention. Here, the video signal common-mode signal removal circuit 100D is used, and in order to improve the electrostatic withstand voltage of the video signal input terminal 101 and the GND signal input terminal 102, they and the video output terminal 201 of the video signal output external device 200 are used. , Resistors Ra and Rb are inserted between the GND signal output terminal 202. The resistance value is Ra = Rb, which is several tens to several hundreds Ω.

また、減算回路として差動増幅器１０７を用い、差動増幅器１０７の非反転入力側と映像信号入力端子１０１との間に抵抗Ｒ１を、基準電圧源１０８との間に抵抗Ｒ２を設け、差動増幅器１０７の反転入力側とＧＮＤ信号入力端子１０２との間に抵抗Ｒ３を、差動増幅器１０７の帰還抵抗として抵抗Ｒ４を設けている。請求項との関係では、抵抗Ｒ１，Ｒ２が第１の抵抗群に、抵抗Ｒ３，Ｒ４が第２の抵抗群に相当する。   Further, a differential amplifier 107 is used as a subtracting circuit, a resistor R1 is provided between the non-inverting input side of the differential amplifier 107 and the video signal input terminal 101, and a resistor R2 is provided between the reference voltage source 108 and a differential. A resistor R3 is provided between the inverting input side of the amplifier 107 and the GND signal input terminal 102, and a resistor R4 is provided as a feedback resistor of the differential amplifier 107. In relation to the claims, the resistors R1 and R2 correspond to the first resistor group, and the resistors R3 and R4 correspond to the second resistor group.

ここで、各抵抗Ｒ１〜Ｒ４は、Ｒ２／（Ｒ１＋Ｒ２）≒Ｒ３／（Ｒ３＋Ｒ４）の関係式を満たす関係となっていて、差動増幅器１０７の非反転入力側のゲインと反転入力側のゲインが同程度に設定され、差動増幅器１０７の同相信号除去機能を発揮できるようにしている。   Here, each of the resistors R1 to R4 satisfies a relational expression of R2 / (R1 + R2) ≈R3 / (R3 + R4), and the gain on the non-inverting input side and the gain on the inverting input side of the differential amplifier 107 are It is set to the same level so that the common-mode signal removal function of the differential amplifier 107 can be exhibited.

そして、抵抗ＲａとＲｂのインピーダンスが抵抗Ｒ１〜Ｒ４に影響を与えないようにするために、映像信号入力端子１０１と抵抗Ｒ１の間にバッファ回路１０９を、ＧＮＤ信号入力端子１０２と抵抗Ｒ３の間にバッファ回路１１０を設けている。   In order to prevent the impedances of the resistors Ra and Rb from affecting the resistors R1 to R4, a buffer circuit 109 is provided between the video signal input terminal 101 and the resistor R1, and between the GND signal input terminal 102 and the resistor R3. Is provided with a buffer circuit 110.

以上により、本実施例４の映像信号入力回路では、ＧＮＤノイズの除去比率を悪化させることなく静電耐圧を向上させることが出来る。   As described above, in the video signal input circuit according to the fourth embodiment, the electrostatic withstand voltage can be improved without deteriorating the GND noise removal ratio.

図５は本発明の実施例５の映像信号入力回路の構成を示すブロック図である。これは、図４の映像信号入力回路において、抵抗Ｒａ，Ｒｂにそれぞれ容量Ｃ１，Ｃ２を直列接続したものである。このような構成であっても、図４に示した映像信号入力回路と同様に、ＧＮＤノイズの除去比率を悪化させることなく静電耐圧を向上させることが出来る。   FIG. 5 is a block diagram showing a configuration of a video signal input circuit according to the fifth embodiment of the present invention. In the video signal input circuit of FIG. 4, capacitors C1 and C2 are connected in series to resistors Ra and Rb, respectively. Even with such a configuration, the electrostatic withstand voltage can be improved without deteriorating the GND noise removal ratio, similarly to the video signal input circuit shown in FIG.

図６は本発明の実施例６の映像信号入力回路の構成を示すブロック図である。これは、図４の映像信号用同相信号除去回路１００Ｄを、図２で説明したクランプ回路１０５をさらに設けた映像信号用同相信号除去回路１００Ｅに置き換えたものである。クランプ回路１０５は、映像信号入力端子１０１とバッファ回路１０９の間に接続する。これにより、静電耐圧向上とＧＮＤノイズの除去が可能となり、また、シンクチップあるいはペデスタルのクランプも可能となる。   FIG. 6 is a block diagram showing the configuration of the video signal input circuit according to the sixth embodiment of the present invention. This is obtained by replacing the video signal in-phase signal removal circuit 100D in FIG. 4 with the video signal in-phase signal removal circuit 100E further provided with the clamp circuit 105 described in FIG. The clamp circuit 105 is connected between the video signal input terminal 101 and the buffer circuit 109. As a result, the electrostatic withstand voltage can be improved and the GND noise can be removed, and the sink chip or pedestal can be clamped.

図７は本発明の実施例７の映像信号入力回路の構成を示すブロック図である。これは、図４の映像信号用同相信号除去回路１００Ｄを、図３で説明したバイアス回路１０６をさらに設けた映像信号用同相信号除去回路１００Ｆに置き換えたものである。バイアス回路１０６は、映像信号入力端子１０１とバッファ回路１０９の間に接続する。これにより、静電耐圧向上とＧＮＤノイズの除去が可能となり、また、ＡＰＬの中心を所定のレベルに保持できる。   FIG. 7 is a block diagram showing a configuration of a video signal input circuit according to the seventh embodiment of the present invention. This is obtained by replacing the video signal in-phase signal removal circuit 100D in FIG. 4 with a video signal in-phase signal removal circuit 100F further provided with the bias circuit 106 described in FIG. The bias circuit 106 is connected between the video signal input terminal 101 and the buffer circuit 109. As a result, electrostatic withstand voltage can be improved and GND noise can be removed, and the center of the APL can be held at a predetermined level.

図８(a)、(b)は本発明の実施例８の映像信号入力回路の構成を示すブロック図である。図８(a)では、図１で説明した映像信号用同相信号除去回路１００Ａの後段側に映像信号処理回路３００を具備させている。図８(b)では、図１で説明した映像信号出力用外部機器２００の像信号出力端子２０１と映像信号用同相信号除去回路１００Ａの映像信号入力端子１０１の間に映像信号処理回路３００を具備させている。   8A and 8B are block diagrams showing the configuration of the video signal input circuit according to the eighth embodiment of the present invention. In FIG. 8A, the video signal processing circuit 300 is provided on the rear side of the video signal common-mode signal removal circuit 100A described in FIG. 8B, the video signal processing circuit 300 is provided between the video signal output terminal 201 of the video signal output external device 200 described in FIG. 1 and the video signal input terminal 101 of the video signal in-phase signal removal circuit 100A. Equipped.

映像信号処理回路３００は、映像信号を目的に応じて処理する機能を有する回路であり、図８(a)ではＧＮＤノイズ成分を除去した映像信号について処理することになるので、その信号処理が容易となり、図８(b)では映像信号処理の後にＧＮＤノイズが除去されるので、得られる映像処理信号はＧＮＤノイズの影響を除去した映像信号処理済みの信号となる。なお、図８(b)では映像信号処理回路３００の出力側に現れる映像信号に重畳したＧＮＤノイズをＧＮＤ信号に重畳したＧＮＤノイズの瞬時値に合わせる必要がある。映像信号処理回路３００は、例えばフィルタ回路、スイッチ回路、ゲインアンプ回路、出力ドライバ回路等の映像信号処理を行うための回路を含む回路であり、これら以外にも映像信号処理の目的を達するために容易ならしめる回路を含むことは言うまでも無い。なお、図２〜図７で説明した映像信号入力回路においても、図８(a)又は(b)に示すように映像信号処理回路３００を具備させることで、同様な作用効果を得ることができる。   The video signal processing circuit 300 is a circuit having a function of processing a video signal according to the purpose. In FIG. 8A, the video signal from which the GND noise component is removed is processed, so that the signal processing is easy. In FIG. 8B, since the GND noise is removed after the video signal processing, the obtained video processing signal is a video signal processed signal from which the influence of the GND noise is removed. In FIG. 8B, it is necessary to match the GND noise superimposed on the video signal appearing on the output side of the video signal processing circuit 300 to the instantaneous value of the GND noise superimposed on the GND signal. The video signal processing circuit 300 is a circuit including a circuit for performing video signal processing such as a filter circuit, a switch circuit, a gain amplifier circuit, and an output driver circuit, for example. Needless to say, the circuit includes an easy circuit. The video signal input circuit described with reference to FIGS. 2 to 7 can also be obtained by providing the video signal processing circuit 300 as shown in FIG. 8 (a) or (b). .

その他の実施例Other examples

以上、複数の実施例に基づき具体的に説明したが、本発明は前記実施例に限定されるものではなく、その旨を逸脱したい範囲で種々の変更が可能であることは言うまでも無い。   While the present invention has been specifically described above based on a plurality of embodiments, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the scope of the present invention.

実施例１の映像信号入力回路の構成を示すブロック図である。1 is a block diagram illustrating a configuration of a video signal input circuit according to Embodiment 1. FIG. 実施例２の映像信号入力回路の構成を示すブロック図である。FIG. 6 is a block diagram illustrating a configuration of a video signal input circuit according to a second embodiment. 実施例３の映像信号入力回路の構成を示すブロック図である。FIG. 10 is a block diagram illustrating a configuration of a video signal input circuit according to a third embodiment. 実施例４の映像信号入力回路の構成を示すブロック図である。FIG. 10 is a block diagram illustrating a configuration of a video signal input circuit according to a fourth embodiment. 実施例５の映像信号入力回路の構成を示すブロック図である。FIG. 10 is a block diagram illustrating a configuration of a video signal input circuit according to a fifth embodiment. 実施例６の映像信号入力回路の構成を示すブロック図である。FIG. 10 is a block diagram illustrating a configuration of a video signal input circuit according to a sixth embodiment. 実施例７の映像信号入力回路の構成を示すブロック図である。FIG. 10 is a block diagram illustrating a configuration of a video signal input circuit according to a seventh embodiment. (a)、(b)は実施例８の映像信号入力回路の構成を示すブロック図である。(a), (b) is a block diagram which shows the structure of the video signal input circuit of Example 8. FIG. 従来のＧＮＤノイズ除去回路の回路図である。It is a circuit diagram of the conventional GND noise removal circuit.

符号の説明Explanation of symbols

１００：映像信号用同相信号除去回路、１０１：映像信号入力端子、１０２：ＧＮＤ信号入力端子、１０３：映像信号出力端子、１０４：減算回路、１０５：クランプ回路、１０６：バイアス回路、１０７：差動増幅器、１０８：基準電圧源、１０９，１１０：バッファ回路
２００：映像信号出力用外部機器、２０１：映像信号出力端子、２０２：ＧＮＤ信号出力端子
３００：映像信号処理回路 100: Video signal common-mode signal removal circuit, 101: Video signal input terminal, 102: GND signal input terminal, 103: Video signal output terminal, 104: Subtraction circuit, 105: Clamp circuit, 106: Bias circuit, 107: Difference Dynamic amplifier, 108: reference voltage source, 109, 110: buffer circuit 200: external device for video signal output, 201: video signal output terminal, 202: GND signal output terminal 300: video signal processing circuit

Claims (3)

独立したＧＮＤをもち、ＧＮＤノイズが重畳したＧＮＤ信号を出力するとともに前記ＧＮＤノイズが重畳した映像信号を出力し、且つ前記ＧＮＤ信号に重畳したＧＮＤノイズと前記映像信号に重畳したＧＮＤノイズの瞬時値が同一である映像信号出力用外部機器と、
前記映像信号出力用外部機器から出力する前記映像信号と前記ＧＮＤ信号を入力して前記映像信号から前記ＧＮＤ信号を減算する減算手段を有する映像信号用同相信号除去回路と、を具備し、
前記映像信号出力用外部機器の前記映像信号の出力部と前記映像信号用同相信号除去回路の前記映像信号の入力部との間に第１の容量を接続し、
前記映像信号出力用外部機器の前記ＧＮＤ信号の出力部と前記映像信号用同相信号除去回路の前記ＧＮＤ信号の入力部との間に第２の容量を接続し、
前記映像信号用同相信号除去回路の前記映像信号の入力部に、映像信号のＡＰＬの中心レベルをバイアスするバイアス回路を接続したことを特徴とする映像信号入力回路。 It has an independent GND, outputs a GND signal on which the GND noise is superimposed, outputs a video signal on which the GND noise is superimposed, and instantaneous values of the GND noise superimposed on the GND signal and the GND noise superimposed on the video signal An external device for video signal output with the same
A video signal common-mode signal removal circuit having subtracting means for inputting the video signal output from the video signal output external device and the GND signal and subtracting the GND signal from the video signal ;
A first capacitor is connected between the video signal output unit of the video signal output external device and the video signal input unit of the video signal in-phase signal removal circuit;
A second capacitor is connected between the output portion of the GND signal of the external device for outputting the video signal and the input portion of the GND signal of the common-mode signal removal circuit for the video signal;
A video signal input circuit, wherein a bias circuit for biasing the center level of the APL of the video signal is connected to the video signal input section of the video signal in-phase signal removal circuit. 請求項１に記載の映像信号入力回路において、
前記第１の容量に第１の抵抗を直列接続すると共に前記第２の容量に第２の抵抗を直列接続し、
前記映像信号用同相信号除去回路の前記減算手段を差動増幅器で構成して、該差動増幅器の非反転入力側にゲイン設定用の第１の抵抗群を接続すると共に反転入力側に前記第１の抵抗群で設定されるゲインと同程度のゲインを設定する第２の抵抗群を接続し、且つ前記映像信号の入力部と前記第１の抵抗群の間に第１のバッファ回路を接続すると共に前記ＧＮＤ信号の入力部と前記第２の抵抗群の間に第２のバッファ回路を接続した、
ことを特徴とする映像信号入力回路。 The video signal input circuit according to claim 1.
A first resistor connected in series with the first capacitor and a second resistor connected in series with the second capacitor;
The subtracting means of the video signal in-phase signal removal circuit is configured by a differential amplifier, and a first resistor group for gain setting is connected to the non-inverting input side of the differential amplifier and the inverting input side is A second resistor group that sets a gain comparable to that set by the first resistor group is connected, and a first buffer circuit is connected between the video signal input section and the first resistor group. And connecting a second buffer circuit between the GND signal input section and the second resistor group,
A video signal input circuit characterized by the above. 請求項２に記載の映像信号入力回路において、
前記バイアス回路を、前記映像信号の入力部と前記第１のバッファ回路の入力側との間に接続したことを特徴とする映像信号入力回路。 The video signal input circuit according to claim 2,
A video signal input circuit, wherein the bias circuit is connected between an input portion of the video signal and an input side of the first buffer circuit.
JP2005200573A 2005-07-08 2005-07-08 Video signal input circuit Active JP4763367B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005200573A JP4763367B2 (en) 2005-07-08 2005-07-08 Video signal input circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005200573A JP4763367B2 (en) 2005-07-08 2005-07-08 Video signal input circuit

Publications (2)

Publication Number Publication Date
JP2007019983A JP2007019983A (en) 2007-01-25
JP4763367B2 true JP4763367B2 (en) 2011-08-31

Family

ID=37756719

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005200573A Active JP4763367B2 (en) 2005-07-08 2005-07-08 Video signal input circuit

Country Status (1)

Country Link
JP (1) JP4763367B2 (en)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6171777A (en) * 1984-09-14 1986-04-12 Olympus Optical Co Ltd Differential amplifier
JPH05316338A (en) * 1992-05-08 1993-11-26 Nec Corp Sample-and-hold circuit
JPH0661853A (en) * 1992-08-10 1994-03-04 Sony Corp Electronic device
JP3064703B2 (en) * 1992-11-09 2000-07-12 日本電気株式会社 Sample hold circuit
JPH07274039A (en) * 1994-03-28 1995-10-20 Hitachi Ltd Picture signal corrector and signal converter
JP3292167B2 (en) * 1999-02-18 2002-06-17 インターナショナル・ビジネス・マシーンズ・コーポレーション Differential input interface

Also Published As

Publication number Publication date
JP2007019983A (en) 2007-01-25

Similar Documents

Publication Publication Date Title
JP6212922B2 (en) Chopper amplifier
US7560969B2 (en) Receiver of high speed digital interface
US6259300B1 (en) Differential input interface circuit and method for adjusting DC levels of differential input signals
US20190356282A1 (en) Mems sensor
JP2011109721A (en) Amplitude limit amplifier circuit
JP4763367B2 (en) Video signal input circuit
JPH09190699A (en) Correlation double sampling device
US20070247341A1 (en) Sigma-delta modulator
JP5578048B2 (en) Video signal output circuit
US6963238B2 (en) Level shift circuit
JP5169861B2 (en) Semiconductor integrated circuit, video signal output circuit
US9900018B1 (en) Methods and systems for reducing transient kickback from an analog-to-digital converter
US9680420B2 (en) Apparatus for compensation of electronic circuitry and associated methods
US20100150357A1 (en) Amplifier circuit and method of signal amplification
JP2013251657A (en) Voltage follower input type differential amplifier
US10566984B2 (en) Signal processing circuit
JP2010283522A (en) Offset voltage correction circuit
JP5113503B2 (en) Video output circuit
JP4351857B2 (en) External output video signal processor
JP4729658B2 (en) Filter circuit
KR101128451B1 (en) Input signal amplifying device
JP2015154304A (en) Amplifier circuit, amplification device, afe circuit and signal processing system
CN107959911B (en) Amplifier device
JP2004274434A (en) Video signal correction circuit
JP5697144B2 (en) Voltage amplification device and voltage amplification method

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080507

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100603

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100609

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100727

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110310

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110502

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110524

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110609

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140617

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4763367

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250