JPH05316338A - Sample-and-hold circuit - Google Patents

Abstract

PURPOSE:To obtain a sample-and-hold circuit applying feedback clamp even at the outside of an optical black period for a CCD image sensor. CONSTITUTION:In the sample-and-hold circuit 1 provided with a CCD image sensor 19, a capacitor 20, a comparator 21, a buffer amplifier 2(3) corresponding to a differential amplifier circuit 22, a clamp capacitor 6(12), a feed-through clamp switch 7 (13), a buffer amplifier 8(14), a sampling switch 9(15), a sample- and-hold circuit 5(11) including a sampling capacitor 10(16), a feedback clamp control voltage source 17 and a feed-through clamp reference voltage source 18, a feedback clamp switch 4 is provided between both sample-and-hold circuits, which is thrown to the position (b) for a video signal period from the CCD and thrown to the position (a) for a feedback clamp period to give the same signal to the feed-through clamp capacitors 6,12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit, and more particularly to a sample and hold circuit used to reduce low frequency 1 / f noise and reset pulse noise of an image signal obtained from a CCD image sensor.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional sample and hold circuit corresponding to a CCD image sensor constructed by connecting a feed through clamp circuit and a video signal sample and hold circuit in series. As shown in FIG. 2, the sample and hold circuit 23 of the conventional example is a CCD
The buffer amplifier 24 corresponding to the image sensor 40, the capacitor 41, the comparator 42 and the differential amplifier 43.
And 25, a capacitor 27 for feed-through clamp and a capacitor 31 for sampling, a switch 28 for feed-through clamp and a switch 30 for sampling, and a sample hold 26 including a buffer amplifier 29, and a feed-through clamp. Capacitor 33 and sampling capacitor 37,
A switch 34 for a feedthrough clamp, a switch 36 for sampling, and a sample hold 32 including a buffer amplifier 35 are provided. Also,
FIG. 4 is an operation waveform diagram of an image output signal output from the CCD image sensor 40.

The image output signal for each pixel output from the CCD image sensor 40 is a reset pulse given to clear all the pixels inside the CCD image sensor 40, as shown in FIG. The signal required for the level of the video signal is expressed as a voltage difference A between the voltage during the feedthrough period and the voltage during the video signal period. Be done. The reset noise has nothing to do with the video signal level, and when the video signal level is low, the video signal is buried in the reset noise and the S / N ratio deteriorates. Further, the low frequency 1 / f noise is usually superposed on the image output signal output from the CCD image sensor 40. Therefore, in order not to remove the low frequency 1 / f noise, the same applies to the image. The image quality will deteriorate.

These reset noise and low frequency 1 / F
In order to remove noise, the above-described sample hold circuit for the CCD image sensor output signal shown in FIG. 2 has been conventionally proposed.

The image output signal from the CCD image sensor 40 input from the input terminal 56 is a buffer amplifier 24.
Is input to the sample hold 26 via the capacitor 27 for feedthrough clamp and the feedthrough
The clamp switch 28 clamps the voltage of the image input signal during the feed-through period to the clamp reference voltage V _R for each pixel through the feed-through clamp action to remove low-frequency 1 / f noise. It Here, the clamp reference voltage V _R is a voltage set by the feedthrough clamp control voltage source 39.

Next, the buffer amplifier 29, the sampling switch 30, and the holding capacitor 31 sample and hold the signal voltage of the maximum amplitude level during the video signal period, and output it via the output terminal 58. The image signal output from the output terminal 58 is output as a video signal based on a feedthrough voltage from which low frequency 1 / f noise is removed and reset noise and a feedthrough period are removed.

Further, in order to remove the fluctuation component of the clamp reference voltage V _R and sampling noise at the time of sampling and holding, a capacitor 33 for feed through clamp, a switch 34 for feed through clamp,
A non-signal side sample and hold 32 including a buffer amplifier 35, a sampling switch 36 and a holding capacitor 37 is provided in parallel with the signal side sample and hold 26 in the same form, and corresponds to both of these sample and hold. The output signals of the output terminals 58 and 59 are input to the differential amplifier 43, and the clamp reference voltage V _R
The fluctuating voltage component, sampling noise, and the like are removed, and the image signal having an excellent S / N ratio is output.

Further, even if the clamp reference voltage V _R is common to the signal side sample hold 26 and the non-signal side sample hold 32, the corresponding feed through clamp switches 28 and 34 and the buffer amplifier 29 are respectively provided. And 35, switch 3 for sampling
An offset voltage often occurs in the DC voltage obtained at the above-mentioned output terminals 58 and 59 due to variations in characteristics of 0 and 36 and the like. When the differential amplifier 43 connected to the output terminals 58 and 59 also has a function as an AGC (automatic gain control) amplifier for amplifying an image signal in low illuminance, the maximum gain is about 40 dB. , And correspondingly to the output terminals 58 and 5 of the sample and hold 26 and 32, as shown in FIG.
A comparator 42 is provided so that the DC voltage in 9 becomes the same potential. Both of these DC voltages are compared in the comparator 42, and the comparison output voltage is the terminal 6
It is considered that the clamp control voltage V _C on the non-signal side is made variable by being input to the feedback clamp control voltage source 38 via 0. As a method of making the clamp reference voltage variable, as shown in FIG. 2, the voltage on the clamp switch 34 side on the non-signal side may be made variable,
There is no problem in terms of characteristics.

[0009]

In the conventional sample and hold circuit described above, the image output signal output from the CCD image sensor every horizontal period is, as shown in FIG. Optical black (hereinafter referred to as OB) period [1] in which the diode is covered with aluminum and outputs an ideal black signal, and there is no photodiode or CCD transfer part, and an undefined signal is output. And the OB period [2], the period during which the feedback for absorbing the offset voltage of the DC voltage at the output terminals 58 and 59 is applied in the sample hold circuit for the conventional CCD image sensor described above. The substance is that there is only the OB period of the image output signal from the CCD image sensor. In FIG.
The signal given to the amplifier of the next stage is given by the differential form of the output terminals 58 and 59, the DC voltage output from the output terminal 59 on the non-signal side is a black level, and the output terminal 58 on the signal side. It is necessary to compare and match with the DC voltage of the OB period output more.

However, the OB period signal once used in the feedback clamp is damaged by the clamp, and if the clamp is used two or more times at the same timing, the clamp shift may occur. There is Further, in the OB period of a general CCD image sensor, the OB shown in FIG.
In the portion corresponding to the period [1], it is about 3 μsec, and in the OB period [2], it is as short as about 0.2 μsec.
In the OB period [1], the feedback clamp can be applied twice with the timing shifted.
In the OB period [2], it is difficult to apply the feedback clamp because the period is extremely short.
For convenience, only two feedback clamps can be used in one horizontal period. However, in the image signal processing corresponding to the CCD image sensor, it is necessary to perform black level adjustment at least in the γ amplification section and, at the time of blanking, in some cases, a feedback clamp in the color separation output section. Later, at least two or three feedback clamps are performed. Therefore, in the current CCD image sensor, the OB period is short and the OB in the next stage is short.
There is a drawback that it becomes difficult to perform the period clamp.

[0011]

A sample and hold circuit according to a first aspect of the present invention uses a predetermined clamp operation control signal to control a voltage level of an image output signal of a CCD image sensor input through a first signal input terminal. Via a first clamp circuit for clamping and outputting to a predetermined reference clamp voltage, the image output signal is input to a first input terminal, and a second input terminal is a second signal input terminal. An input switching circuit that is grounded through a low impedance via a switch and selectively outputs one of the signals at the first and second input terminals; and an input signal from the first clamp circuit. , Sample-hold the voltage level of the output signal via a predetermined sampling operation control signal,
The voltage level of the first sample hold circuit that outputs the signal via the signal output terminal and the voltage level of the signal that is switched and selected by the input switching circuit is output via the same clamp operation control signal as that of the first clamp circuit. A second clamp circuit for clamping and outputting the clamp voltage supplied from a predetermined voltage varying means and an output signal of the second clamp circuit, and inputting the voltage level of the output signal to the second clamp circuit. A second sample-and-hold circuit for sampling and holding via the same sampling operation control signal as the first sample-and-hold circuit, and outputting via the second signal output terminal;
At least, and the clamp voltage in the second clamp circuit compares the output voltage levels at the first and second signal output terminals only during a predetermined designated period to output the first and second signal outputs. The input switching circuit is provided with at least the period in which the image output signal of the CCD image sensor is input, which is given by the voltage varying means for adjusting the output voltage levels of the terminals so as to have the same potential. It is set to select and output a signal connected to the second signal input terminal, and output signals at the first and second signal output terminals are output in a differential format.

The sample and hold circuit according to the second aspect of the present invention changes the voltage level of the image output signal of the CCD image sensor input via the first signal input terminal via a predetermined clamp operation control signal. A first clamp circuit that clamps and outputs a clamp voltage supplied from a predetermined voltage varying unit, the image output signal is input to a first input terminal, and a second input terminal is a second signal. An input switching circuit, which is grounded through a low impedance via an input terminal and selectively outputs one of the signals at the first and second input terminals, and the output signal of the first clamp circuit are input. A first sample-hold circuit that samples and holds the voltage level of the output signal via a predetermined sampling operation control signal and outputs the sample-holded voltage level via a first signal output terminal. A second voltage for clamping and outputting a voltage level of a signal which is switched and selected by the input switching circuit and output via the same clamp operation control signal as that of the first clamp circuit. The output signal of the clamp circuit and the second clamp circuit is input, and the voltage level of the output signal is sampled and held via the same sampling operation control signal as that of the first sample and hold circuit, A second sample and hold circuit for outputting via a signal output terminal, wherein the clamp voltage in the first clamp circuit sets the output voltage level at the first and second signal output terminals for a predetermined designated period. And the output voltage levels of the first and second signal output terminals are adjusted so as to have the same potential. The input switching circuit selects a signal connected to the second signal input terminal at least during a period in which the image output signal of the CCD image sensor is input by the voltage varying unit. Is set to output,
The output signals at the first and second signal output terminals are output in a differential format.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in FIG. 1, the sample and hold circuit 1 of the present embodiment corresponds to a CCD image sensor 19, a capacitor 20, a comparator 21 and a differential amplifier 22, and buffer amplifiers 2 and 3 and a feedback clamp circuit. Switch 4 and capacitor 6 for feedthrough clamp and capacitor 1 for sampling
0, a sample-hold 5 including a switch 7 for feed-through clamp and a switch 9 for sampling, and a buffer amplifier 8, a capacitor 12 for feed-through clamp, and a capacitor 1 for sampling
6, switch 13 for feed through clamp, switch 15 for sampling, and buffer amplifier 14
And a feedback clamp control voltage source 17, and a feedthrough clamp reference voltage source 18. In FIG. 1, the capacitor 6, the switch 7, the capacitor 12, and the switch 13 form a clamp circuit that operates through the same clamp operation control signal, and the switch 9, the capacitor 10, the switch 15, and the switch 15 The capacitor 16 forms a sampling and holding circuit that operates via the same sampling operation control signal.

As is apparent from the comparison between FIGS. 1 and 2, the difference between this embodiment and the above-mentioned conventional example is that the output signals of the buffer amplifiers 2 and 3 are switched to the sample-hold 11 on the non-signal side. That is, a switch 4 for feedback clamp acting as an input is added. C
As described above, the image output signal for each pixel output from the CD image sensor 19 is divided into three periods of reset noise, feedthrough, and a video signal, which are generated due to a reset pulse leaking to the output. The signal required as the level of the video signal is represented as a voltage difference A between the voltage during the field through period and the voltage during the video signal period (see FIG. 4). This video output signal is input to the sample hold circuit 1 via the input terminal 51, and via the buffer amplifier 2, the feedthrough clamp capacitor 6 and the sampling capacitor 10, the feedthrough clamp switch 6 and It is input to the signal side sample hold 5 including the sampling switch 9 and the buffer amplifier 8 and to the a side of the feedback clamp switch 4.

In the sample and hold 5, the feedthrough clamp capacitor 6 and the feedthrough clamp are used.
The clamp switch 7 clamps the voltage of the image input signal during the feedthrough period to the clamp reference voltage V _R , and then the buffer amplifier 8, the sampling switch 9 and the holding capacitor 10 in the video signal period. The signal voltage at the maximum amplitude level is sampled and held and output via the output terminal 53. The image signal output from the output terminal 53 has the low-frequency 1 / f noise removed, and the reset noise and the feed-through period removed, as in the case of the above-described conventional example. It is output as a reference video signal.

Further, the non-signal side input terminal 52 is grounded via the capacitor 20 to have a low impedance in order to prevent a disturbance signal such as noise from being inputted, and a buffer amplifier on the signal side. 2 is connected to the input side of a buffer amplifier 3 of the same type as 2 and its output is
It is connected to the b side of the clamp switch 4. The output side of the feedback clamp switch 4 has a feed-through clamp capacitor 12 and a sampling capacitor 16 of the same type as the signal side, a feed-through clamp switch 13 and a sampling switch 15, and It is connected to the non-signal side sample and hold 11 including the buffer amplifier 14, and its output is output through the non-signal side output terminal 54. Needless to say, the signal-side sample and hold 5 and the non-signal-side sample and hold 11 have the same format.

The feedthrough clamp reference voltage source 1 is included in the switch 7 for the feedthrough clamp on the signal side.
8 is supplied with the feedthrough reference voltage V _R, and the feedthrough clamp switch 13 on the non-signal side is supplied with the feedthrough reference voltage V _R by the feedthrough clamp reference power supply 18 and this feedthrough reference voltage. A control voltage V _C from the feedback clamp control voltage source 17 superimposed on V _R is supplied.
The control voltage V _C is compared by the comparator 21 between the outputs of the signal side output terminal 53 and the non-signal side output terminal 54, and the comparison output result is fed back to the feedback / clamp control voltage source 17 via the terminal 55. This is a control voltage resulting from the operation, and by this feedback action, the DC voltage levels at the output terminals 53 and 54 are controlled to be the same level.

During the video signal period of the image output signal output from the CCD image sensor 19, the feedback clamp switch 4 is closed to the side b and the comparator 21 is set to the off state. Therefore, the control voltage V _C according to the feedback clamp control signal given during the feedback clamp period is
It is held at the same level. Next, during the feedback clamp period, the switch 4 for feedback clamp is closed to the side a, and the signals given to the capacitors 6 and 12 for feedthrough clamp are the same. For this purpose, the output terminal 53
The signals output to and 54 are only in-phase components in terms of alternating current, and by using, as the comparator 21 and the differential amplifier 22, a differential amplifier using a constant current source having an excellent common-mode rejection rate, its output voltage is changed. Signal component can be ignored, and in the comparator 21, only the DC voltage components of the signals output to the output terminals 53 and 54 are compared and the comparison result is output. No component is output. In this way, since the in-phase signal component can be ignored, it becomes possible to perform the feedback clamp even in the idling portion other than the OB period. If the feedback clamp can be performed in this idling portion, the fear of damaging the OB period by the feedback clamp in the sample hold circuit for the CCD image sensor is eliminated, and the signal processing unit after the sample hold holds the entire OB period. Can be used. In the idle transfer portion shown in FIG. 3, there may be a potential and a DC offset voltage in the OB period. In such a case, if the idle transfer portion is entirely used as the feedback clamp period. Since the idle transfer portion is input to the differential amplifier 22 as an in-phase component, the differential amplifier 2
The offset voltage component of the idle transfer is not output to the output of 2 and the potential of the OB period is output instead. Therefore, even when the differential amplifier 22 has a high gain,
When the idle transfer portion has an offset voltage in the opposite direction to the signal side, the inversion component is large in the conventional sample hold circuit, and even in the state where circuit saturation or the like becomes a problem, No problem at all.

Further, in the above-described embodiment, the side input to the sample hold via the switch 4 for feedback clamp is the no signal side, but in FIG. 1, conversely, the terminal 52 is connected to the signal side. Even if the circuit is configured by using the input terminal 51 as the input terminal and the input terminal 51 as the terminal on the non-signal side, the present invention can be applied without any problem as long as the input phase or the output phase at the input end of the differential amplifier 22 is set reversely.

The control signal output from the comparator 21 is applied to the switch 13 for the feedthrough clamp on the non-signal side in the above embodiment, but the input phase or output phase of the comparator 21 is inverted. Then, even if it is applied to the switch 7 for the feed-through clamp on the signal side, there is no change in characteristics and the present invention is applied. Furthermore, if the source impedance of the image output signal from the CCD image sensor 19 is sufficiently low,
The buffer amplifiers 2 and 3 shown in FIG. 1 are unnecessary, and the input terminal 51 can be directly connected to the feedthrough clamp capacitor 6 and the a side of the feedback clamp switch 4, and the terminals can be directly connected. It becomes possible to directly connect 52 to the b side of the switch 4 for feedback clamp.

The details of the operations of the sample and hold 5 and 11 are the same as those in the above-mentioned conventional example.

[0023]

As described above, according to the present invention, the CCD
Clamp scratches can be removed by adding a switch for feedback clamp that can be switched so that the image output signal output from the image sensor is also input to the sample hold on the non-signal side. There is an effect that the feedback clamp can be applied even outside the OB period of the CCD image sensor.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

FIG. 3 is a diagram showing an output voltage of a CCD image sensor in one horizontal period.

FIG. 4 is a diagram showing an output voltage in one pixel period of a CCD image sensor.

[Explanation of symbols]

1, 23 Sample and hold circuit 2, 3, 8, 14, 24, 25, 29, 35 Buffer amplifier 4, 7, 9, 13, 15, 27, 31, 33, 37, 4
1 Switch 5, 11, 26, 32 Sample and hold 6, 10, 12, 16, 20, 27, 31, 33, 3
7, 41 Capacitor 17, 38 Feedback clamp control voltage source 18, 39 Feedthrough clamp reference voltage source 19, 40 CCD image sensor 21, 42 Comparator 22, 43 Differential amplifier

Claims (2)

[Claims] 1. A voltage level of an image output signal of a CCD image sensor input via a first signal input terminal is clamped to a predetermined reference clamp voltage via a predetermined clamp operation control signal and output. And a first clamp circuit for inputting the image output signal to a first input terminal, and a second input terminal grounded through a second signal input terminal through a low impedance, An input switching circuit that switches and selects and outputs one of the signals at the second input terminal, and the output signal of the first clamp circuit is input to control the voltage level of the output signal by a predetermined sampling operation control. A first sample and hold circuit that samples and holds via a signal and outputs via a first signal output terminal, and a voltage level of a signal that is switched and selected by the input switching circuit. A second clamp circuit that clamps and outputs the bell to a clamp voltage supplied from a predetermined voltage varying unit via the same clamp operation control signal as that of the first clamp circuit; and the second clamp circuit. Second output signal is input, the voltage level of the output signal is sampled and held through the same sampling operation control signal as that of the first sample and hold circuit, and is output through the second signal output terminal.
The sample hold circuit according to claim 1, wherein the clamp voltage in the second clamp circuit compares the output voltage levels at the first and second signal output terminals only during a predetermined designated period, And the voltage varying means for adjusting the output voltage level of the second signal output terminal so as to have the same potential, and at least during the period when the image output signal of the CCD image sensor is input, The input switching circuit is set to select and output a signal connected to the second signal input terminal, and outputs the output signals at the first and second signal output terminals in a differential format. Sample and hold circuit characterized by. 2. A clamp which supplies a voltage level of an image output signal of a CCD image sensor, which is inputted through a first signal input terminal, by a predetermined voltage varying means through a predetermined clamp operation control signal. A first clamp circuit that clamps and outputs a voltage and the image output signal is input to a first input terminal, and a second input terminal is grounded through a second signal input terminal through a low impedance. An input switching circuit that switches and selects and outputs one of the signals at the first and second input terminals, and inputs the output signal of the first clamp circuit to change the voltage level of the output signal. A first sample-hold circuit that performs sample-holding via a predetermined sampling operation control signal and outputs via a first signal output terminal, and is switched and selected by the input switching circuit. A second clamp circuit that clamps the voltage level of the output signal to a predetermined reference clamp voltage via the same clamp operation control signal as the first clamp circuit, and outputs the clamp signal; Second output signal is input, the voltage level of the output signal is sampled and held through the same sampling operation control signal as that of the first sample and hold circuit, and is output through the second signal output terminal.
The sample hold circuit according to claim 1, wherein the clamp voltage in the first clamp circuit compares the output voltage levels at the first and second signal output terminals only during a predetermined designated period, And the voltage varying means for adjusting the output voltage level of the second signal output terminal so as to have the same potential, and at least during the period when the image output signal of the CCD image sensor is input, The input switching circuit is set to select and output a signal connected to the second signal input terminal, and outputs the output signals at the first and second signal output terminals in a differential format. Sample and hold circuit characterized by.