JPH04258093A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To eliminate an undesired noise component appearing a CCD sensor output for a blanking period. CONSTITUTION:A 1st sample circuit 25 is used to sample a picture signal for a picture signal output period being a CCD output signal and a 2nd sample circuit 33 samples a potential from a voltage source for a blanking period of the picture signal. Outputs of the two sample circuits 25,33 are subject to holding by a common capacitor C2 and either of the sample circuits 25,33 is operated by an external switching signal. A 3rd sample circuit 27 samples and holds an output for an optical black level output period when the 1st sample circuit 25 is in operation and a 4th sample circuit 28 samples and holds a blanking level when the 2nd sample circuit 33 is in operation, the 3rd and 4th sample and hold voltages are compared and the voltage source of the 2nd sample circuit 33 is controlled so that the 3rd and 4th sample and hold voltages are equal to each other.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit for processing CCD output signals, and more particularly to a signal processing circuit for processing even minute output signal levels, such as in a CCD area image sensor.

0002

2. Description of the Related Art Conventionally, there is a signal processing circuit for a CCD area image sensor as shown in the block diagram of FIG. This circuit includes a clock generator 11 that outputs a sample timing f and a CCD reference clock, a CCD area image sensor 12, a buffer amplifier 13 that amplifies the output of this CCD sensor 12, and this buffer amplifier 13.
The signal processing circuit 10b processes the output of the signal processing circuit 10b, and the AGC circuit 14 amplifies the output of the signal processing circuit 10b. Further, the signal processing circuit 10b includes a clamp switch 2
3 and sample switch 25, a clamping voltage source 22, buffer amplifiers 24 and 25, and capacitors C1 and C2.

FIGS. 5(a) to 5(c) show operational waveform diagrams of FIG. 4. The output signal from the CCD sensor 12 is shown in FIG.
As shown in (a), the feedthrough period T1 of the charge detection capacitor reset pulse is followed by the zero level output period T.
2, and then a signal output period T3 due to signal charges.
There is. By turning on and off the clamp switch 23 using the clamp pulse (FIG. 5(b)) which is the output of the pulse generator 20, the zero level of the output signal from the CCD sensor (FIG. 5(a)) can be adjusted. The potential during the output period T2 is clamped by the voltage source 22. As a result, the signal obtained from the buffer amplifier 24 can have components such as 1/f noise and reset noise significantly reduced compared to the output signal of the CCD sensor.

Furthermore, by using this signal as a sample pulse (FIG. 5(c)), which is the output of the pulse generator 20, to turn on and off the sample switch 25, the voltage level during the signal output period T3 due to the signal charge can be adjusted. sample to the hold capacitor C2 of C2, and the other period T1,
Hold this capacitor at T2. This allows the buffer amplifier 26 to output only voltage changes as a video signal.

[0005]

[Problems to be Solved by the Invention] Since the conventional signal processing circuit 10b described above continuously performs this clamping/sampling operation, it actually does not perform the horizontal blanking period during which the pixel signal of the CCD sensor is not output, nor during the vertical blanking period. It also operates during the period. However, the CCD area image sensor 12 performs vertical transfer during this blanking period, and this transfer pulse has a large amplitude of 7 to 8 VP-P. Therefore, the output signal from the CCD is affected by the drive pulse during this blanking period, and is usually several mV to several tens of mV.
Some noise is observed.

[0006] The output signal of the CCD sensor is 2 when normal.
Since signal processing is performed with a value around 00mVP-P as a 100% white level, this level of noise during the blanking period is not much of a problem, but if the sensitivity is increased in low illuminance, it will be amplified by about 18dB by the AGC circuit in the subsequent stage. Ru. As a result, the output signal of the CCD sensor is 25mVP
-P is the 100% white level, so the noise during the blanking period is at a level equivalent to or higher than that of the regular output signal (see FIG. 2(b)). This causes a problem in that a voltage with a large amplitude is output to the AGC circuit 14, and in some cases, it may appear as interference to the image, such as sub-shading or the like.

An object of the present invention is to solve these problems and to prevent noise components that interfere with video signals from occurring not during the pixel signal output period of the CCD sensor but during the blanking period that is unnecessary for the video. It is an object of the present invention to provide a video signal processing circuit which blocks samples of unnecessary noise components by switching to samples of DC potential corresponding to the black level during unnecessary periods.

[0008]

[Means for Solving the Problems] The configuration of the present invention includes a CCD
In a video signal processing circuit having a correlated double sampling circuit that reduces noise in a video signal by clamping the output signal immediately after reset and sampling the video signal output period, sampling is performed by a switching signal during the video signal output period. a second sample circuit that samples the potential from the voltage source using an inverted signal of the switching signal during the blanking period of the image signal; and outputs of these first and second sample circuits. a capacitor that is held in common; a third sample circuit that samples and holds the optical black level output period while the first sample circuit is operating; and a third sample circuit that samples and holds the blanking level while the second sample circuit is operating. 4th to do
The present invention is characterized by comprising a sample circuit, and a feedback circuit that compares the third and fourth sample-and-hold voltages and controls them so that they are equal, and uses the third and fourth sample and hold voltages as a voltage source for the second sample circuit.

[0009]

[Embodiment] Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2
(a) to (e) are waveform diagrams illustrating the operation.

This embodiment differs from the conventional example in that optical black (
A sample switch 27 and a capacitor C3 for sampling and holding the level (hereinafter referred to as OB; optical black), a sample switch 28 and a capacitor C3 for sampling and holding the level during the blanking period.
4 is added to the buffer amplifier 26, and the respective hold values are input to the integrating circuit and voltage source 31 through the buffer amplifiers 29 and 30. Here, the hold value of the OB level is used as a reference voltage, the hold value of the blanking period is subtracted, and it is configured to become a voltage source for the sample switch 33 via the buffer amplifier 32.

The output signal from this CCD sensor 12 is
After the impedance is converted by the buffer amplifier 13, DC cut is performed by the capacitor C1, and a clamping operation is performed by charging the capacitor C1 with the voltage source 22 by the clamp switch 23, which is the same as in the conventional circuit.

Next, after passing through the buffer amplifier 24, the signal period is sampled by the sample switch 25 and held by the capacitor C2.
A sample switch 33 is connected to the sample switch 33, and sample pulses are distributed to the sample switches 25 and 33 through the sample pulse changeover switch 21 according to the blanking pulse k, and during the blanking period T4, the sample switch 33 is connected to During the pixel signal output period T6, the sample switch 25 operates. As a result, the video signal obtained from the buffer amplifier 26 is replaced with the voltage from the integrating circuit (and voltage source) 31 during the blanking period, so that the video signal obtained from the buffer amplifier 26 is a signal from which noise during the blanking period has been removed, as shown in FIG. 2(e). becomes.

Further, the voltage of the voltage source 31 is inputted to the buffer amplifier 32 as an inverted signal of the difference between the OB section and the blanking section output from the buffer amplifier 26 by subtracting the OB level and the blanking level. For,
A feedback circuit is configured with a path passing through the buffer amplifier 26, sample switch 28, buffer amplifier 30, integrating circuit (voltage source) 31, buffer amplifier 32, sample switch 33, and buffer amplifier 26, and thereby the OB level and blanking. It operates so that the voltage difference between the

FIG. 3 is a block diagram of a second embodiment of the present invention. In this embodiment, the output of the buffer amplifier 26 is subjected to impedance conversion independently by the buffer amplifiers 34 and 35 in contrast to FIG. As a result, the number of buffers increases, or the sample noise caused by the sample switches 27 and 28 is input directly to the AGC amplifier 14 in the case of FIG. 1, but it is clear that it is considerably reduced in this embodiment. This is an effective countermeasure when this sample noise causes a level difference in the OB clamp at the subsequent stage depending on the gain of the AGC amplifier.

[0015]

Effects of the Invention As explained above, the present invention can remove unnecessary noise components that appear in the CCD sensor output during the blanking period, thereby preventing image interference such as shading that is likely to occur in the subsequent AGC amplifier. The effect is that it can be done.

[Brief explanation of the drawing]

FIG. 1: Block diagram of one embodiment of the present invention

[Figure 2] Waveform diagram explaining the operation of Figure 1

FIG. 3 is a block diagram of a second embodiment of the present invention.

[Fig. 4] Block diagram of an example of a conventional video signal processing circuit

FIG. 5 is a waveform diagram illustrating the operation of FIG. 4;

[Explanation of symbols]

10, 10a, 10b signal processing circuit 11
Clock generator 12 Image sensors 13, 24, 26, 29, 30, 32, 34, 35
Buffer amplifier 14 AGC amplifier 20 Pulse generation circuit 21 Sample pulse selection switch 22
Voltage source 23 Clamp switch 25, 27, 28, 33 Sample switch 31
Integrating circuit (voltage source)

Claims (2)

[Claims] 1. A video signal processing circuit having a correlated double sampling circuit that reduces noise in a video signal by clamping the output signal of a CCD immediately after reset and sampling the video signal output period, wherein the video signal output period is a first sample circuit that samples a potential from a voltage source using an inverted signal of the switching signal during a blanking period of the image signal; a capacitor in which the outputs of the two sample circuits are commonly held; a third sample circuit that samples and holds the optical black level output period during the operation of the first sample circuit; A fourth sample circuit samples and holds the planking level, and these third sample circuits sample and hold the planking level.
, and a feedback circuit that compares the fourth sample-and-hold voltages and controls them so that they are equal, and uses the feedback circuit as a voltage source for the second sample circuit. 2. The video signal processing circuit according to claim 1, wherein the common output of the first and second sample circuits is supplied to the third and fourth sample circuits via a buffer amplifier.