JP2784782B2 - CCD output circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CCD output circuit suitable for use in, for example, a solid-state imaging device using a CCD (charge-coupled device).

[Summary of the Invention]

A CCD output circuit according to the present invention is a CCD output signal in which at least a reference level section and a signal section are repeated at a constant clock cycle, and outputs the CCD output signal to a sample hold circuit that samples the reference level section and a sample hold circuit that samples the signal section. The input and output signals of the sample and hold circuit that sampled the reference level portion and the sample and hold circuit that sampled the signal portion are output using a common sampling pulse having a different phase from the sampling pulse that samples the signal portion. By sampling, noise during the sampling period of the signal section is removed, and errors due to differences in the hold time of the input signal input to the differential circuit are reduced.

[Conventional technology]

FIG. 3 shows a schematic block diagram of a conventional CCD output circuit.

In this Figure 3, the input terminal 31 as shown in FIG. 4 (a), CCD output signal as at least a reference level portion R _G and the signal portion R _H is repeated at a constant clock period T _E is input Have been. Incidentally, R _F shown in FIG. 4 (a) is a pre-charge pulse unit.

Such a CCD output signal is input to each of the sample and hold circuits 32 and 33 shown in FIG.

The above-mentioned CCD hold input circuit 32
The output signal is the sampling pulse SHP shown in FIG.
And the reference level portion _RG is sampled and held to obtain an output signal _VP1 shown in FIG. This output signal _VP1 is input to the sample and hold circuit 34.

In the sample hold circuit 33, the input CC
By sampling and holding with the sampling pulse SHD showing a signal portion R _H of the D output signal to the fourth view (c), the output signal V _D shown in FIG. (F).

Here, as each sample-hold output signal to be input to a pair of input terminals of the differential amplifier 35 described later, in order to prevent an error due to a level change at the time of holding, a signal sampled at the same timing is input. The same sampling pulse is used for the sample and hold circuits 33 and 34.

Therefore, in the sample hold circuit 34, the input output signal VP1 is sampled using the sampling pulse SHD, and the output signal V _P1 shown in FIG.
Outputs _P2 .

These output signals V _P2 and the output signal V _D is inputted to the non-inverting input terminal 35a and the inverting input terminal 35b of the differential amplifier 35.

In the differential amplifier 35, the input output signal V
_P2 and compares the output signal V _D is taken out via the output terminal 36 an output signal V _OUT shown in FIG. 4 amplifies the difference (g).

[Problems to be solved by the invention]

However, the input CCD output signal includes, for example, the C
Noise caused by fluctuations in the CD output signal, jump noise such as CCD drive pulse components, power supply noise, etc. are superimposed. Also, the sampling pulse has a pulse width (hereinafter referred to as sampling period _TP2 ). C
When a CD output signal is sampled and held by the sample-and-hold circuit 32 and 33, the noise N ₃ The superimposed CCD output signal of the noise as described above during the sampling period T _P2 of the sampling pulse in the output signal for thereby sampling, N _Four
Are superimposed.

Then, the output signal V _D of the sample hold circuit 33 would be input to the left differential amplifier 35 which is superposed above the noise N _4, the output signal of the differential amplifier 35 shown in FIG. 4 (g) the V _OUT, high-frequency noise N ₅ that the noise N ₄ is amplified has fallen superimposed.

This becomes remarkable when the duty ratio of the sampling pulse due to the density of CCD pixels is increased, especially in the case of black object, the output signal V _OUT for amplifier gain is large signal component is small just large level noises This causes an error in signal processing such as clamp processing which is signal processing later.

The present invention has been made in view of the above problems, and has as its object to provide a CCD output circuit capable of removing noise during a sampling period and obtaining an output signal on which noise is not superimposed.

[Means for solving the problem]

In order to solve the above-described problem, the CCD output circuit according to the present invention is configured to obtain an output corresponding to the signal unit from a CCD output signal in which at least the reference level unit and the signal unit repeat at a constant clock cycle. An output circuit to which the CCD output signal is input, a first sample and hold circuit for sampling a reference level portion thereof by a first sampling pulse, and a second sampling pulse to which the CCD output signal is input; A second sample-and-hold circuit that performs sampling by the first and second sample-and-hold circuits, a third sample-and-hold circuit that receives an output from the first sample-and-hold circuit, and samples by the second sampling pulse, and the third and second sample-and-hold circuits The outputs from the circuits are supplied respectively, and the sampling is performed by the first sampling pulse. A fourth and fifth sample and hold circuit graying, is characterized by comprising a differential circuit which outputs of said fourth and fifth sample-and-hold circuit is inputted.

(Operation)

A CCD output circuit according to the present invention resamples noise superimposed during a sampling period when a signal portion in a CCD output signal is sampled and held using a sampling pulse having a phase different from the sampling pulse of the signal portion. Can be removed.

〔Example〕

Hereinafter, embodiments of a CCD output circuit according to the present invention will be described with reference to the drawings.

FIG. 1 is a schematic block diagram showing an embodiment of a CCD output circuit according to the present invention.

Here, the above-described first, second, third, and fourth sample-and-hold circuits correspond to the sample-and-hold circuits 2, 3, 5, and 6 in FIG. 1, respectively.

In the first diagram, the output signal from the CCD solid-state image pickup device such as a reference level portion R _C and the signal unit R _D shown in FIG. 2 (A) is repeated at a constant clock period T _A is through the input terminal 1 Input to each of the sample and hold circuits 2 and 3. Note that the CCD shown in FIG.
R _B of the output signal is a precharge pulse portion, the said CCD output signal, for example, noise and caused by variation of the CCD output signal, jump noises of the sampling pulse drive components of the CCD are superimposed.

The sample and hold circuit 2 samples and holds the reference level portion _RC of the CCD output signal by the sampling pulse SHQ shown in FIG.
The output signal V _Q1 shown in FIG. Here, the input signal is sampled during the pulse width (sampling period T _P1 ) of the sampling pulse SHQ. Since noise is superimposed on the CCD output signal, as described above, the noise N ₁ shown in FIG. 2 (d) is superimposed on the output signal V _Q1 during the sampling period T _P1 of the sampling pulse SHQ.

This output signal V _Q1 is input to the sample and hold circuit 4 next.

In the sample hold circuit 3, the input CC
The signal portion R _D of the D output signal, and outputs an output signal V _E1 shown in sampled second diagram (g) by the sampling pulse SHR. This output signal _VE1 has a sampling pulse S
Noise N ₂ during the sampling period T _P1 of HR is superimposed.

This output signal _VE1 is input to the sample and hold circuit 6.

Here, as the sampling pulse of the sample and hold circuit 4, the same pulse as the sampling pulse SHR of the sample and hold circuit 3 is used. Sampling pulse SHR of the sample hold circuit 4, since the above sampling pulse SHQ have different phase, avoiding superposition to that of the noise N ₁ of the output signal V _Q1 to be input, of the noise N ₁ You can sample the signal F ₁ portion does not overlap, it is possible to output an output signal V _Q2 that is not superimposed the noise shown in FIG. 2 (e).

The output signal _VQ2 from the sample and hold circuit 4 is input to the sample and hold circuit 5.

The sample and hold circuit 5 and the sample and hold circuit 6 sample with a common sampling pulse having a different phase from the sampling pulse SHR of the sample and hold circuit 3, for example, SHQ. Here, the above signal V _E1 input to the sample-hold circuit 6, but not the noise N ₂ at the sampling timing of the sampling pulse SHR is superimposed,
Since the sampling pulses SHQ phase of the sample and hold circuit 6 is different from the sampling pulse SHR, it is possible to sample the signal F ₂ of the portion does not overlap the noise N _2, shown in FIG. 2 (h) An output signal _VE2 without noise is output. This output signal _VE2 is input to the inverting input terminal 7b of the differential amplifier 7. The sample hold circuit 5 outputs an output signal _VQ3 shown in FIG. 2 (f), and this output signal _VQ3 is input to the non-inverting input terminal 7a of the differential amplifier 7.

As described above, the output signals V _Q3 and V _E2 from the respective sample and hold circuits 5 and 6 are supplied to the pair of input terminals 7a and 7b of the differential amplifier 7, respectively.
By performing sampling at the same timing, the level error of the differential input pair due to the difference in each hold time can be eliminated.

The differential amplifier 7 receives the output signal V _Q3
It compares the output signal V _E2 and amplifies the difference, and outputs an output signal V ₀ shown in FIG. 2 (i) which does not overlap the noise.

〔The invention's effect〕

According to the CCD output circuit according to the present invention, the output signals from the third and second sampling and holding circuits that sample the reference level portion and the signal portion of the CCD output signal with the second sampling pulse are output by the fourth and fourth sampling hold circuits, respectively. Since the fifth sample and hold circuit samples the signals with the first sampling pulse having a phase different from that of the second sampling pulse and supplies the signals to the differential circuit, the noise of the high frequency component superimposed on the signal section Can be eliminated, and the noise-eliminated signal is output through the differential circuit, so that a stable output signal free of the noise can be output.

Further, since only two types of sampling pulses, the first and second, are used, the generation of sampling pulses and wiring are simple.

Further, the level error between the pair of inputs of the differential circuit can be reduced by using the same sampling pulse for the fourth and fifth sample-hold circuits that supply the output to the differential circuit.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing an embodiment of a CCD output circuit according to the present invention, and FIG. 2 is a time chart for explaining the operation of the embodiment. FIG. 3 is a schematic block diagram of a conventional CCD output circuit, and FIG. 4 is a time chart for explaining the operation of the conventional CCD output circuit. 1 input terminal 2-6 sample hold circuit 7 differential amplifier 7a non-inverting input terminal 7b inverting input terminal 8 output terminal

────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Akihiko Ikeda 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Yutaka Murakami 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (56) References JP-A-61-273092 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04N 5/30-5/335

Claims (1)

(57) [Claims] A CCD output circuit configured to obtain an output corresponding to the signal portion from a CCD output signal in which at least a reference level portion and a signal portion are repeated at a constant clock cycle, wherein the CCD output signal is input; The reference level part is the first
A first sample-and-hold circuit that samples with a sampling pulse of the above, a second sample-and-hold circuit that receives the CCD output signal, and samples its signal portion with a second sampling pulse, and a first sample-and-hold circuit. And a third sample-and-hold circuit that is supplied with the output of the second sampling pulse and outputs the signals from the third and second sample-and-hold circuits, and performs sampling with the first sampling pulse. A CCD output circuit comprising: fourth and fifth sample and hold circuits; and a differential circuit to which the outputs of the fourth and fifth sample and hold circuits are supplied.