JPH099149A - Ccd image pickup signal processing circuit - Google Patents

Abstract

PURPOSE: To obtain the CCD image pickup signal processing circuit in which noise of an output signal of a charge transfer element having a gate inclusive charge integration output circuit is reduced, the S/N is improved and a noise eliminating characteristic is improved. CONSTITUTION: A charge coupled element 1a is provided with gate inclusive charge integration output circuits 15, 16 each providing an output of a signal corresponding to a reference level and a signal charge for each period of a transfer clock pulse. Clamp circuits 31, 32 clamp each output signal corresponding to the reference level obtained from the gate inclusive charge integration output circuits 15, 16 to a preset potential. The clamped signal is given to a selection circuit consisting of transistors(TRs) 33, 34, and a signal with a larger amplitude in two signals corresponding to the signal charge after clamping is outputted to an output terminal 36. Then the reference potential is clamped to a reset potential and reset noise is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CCD image pickup signal processing circuit, and more particularly to a CCD having a dual channel read structure and a horizontal shift register with improved noise elimination characteristics.
The present invention relates to an image pickup signal processing circuit.

[0002]

2. Description of the Related Art Conventionally, charge-coupled devices (hereinafter also referred to as CCDs) have been increased in number of pixels in order to achieve high image quality, and in high definition television systems such as HDTV, ultra high definition of 2 million pixels or more. The CCD has been developed. Along with the progress of the increase in the number of pixels, there is a tendency that the pattern density is increased, the clock rate is increased, and the sensitivity per unit pixel is decreased. CCD signal processing circuits that handle CCD output signals in such a tendency are required to have higher sensitivity and lower noise.

On the other hand, as an effective noise elimination circuit devised for noise reduction, there is a gate type noise elimination circuit. In this method, a gate circuit is used instead of the S / H circuit, and only the effective signal component in the CCD output is extracted, thereby suppressing the aliasing of high frequency noise generated during sample hold into the band. ing.

On the other hand, as a method for increasing the sensitivity, there is a horizontal pixel addition mode in a high definition CCD having a horizontal CCD having a dual channel read structure. This is because when the signal charges of pixels adjacent in the horizontal direction are distributed from the vertical shift register to the two horizontal shift registers, the transfer electrodes arranged between the two horizontal shift registers are turned off. The allocation to the horizontal shift register of the second channel on the side is stopped. As a result, the addition can be performed on the upper horizontal shift register of the first channel, the signal amplitude is increased, and the sensitivity can be equivalently increased.

If the above-described method of increasing the sensitivity (horizontal pixel addition mode) can be applied to the above-mentioned gate type noise eliminating circuit, the effect of increasing the sensitivity and reducing the noise can be further enhanced. However, a simple combination of both methods cannot provide the effect of increasing the sensitivity. These relationships will be described in more detail below with reference to the drawings.

(Conventional Technology for Noise Reduction) FIG. 6 shows an example of conventional technology for noise reduction. In the conventional example, a detection diode 8 for detecting a signal charge transferred by the CCD 1a and converting it into an output voltage is provided near one transfer electrode 7 of the charge coupled device (CCD) 1a. . The signal charge transferred by the transfer electrode 9 to which the transfer clock pulses φ1 and φ2 are applied flows into the detection diode 8 for each cycle of the transfer clock pulse, and changes its potential.

The buffer circuit 40 receives this potential change and takes out the output signal Vout to the outside. A reset pulse φR is applied to the gate of the reset transistor 41 at the same period as the transfer clock pulse, and the reset transistor 4 is applied.
By putting 1 into conduction, the detection diode 8
The potential of is reset to the reference potential. This gated charge integration output circuit 42 (hereinafter, also referred to as charge integration output circuit).
Is well known.

In the charge integration output circuit 42, the reset transistor 41 generates noise as described below. FIG. 7 is a waveform diagram for explaining the operation of the charge integration output circuit shown in FIG. In FIG. 7, when the reset pulse φR is applied from time t0 to time t1 and the reset transistor 41 becomes conductive, the potential of the detection diode 8 rises to the drain voltage V of the reset transistor 41.

Next, at time t1, the reset transistor 4
When 1 becomes non-conducting, the charge of the detecting diode 8 has two capacitances, that is, the capacitance 43 corresponding to the total of the detecting diode 8 and the gate capacitance of the buffer circuit 40 and the capacitance between the gate and the source of the reset transistor 6. It becomes a fixed reference potential V0. Next, at time t2, the detection diode 8
The signal charge is transferred to and injected into, and its potential is changed to obtain the output voltage Vs.

Here, while the reset transistor 41 is conducting from time t0 to t1, the reset transistor 4 generates a noise En of a certain magnitude. The noise En affects and changes the reference potential V0.
For example, as shown in the figure, each time the reset pulse .phi.R is applied, the voltage changes from V0 to Vn, resulting in reset noise Vn.

In addition to the noise Vn, noise generated by the buffer circuit 40 for extracting the signal to the outside is further superimposed. In FIG. 7, the noise Vb included in the output signal Vout shows the noise generated by the buffer circuit 40.

As described above, in the charge integration output circuit, the reset noise Vn generated when the charges are reset in the output signal and the noise Vb generated by the buffer circuit for extracting the signal to the outside are included in a superimposed manner. . The correlated double sampling method is well known as a method for removing the noise.

(Prior Art for Increasing Sensitivity) FIG. 8 shows a general circuit configuration example of a conventional CCD image pickup signal processing circuit for increasing sensitivity. The CCD image pickup signal processing circuit in FIG. 8 is C
It is composed of a CD 1b and an image pickup signal processing circuit 2.

One of the CCDs 1b includes an image pickup section composed of a photodiode 10 and a vertical shift register 11, two horizontal shift registers 13 and 14, and two gated charge integration output circuits 15 and 16 (hereinafter referred to as "charge integrated output circuits"). , And also simply referred to as a charge integration output circuit).

The other signal processing circuit is a gate type noise removing circuit, and an example of the signal processing circuit configuration in the case where the horizontal plane element mode is simply applied is shown. First, the operation in the normal operation mode in this conventional example will be described.

The signal charges photoelectrically converted by the photodiode 10 are read out to the vertical shift register 11 and transferred line by line to the horizontal shift registers 13 and 14. In the normal operation mode, the vertical shift register 11
The signal charges transferred from the first and second horizontal shift registers 13 and
It is distributed to the horizontal shift register 14 of the channel. The distributed signal charges are transferred on the horizontal shift registers 13 and 14, respectively, and the charge integration output circuit 1
It is output from 5 and 16. The output signals of the charge integration output circuit 15 of these first channels are input to the clamp circuit 22 via the buffer circuit 19. The output signal of the charge integration output circuit 16 of the second channel is input to the delay line 20 and delayed by 1/2 pixel cycle. The output signal from the delay line 20 is input to the amplifier circuit 21, and the attenuated signal level is amplified to the signal level of the first channel (the output signal of the buffer circuit 19). Further, the output signal of the amplifier circuit 21 is input to the clamp circuit 23.

By the above operation, the CCD output signals of the first and second channels whose signal levels are 180 ° out of phase with each other and whose signal levels are equal are input to the respective clamp circuits 22 and 23. Further, the clamp pulse generated by the pulse generator 26 is applied during the feed-through period of each CCD output signal, and the potential during the feed-through period of each signal is clamped to the constant level VDC. The output signals A and B of the clamp circuits 22 and 23 are supplied to the gate circuit 24.
Is input to. The gate circuit 24 opens and closes based on the signals A and B, and outputs a combined signal of the CCD output signals A and B of the first and second channels. Gate circuit 24
The output signal C of is output to the subsequent process circuit via the buffer circuit 25.

On the other hand, in the horizontal pixel addition mode, the transfer electrodes ΦT arranged with the two horizontal shift registers 13 and 14 interposed therebetween are set to the off state. Therefore, the signal charges of the horizontally adjacent pixels transferred from the vertical shift register 11 are read in parallel to the horizontal shift register 13 of the upper first channel. However, since the transfer electrode ΦT is in the off state, the signal charges of the pixels adjacent in the horizontal direction are not distributed to the horizontal shift register 14 of the lower second channel, and the signal charges of the adjacent pixels are generated in the subsequent horizontal transfer process. The two are mixed.

As described above, in this mode, the signal charges of pixels in the horizontal direction are added to each other, and only the charge integration output circuit 15 of the first channel outputs the signal A'of the effective pixel having the increased signal level. An output signal B ′ having a signal level of zero is output from the charge integration output circuit 16 of the second channel. Therefore, the signal level of which the signal level is increased every other pixel is extracted from the gate circuit 24 and output as the output signal C ′ via the buffer circuit 25.

Next, the operation of the signal processing circuit in the normal operation mode and the horizontal pixel addition mode will be described with reference to the time charts of FIGS. 9 and 10 and the waveform chart of FIG. In the normal operation mode, the signal charges transferred through the vertical shift register 11 and the horizontal shift registers 13 and 14 are output from the charge integration output circuits 15 and 16 of the respective channels. In this embodiment, the output signals of the two-channel charge integration output circuit have the same phase, that is, the effective signal voltages are output at the same timing. As shown in FIG. 11, the output signal of the CCD has a reset period a in which a reset pulse is applied to the reset transistor of the output portion in one pixel cycle and a feedthrough period in which the detection capacitance is reset to a constant potential by the operation of the output portion. B, and a signal period C in which signal charges are injected into the detection capacitor.

With respect to the CCD output signal of the first channel, the voltage in the feed-through period (b) of the clamp circuit 22 is constant potential V.
It is clamped to DC and output as signal A. On the other hand, the CCD of the second channel which has the same phase as the output signal of the first channel
If the output signal Z ′ is mixed with the signal of the first channel in the same phase as it is, the resolution deteriorates. Therefore, the delay line 20 delays by 1/2 pixel period,
It is set to a phase (180 ° delay) that interpolates the channel signal. Then, it is amplified by the amplifier 21, further clamped by the clamp circuit 23 so that the voltage during the feed-through period (b) becomes the constant voltage VDC, and output as the signal B. The gate circuit 24 that mixes the signals A and B has a configuration of a clipping circuit, and one input signal has a relation of a reference potential at which one input signal is clipped to another, and the output of the gate circuit 24 Outputs the signal with the lower potential in terms of direct current. In the time charts of FIGS. 9 and 10, the effective signal charge of the output signal A of the clamp circuit 22 is A1, A2, A3, A4, below the clamp potential VDC.
Appears as ... Similarly, the output signal B of the clamp circuit 23
Then, they appear as B1, B2, B3, B4, ....

Regarding the phase relationship between the two signals, the signal period of one signal is set to be the reset period B and the feedthrough period B of the other signal. Therefore, from the output of the gate circuit 24, only the signal level equal to or lower than the potential VDC of the feedthrough level is output. That is, the output signal, like the signal C, has A1, B
2 in the order of 1, A2, B2, A3, B3, A4, B4, ...
The effective signals of the two channels are mixed and output alternately.

By the above operation, the CCD output signals of the two channels can be converted into continuous signals without sample and hold. In this method, since the sample and hold is not performed, the high frequency noise is not folded back within the band, and the noise component of the CCD can be effectively removed.

Next, the operation when the present system is simply adapted to the horizontal pixel addition mode will be described. In the horizontal pixel addition mode, signal charges (A1
And B1, A2 and B2, A3 and B3, A4 and B4, ... Are added, and a signal A ′ (effective signal voltage A1 + B) of the effective pixel is added.
1, A2 + B2, A3 + B3, A4 + B4, ...) Is output from the charge integration output circuit 15 of the first channel.

On the other hand, since the signal charges are not distributed on the horizontal shift register 14 of the second channel, the signal output from the charge integration output circuit 16 of the second channel is the signal voltage B'in the signal period as shown by B '. It does not appear and is kept at the potential VDC at the feedthrough level. Therefore, in the output signal of the gate circuit 24, the signal levels A1 + B1, A2 + B2, A3 + B3, A4 obtained by adding the signals of the two pixels
+ B4, ... Are output every other pixel.

As a prior art similar to the present invention in the technical field, Japanese Patent Laid-Open No. 62-139358 for clamping the feedthrough level of an output signal at a constant potential, and Japanese Patent Laid-Open No. 63-90852 for providing an integrating circuit and a sample hold circuit. There are issues, etc.

[0027]

However, the noise that can be removed by the above procedure for reducing noise is limited to the reset noise Vn. That is, the above-described conventional noise removal circuit for the charge coupled device removes the noise Vb generated by the buffer circuit as a result of sampling the output signal on which the noise Vb generated by the buffer circuit is superimposed in the sampling circuit. I can't. Therefore, there is a problem of deteriorating the signal-to-noise ratio.

In addition, in order to increase the above-mentioned sensitivity, a signal after sampling is usually subjected to removal of signal components outside the band by a low-pass filter. At this time, since the signal level of this output signal appears only every other pixel, LP
The signal component smoothed by F and having the signal level increased by the horizontal pixel addition operation is reduced. Therefore, there is a problem that the sensitivity cannot be increased simply by applying the gate type noise removal circuit to the horizontal pixel addition mode.

It is an object of the present invention to provide a CCD image signal processing circuit which is applied to a CCD image sensor having a dual channel readout structure and which has a reduced noise and a higher sensitivity and has an improved noise elimination characteristic.

[0030]

To achieve the above object, the CCD image pickup signal processing circuit of the invention of claim 1 outputs a signal corresponding to a reference potential and a signal charge for each cycle of a transfer clock pulse. A charge-coupled device including first and second charge-integrated output circuits with gates, and a first predetermined value in which an output signal corresponding to a reference potential obtained from the first charge-integrated output circuits with gates is preset. A first clamp means for fixing the potential to a potential, and a second clamp means for fixing an output signal corresponding to a reference potential obtained from the second charge-integrated output circuit with a gate to a preset second predetermined potential. The output from the first and second clamping means is connected, and the selecting means outputs the signal having the larger amplitude of either of the two signals corresponding to the signal charges after clamping.

Further, the first gate-integrated charge integration type output circuit and the second gate-integrated charge integration type output circuit are provided in the same charge coupled device, and the first gate-integrated charge integration type output circuit is the first It is preferable that one charge-coupled device be provided with the second charge-integrated output circuit with a gate and the second charge-coupled device be provided so that the first predetermined potential and the second predetermined potential are the same.

According to a fifth aspect of the present invention, in the CCD image signal processing circuit, two signal charges adjacent to each other in the horizontal direction of the photodiode groups arranged in a matrix form first and second signal charges.
The horizontal shift registers of the channels read in parallel, and the transistor electrodes arranged between the two horizontal shift registers transfer the signal charge from the horizontal shift register of the first channel to the horizontal shift register of the second channel. An image pickup signal processing circuit for processing a signal of a charge-coupled device including a charge integration output circuit for inputting a signal based on a signal charge from the horizontal shift registers of the first and second channels, and a charge integration output of the first and second channels. First and second switch means connected to the output of the circuit for selecting and outputting the signals of these two channels, buffer means connected to the first switch means, and second switch means. A delay line and an amplifying means, and first and second clocks connected to respective outputs of the buffer means and the amplifying means. Pump means, gate means connected to the outputs of the first and second clamp means and mixing the two output signals, and pulse generation means for generating a clamp pulse for controlling the timing of the clamp operation of the clamp means. It is characterized by being configured as.

In the normal read operation of the CCD image pickup signal processing circuit, the output signals of the charge integration output circuits corresponding to the respective channels are connected to the subsequent stages in the first and second switch means, and the horizontal direction is also applied. In the operation of adding and reading the signal charges of the photodiodes adjacent to, the output of the charge integration output circuit of the second channel is connected in the first switch means, and the charge integration of the first channel is connected in the second switch means. The output of the output circuit should be connected.

Further, the delay time of the delay line is set to 1/2 pixel cycle of the output of the charge integration output circuit, and the clamp pulses generated by the pulse generating means and having a phase difference of 180 ° are applied to the clamp means. It is preferable that the output signals of the buffer means and the amplifying means of No. 1 are used as input signals and clamped so that the feedthrough level of the signals becomes a constant potential. In the gate means, it is preferable to extract only the effective signal level from the output signals of the first and second clamp means.

[0035]

Therefore, according to the CCD image pickup signal processing circuit of the first aspect of the invention, the CCD image pickup signal processing circuit is connected to the charge coupled device for outputting the signal corresponding to the reference potential and the signal charge for each cycle of the transfer clock pulse. The output signal corresponding to the reference potential is fixed to a preset first predetermined potential, and the output signal corresponding to the second reference potential is fixed to a preset second predetermined potential. One of the two signals corresponding to the signal charges after the clamping, which has the larger amplitude, is selected and output. Therefore, the reference potential is clamped to the reset potential.

Further, according to the CCD image pickup signal processing circuit of the invention of claim 5, it is connected to the outputs of the charge integration output circuits of the first and second channels of the charge coupled device, and the signals of one of these two channels are connected. The signal is buffer-amplified, the other signal is delayed and the amplified amount is amplified, and the respective signals are clamped. The two clamped signals are mixed. Therefore, by setting the delay phase to 180 °, only the effective signal components of the two signals can be extracted.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A CCD according to the present invention will now be described with reference to the accompanying drawings.
An embodiment of the image pickup signal processing circuit will be described in detail. Referring to FIGS. 1 to 5, a CCD having improved noise reduction characteristics according to the present invention
An example of an imaging signal processing circuit is shown. 1 and 2 show a first embodiment, and FIGS. 3 to 5 show a second embodiment.

(First Embodiment) FIG. 1 is a circuit diagram showing a first embodiment. In FIG. 1, the charge coupled device (CC
D) The signal charges photoelectrically converted in 1a are output from the first and second charge integration output circuits 15 and 16 as phase signals different from each other by 180 degrees. The output signal Vout1 output from the first charge integration output circuit 15 of the two charge integration output circuits of the CCD 1a is supplied to the clamp circuit 31 composed of the capacitor C1 and the switch S1. Similarly, the output signal Vout2 output from the second charge integration output circuit 16 is supplied to the clamp circuit 32 including the capacitor C2 and the switch S2.

The output signal Vout1 clamped by the clamp circuit 31 is then supplied to the base of the first transistor 33 of the selection circuit for selectively extracting the signal component corresponding to the signal charge in the output signal. . Similarly, the output signal Vout2 clamped by the clamp circuit 32 is supplied to the base of the second transistor 34 of the selection circuit. The transistors 33 and 34 of the selection circuit are an emitter follower circuit in which the collector and the emitter are commonly connected, and the emitter thereof is connected to the load resistor 35.

The selection circuit composed of the transistor 33 and the transistor 34 clips and erases the signal components corresponding to the reset pulse in the positive direction of the output of the clamp circuit 31 and the output of the clamp circuit 32, and erases the signal charge in the negative direction. The signal components corresponding to are alternately taken out pixel by pixel and combined into a continuous signal to obtain an output signal from which noise is removed from the output terminal 36.

Next, FIG. 2 is a waveform diagram for explaining the operation of this embodiment. The operation of this embodiment will be described below with reference to FIG.
This will be described with reference to FIG.

Referring to FIG. 10 described in the section of the prior art, the output signal is reset to the reference potential V0 every time the reset pulse φn having the same period as the transfer clock pulse is applied to the gate of the reset transistor 41 of the charge integrator circuit. To be done. At this time, the reset reference potential V is reset due to the influence of noise generated by the reset transistor 41.
0 fluctuates and becomes reset noise Vn. For example, as shown in FIG. 11, during the period from time t0 to t1, the reset pulse φ
When R is applied, it is reset to the reference potential V0, and when a reset pulse φR one cycle later is applied, the reference charge V0 is reset to a potential which is changed by Vn due to the influence of noise.

Next, at time t2, the signal charge is transferred and flows into the detection diode 8, and the potential thereof is lowered to obtain the output voltage Vs. As shown in FIG. 11, the output from time t2 is the reference. The voltage drop from the potential V0 is output Vs
However, in the next one cycle, the output Vs is the voltage drop from the potential that is changed by Vn due to the influence of the reset noise Vn. In addition to the reset noise Vn, noise generated by the buffer circuit 42 is further superimposed on the output voltage. Vb shown in the output Vout of FIG. 11 indicates the noise generated by the buffer circuit 42.

In FIG. 1, the first clamp circuit 31 has an output signal Vou obtained from the first charge integration output circuit 15.
The reference potential V0 at t1 is clamped to the clamp potential V1 by the clamp pulse 1 at the time ta shown in FIGS. Similarly, the second clamp circuit 32 sets the reference potential V0 of the output signal Vout2 obtained from the second charge integration output circuit 16 in which the signal is output in a phase opposite to that of the first charge integration output circuit 15, as shown in FIG. ), At time tb shown in (d), the clamp pulse 2 clamps the clamp potential V1. Due to this clamp operation, the potential that has changed from the reference potential V0 by Vn due to the influence of the reset noise Vn is fixed to the constant clamp potential V1, and the reset noise is removed.

Next, the output signal Vout1 from which the reset noise is removed is supplied to the base of the first transistor 33 of the selection circuit. Similarly, the output signal Vout2 is supplied to the base of the second transistor 34 of the selection circuit.

The selection circuit consisting of the transistor 33 and the transistor 34 constitutes a white clipping circuit with the emitters connected in common, and operates so as to clip the signal on the positive polarity side. At this time, the transistor 33 operates so as to determine the clipping potential of the other transistor 34, and similarly, the transistor 33 operates so as to determine the clipping potential of the other transistor 34. Therefore, the signal component a corresponding to the signal charge of the first output signal Vout1 shown in FIG.
, 1, a2, a3, ... Clip the signal corresponding to the reset pulse, which does not correspond to the signal charge of the second output signal Vout2 shown in FIG. 2C, and similarly, FIG. )
The signal components c1, c2, c3, ... Corresponding to the signal charge of the second output signal Vout2 shown in FIG. 2 do not correspond to the signal charge of the first output signal Vout1 shown in FIG. Clips the signal corresponding to the reset pulse.

The signal clipped by the signal corresponding to the reset pulse is then connected to the commonly connected transistor 33.
Are mixed and output by the emitter of the transistor 34. As shown in FIG. 2 (e), the mixed signal has a signal component corresponding to the signal charge alternately a for each pixel.
They are added in the order of 1 → c1 → a2 → c2 → a3 ... And restored to a continuous video signal.

As described above, the two clamp circuits 31,
Reference numerals 32 respectively clamp the reference potential of the output signal to the reset potential, so that reset noise is removed. Further, the noise generated by the buffer circuit in the output signal is output to the output terminal 25 of the selection circuit without sampling the noise as in the conventional sampling circuit. However, this noise has a frequency domain higher than that of the video signal. Since it is high, it is removed by a normal low pass filter for band limitation. As a result, a video signal with an improved signal-to-noise ratio can be obtained from the selection circuit.

As described above, the noise removal circuit for the charge-coupled device of the present invention is configured by the white clip circuit in which the emitters are connected in common after the reference potential in the output signal is clamped to remove the reset noise. By taking out the output signal component corresponding to the signal charge in the selection circuit, the conventional sampling circuit is not required, and it is possible to avoid sampling the noise generated by the buffer circuit. Therefore, the output signal with a good signal-to-noise ratio can be obtained. There is an effect that can be obtained.

(Second Embodiment) FIG. 3 is a block diagram showing the configuration of the second embodiment of the present invention. The present embodiment is a gate type noise eliminator, which is a signal processing circuit when the horizontal pixel addition mode is applied, and is characterized in that switch circuits are arranged at two inputs of the noise eliminator. First, the operation in the normal operation mode will be described.

The operation in the normal operation mode is almost the same as that of the conventional example. The signal charges photoelectrically converted by the photodiode 10 are read out to the vertical shift register 11 and transferred to the horizontal shift registers 13 and 14 line by line. In the normal operation mode, the signal charges transferred from the vertical shift register 11 are distributed to the horizontal shift registers 13 and 14 of the first channel and the second channel arranged above and below every other pixel. Then, the signal charges are transferred on the horizontal shift registers 13 and 14, respectively,
It is output from the charge integration output circuits 15 and 16. And
The output signals of the charge integration output circuits 15 and 16 of the two channels are respectively branched and connected to both the first switch circuit 17 and the second switch circuit 18. The output signals from the charge integration output circuits 15 and 16 of this embodiment are in-phase signals, unlike the first embodiment.

The output signal of the first switch circuit 17 is input to the clamp circuit 22 via the buffer circuit 18,
The output signal of the second switch circuit 18 is input to the delay line 20 and delayed by 1/2 pixel cycle, and the output thereof is input to the amplifier circuit 21 and the signal level attenuated by the delay line 20 is input to the first channel. The signal is amplified to the signal level (output signal of the buffer circuit 19) and further input to the clamp circuit 23.

Through the above operation, the two-channel clamp circuits 22 and 23 are supplied with the two-channel CCD output signals having the same signal level with a phase difference of 180 °. Further, the clamp pulse generated by the pulse generator 26 is applied during the feed-through period of each CCD output signal to clamp the potential during the feed-through period of each signal to a constant level VDC. And the clamp circuit 2
The output signals A and B of 2 and 23 are input to the gate circuit 24, only the effective signal components of the CCD output signals A and B are extracted, and the output signals C are output to the subsequent process circuit via the buffer circuit 25. Is output.

On the other hand, in the horizontal pixel addition mode, similarly to the conventional example, the transfer electrodes ΦT arranged with the two horizontal shift registers 13 and 14 interposed therebetween are set to the off state. The signal charges transferred from the vertical shift register 11 are transferred only to the horizontal shift register 13 of the first channel, and the signal charges of adjacent pixels are added in the subsequent horizontal transfer process. As described above, in this mode, the signal charges of pixels that are horizontally adjacent to each other are added. The signal A ′ having the added signal level and increased in level is output only from the charge integration output circuit 15 of the first channel. Further, the charge integration output circuit 16 of the second channel outputs an output signal B ′ having a signal level of zero. In this mode, the first and second switch circuits 17 and 18 have two input terminals of the signal processing circuit to which the output signal of the charge integration output circuit 15 of the first channel follows, that is, the buffer circuit 19 and the delay line. It is input to 20. As a result, the gate circuit 2
Only the effective signal components of the signals A ′ and B ′ are extracted from 4 and output as the output signal C ′, and further output to the process circuit via the buffer circuit 25.

Next, the operation of the signal processing circuit in the normal operation mode and the horizontal pixel addition mode will be described with reference to the time charts of FIGS. In the normal operation mode, the signal charge photoelectrically converted by the photodiode 10 and transferred to the vertical shift register 11 and the horizontal shift registers 13 and 14 is the charge integration output circuit 1 of each channel.
It is output from 5 and 16.

In this mode, similarly to the conventional example, the voltage of the CCD output signal of the first channel is clamped to the constant potential VDC by the clamp circuit 22 during the feed-through period and output as the signal A. On the other hand, the CCD output signal of the second channel, which has the same phase as the output signal of the first channel, is delayed by ½ pixel cycle by the delay line 20, and the phase of interpolating the signal of the first channel, that is, the phase shifted by 180 °. Is set to. The delayed signal is then sent to the amplifier 2
The signal is amplified by 1 and is further clamped by the clamp circuit 23 so that the voltage in the feed-through period becomes the constant potential VDC and output as the signal B. The gate circuit 24 that mixes the signals A and B is configured as a clip circuit, and the two input signals are out of phase with each other by 180 °. Therefore, from the output of the gate circuit 24, the feedthrough level VDC or less is obtained. Only the signal level of the potential is output. That is, like the output signal C, A1, B1, A2, B2,
A3, B3, A4, B4, ... And the effective signal components of the two channels are alternately mixed and output. By the above operation, the CCD output signals of the two channels can be converted into continuous signals without performing sample and hold.

Next, the operation of the present invention when the above-mentioned noise elimination circuit is adapted to the horizontal pixel addition mode will be described. In the horizontal pixel addition mode, signal charges (A1 and B1, A2 and B2, A3 and B) of pixels that are adjacent in the horizontal direction are generated.
3, A4 and B4, ...) Are added, the signal level is increased, and the signal A ′ (effective signal voltages A1 + B1, A2 + B2, A) is added.
3 + B3, A4 + B4, ...) Is output from the charge integration output circuit 15 of the first channel. In the present invention, the output signal of the charge integration output circuit 15 of the first channel is branched into two systems by switching the two switch circuits 17 and 18, and at the same time, the buffer circuit 19 and the delay line 20.
Is input to Therefore, the output signal input to the delay line 20 is delayed by 1/2 pixel period, and is amplified by the amplifier circuit 21 so as to be equal to the signal level input to the buffer circuit 19 of the first channel.

Then, the CCD output signals branched into the two systems are clamped by the clamp circuits 22 and 23 to the constant potential VDC in the feed-through period in one pixel cycle, and the gate circuit 24 outputs the signals A'and B '.
Is input to Here, the signal A ′ and the signal B ′ are in a relationship of being 180 ° out of phase with each other. From the output of the gate circuit 24, among the input signals A ′ and B ′, effective signal voltages A1 + B1, A2 + B2, A3 + B3, A4 + B4, ...
Are read alternately. In other words, A1 like signal C '
+ B1, A2 + B2, A3 + B3, A4 + B4, ... Are output in this order. After that, the sampled signal is
The low-pass filter removes signal components outside the band.

In this method, since the signal component is continuously output, even if the signal is smoothed by the low pass filter, the signal level is not halved unlike the conventional example. Therefore, according to the present method in which the gate type noise removal circuit is applied to the horizontal pixel addition mode, the noise is reduced by suppressing the aliasing of the high frequency noise component outside the band, and the sensitivity is increased by the horizontal pixel addition. It becomes possible to do.

According to the present embodiment, a gate circuit is used for C
Since the effective signal component of the CD is sampled, aliasing of high frequency noise that occurs during sample hold does not occur, and an effective noise elevation control effect is obtained. Further, even if the noise removal circuit is applied to the horizontal pixel addition mode, the signal level does not deteriorate due to the smoothing by the LPF, and high sensitivity can be realized. Therefore, a high-quality image with high sensitivity and low noise can be obtained even under low illuminance.

Although the above-described embodiment is a preferred embodiment of the present invention, the present invention is not limited to this, and various modifications can be made without departing from the gist of the present invention.

[0062]

As is apparent from the above description, in the CCD image pickup signal processing circuit of the present invention, the charge coupled device outputs a signal corresponding to the reference potential and the signal charge for each cycle of the transfer clock pulse. The output signal corresponding to the first reference potential is fixed to a preset first predetermined potential, and the output signal corresponding to the second reference potential is fixed to a preset second predetermined potential. One of the two signals corresponding to the signal charges after the clamping, which has the larger amplitude, is selected and output. Therefore, the reference potential is clamped to the reset potential and the reset noise is removed.

In addition, the CCD image pickup signal processing circuit of the present invention buffer-amplifies one signal of the first and second channels of the charge coupled device, delays and amplifies the other signal and delays each signal. Clamp and the two clamped signals are mixed. Therefore, the phase of the delay is 180
By setting it to °, 2
Only the effective signal components of the two signals can be extracted.
It is possible to effectively remove the noise component of the charge coupled device without lowering the sensitivity.

[Brief description of drawings]

FIG. 1 is a circuit configuration block diagram showing a first embodiment of a CCD image pickup signal processing circuit with improved noise elimination characteristics according to the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the CCD image pickup signal processing circuit in FIG.

FIG. 3 is a circuit configuration block diagram showing a second embodiment of a CCD image pickup signal processing circuit with improved noise elimination characteristics according to the present invention.

4 is a timing chart in a normal operation mode of the CCD image pickup signal processing circuit of FIG.

5 is a timing chart in the horizontal pixel addition mode of the CCD image pickup signal processing circuit of FIG.

FIG. 6 is a block diagram showing a circuit configuration example of a charge integration output circuit.

7 is a waveform diagram for explaining the operation of the charge integration output circuit shown in FIG.

FIG. 8 is a block diagram showing a configuration example of a conventional CCD image pickup signal processing circuit.

FIG. 9 is a timing chart in a normal operation mode of a conventional CCD image pickup signal processing circuit.

FIG. 10 is a timing chart in a horizontal pixel addition mode of a conventional CCD image pickup signal processing circuit.

FIG. 11 is a waveform diagram in the CCD image pickup signal processing circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Charge coupled device (CCD) 2 Imaging signal processing circuit 10 Photodiode, 11 Vertical shift register, 13, 14 Horizontal shift register, 15, 16 Charge integration output circuit, 17, 18 Switch circuit, 19, 20 Buffer circuit, 20 Delay Line, 21 amplifier circuit, 22, 23, 31, 32 clamp circuit, 24 gate circuit, 26 clamp pulse generator 33, 34 transistor 35 load resistor 36 output terminal 37 clamp potential V1

Claims (9)

[Claims] 1. A charge coupled device comprising first and second gate-integrated charge integration type output circuits for outputting a signal corresponding to a reference potential and a signal charge for each cycle of a transfer clock pulse, A first clamp means for fixing an output signal corresponding to the reference potential obtained from the gated charge integration type output circuit to a preset first predetermined potential; Second clamp means for fixing an output signal corresponding to the obtained reference potential to a preset second predetermined potential, and outputs from the first and second clamp means are connected,
A CCD image pickup signal processing circuit, comprising: a selection unit that outputs a signal having a larger amplitude of either of the two signals corresponding to the signal charges after being clamped. 2. The charge-coupled output circuit with a first gate and the charge-integrated output circuit with a second gate are provided in the same charge-coupled device. CCD image signal processing circuit. 3. A first charge-integrated output circuit with a gate is provided in a first charge-coupled device, and a second charge-integrated output circuit with a gate is provided in a second charge-coupled device. The CCD image pickup signal processing circuit according to claim 1. 4. The CCD image signal processing circuit according to claim 1, wherein the first predetermined potential and the second predetermined potential are the same potential. 5. The two signal charges that are horizontally adjacent to each other in a group of photodiodes arranged in a matrix are
And the horizontal shift registers of the second channel read in parallel, and the transistor electrodes arranged between the two horizontal shift registers are arranged to sandwich the signal charge from the horizontal shift register of the first channel to the horizontal shift register of the second channel. A CCD image pickup signal processing circuit for processing the signal of a charge coupled device having a charge integration output circuit for inputting a signal based on the signal charge from the horizontal shift registers of the first and second channels, First and second switch means connected to the outputs of the charge integration output circuits of the first and second channels to select and output the signals of these two channels; and buffer means connected to the first switch means. A delay line connected to the second switch means and an amplifying means, the buffer means and the amplifying means. First and second clamp means connected to respective outputs of the width means, and connected to outputs of the first and second clamp means, and
A CCD image pickup signal processing circuit comprising: gate means for mixing two output signals; and pulse generation means for generating a clamp pulse for controlling the timing of the clamp operation of the clamp means. 6. In a normal read operation of the CCD image pickup signal processing circuit, in the first and second switch means, the output signals of the charge integration output circuits corresponding to the respective channels are connected to the subsequent stage, and also in the horizontal direction. In the operation of adding and reading the signal charges of the photodiodes adjacent to, the output of the charge integration output circuit of the second channel is connected in the first switch means, and the first channel is connected in the second switch means. 6. The CCD image pickup signal processing circuit according to claim 5, wherein the output of the charge integration output circuit is connected. 7. The CCD image pickup signal processing circuit according to claim 5, wherein the delay time of the delay line is set to a 1/2 pixel cycle of the output of the charge integration output circuit. 8. A clamp pulse generated by said pulse generating means and having a phase difference of 180 ° from each other is applied to said clamp means, and an output signal of said buffer means and said amplifying means is used as an input signal, and a feedthrough level of the signal. 6. The CCD image pickup signal processing circuit according to claim 5, wherein is clamped so as to have a constant potential. 9. The CCD according to claim 5, wherein in the gate means, only the effective signal level is extracted from the output signals of the first and second clamp circuits.
Imaging signal processing circuit.