JPH03145285A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To suppress waveform deterioration by reading channels signals from plural horizontal transfer registers in phase when the signals are outputted, adjusting the phase of the outputs and adding them in phase so as to obtain one time serial signal output. CONSTITUTION:The device is provided with charge coupling elements H-1, H-2 formed by reading outputs of horizontal transfer registers in phase, a delay means 11 adjusting the relation of phase between outputs of the horizontal transfer registers, and an adder means 20 adding each output of the horizontal transfer register after the adjustment of the relation of phase by the delay means 11 to form one time series signal. Thus, plural channel signals outputted from CCD terminals of the charge coupling elements H-1, H-2 are subject to phase adjustment between plural channels through the delay means 11 and the adder means 20 forms the plural outputs after phase adjustment into one time series signal output. Thus, the waveform deterioration due to the interference between channels.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to improvement of a solid-state imaging device, and more specifically, to photoelectrically convert an image and at the same time accumulate it as a signal charge,
The accumulated charge is transferred to a charge coupled device (Charge Couple).
The present invention relates to a CCD type solid-state imaging device that transfers image signals using CCD devices (hereinafter abbreviated as rCCDJ) and extracts image signals.

(Prior Art) A conventional CCD type solid-state imaging device 30 of this type was constructed as shown in FIG. 21. That is, the element section A-1 of the drive circuit connects a plurality of vertical transfer registers v-1, . 1 and H-2, and a plurality of photodiodes PDII, PD12 . PDI-;・・
ko,...;PD,,,PD,2. . . , PD, , are connected to each other in a matrix (Matrlx) arrangement so that they can be photoelectrically converted into a plurality of pixels corresponding to an image (not shown), and the photoelectrically converted signals are simultaneously A signal pulse φHG having the waveform shown in FIG. 24 is sent to the horizontal separation gate HG to transfer the charge to the horizontal transfer register H.
The configuration was such that every other pixel was alternately distributed to -1 and H-2.

Further, horizontal transfer registers H-1 and H-2 have transfer electrodes H1, H2, . . . sequentially from the right side to the left side in the figure.
is provided, and horizontal transfer registers H-1 and H- are provided on the output side.
On the left side of the final electrode H2o, a terminal electrode H1o is arranged at the end of the horizontal transfer register H-2, and the signal charge transferred by the horizontal transfer register H-2 is delayed by one pixel. It is configured to allow

Further, a reset section A-2 of the drive circuit A is provided on the left side of the final electrode H2o and the terminal electrode H1o (see FIG. ), an adder circuit 20a (see FIG. 21) is provided on the output side of the reset section A-2, which adds the outputs outl and 2 of the horizontal transfer registers H-1 and H-2, and adds the outputs of the horizontal transfer registers H-1 and H-2. It was configured to output as a series signal output.

When reading a predetermined image using the solid-state imaging device 30 configured as described above, before the horizontal transfer registers H-1 and H-2 start the signal image, the image is first distributed on H-2 and below the transfer electrode H1. Then, as shown in FIG. 24, the signal charges are transferred to the output side (to the left) alternately using pulses φH1 and φH2 that are 180 degrees out of phase.

In this way, the signal charge is transferred to the final electrode H2o. Horizontal transfer pulse φH2(
(See FIG. 24) In addition to this, deterioration of the output waveform is suppressed by performing rectangular wave driving.

Final electrodes H2o and Hl. The signal charge transferred downward is
It passes through the reset section A-2 of the drive circuit 10 provided on the left side of the final electrode H2, , and the terminal electrode H1o, and becomes the output outl.

Further, the signal charges transferred by the horizontal transfer register H-2 also arrive at the final electrode H2o at the same time. However, the signal charges transferred by horizontal transfer register H-2 must be output with a delay of one pixel compared to the signal charges transferred by H-1, The terminal electrode H1o performs the delay.

By driving the terminal electrode Hlo with a rectangular wave similarly to the final electrode H2o, it is possible to suppress the waveform deterioration of the output out2 of H, -2, as shown in FIG.

After passing through the terminal electrode H1o, it takes exactly the same route as the output 0utl.

In this way, the two outputs (outl, out2) obtained from the horizontal transfer registers H-1 and H-2 are input to the adder circuit 20a, as shown in FIG. A resolution corresponding to the number of pixels can be obtained.

FIG. 24 shows an example of adding ou with pulse SPI.
This is an example in which the tl signal is gated, the out2 signal is gated with the pulse SP2, and the two signal outputs are added.

Conventionally, the above-mentioned CCD type solid-state imaging device 30 was driven as described above, but in such driving, the CCD type solid-state imaging device 30 is
In order to have a phase difference of one pixel (that is, 180 degrees) between two output signals when outputting a CD, as shown in the timing chart shown in FIG. It is necessary to perform the reset operation of the output obtained from H-2 and H-2 using two types of pulses whose phases differ by 180 degrees. Regarding the phase relationship between the reset pulse and the output waveform, the reset pulse φRS2 of out2 is applied during the output period of outl, and the reset pulse φR3I of outl is applied during the output period of out2.

The general configuration of the reset section A-2 is as shown in FIG. 22, and the signal charges transferred by the horizontal transfer registers H-1 and H-2 pass through the final electrode H2° and the final electrode H1°, It is output as a voltage signal via the sense capacitors C, , C2 (outl, out2). At this time, after detecting the output for each pixel, MOSFETQ+, Q2
A reset pulse φRS with the waveform shown in FIG. 24 is applied to the gate of
I.

Add φRS2 and M OS F E T Q r ,
Q2 is turned on, and the signal charges accumulated in the sense capacitors C, C2 are discharged to the reset drain RD to perform a reset operation.

(Problem to be solved by the invention) However, the two output paths outl mentioned above.

out2 is provided on the same chip, so it is difficult to completely eliminate interference between channels, and interference between channels due to the phases of mutual reset pulses can significantly degrade each output waveform. There was a problem.

Further, in a CCDC solid-state imaging device having a structure having two horizontal transfer registers, the number of pixels in the horizontal direction is large, and the drive frequency for horizontal transfer is often high. For this reason, as the number of pixels is increased with the aim of achieving higher resolution, there has been an inconvenient problem in that the deterioration of the output waveform due to interference between channels becomes more significant. Such waveform deterioration is caused by the CCD in a CCD having at least two horizontal transfer registers.
In order to output the output signals of two channels shifted by one pixel at the time of output from D, two types of reset pulses having a phase difference of 180 degrees are required. On the other hand, considering that the phenomenon of output waveform deterioration due to inter-channel interference caused by two types of reset pulses is an essential problem that cannot be avoided, two channel signals are read out in the same phase at the time they are output from the CCD. This aims to provide a solid-state imaging device that can suppress deterioration of the output waveform due to interference between two channels and read out high-quality images.

[Structure of the invention]

(Means for Solving the Problems) One of the basic configurations of the solid-state imaging device of the present invention for achieving the above-mentioned problems (claim (1)) is as shown in FIG. A plurality of vertical transfer registers V-1,..., V-n and horizontal transfer registers H-1,..., H-2 arranged in parallel to each other, and a plurality of vertical transfer registers V -1, . Transfer registers H-1, H-2 are horizontal transfer registers H-1. charge-coupled devices H-1 and H-2 formed so that outputs between H-2 can be read in the same phase;
A delay means 11 for adjusting the phase relationship between the outputs of each horizontal transfer register; and a time-series signal by adding the outputs of each horizontal transfer register after the phase relationship has been adjusted by the delay means 11. This is characterized in that an adding means 20 is provided.

The element section A-1 of the drive circuit 10 of the solid-state imaging device shown in FIG.
, V-2, ..., Vn; and horizontal transfer register H-1
, H-2, horizontal transfer registers H-1 and H-2 are:
As shown in FIG. 2, horizontal transfer register H-1. In order to make it possible to read the output between H-2 in the same phase, the number of stages is the same, and the final electrode H0 is provided at the output side end. In addition, vertical transfer registers V-1, V-2, ... V
The signal charges transferred through -n are distributed pixel by pixel to horizontal transfer registers H-1 and H-2 by a horizontal separation gate HG.

A reset section A-2 shown in FIG. 3 is provided on the output side of the horizontal transfer registers H-1 and H-2, and is configured to be reset or output by the output amplifiers FDAI, FDA2 and reset R8. ing.

Another basic configuration of the solid-state imaging device according to the present invention (claim (2)) is that, as shown in FIG. register, and each of the plurality of vertical transfer registers is provided with a plurality of photoelectric conversion elements for photoelectrically converting a received image and transmitting a signal charge to the vertical transfer register, The horizontal transfer register includes charge-coupled devices H-1 and H-2a configured to maintain and delay the phase relationship of the output signal of each horizontal transfer register, and a delay operation stop bias setting means 10a for the horizontal transfer register. A driving means for reading the force of each horizontal transfer register in the same phase, a delay means 11 for adjusting the phase relationship between the outputs of each horizontal transfer register, and each horizontal transfer after the phase relationship is adjusted by the delay means 11. Add the outputs of the registers and
The present invention is characterized in that an adding means 20 is provided for converting the signals into one time-series signal.

However, the element section A-2 and the reset section A-2 of the drive circuit 10 of the solid-state imaging device according to claim (2) are shown in FIGS.
The same configuration as shown in Figure 3 is used.

(Function) As described above, the solid-state imaging device 30-I of claim (1)
Then, the multiple channel signals outputted from the CCD end of the horizontal transfer register in the same phase are output from the CCD end, and then one signal output is passed through the delay means 11 to adjust the phase between the multiple channels. Since the plurality of outputs are converted into a single time-series signal output by the adding means 20, waveform deterioration due to interference between channels is greatly suppressed.

Further, the solid-state imaging device 30■ according to claim (2) uses a CCD of a conventional structure, and uses a bias setting means to control the CCD.
The outputs from the horizontal transfer registers can be read out in the same phase by stopping the delay operation provided therein and driving the CCD by the in-phase driving means. Then, similarly to the solid-state imaging device 30-■ of claim (1), one output signal is passed through the delay means 11 to adjust the phase between the plurality of channel signals, and each output is added to the addition means 20.
Since it is converted into a single time-series signal through the channels, waveform deterioration due to interference between channels is greatly suppressed.

(Example) Next, an example of the solid-state imaging device according to the present invention will be described based on the drawings.

Embodiment 1: FIGS. 5 and 13 are block diagrams showing a schematic configuration of a first embodiment of a solid-state imaging device 30-1 according to claim (1) of the present invention, and diagrams of drive pulse waveforms of the drive circuit 10. It is a timing chart figure.

In FIG. 5, H-1 and H-2 are CCDs formed so that outputs between horizontal transfer registers can be read out in the same phase.
a is an analog delay line (hereinafter abbreviated as rDLYJ) that adjusts the phase by passing one of the two CCD outputs output in the same phase from the transfer registers H-1 and H-2; 11b;
is a gate circuit.

Then, when a pulse φHG having the waveform shown in FIG. 13 is applied to the horizontal separation gate HG to turn it into an "on" state, the signal charges transferred by the vertical transfer registers V-1, ... V-n are transferred to the horizontal transfer register H. -1°H-2, and further distributed to horizontal transfer register H-1. A horizontal transfer pulse φH having a waveform shown in FIG. 13 is applied to transfer electrodes H1 and H2 on H-2.
When 1 and φH2 are added, the signal charges under the transfer electrodes H1 and H2 are transferred to the final electrode H8.

When driving at this timing, before starting horizontal transfer, the signal charges distributed to horizontal transfer registers H-1 and H-2 are aligned on the same column, and then horizontal transfer is performed. 1 and H-2 have the same number of stages of transfer electrodes up to the final electrode, and are output in the same phase.

Furthermore, the outputs of the horizontal transfer registers H-1 and H-2 are sent to the reset section A-2 (the schematic configuration of the reset section A2 is shown in FIG. 3) of the solid-state imaging device 30a of this embodiment via the final electrode H8. When a reset pulse φRS as shown in FIG. 13 is applied to the gate by the output amplifiers FDAI, FDA2 and reset R3 (see FIG. 3), the MO
SFEF is in the “on” state and the reset capacity Jt c
1°The signal charge stored in C2 is reset drain RD
and a reset operation is performed.

In the drive of this embodiment, unlike the conventional example, the phase of the other reset pulse does not exist in the signal period of each channel, so waveform deterioration due to interference between channels due to the reset pulse is significantly improved compared to the conventional example. be done. Below, CCD output 0UTI, 0 outputted in the same phase
Of UT2, OUT performs phase adjustment by passing through DLYlla, and then converts each signal period to SPI.
.

By adding the two signals using a gate pulse SF3, it is possible to obtain an angle q image degree corresponding to the number of horizontal pixels. With this method, waveform deterioration during the signal period can be significantly suppressed, so high-quality images can be obtained.

Embodiment 2: FIG. 6 and FIG. 15 respectively represent claims (1) of this invention.
FIG. 2 is a block diagram showing a schematic configuration of a second embodiment of the solid-state imaging device 30-(2) and a timing chart of a drive pulse waveform for driving the drive circuit 10. H-1 and H-2 in FIG. 6 are CCDs for transfer registers, and H-1 and H-2 are CCDs for transfer registers.
It is a horizontal transfer register that can read the outputs of H-1 and H-2 in the same phase, and llc is the horizontal transfer register H-1.
11d is a circuit (hereinafter abbreviated as rS/HJ) which clamps (hereinafter abbreviated as rCLPJ) the two CCD outputs which are outputted with the same phase as H-2, and performs sample and hold processing (hereinafter abbreviated as rS/HJ).

As the element structure A-1 and the structure of the reset section A-2 of the CCD used in this embodiment, those shown in FIGS. 2 and 3 described above are used.

Further, in this embodiment, clamp and sample hold processing is performed after the CCD output, and the CCD output waveform is shown in FIG. 25 to explain this. In Figure 25, T,
is a reset period, T2 is a feedthrough period, and T is a signal period.

In this example, two
Channel signal with common clamp pulse P CLP
The feedthrough period of the CD output is clamped to suppress the 1/f noise contained in the CCD output, and then the signal period is sampled and held using pulse PS/H. This makes it possible to suppress reset noise that occurs during the feedthrough period and the signal period.

These clamps and sample holds are performed in the same phase for the two channels, and subsequent delays and additions are the same as those shown in the first embodiment.

Further, drive pulses are applied according to the timing chart shown in FIG.

The method shown in this embodiment of clamping the feed-through period and sampling and holding the signal period to suppress noise has been used in the past, but in the conventional case, the phase of the reset pulse is shifted by 180 degrees between channels. Due to waveform deterioration at the time of CCD output due to this, the feed-through period to be clamped and the signal period to be sampled and held are not clear. Also, the phase of the clamp pulse and sample hold pulse is 1 between the two channels.
80" and the waveform deterioration caused by this cannot be ignored. For this reason, there was a problem that the noise suppression effect was not clear.

According to this embodiment, the waveform deterioration at the CCD output terminal is suppressed by reading the CCD output in the same phase for two channels, and the clamp pulse and sample hold pulse used in the subsequent noise suppression processing are shared, so that the two channels can be read out in the same phase. By minimizing the mutual interference between
High quality images can be obtained.

Embodiment 3: FIG. 7 shows a solid-state imaging device 30 according to claim (1) of the present invention.
FIG. 16 is a block diagram showing a schematic configuration of the third embodiment of Embodiment 1, and FIG. 16 shows a time chart of drive waveforms. In this embodiment as well, horizontal transfer registers H-1 and H2 are used as CCDs with the same phase readout structure, and when these three horizontal transfer registers output the CCD, the two channels are output in the same phase. However, the difference from Embodiments 1 and 2 is that, as is clear from the timing chart of FIG. 16, the reset pulses φR8 and φH2° are common, and the duty of the reset period of the output signal is 50%
This is what we are doing.

In Examples 1 and 2, the pulse width of φR3 was made narrower than the pulse width of φH2, so that a feed-through period always existed between the reset period and the signal period, but the number of pixels of CC and D increased. As the drive frequency increases, it becomes difficult to reset with a narrow pulse and secure a feedthrough period before the signal period. Furthermore, even if a reset operation is to be performed, it becomes difficult to perform the reset operation reliably in a short period of time.

For this reason, first of all, in order to perform the reset operation reliably, the duty of the reset pulse is set to 50%, and by clamping the widened reset part, the visually noticeable 1/f noise is suppressed and the image quality is improved. The purpose of this embodiment is to achieve this.

The means of delay and addition after 1/f noise suppression are the same as in the previous embodiment, but the process of adding the two-channel signals after delaying 0UT2 in the delay line requires a higher driving frequency and , SF3 makes it difficult to perform gate addition, it is possible to obtain a resolution corresponding to the number of pixels by simple resistance addition.

In this embodiment as well, it is possible to obtain a high quality image in which visually noticeable 1/f noise is suppressed.

Although the above effects have been described for the case where there are two horizontal transfer registers, they can also be applied to the case where there are two or more horizontal transfer registers.

Embodiment 4: FIGS. 8 and 14 are block diagrams showing a schematic configuration of a fourth embodiment of the solid-state imaging device 30-■ of claim (1) of the present invention, and timing charts of drive pulse waveforms. It is.

In this embodiment, as in the first embodiment, a CCD having the same phase readout structure is driven, and at the time of output from the CCD, both channels are output in the same phase. In this example, 0 after CCD output
The delay operation of UT2 and the addition operation with 0UT1 are performed by a sample hold circuit and a gate circuit. Sample and hold is performed with the CCD output in the same phase and at the same time with a pulse called PS/H. The results are waveforms 0UTIS/H and 0UT2S/H shown in FIG.

In this state, S gates the first half of the sample hold period.
A signal output is obtained by gating and adding the 0UTIS/H signal at PI and 0UT2S/H at SF3, which gates the second half of the hold period. In this method, waveform deterioration caused by mutual interference between channels, which is seen in the conventional example, is greatly improved, so a high-quality image can be obtained.

Example 5: Claim (2) of this invention is shown in FIG. 9 and FIG. 17, respectively.
A block diagram showing a schematic configuration of a first embodiment of the solid-state imaging device 3O-II and a timing chart of drive pulse waveforms are shown. However, the element structure A-1 and reset section A-2 of the drive circuit of the solid-state imaging device of this example were the same as those shown in FIGS. 22 and 23 described above.

In the figure, v-1,...V-n are vertical transfer registers, PD is a photodiode, FDAI, FDA2 are output amplifiers,
H-1 and H-2 are horizontal transfer registers, and DLY is an analog delay line. In the embodiment, a CCD having two horizontal transfer registers as in the conventional example will be described.

Here, horizontal transfer pulses (φH1, φH2) applied to G1 transfer electrodes H1, H2 in the horizontal separation gate, horizontal register H
The pulse φH2o applied to the -1 final electrode H2o has exactly the same timing as in the conventional example. When driven at this timing, the transfer register H-
Since the signal charges distributed to 1 and H-2 are aligned on the same column and then horizontally transferred, the transfer is performed in the same phase up to H2o, which is the same as in the conventional example, but in the conventional example, the final Since the pulses φH1o and φH2o applied to the electrodes H1, H2o are pulses with reversed phases, the signal charge of H-2 is delayed by one pixel, the phase of the reset pulse is also reversed, and the phase of the output is also reversed. It turns out. In this embodiment, by applying a fixed bias voltage of V to the final electrode H1o of H-2, a potential well is always formed under the final electrode H1. In this state, when the final electrode H2o changes from Hi level to Lo level, the signal charges transferred from transfer electrode H2,
It passes directly under the electrode without any delay. Therefore, the signal charges transferred by the transfer registers H-1 and H-2 are transferred in the same phase up to the reset portion.

Therefore, the signal charges of two channels can be reset at the same time, so that a common reset pulse can be used. As a result, the two-channel signals are output in the same phase at the CCD output end.

In the conventional example, the two-channel signals are already output at the CCD output end with a 180° shift from each other, so if the two signals are then simply added, a resolution equivalent to the number of horizontal pixels can be obtained. Since the phase of the reset pulse of the other channel exists in the signal period of each output signal, deterioration of the waveform of the signal period cannot be avoided due to mutual interference. Since this deterioration already occurs in the output of the CCD, it cannot be improved by subsequent signal processing, etc., and becomes the main cause of image quality deterioration.

In this example, the phase is the same at the CCD output end, but by making the reset pulse common, the phase of the reset pulse does not exist in the signal period of the output signal, so waveform deterioration due to mutual interference is greatly improved. Ru. After outputting from the CCD, the signal of 0UT2 is passed through a delay line corresponding to one pixel in order to restore the original phase relationship, and then the signal period of each output signal is gated alternately by gate pulses SPI and SF3. By adding them, it is possible to obtain a resolution corresponding to the original number of horizontal pixels. With this method, it is possible to suppress waveform deterioration during the signal period, so it is possible to obtain high-quality images.

The solid-state imaging devices listed in Examples 5 to 8 are all examples of the solid-state imaging device 3O-II of claim (2), and include the element section A-2 and the reset section A of the drive circuit.
-2 element structure is the same as the conventional one (Fig. 22 and 2).
Figure 3).

Embodiment 6: FIG. 10 and FIG. 18 respectively show the claims (
2) is a block diagram showing a schematic configuration of a second embodiment of the solid-state imaging device 30-n and a timing chart of drive pulse waveforms; FIG.

In this embodiment, two CCDs are driven, which is the same as in the first embodiment, and the CCD outputs are outputted in the same phase for both channels. Here, the subsequent delay and addition of the two channel signals are performed by a sample hold circuit and a gate circuit. Sample and hold is performed simultaneously with the pulse P57□ while the CCD outputs are output in the same phase.As a result, the 18th
The waveforms are 0UTIs/H and 0UT2S/H in the figure. In this state, SPI which gates the first half of the sample hold period is 0UTIS/H, and SF3 which gates the second half is 0UTIS/H.
If the UT2S/H is gated and added, the output signal OUT
is obtained.

In this embodiment as well, since the signals are read out in the same phase when outputting from the CCD, deterioration in the signal period is suppressed and a high quality image can be obtained.

Embodiment 7: FIG. 11 and FIG. 19 respectively represent the claims (
2) is a block diagram showing a schematic configuration of a third embodiment of the solid-state imaging device and a timing chart of drive pulse waveforms; FIG.

In addition, in order to explain each part of the CCD output waveform, the 25th
Use diagrams. In FIG. 25, T: reset period, T2: feed-through period, T3: signal period.

In this embodiment as well, the two-channel signals at the CCD output end are driven to be in the same phase, and then a common clamp pulse Pctpl: is used to clamp the feed-through period of the CCD output so that the 1-channel signal included in the CCD output is /f noise is suppressed and the signal period is pulsed P
By performing sample and hold using the S/H, it is possible to suppress reset noise that occurs during the feedthrough period and the signal period. The subsequent phase adjustment and addition method between the two channels is exactly the same as the method shown in Example 2.

Clamping the feedthrough period shown in this example,
A method of suppressing noise by sample-holding the signal period has been used in the past, but in the conventional case, due to the phase difference of the reset pulse, mutual interference with the waveforms of the two channel signals is large, resulting in waveform deterioration. Therefore, the feedthrough period and signal period are not clear, and the noise suppression effect cannot be clearly confirmed.

In this embodiment, by reading out the CCD output in two channels in the same phase, there is little waveform deterioration during the signal period.

In addition, since the phase of the clamp pulse is common to both channels and does not affect the signal period, there is little signal deterioration, and the noise suppression effect is clearer than with conventional solid-state imaging devices, making it possible to obtain high-quality images. It has been confirmed that this is possible.

Embodiment 8: FIG. 12 and FIG. 20 are the claims of this invention (
FIG. 2 is a block diagram showing a schematic configuration of a fourth embodiment of the solid-state imaging device 30-(2) and a timing chart of drive pulse waveforms.

In this embodiment, as in the previous embodiment, the two-channel signals are driven to have the same phase at the CCD output end. However, the difference from the other examples is that, as can be seen from the timing chart of FIG. 20, φR3 and φH2o are shared, so the reset period of the output signal is set to 50% duty.

In the above embodiment, the pulse width of φR8 was made narrower than the pulse width of φH2o, and there was always a feed-through period between the reset period and the signal period, but the number of pixels of the CCD increased and the driving frequency was also increased. Then, it becomes difficult to secure a feedthrough period before the signal period by resetting with a narrow pulse. Furthermore, even if a reset operation is to be performed, it becomes difficult to perform the reset operation reliably in a short period of time.

For this reason, first of all, in order to perform the reset operation reliably, the duty of the reset pulse is set to 50%, and by clamping the widened reset part, the visually noticeable 1/f noise is suppressed and the image quality is improved. is the purpose of this embodiment.

The delay and addition means after 1/f noise suppression are the same as in the previous embodiment, but the 2
In the process of adding channel signals, when the driving frequency becomes high and gate addition is difficult due to SPI and SF3, a resolution corresponding to the number of pixels can be obtained by simple resistance addition.

In this embodiment as well, it is possible to obtain a high quality image in which visually noticeable 1/f noise is suppressed.

Note that although the effects shown above have been described in the case of two horizontal transfer registers, they can also be applied to a plurality of horizontal transfer registers.

In the above embodiments, only two horizontal transfer registers are used, but the CCD may have a structure having three horizontal transfer registers.

Even in the case of using a horizontal transfer register having the above nine configurations, the signal charges transferred by the plurality of vertical transfer registers are transferred to the horizontal separation gate, as in the above-mentioned embodiment.
The signal charges may be sequentially distributed to horizontal transfer registers, and driving pulses may be applied to the transfer electrodes via the transfer electrodes on the horizontal transfer registers to sequentially move the signal charges to the output end side.

〔Effect of the invention〕

As is clear from the above description, the present invention provides a solid-state imaging device in which vertical transfer registers and horizontal transfer registers are configured with CCDs, in which outputs from transfer registers such as a plurality of horizontal transfer registers are also in the same phase at the time they are output. Since the signals are read out in the same phase and output in the same phase, phase adjustment and addition are performed to output a single time-series signal, waveform deterioration due to interference between channels is greatly suppressed, and high-quality images can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of the solid-state imaging device according to claim (1) of the present invention, and FIGS. 2 and 3 are element configuration diagrams of the drive circuit of the solid-state imaging device having the configuration shown in FIG. The configuration diagram of the reset section, FIG. 4, is claim (2) of the present invention.
5 is a block diagram showing the basic configuration of a solid-state imaging device according to claim (1), FIG. 5 is a schematic configuration block diagram of a first embodiment of the solid-state imaging device according to claim (1), and FIG. FIG. 7 is a schematic block diagram of the second embodiment of the invention.
), FIG. 8 is a schematic configuration block diagram of the fourth embodiment of the solid-state imaging device according to claim (1), and FIG. 9 is a schematic configuration block diagram of the fourth embodiment of the solid-state imaging device according to claim (2). A schematic configuration block diagram of the first embodiment of the device, FIG. 10 is claimed in claim (2).
A schematic configuration block diagram of a second embodiment of the solid-state imaging device,
FIG. 11 is a schematic configuration block diagram of a third embodiment of the solid-state imaging device according to claim (2), and FIG. 12 is a schematic configuration block diagram of a fourth embodiment of the solid-state imaging device according to claim (2). 13th
Figures 1 to 16 are the first diagrams of the solid-state imaging device according to claim (1).
．． Second. Third. Timing charts of drive pulse waveforms applied to drive the drive circuit of the fourth embodiment, FIGS. 17 to 20 are for the drive circuits of the first to fourth embodiments of the solid-state imaging device of claim (2). 21 is a schematic block diagram of a conventional CCD type solid-state imaging device, and FIG. 22 is a timing chart of driving pulse waveforms added in FIG. 21.
A schematic block diagram of the element section of the drive circuit of the D-type solid-state imaging device, FIG. 23 is a block diagram of the configuration of the reset section of the drive circuit of FIG. 22, and FIG. 24 shows the drive of the CCD-type solid-state imaging device shown in FIG. FIG. 25 is a timing chart of drive pulse waveforms applied to the circuit, and is an output waveform diagram of the CCD type solid-state imaging device shown in FIG. 21. H-1, H-2-...Horizontal transfer register (CCD) V-
1, V-2,...V-n...Vertical transfer register (C
CD) P D ++, P D 12. ...PD...
PDfill... Photodiodes Hl, H2... Transfer electrodes Hlo, H2o... Final electrode HG... Horizontal separation gate 10... Drive circuit 11... Delay means 20... Adding means 11a... DLY 11b...Gate circuit 11 c-CL P lid...Sample hold circuit 30...Conventional solid-state imaging device

Claims (2)

[Claims] (1) It is composed of a charge-coupled device and has a plurality of vertical transfer registers and horizontal transfer registers arranged in parallel to each other, and each of the plurality of vertical transfer registers photoelectrically converts the received image to charge a signal. In a solid-state imaging device comprising a plurality of photoelectric conversion elements that transfer signals to vertical transfer registers, the plurality of horizontal transfer registers are charge-coupled devices formed to be able to read outputs between the respective horizontal transfer registers in the same phase. , a delay means for adjusting the phase relationship between the outputs of each horizontal transfer register, and an addition unit that adds the outputs of each horizontal transfer register after adjusting the phase relationship by the delay means to form one time-series signal. A solid-state imaging device characterized by being provided with means. (2) It is composed of a charge-coupled device and includes a plurality of vertical transfer registers and horizontal transfer registers arranged vertically to each other, and photoelectrically converts the received image into each vertical transfer register and vertically transfers the signal charge. In a solid-state imaging device comprising a plurality of photoelectric conversion elements for transferring to registers, the plurality of horizontal transfer registers are charge-coupled devices formed so as to maintain and delay the phase relationship of the output signals of the respective horizontal transfer registers. , a delay operation stop bias setting means for the horizontal transfer register, a driving means for reading the output of each horizontal transfer register in the same phase, a delay means for adjusting the phase relationship of the output of each horizontal transfer register, and the delay. 1. A solid-state imaging device, comprising: an adding means that adds the outputs of the respective horizontal transfer registers after the phase relationship has been adjusted by the means to form one time-series signal.