JP2867680B2 - Driving method of solid-state imaging device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a solid-state imaging device, and more particularly, to a method for driving a solid-state imaging device that can support a non-interlaced scanning method.

<Summary of the Invention> The present invention relates to a solid-state imaging device capable of supporting a non-interlaced scanning method, wherein a light receiving unit provided for each of a plurality of pixels arranged two-dimensionally in a matrix in the horizontal and vertical directions includes: It has an amplifying element for amplifying signal charges accumulated in accordance with the amount of incident light, and holds each amplified output of two vertically adjacent pixels during a horizontal blanking period, and sequentially reads out the held outputs. Thus, the circuit scale can be reduced, and the solid-state imaging device can be downsized.

<Prior Art> A television screen is composed of a large number of scanning lines that sequentially scan from the upper left to the right. In a standard television system, in order to reduce screen flicker called flicker, one screen is used. Interlaced scanning in which scanning is performed every other line is performed.

In this interlaced scanning, one field (odd field) screen is formed by interlaced scanning every other line in the first 1/60 second, and in the next 1/60 second, the scanning line in the odd field is formed. The next field (even field) screen is formed by interlacing scanning every other line to fill the gap, and one composite screen (frame screen) is formed every 1/30 second on the odd and even field screens. It is to be completed.

As described above, since the standard television system is the interlaced scanning system, the solid-state imaging device used in the television camera also employs a transfer system compatible with the interlaced scanning system as a signal charge transfer system.

However, the non-interlaced scanning method is more advantageous than the interlaced scanning method in improving the vertical resolution, and has the advantage that signal processing is simplified.

As a conventional example of a solid-state imaging device that can support this non-interlaced scanning method, as shown in FIG. 7, signal charges accumulated in the photosensitive unit 70 in accordance with the amount of incident light are vertically During the ranking period, the odd lines are simultaneously transferred to the odd field vertical transfer unit 71, and the even lines are transferred to the even field vertical transfer unit 72 at the same time. Part 7
3 and alternately selected and sent to the horizontal transfer section 74. The output section 75 provided at the last end of the horizontal transfer section 74 reads out serially in one horizontal scanning period and derives it as a video signal for one frame. Is known (JP-A-64-4938)
No. 2).

<Problems to be Solved by the Invention> However, the conventional solid-state imaging device described above has a configuration in which two vertical transfer units are provided for each vertical column of the photosensitive units 70, so that the circuit scale is small. There has been a problem that it is difficult to reduce the size of the apparatus by increasing its size.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a driving method of a solid-state imaging device which can support a non-interlace scanning method and can reduce the circuit scale, thereby contributing to downsizing of the device.

<Means for Solving the Problems> A driving method of a solid-state imaging device according to the present invention is provided for each of a plurality of pixels arranged two-dimensionally in a matrix in the horizontal and vertical directions and accumulates according to the amount of incident light. A light receiving unit having an amplifying element for amplifying and outputting the signal charge,
A method for driving a solid-state imaging device comprising first and second signal holding means, wherein the amplified output of each light receiving unit of two pixels adjacent in the vertical direction during a horizontal blanking period is converted into a first signal and a second signal. The holding means respectively hold the signals, and the held outputs of the signal holding means are sequentially read.

<Operation> In the driving method of the solid-state imaging device according to the present invention, the amplified outputs of the light receiving units of two pixels adjacent in the vertical direction are respectively held in the horizontal blanking period, and the held outputs are sequentially read out, so that the non-interlaced Obtain a television signal.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing only a main part of an embodiment of a solid-state imaging device according to the present invention. In this figure, for convenience of explanation, the circuit configuration of only one pixel of each of two adjacent n-th and (n + 1) -th lines among a plurality of pixels arranged two-dimensionally in a matrix in the horizontal and vertical directions is shown. It is assumed that all the remaining pixels have the same circuit configuration.

In the figure, when light is incident on each pixel, a signal charge corresponding to the amount of incident light is stored in a storage (ST) 1.
This storage 1 and its output gate (OG) switch 2
Form a 1-bit CCD (Charge Coupled Device). A reset MOS-FET 3 and a source follower amplifying MOS-FET 4 are formed on the same chip as the CCD. The amplifier (FDA) 5 is formed.

In the floating diffusion amplifier 5, the gate electrode of the output gate switch 2 is connected to the output gate (OG) signal line 6, and the reset MOS-FET 3
Is connected to a reset gate (RG) signal line 7a, and the reset electrode is connected to a reset drain (RD) signal line 7b. The vertical scanning shift register 8 outputs the output gate pulse φ _OG to the gate electrode of the output gate switch 2, the reset gate pulse φ _RG to the gate electrode of the reset MOS-FET 3, and the reset drain pulse φ _RD to the drain electrode. A horizontal line is selected by being applied respectively. Also for amplification
The power supply voltage V _DD is applied to the drain electrode of the MOS-FET 4,
The source electrode is connected to the vertical signal line 9 as an output terminal _Vout . And when one horizontal line is selected,
The signal charge of the pixel on the selected horizontal line is
The signal is amplified by the S-FET 4 and output to the vertical signal line 9.

The vertical signal line 9 is connected to the load transistor 11 through the transfer gate switch 10, the amplified output of each pixel output to the vertical signal line 9 is stored in the noise eliminating capacitor C _0. The output end of the capacitor C ₀ is connected clamp switch 12, by which is turned by the clamp switch 12 is clamp pulse phi _CL to the gate electrode is applied, the output end of the capacitor C ₀ The potential is clamped to the clamp level V _CLP . The noise removing capacitor C ₀ and the clamp switch 12, CDS (correlated double sampling) circuit 15 for reducing noise reset noise and the like included in the source output of the amplifying MOS-FET 4 is configured.

The output of the noise removal capacitor C _0, the buffer amplifier
After passing through 13, the signal is selectively supplied to sample / hold capacitors C ₁ and C ₂ as _first and _second signal holding means by a change-over switch 14 and sampled / held by these capacitors C ₁ and C ₂ . . The switching control of the selector switch 14 is performed for each line by a sample / hold pulse φ _SH generated in a horizontal blanking period. Thus, for example, the pixel output of the even lines in the capacitor C _1, the pixel output of the odd line is to be held respectively in the capacitor C _2.

The hold output of capacitors C ₁ and C ₂ is
After passing through 16 _-1 and 16 _-2, they are led to the horizontal signal lines 18 _-1 and 18 _-2 by switching by the horizontal gate switches 17 _-1 and 17 _-2 . Switching control of the horizontal gate switches 16 _-1 and 16 _-2 is performed by a horizontal shift pulse φ _H output from the horizontal scan shift register 19.

FIG. 2 shows a sectional structure of the solid-state imaging device according to the present invention having such a configuration. FIG. 2 is a cross-sectional view of the drain electrode (V _DD ) -gate electrode-source electrode (V _out ) of ST-OG-RG-RD... FET4 in one unit cell. As is clear from the figure, the solid-state imaging device according to the present invention has an electrode element group constituting a floating diffusion amplifier (FDA) on the surface of a thin silicon substrate 20, and further has a CVD (Chemical Vapor Vapor Deposition) thereon. The SiO ₂ film 21 is deposited by a method such as Deposition) while the horizontal aluminum wires 23 and the vertical aluminum wires 23 are patterned and arranged in an XY matrix on the SiO ₂ film 22 disposed on the back surface of the silicon substrate 20 as shown in FIG. Reset drain (RD) and MOS-FET for amplification on aluminum wire 24
4 output terminals (V _out ) are connected to each other,
Has a so-called back-illuminated structure in which irradiation light is taken in from the back side.

As described above, the solid-state imaging device has a back-illuminated structure.
Since only the 23 and the vertical aluminum wires 24 are patterned, the aperture ratio can be dramatically improved.

Subsequently, in the solid-state imaging device according to the present invention, one pixel selected by the vertical scanning shift register 8 and the horizontal scanning shift register 19 will be described with reference to the cell sectional view of FIG. 2 and the potential distribution diagram of FIG. The operation will be described with reference to the time chart of FIG.

First, in the horizontal blanking period, as shown in FIG. 3, only for the n-th horizontal lines to be selected in the vertical direction RD (reset drain), at time t ₁ the reset drain pulse phi _RD with high levels ( For example, 5V)
Of applying a reset voltage V _RD, the RD of the remaining horizontal lines by applying a voltage of low level (e.g., 1.5V), performs the line selection. At this time, if the FD of the pixel on the selected horizontal line is reset by the reset gate pulse _φRG , the potential of the FD becomes high level, thereby
The gate potential of the S-FET 4 also becomes high. On the other hand, in the pixels of the horizontal line that are not selected, the FD potential is held at a low level, so that the gate potential of the amplifying MOS-FET 4 is lower than the FD potential by a threshold level as shown by a dotted line in FIG. Low level by V _th (for example, 0.5
V) and a cutoff state is established.

Next, the reset gate pulse phi _RG at time t ₂ is changed to the low level, MOS-FET 3 is reset becomes cut off. In this state, the clamp switch 12 is fixed to the output end of the capacitor C ₀ to the clamp level V _CLP turned on by the clamping pulse phi _CL. And
By clamp pulse phi _CL is extinguished at time t _3, the clamp switch 12 is turned off.

Due to the action of the capacitor C ₀ and the clamp switch 12 in the CDS circuit 15, fixed pattern noise (FPN) including a flaw, _Vth unevenness due to input offset variation of the source follower, low frequency (1 / f) noise of the source follower and
Reset noise generated when the FDA is reset, as well as smear caused by light entering signal lines and CCDs, can be canceled. This eliminates the need for the FPN removal frame memory conventionally used in the signal processing system for the output signal of the solid-state imaging device.

Then, by the output gate (OG) 2 turned on at time t _4, the output gate pulse phi _OG, to transfer signal charges that are stored in the storage (ST) 1 to the FD, the output gate pulse phi _OG transferring all signal charges to the FD until time t ₅ to disappear. Then, the sample / hold pulse φ
Capacitor signal voltage switches the switch 14 switching at time t ₆ to the sample / hold capacitor C ₁ side by _SH
Type in C _1, the sample / hold pulse phi _SH off switch 14 switchable time t ₇ which disappears state (neutral position in the figure)
It holds the signal voltage of the capacitor C ₁ as.

The n-th signal charges of the horizontal line and amplified by the amplifying MOS-FET 4 by the operation timing described above, if the stored in the capacitor C ₁ of the CDS circuit 15, n + 1 th signal charges of horizontal lines by the same operation timing continues Amplify MO
It is amplified by the S-FET 4 and stored in the capacitor C ₂ of the CDS circuit 15.
As a result, the horizontal gate switches 17 _-1 and 17 _-1 by the horizontal shift pulse φ _H generated from the horizontal scan shift register 19 are _output .
Vertically adjacent 2 by switching control of 7 _-2
Pixel signals can be read out independently during the horizontal scanning effective period. During the horizontal scanning valid period, the reset gate (RG) is set to high level and the reset drain (RD)
To a low level (about 1.5V).

In this reading, a non-interlaced television signal can be obtained by sequentially reading out the hold outputs of the capacitors C ₁ and C ₂ . Alternatively, the hold outputs of the capacitors C ₁ and C ₂ may be simultaneously read out. In this case, the read signals are appropriately processed by a signal processing system (not shown), so that the same as in the case of sequential reading is performed. In addition, a non-interlaced television signal can be obtained.

When the storage (ST) 1 overflows with signal charges, the signal charges are discarded by a horizontal overflow from ST → OG → FD → RD. Thus, the reset MO
By using the drain electrode (RD) of the S-FET 3 for selection of the horizontal line and sharing it with the overflow drain, the configuration of the horizontal line selection element and the overflow drain can be simplified.

In the above embodiment, the case where _two output systems for reading the hold outputs of the sample / hold capacitors C ₁ and C ₂ are described as two systems, but as shown in FIG.
The output system may be configured as one system so that the hold outputs of the capacitors C ₁ and C ₂ are alternately and sequentially read. In this case, it is necessary to control the changeover of the changeover switch 14 at twice the speed of the above embodiment.

<Effects of the Invention> As described above, according to the present invention, in the horizontal blanking period, the amplified outputs of the light receiving units of two vertically adjacent pixels are respectively held, and the held outputs are sequentially read. Thus, since the circuit scale can be reduced and the non-interlaced scanning method can be supported, the solid-state imaging device can be downsized.

In addition, the EDTV expected as a high-definition TV in the future employs a non-interlaced scanning method, and even when applied to this EDTV, the solid-state imaging device according to the present invention can obtain a non-interlaced television signal, so There is also an effect that the processing can be easily performed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing only a main part of an embodiment of a solid-state imaging device according to the present invention, FIG. 2 is a sectional configuration diagram showing a structure of one unit cell, and FIG. 3 corresponds to FIG. FIG. 4 is a rear view showing a part of the solid-state imaging device according to the present invention, FIG. 5 is a time chart for explaining the circuit operation of FIG. 1, and FIG. FIG. 7 is a circuit diagram showing another embodiment of the present invention. FIG. 7 is a block diagram of a conventional example. 1… Storage (ST), 2… Output gate (OG), 3…
Reset MOS-FET, 4 …… Amplification MOS-FET, 5 …… FDA
(Floating diffusion amplifier), 12…
… Clamp switch, 15… CDS (correlated double sample hold) circuit, C ₁ , C ₂ … Capacitor for sample / hold.

Claims (1)

(57) [Claims] 1. A light receiving device provided for each of a plurality of pixels arranged two-dimensionally in a matrix in the horizontal and vertical directions, and having an amplifying element for amplifying and outputting accumulated signal charges according to the amount of incident light. And a first and second signal holding means, wherein the amplified output of each light receiving unit of two pixels adjacent in the vertical direction during the horizontal blanking period is converted into the first and second signals. A driving method for a solid-state imaging device, comprising: respectively holding in a second signal holding unit, and sequentially reading each held output of the first and second signal holding units.