JPH04154284A - Solid image pickup apparatus - Google Patents

Abstract

PURPOSE:To miniaturize a solid image pickup apparatus by providing the fixed image pickup apparatus with the function that in a horizontal blanking period of time the amplification output of each photorecepting section of two vertically adjacent picture elements is held and by reading these holding outputs independently. CONSTITUTION:The signal electron charge on the nth horizontal line is amplified by an amplification purpose MOS-FET4 and the amplified signal charge is held in capacitor C1, followed by using amplification purpose MOS-FET4 to amplify signal charge on the n+1st horizontal line in the similar timing, and further followed by holding a result of amplified signal charge in capacitor C2 of the CDS circuit 15. Accordingly, when horizontal scanning shift register 19 exerts a horizontal shift pulse phiH, this pulse activates horizontal gate switches 17-1 and 17-2, and by the switching control of the horizontal gate switches, signals of two vertically adjacent picture elements can be read independently in a horizontal scanning valid period of time. As a result, since the present solid image pickup apparatus can deal with non-interlace scanning method while reducing circuit scale, thereby being able to miniaturize the solid image pickup apparatus.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a solid-state imaging device, and particularly to a solid-state imaging device compatible with a non-interlaced scanning method.

<Summary of the Invention> The present invention provides a solid-state imaging device compatible with a non-interlaced scanning method, in which a light receiving section provided for each pixel of a plurality of pixels arranged two-dimensionally in a matrix in the horizontal and vertical directions, It has an amplification element that amplifies the signal charge accumulated according to the amount of incident light, and has a configuration in which each amplified output of two pixels adjacent in the vertical direction is held during the horizontal blanking period, and these held outputs are read out independently. By doing so, it is possible to reduce the circuit scale and downsize the solid-state imaging device.

<Prior Art> A television screen is made up of a large number of scanning lines that are sequentially scanned from the upper left to the right. In the standard television system, one There are 95 interlaced scans in which scanning is performed by skipping every other line.

In this interlaced scanning, one field (odd field) picture m is formed by interlacing scanning every other line in the first 1/60 second, and then in the next 1/6
At 0 seconds, the next field (even field) screen is formed by scanning over the shore every other line to fill in the spaces between the scanning lines of the odd field, and between the odd and even numbers, the field screen is 1/30 seconds. One composite image (frame screen) is completed each time.

As described above, since the standard television system is an interlace scanning system, solid-state imaging devices used in television cameras also adopt a transfer system compatible with the interlace scanning system as a signal charge transfer system.

However, the non-interlaced scanning method is more advantageous than the interlaced scanning method in terms of improving vertical resolution, and also has the advantage that signal processing is simpler.

As shown in FIG. 7, a conventional example of a solid-state imaging device that is compatible with the second non-interlaced scanning method is to reduce the signal charge accumulated in the photosensitive section 70 to 1/30 according to the amount of incident light.
During the vertical blanking period at a period of seconds, the data on the odd lines is transferred to the odd field vertical transfer unit 71, and the data on the even lines is transferred to the even field vertical transfer unit 72 at the same time.
After the vertical transfer units 71 and 72 transfer the data in the vertical direction, the vertical transfer switching unit 73 alternately selects the
4, and is serially read out in one horizontal scanning period from an output section 75 provided at the final end of this horizontal transfer section 74, and is derived as a video signal for one frame. (Refer to Japanese Patent No. 1983-49382).

<Problems to be Solved by the Invention> However, in the conventional solid-state imaging device described above, two vertical transfer units are provided for one vertical column of photosensitive units 70.
Since the arrangement is such that each row is provided, there is a problem in that the circuit scale becomes large and this becomes an obstacle to miniaturizing the device.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a solid-state imaging device that is compatible with the non-interlaced scanning method and that can be downsized by reducing the circuit scale.

<Means for Solving the Problems> A solid-state imaging device according to the present invention provides signals for each pixel of a plurality of pixels arranged two-dimensionally in a matrix in the horizontal and vertical directions and accumulated according to the amount of incident light. a light receiving section having an amplification element that amplifies and outputs electric charges; first and second signal holding means that respectively hold the amplified outputs of the respective light receiving sections of the vertically adjacent 2WJ elements during the horizontal blanking period; The configuration includes signal reading means for independently reading each output of the first and second signal holding means.

<Operation> In the solid-state imaging device according to the present invention, vertically adjacent 2i! A non-interlaced television signal is obtained by holding the amplified outputs of each elemental light receiving section and independently reading out these held outputs.

<Example> Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 1 is a circuit diagram showing only essential parts of an embodiment of a solid-state imaging device according to the present invention. In this figure, for convenience of explanation,
Of the multiple pixels arranged two-dimensionally in a matrix in the horizontal and vertical directions, the circuit configuration of only one pixel in each of the two adjacent lines, nth and n+1st, is shown, but the remaining pixels all have the same circuit configuration. It is assumed that

In the figure, when light is incident on each pixel, signal charges corresponding to the amount of incident light are stored in a storage (ST) 1.

This storage l and its output gate (OG") switch 2 allow 1-bit COD (Charge Cou
pled Device) is configured.

Also, on the same chip as this CCD, there is a reset MO3-
FET3 and source follower amplification MO3FET4 are made, and the gates of amplification MO3-FET4 are floating diffusion (Fl).

floating diffusion amplifier (FDA) 5.

In this floating diffusion amplifier 5, the gate electrode of the output gate switch 2 is output
(QC) Connected to signal line 6 and also for reset MO3-
The gate electrode of the FET 3 is connected to a reset gate (RG) signal line 7a, and the reset electrode is connected to a reset drain (RD) signal line 7b. Then, an output gate pulse φ is output from the vertical scanning shift register 8 to the gate electrode of the output gate switch 2. . However, MO3 for reset
- reset gate pulse φ to the gate electrode of FET3,
However, a reset drain pulse φ is applied to the drain electrode. A horizontal line is selected by applying each of them. Moreover, the power supply voltage VDD is applied to the drain electrode of MO3-FE74 for amplification, and its source electrode is the output terminal (2). It is connected to the vertical signal line 9 as ul. Then, when one horizontal line is selected, the signal charge of the pixel of the selected horizontal line is transferred to the MO3-FE for amplification.
74 and output to the vertical signal line 9.

A load transistor 11 is connected to the vertical signal line 9 via a transfer gate switch 10, and the amplified output of each pixel output to the vertical signal line 9 is connected to a noise removal capacitor C.
Stored at 0. A clamp switch 12 is connected to the output end of this capacitor C0, and when the clamp switch 12 is turned on by applying a clamp pulse φct to its gate electrode, the potential at the output end of the capacitor C0 is clamped. It is clamped to the level V ctp. This noise removal capacitor C0 and clamp switch 12 constitute a CDS (correlated double sampling) circuit 15 for reducing noise such as reset noise included in the source output of the amplification MO3-FET4.

After passing through the buffer amplifier 13, the output of the noise removal capacitor C0 is switched to the first. Sample/hold capacitor C, which is the second signal holding means
1, Cz, and these capacitors CI,
Sampled/held by Ct. The switching control of the changeover switch 14 is performed by sample/hold pulses φ and H generated during the horizontal blanking period.
This is done line by line. As a result, for example, the pixel outputs of the even lines are held in the capacitor C1, and the pixel outputs of the odd lines are held in the capacitor C2.

The hold outputs of the capacitors C, ,C, pass through the buffer amplifiers 16-+ and 16-t, and then are sent to the horizontal gate switch l'
1. ．． The signal is led out to the horizontal signal line 1B-1, 18-z by switching by I'll. Horizontal gate switches 16-, . 16-z is controlled by a horizontal shift pulse φ output from the horizontal scanning shift register 19.
It is done by □.

FIG. 2 shows a cross-sectional structure of a solid-state imaging device according to the present invention having such a configuration. Note that FIG. 2 is a cross-sectional view of the drain electrode (Van)-gate electrode-source electrode (■., L) of the 5T-OG-RG-RD...FET4 in one unit cell. As is clear from the figure, in the solid-state imaging device according to the present invention, a group of electrode elements constituting a floating diffusion amplifier (FDA) is arranged on the surface of a thin silicon substrate 200, and further CV D (
Chemical Vapor Deposition)
5iOzl! 21 is deposited, while a reset drain (RD ) and the output terminal of the amplification MOS-FET4 (
■. □) are connected to each other, and has a so-called back-illuminated structure in which irradiation light is taken in from the back side of the silicon substrate 20.

In this way, by making the structure of the solid-state imaging device a back-illuminated type, only the horizontal aluminum wire 23 and the vertical aluminum wire 24 are patterned on the back side of the silicon substrate 20, so the aperture ratio can be dramatically increased. This means that you can improve your performance.

Next, in the solid-state imaging device according to the present invention, for each pixel selected by the vertical scanning shift register 8 and the horizontal scanning shift register 19, the following will be described with reference to the cell cross-sectional diagram in FIG. 2 and the potential distribution diagram in FIG. 3. The operation will be explained according to the time chart shown in FIG.

First, during the horizontal blanking period, as shown in FIG. 3, only the RD (reset drain) of the nth horizontal line selected in the vertical direction is set to a high level (for example, by the reset drain pulse φ■) at time t1. ,5
Line selection is performed by applying a reset noise VIIID of V) and applying a low level voltage (for example, 1.5 V) to RD of the remaining horizontal lines. At this time, if the FD of the pixel of the selected horizontal line is reset by the reset gate pulse φ1, the potential of the FD becomes high level, and thereby the gate potential of the amplification MOS-FET 4 also becomes high level. On the other hand, in the pixels of the unselected horizontal line, by keeping the FD' at a low level, the amplifying MO3-FET4 has a gate potential that is lower than the FD potential as shown by the dotted line in FIG. Short level (2) becomes a low level (for example, 0.5V) for 0 minutes, and enters a cut-off state.

Next, at time t2, the reset gate pulse φIIG transitions to low level, so that the reset MOS-FET
3 is in a cant-off state. In this state, the clamp switch 12 is turned on by the clamp pulse φ, and the output terminal of the capacitor C0 is clamped by the clamp pulse n.When the clamp pulse φc1 disappears at point t3, the clamp switch 12 is turned off.

The effects of the capacitor C0 and the clamp switch 12 in the CDS circuit 15 cause fixed pattern noise (FPN) including scratches, unevenness caused by source follower input offset variations, and source follower low frequency (1/f
) Noise, reset noise generated when resetting the FDA, and smear caused by light entering the signal line or COD can be canceled. This eliminates the need for a frame memory for FPN removal, which has been conventionally used in a signal processing system for output signals of a solid-state imaging device.

Then, the output gate pulse φ. 6, by turning on the output gate (OG) 2 at time t4, the signal charge stored in the storage (ST) 1 is transferred to the FD,
All signal charges are transferred to the FD until time t when the output gate pulse φQG disappears. After that, changeover switch 1 is turned on at time t by sample/hold pulse φ3H.
4 to the sample/hold capacitor C3 side and input the signal voltage to the capacitor CI, and at the time t when the sample/hold pulses φ and H disappear, the selector switch 14 is turned off (neutral position in the figure) and the signal voltage is input to the capacitor CI.
Hold the signal voltage.

After the signal charge of the n-th horizontal line is amplified by the amplification MO3-FET4 and stored in the capacitor C1 of the CDS circuit 15 according to the operation timing described above, the signal charge of the n+1-th horizontal line is subsequently amplified by the same operation timing. Amplify with MO3-FET4 for amplification, CDS circuit 15
is stored in capacitor C3. As a result, the horizontal gate switches 17-1 . By controlling the switching of 17-z, the signals of two vertically adjacent pixels can be read out independently during the valid horizontal scanning period. Note that during the horizontal scanning valid period, the reset gate (
RG) to high level and reset drain (RD) to low level (approximately 1.5V).

During this readout, by sequentially reading out the hold outputs of the capacitors C, , C, a non-interlaced television signal can be obtained. Also, capacitors C,,C.

It is also possible to read out each hold output at the same time.
In this case, by appropriately processing the read signal in a signal processing system (not shown), a non-interlaced television signal can be obtained as in the case of sequential readout.

When the storage (ST) 1 overflows with signal charges, the signal charges are discarded from ST to ○G and FD-4RD due to horizontal overflow. In this way, by using the drain electrode (RD) of the reset MO3-FET3 for horizontal line selection and also using it for the overflow train, the configuration of the horizontal line selection element and overflow train can be simplified.

In the above embodiment, the case where there are two output systems for reading out the hold outputs of the sample/hold capacitors C, , C, was explained, but as shown in FIG. It is also possible to configure the hold outputs of the capacitors C, , C2 to be read out alternately and sequentially.

In this case, it is necessary to perform switching control of the changeover switch 14 at twice the speed as in the above embodiment.

<Effects of the Invention> As explained above, according to the present invention, the amplified outputs of the respective light receiving parts of two vertically adjacent pixels are held during the horizontal blanking period, and these held outputs are read out independently. By doing so, it is possible to support the non-interlaced scanning method while reducing the circuit scale, which has the effect of reducing the size of the solid-state imaging device.

In addition, HDTV, which is expected to be a high-definition TV in the future, uses a non-interlace scanning method, and even when applied to this HDTV, the solid-state imaging device according to the present invention can obtain a non-interlace television signal, so the signal It also has the effect of making processing easier.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing only the essential parts of an embodiment of a solid-state imaging device according to the present invention, FIG. 2 is a cross-sectional structural diagram showing the structure of one unit cell, and FIG. 3 corresponds to FIG. 4 is a back view showing a part of the solid-state imaging device according to the present invention, FIG. 5 is a time chart for explaining the circuit operation of FIG. 1, and FIG. 6 is a FIG. 7, a circuit diagram showing another embodiment of the present invention, is a configuration diagram of a conventional example. 1...Storage (ST). 2... Output gate (COG). 3...MO3-FET for reset. 4...MO3-FET for amplification. 5...FDA (Floating Diffusion)
Amplifier). 12...Clamp switch. 15...CDS (correlated double sample and hold) circuit C,, C,...Sample/hold capacitor. Patent applicant Sony Corporation agent
Patent Attorney Funa Kuninori Hashi Figure 1 Figure 1 Uni 7F Nagi Tsumu's ffT side B Figure 2 Figure 3 Fixed salary imaging Offshore 1's mo face day Figure 4 Sun's evening f Whip v-t- Figure 5

Claims (1)

[Claims] An amplification element is provided for each pixel of a plurality of pixels arranged two-dimensionally in a matrix in the horizontal and vertical directions and amplifies and outputs signal charges accumulated according to the amount of incident light. a light receiving section; first and second signal holding means that respectively hold the amplified outputs of the light receiving sections of two vertically adjacent pixels during the horizontal blanking period; and each of the first and second signal holding means. A solid-state imaging device comprising: signal reading means for independently reading out outputs.