JPH11313256A - Amplifier type solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a high quality video signal by outputting voltages of 1st and 2nd hold capacitors to a common signal line via an impedance conversion circuit as each set of voltages independently and respectively for a conduction period of a read switch circuit. SOLUTION: Operations of signal reading, signal charge discharging and no-signal reading are conducted in common by pixels in a direction of rows, while a signal voltage and a non-signal voltage in the unit of a pixel are respectively stored in hold capacitors 203, 204. The non-signal voltage and the signal voltage of the stored pixels are fed to the gate of a driver transistor(TR) 152 used in common by switches 203, 204. The switches 203, 204 are driven separately and sequentially by clocks ϕH outputted from a horizontal scanning circuit 145. The drive pulses given to the switches 203, 204 are synthesized by an OR circuit 213 to make a horizontal selection TR 153 conductive over a period when the non-signal voltage and the signal voltage are read. The non-signal voltage and the signal voltage of pixels are read on a horizontal signal line 154 in pairs.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifying solid-state imaging device, and more particularly to an amplifying solid-state imaging device that achieves excellent fixed pattern noise suppression.

[0002]

2. Description of the Related Art As a solid-state image pickup device, each pixel is generated.
Instead of reading out the signal charge itself,
After converting and amplifying the load into a voltage or current signal, this voltage
Amplified solid that reads out current signal by scanning circuit
An imaging device has been proposed. This amplification type solid-state imaging device
The photoelectric conversion unit and the amplification unit are flat depending on the arrangement of the pixel unit.
Horizontal type arranged in a plane and these are arranged three-dimensionally
It is classified into vertical type. As a horizontal example, an AP shown in FIG.
The S type is known. Reference 1: S.K. Mendis, et al., "
A 128x128 COMS Active Pixel Image Sensor for High
ly Integrated Imaging Systems ", IEDM'93-583 ~ 58
6, Dec. 1993. In FIG. 7, generated in the photoelectric conversion unit 101.
The transferred signal charge is transferred through the transistor 102.
The voltage signal is transferred to the gate of the
Is subjected to impedance conversion (current amplification), and the pixel selection switch
Signal V via switch 104_sigIs read. Signal reading
After the discharge, the signal charges accumulated in the gate of 103 are reset.
V by the reset transistor 105 _DIs discharged to

As a vertical type, a CMD type shown in FIG. 8 is known. Reference 2: Nakamura et al., “Gate Storage MOS
Phototransistor Image Sensor ", Journal of the Institute of Television Engineers of Japan, Vol. 41, No. 11, pp. 1047-1053, 1987. In FIG. 8, in the transistor 111, signal charges generated by photoelectric conversion are held under the gate. Next, by applying a read voltage (φ _X ) to the gate, a change in the characteristics of the transistor due to the signal charge is read as the output signal voltage V _sig . That is, in the transistor 111, photoelectric conversion, amplification, and pixel selection are performed. The reset operation is
This is achieved by applying a reset voltage (φ _R ) sufficiently higher than the read voltage to the gate to discharge signal charges to the substrate. Therefore, φ _X
/ Φ _R ternary high voltage pulse is required.

[0004] Furthermore, the inventor of the present invention has made driving easier.
FIG. 9 shows an example of a vertical type proposed in Japanese Patent Application Laid-Open No. Hei 8-7865.
No. 3). The transistor 121 is used for photoelectric conversion, amplification,
And read. For reading, read voltage is applied to the gate.
φ_XIs applied. Transistor 12
In the case of 2, the reset voltage φ is applied to the gate._RBy applying
Drain signal charges. Therefore, each drive is independent
Low voltage binary pulse φ_X, φ_ROnly need to be applied.

The pixel sections of the various amplification type solid-state imaging devices shown in FIGS. 7, 8 and 9 are represented by a common schematic diagram as shown in FIG. Here, the photoelectric conversion unit 131 performs photoelectric conversion, readout, and reset operation. The read and reset operations are performed by a read voltage φ input from each signal line.
It is controlled by the _X and the reset voltage phi _R. The output of the photoelectric conversion unit 131 is amplified by the amplification unit 132 and the signal V _sig
Is output as

FIG. 11 shows an example in which a two-dimensional image sensor is configured using the pixel portion of the above-mentioned amplification type solid-state imaging device. Here, each pixel portion has the same configuration as that of FIG. The read operation of the pixel portion is controlled by a signal 143 from the first vertical scanning circuit 141, and the reset operation is controlled by a signal 144 from the second vertical scanning circuit 142. The output signal of the pixel corresponds to the correlation 2 provided for each vertical signal line 140.
The signal is guided to a double sampling (CDS) circuit, and a difference between a signal at the time of reading and a signal at the time of reset is output. Therefore, the variation of the threshold value for each pixel is canceled, and the fixed pattern noise (FPN) for each pixel is suppressed. The CDS circuit includes a clamp circuit and a sample-and-hold circuit described later. A configuration in which a CDS circuit is provided for each vertical signal line is described in J. Pat. Hynecek, ”A New Device Architectu
re Suitable for High Resolutionand High Performanc
e Image sensors ”, IEEE Trans.Electron Devices, Vo
l. 35, No. 5, p. 646-652, May 1988. The vertical signal line 140 is connected to the sample / hold transistor 151 via the clamp capacitance 149. In parallel with this, it is connected to the clamp potential V _VCP via the clamp transistor 150. The clamp operation to the clamp potential is performed at the time of reading a signal at the pixel, and the sample-hold operation is performed at the time of a reset operation at the pixel.

A signal from the sample-and-hold transistor 151 is guided to the gate of a driver transistor 152 of a source follower circuit that performs impedance conversion (current amplification), and the gate serves as a sample-and-hold capacitor to hold the signal. The signal amplified by the driver transistor 152 is guided to a horizontal signal line 154 via a horizontal selection transistor 153 controlled by a signal 146 from a horizontal scanning circuit 145. The horizontal signal line 154 is connected to a transistor 155 serving as a load of the driver transistor 152, and a transistor 156.
Connected to the gate. The transistor 156 forms a source follower circuit with the transistor 157, and outputs the signal OS. Note that the vertical signal lines 140 to the horizontal signal lines 15
An example of a configuration in which a source follower circuit is provided for each vertical signal line to transfer a signal to the X.4 signal is disclosed in the above-mentioned document 1.

Next, FIG. 12 shows the drive timing of the two-dimensional image sensor shown in FIG. From the first vertical scanning circuit 141, read voltage pulses φ _X (i), φ _X (i + 1) for controlling the timing of reading signals from each pixel are sequentially applied for each horizontal scanning period (1H). Is done. From the second vertical scanning circuit 142, voltage pulses φ _R (i), φ _R (i +
1) and the like are sequentially applied every 1H. The pulses φ _{X and} φ _R are set, for example, to perform read and reset operations at a high level, respectively. Therefore, the vertical signal line 140 is the read level in a period T ₁ for each 1H period,
Reset level appears at T _2. Thus, the clamp pulse φ _VCP is in the period T ₁ and the sample hold pulse φ _VSH
The period T _2, to operate each of the signal corresponding to the difference between the sample-and-hold capacitor and read and reset levels, i.e. only the net signal is retained, the FPN due to variation in the threshold value of each pixel is suppressed .

The source follower circuit driver transistor 152 whose gate also serves as a sample-and-hold capacitor performs impedance conversion (current amplification). Horizontal scanning circuit 14
5, the pulses φ _H (j), φ sequentially selected in the horizontal direction
_H (j + 1) and the like are applied in one pixel cycle, and the horizontal signal line 15 is applied.
4 sequentially outputs each pixel signal. However, if there is a variation in the threshold value of the driver transistor 152 provided for each vertical column, the signal OS has a variation for each pixel. In Figure 12 the variation shown by [Delta] V _T. This variation ΔV _T is random in the horizontal direction and common in the vertical direction.
PN becomes a cause of significantly deteriorating the image quality. further,
Variations in the conductance of the horizontal selection transistor 153 also cause vertical stripe pattern FPN.

As a method for solving the above-mentioned vertical stripe pattern FPN, the present applicant has proposed a technique shown in FIG. 13 (Japanese Patent Application No. 8-330014). That is, FIG.
Follower Circuit Driver Transistor 15
2 is provided with a reset transistor 13 for resetting its gate potential to the reference power supply V _VCP, and the gate of the reset transistor 13 is turned on in the latter half of the period in which the signal from the driver transistor 152 is read out to the signal line 154 by the horizontal selection transistor 153. , The pixel signal is read out in the first half, and the reference signal (V _VCP ) is read out in the second half. Here the pixel signal and the reference signal both contain the same characteristic deviation (variation in the conductance of the [Delta] V _T and the horizontal selection transistor 153 of the driver transistor 152). Therefore, if the difference between the paired pixel signal and the reference signal is obtained in the output signal OS, these characteristic deviations are cancelled, and only a net pixel signal is obtained. That is, the vertical stripe pattern FPN due to the variation in the characteristics of the transistor for each pixel is prevented. Note that taking the difference between the pixel signal and the reference signal in the output signal OS is based on the aforementioned C
It is easily realized by a DS circuit.

[0011]

However, FIG.
Has the following problems. That is, during a period in which pixel signals of one horizontal column are read out,
The pixel signal voltage is held in a capacitor formed in the gate of the driver transistor 152 and a region connected thereto (eg, a source region of the transistor 151 or the transistor 13). The holding period is distributed over the period during which the horizontal scanning circuit scans, and the holding time is short at the first pixel and long at the last pixel. Therefore, if a leak current exists in the gate region of the driver transistor 152, the effect becomes non-uniform from the first pixel to the last pixel. That is, in the output signal, shading-like non-uniformity distributed from the left side to the right side on the screen occurs. This is also a kind of FPN. The reason for this is that the above-mentioned storage capacitance is small, so that it is affected by the surrounding capacitance.

As another technique for solving the vertical stripe pattern FPN, a technique shown in FIG.
No. 42330). Here, a pair of capacitors 3a and 3b are connected to each vertical signal line, and hold a bright signal and a dark signal, respectively. The signals held in these capacitors are read out to separate horizontal signal lines 9 and 10 via separate impedance conversion circuits 4a and 4b and separate selection switching elements 5a and 5b. The gates of the impedance conversion circuits 4a and 4b are respectively connected to reset means 6a,
It is connected to the power supply 11 via 6b. Accordingly, by performing a differential operation between the two horizontal signal lines 9 and 10, a difference between a bright signal and a dark signal, that is, a net signal is obtained. However, in the case of this method, since the bright signal and the dark signal are read out through separate impedance conversion circuits, selective switching elements, and horizontal signal lines, if there is a difference in the characteristics of these circuit elements, they cannot be removed. Produces possible spurious signals. Since this false signal varies from one vertical signal line to another, there is a serious problem that a vertically striped FPN is generated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and greatly reduces the FPN associated with horizontal pixel selection, reduces shading-like non-uniformity, and obtains a high-quality image. An object of the present invention is to provide an amplification type solid-state imaging device that can be used.

[0014]

An amplifying solid-state imaging device according to the present invention comprises a plurality of amplifying photoelectric conversion elements, a plurality of vertical signal lines each connected to the plurality of amplifying photoelectric conversion elements, and A common signal line for reading signals of the plurality of vertical signal lines via the impedance conversion circuit and the read switch circuit, and first and second hold capacitors for holding a voltage of the vertical signal line; While the read switch circuit is in the conductive state, the voltages of the first hold capacitor and the second hold capacitor are output to the common signal line via the impedance conversion circuit as independent sets of voltages, respectively. This achieves the above object.

The first and second hold capacitors are connected to the vertical signal line via first and second switching elements, respectively, and are connected to the first hold capacitor and an input terminal of the impedance conversion circuit. A third switching element, and a fourth switching element connected to the second hold capacitor and the input terminal of the impedance conversion circuit, wherein the read switch circuit is in a conductive state, The third and fourth switching elements become conductive during a period independent of each other, and the voltage of the first hold capacitor and the voltage of the second hold capacitor are set as independent sets of voltages via the impedance conversion circuit via the common communication circuit. It may be configured to output to the line.

A signal reading period for reading a voltage corresponding to a signal charge of the amplification type photoelectric conversion element from the amplification type photoelectric conversion element, a discharge period for discharging the signal charge of the amplification type photoelectric conversion element, and a discharge period And a non-signal reading period for reading a voltage corresponding to the no signal after
The switching element becomes conductive during the signal readout period, the voltage from the amplification type photoelectric conversion element is held as a signal voltage in the second hold capacitor, and the first switching element becomes conductive during the non-signal readout period. In this case, the voltage from the amplification type photoelectric conversion element may be held in the first hold capacitor as a non-signal voltage.

The order in which the voltage from the amplifying photoelectric conversion element is held in the first hold capacitor and the second hold capacitor, and the order in which the voltage held in the first hold capacitor and the second hold capacitor are independent of each other. The order of outputting the set of voltages to the common signal line via the impedance conversion circuit may be different from each other.

The period in which the third switching element is conducting and the period in which the fourth switching element is conducting are continuous without overlapping each other, and the period in which the third switching element is conducting is such that the fourth switching element is not conducting. It may be before the conduction period.

A reset power supply is further connected to the input terminal of the impedance conversion circuit via a fifth switching element, and the fifth switching element is turned on before the third switching element and the fourth switching element become conductive. The switching element may be in a conductive state, and a reference potential may be applied to the input terminal of the impedance conversion circuit.

A period in which the sixth switching element is connected in parallel with the fifth switching element between the input terminal of the impedance conversion circuit and the reset power supply, and the third switching element is in a conductive state; And the sixth switching element may be turned on during a period in which the fourth switching element is turned on.

The semiconductor device further includes first clamp means and a first sample hold circuit connected to the common signal line, wherein the first clamp means is connected to the first signal of the set of voltages from the common signal line. The first sample and hold circuit samples and holds the voltage of the second hold capacitor, thereby corresponding to the difference between the voltage of the first hold capacitor and the voltage of the second hold capacitor. May be output.

The semiconductor device further includes first and second sample-and-hold circuits connected to the common signal line, and an arithmetic circuit, wherein the first sample-and-hold circuit includes one of the set of voltages from the common signal line. The voltage of the first hold capacitor is sampled and held, the second sample and hold circuit samples and holds the voltage of the second hold capacitor, and the arithmetic circuit is held by the first and second sample and hold circuits. It may be configured to output a voltage difference.

The plurality of amplifying photoelectric conversion elements are arranged in a matrix, and the first hold capacitor and the second
The operation of outputting the voltage of the hold capacitor as an independent set of voltages to the common signal line is performed for each of the plurality of amplifying photoelectric conversion elements arranged in the row direction, and may be repeated for each row. Good.

The operation of outputting the voltage of the first hold capacitor and the voltage of the second hold capacitor as an independent set of voltages to the common signal line may be repeated a plurality of times for each row.

The operation will be described below.

In the solid-state imaging device according to the present invention, the non-signal voltage and the signal voltage from the amplification type photoelectric conversion element are:
The signals are stored in the first hold capacitor and the second hold capacitor, respectively, and transmitted as an independent set of signals to the same common signal line via an impedance conversion circuit. By taking the difference between these one set of signals, the F caused by the non-uniformity of the horizontal reading means provided for each vertical signal line is obtained.
Not only PN is canceled, but also shading due to non-uniformity of the hold time of each horizontal readout unit is suppressed, and a video signal of extremely high image quality can be obtained.

The order of reading out signals and non-signals is determined in each of the case where each amplification type photoelectric conversion element is read out to a vertical signal line and the case where reading out is performed from a vertical signal line to a common signal line.
It is possible to exchange the data, facilitating an accurate clamping operation at the time of a clamping / sample-hold operation described later.

Further, by clearing the immediately preceding signal held in the impedance conversion circuit by a reset operation, one set of signals is prevented from being affected by the immediately preceding set of signals. Also, it is possible to prevent the signal voltage in one set of signals from being affected by the no-signal voltage.

By the configuration of the clamp circuit and the sample-and-hold circuit, or the configuration for obtaining the difference between the outputs of the two sample-and-hold circuits, the non-signal from the amplifying photoelectric conversion element is read out to the horizontal signal line in a pair. The difference between the voltage and the signal voltage is obtained, so that not only the FPN caused by the non-uniformity of the characteristics of the horizontal readout means is canceled, but also the shading due to the non-uniformity of the hold time of each horizontal readout means is suppressed.

Further, pixel read and reset operations,
The signal voltage appearing on the vertical signal line and the non-signal voltage are held during the horizontal scanning blanking period, and then these voltages are read out in the horizontal direction, thereby reading out each horizontal pixel column for each horizontal scanning period. F in operation
PN and shading can be suppressed.

In the blanking period at the beginning of the first horizontal scanning period, pixel readout and reset operation, signal voltage and non-signal voltage appearing on the vertical signal line are held, and then horizontal signal readout is performed. By performing nothing in the blanking period over a plurality of horizontal scanning periods after the second horizontal scanning period, the second signal reading in the horizontal direction is performed, and if necessary, the signal reading operation in the third and subsequent horizontal directions is repeated. By repeating the read operation of each horizontal pixel column over a plurality of horizontal scanning periods,
This can be performed with PN and shading suppressed.

[0032]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of an amplification type solid-state imaging device according to the present invention. The device according to the present embodiment includes two hold circuits controlled by switches 201 and 202, respectively, instead of the clamp circuit and the sample hold circuit provided for each vertical signal line in the conventional amplification type solid-state imaging device shown in FIG. Capacitors 211 and 212 are provided. Since the hold capacitors 211 and 212 hold a signal as a voltage, the capacitance values may be different from each other. Also, two hold capacitors 211 and 21
The reading of the signal (voltage) from the two switches 203 and 20 controlled by the signal from the horizontal scanning circuit
4, and an OR circuit. In FIG. 1, components that perform the same operations as those in FIG. 13 are denoted by the same reference numerals.

The photoelectric conversion unit 13 of each pixel in one row in the horizontal direction
1 simultaneously inputs the read voltage pulse φ _X from the first vertical scanning circuit 141 during the read period, and _{applies the} respective signal voltages V _sig via the amplifier 132 to each vertical signal line 14.
0 (signal read operation). The photoelectric conversion unit 131 of each pixel in the same row, the discharge period, apply voltage pulses phi _Y from the second vertical scanning circuit 142 simultaneously, to discharge the respective signal charges (reset operation).

During the signal reading period, the switch 202 driven by the clock φ _S1 is turned on, and the signal voltage corresponding to the signal charge photoelectrically accumulated in the pixel is applied to the hold capacitor 2.
12 is held. Next, after the discharge period (reset period), the switch 201 driven by the clock φ _S2 is turned on, and the signal charge is discharged. The subsequent no-signal voltage is held in the hold capacitor 211 during the no-signal reading period. The operations of signal reading, signal charge discharging, and non-signal reading are performed commonly for each pixel in the row direction, and the signal voltage and the no-signal voltage are held in the hold capacitors 211 and 212 in pixel units, respectively.

The no-signal voltage and signal voltage of the pixel held by the hold capacitors 211 and 212 are applied to the switch 2
03 and 204, the common driver transistor 152
Is applied to the gates. Switches 203 and 204 are controlled by clock φH output from horizontal scanning circuit 145.
The driving pulses of the switch 203 and the driving pulse of the switch 204 are sequentially and separately driven.
And the horizontal selection transistor 153 is in a conductive state (ON) over a period during which the no-signal voltage and the signal voltage are read. With the above operation, the horizontal signal line 1
The non-signal voltage and the signal voltage of the pixel are read out as a pair at 54.

When the switch 203 is turned on before the switch 204, the non-signal readout period precedes the signal readout period, and the order in which both signals are read out from the pixels to the vertical signal lines is switched. It becomes possible. This makes it possible to clamp a non-signal at the time of a clamp / sample hold operation described later.

A signal from the horizontal signal line 154 becomes an output signal OS via a driver transistor 156 and load transistors 155 and 157. By passing the output signal OS through a correlated double sampling (CDS) circuit, which will be described later, a difference signal between the no-signal voltage and the signal voltage of each pixel which is read as a pair can be obtained.
FIG. 1 shows only the solid-state imaging device main body. Therefore, in order to obtain the difference between the signal output from the OS and the no-signal output, it is necessary to provide an external signal processing circuit. This signal processing circuit can be configured by a known technique. In the above operation, even if there is a unique offset voltage in each pixel, they are shared by the hold capacitor 211.
And appear in 212. In addition, each driver transistor 15
2 and the horizontal select transistor 153 have an inherent variation in conductance, they are common to the non-signal voltage and signal voltage of each pixel read out in pairs. Appears in Therefore, if the difference signal between the no signal and the signal is obtained by the CDS operation, these variations are canceled, and the fixed pattern noise (FPN) having a zigzag shape caused by the variation of each pixel and the variation of the readout circuit are caused. Vertical FPN is canceled.

Note that, in FIG.
It is necessary to reset the gate potential before reading the no-signal and signal from the hold capacitor to the gate again as a voltage after reading the no-signal and signal held in the and 212 as a voltage to the gate of the driver transistor 152 again. In this example, the voltage is reset to the voltage V _CP by the transistor 205. V _CP may be a ground voltage.

FIG. 2 shows the apparatus of the embodiment shown in FIG.
4 shows the timing of each signal in the embodiment. Vertical scanning circuit 1
From 41, the timing of signal reading from each pixel is controlled.
Pulse φ to control_X(i), φ_X(i + 1) etc. is one horizontal scanning period
It is applied sequentially every (1H). The vertical scanning circuit 142
Controls the timing to discharge the signal charge of each pixel
Pulse φ_Y(i), φ_Y(i + 1) etc. are sequentially applied every 1H.
It is. Note that φ_X,φ_YEach pulse is read at a high level.
Output and reset operations. Therefore, the signal line 140
Has a period T every 1H period₁And the read level is T_TwoIn
Set level appears. From this, the clock φ_S1Is the period
T₁And the clock φ_S2Is the period T_TwoSo, each work
Thus, the hold capacitor 212 receives the pixel signal voltage,
The non-signal voltage of the pixel is applied to the hold capacitor 211, respectively.
Will be retained. Note that the read pulse φ _X(I) Immediately after termination
Later, the gate potential of driver transistor 152 is reset.
Reset pulse φ_R1Is applied.

The driver transistor 152 performs impedance conversion (current amplification). From the horizontal scanning circuit 145, pulses φ _H (2j) and φ _H (2
j + 1) and the like are applied to the selection switches 203 and 204 at a cycle of 2 pulses / pixel, and the OR circuit 213 outputs φ _H (2
j), φ _H (2j + 1) and other two-pulse sum signals φ _K (j) are applied to the horizontal selection transistor 153. Therefore, the non-signal voltage held by the hold capacitor 211 and the signal voltage held by the hold capacitor 212 are sequentially output to the horizontal signal line 154 in pairs. The signal line 154 outputs the signal OS via the next-stage source follower circuit. Signal OS
Since a signal voltage is output in pair with a no-signal voltage in pixel units even when ΔV _T which is the sum of the variation in the threshold value of each pixel and the variation in the threshold value of the driver transistor 152 is output, By taking the difference between the signal voltages, the variation ΔV _T is canceled, and a net signal V _O is obtained.

FIGS. 3 and 4 show circuit means for taking the difference between the no-signal voltage and the signal voltage for each pixel signal. FIG.
Then, the signal OS is guided to the second clamp circuit 21 and the subsequent first sample hold circuit 22, and the output V _O is obtained via the amplifier circuit 23. FIG. 2 shows the timing of the signal φ _HCP for controlling the operation timing of the clamp circuit and the timing of the signal φ _HSH for controlling the operation timing of the first sample and hold circuit. Thus, since the signal is clamped with no signal and sampled and held with the signal, the output V _O becomes a difference between the no-signal voltage and the signal voltage, that is, a net signal.

Here, since the clamp operation is performed during the non-signal readout period, the change in the potential level of each pixel to be clamped is small irrespective of the amount of light incident on the light receiving section.
Enables accurate clamping operation.

In FIG. 4, the signal OS is guided in parallel to the second sample-hold circuit 31 and the third sample-hold circuit 32, and the output V _O is obtained by taking the difference between the output signals by the differential amplifier circuit 33. obtain. Here, the signal φ _HCP for controlling the operation timing of the second sample and hold circuit
FIG. 2 shows the timing of the signal φ _HSH for controlling the operation timing of the third sample and hold circuit. From this, V _O is the difference between the sample and hold at the no signal level and the sample and hold at the signal level, and the net signal V _O
Becomes

In the above operation, the hold capacitance 211
And 212 (both common values for simplicity: a C ₁₎
Is compared with the gate capacitance of the driver transistor 152 (the value including the stray capacitance on the same connection and C _2), is required to be sufficiently large value. The reason will be described below. First, it is assumed that the gate capacitance of the driver transistor 152 is initially reset to 0 V potential. Then, when the potential V ₁ of the no-signal is applied through the switch 203 from hold capacitor 211, the gate potential V _G of the driver transistor 152 is expressed as follows.

V _G (1) = V ₁ / (1 + α), α = C ₂ / C _{1. After the} switch 203 is turned off (OFF), the switch 204 is turned on (ON) and the hold capacitance is set. 2
12, when the signal potential V ₂ is applied via the switch 204, the gate potential V
_G is as follows:

V _G (2) = (αV ₁ + (1 + α) V ₂ ) / (1 + α) ^2. Thus, the difference between the no-signal voltage and the signal voltage is as follows.

V _G (2) −V _G (1) = ((1 + α) V ₂ −V
_l ) / (1 + α) ^2. Therefore, (1 + α) ≒ 1, that is, α ≒ 0, must be satisfied in order to cancel the △ V _T that appears commonly in V ₁ and V ₂ . That is, C ₂ << C ₁ must be satisfied.

The signals held by the hold capacitors 211 and 212 provided for each of the vertical signal lines 140 are sequentially read out to the gate of the driver transistor 152 by sequentially turning on the switches 203 and 204. The gate is reset, but the signal amount of the hold capacitor is reduced to 1 / (1 + α) in one horizontal read operation. If α ≒ 0, ie, C ₂ << C ₁ , this value can be ignored. That is, since the pixel portion has a memory function, the same pixel information can be read many times.
For example, when α is set to 0.01 and the signal amount of the hold capacitance is read out four times in succession, the decrease in the signal amount is 4%, which is an acceptable range in normal imaging. For example, in order to perform image processing such as interpolation processing, it is necessary to read the signal of the same pixel a plurality of times, so that this memory function can be effectively used.

Next, even if C ₂ << C ₁ is not satisfied,
A method of canceling the variation ΔV _T that appears commonly in V ₁ and V ₂ will be described below.

FIG. 5 shows another embodiment of the amplification type solid-state imaging device according to the present invention. The device of this embodiment is different from the device of FIG. 1 in that the device further includes a transistor 206 to reset the gate potential of the driver transistor 152. Thereby, the hold capacitors 211 and 2
Before reading no signal and signal as a voltage from 12 to the gate, the gate is set to the voltage V
_The following operation is performed in addition to the operation of resetting to _CP . That is,
After reading a no-signal from the hold capacitor 211 to the gate and before reading a signal from the hold capacitor 212 to the gate as a voltage, the gate is reset to the voltage V _CP by using the transistor 206. This operation needs to be performed for each driver transistor 152, and the gate of the transistor 206 is driven and controlled by a signal from the horizontal scanning circuit 145.

The operation will be described with reference to the timing chart of FIG. Note that, in the figure, the same reference numerals are given to the signals that perform the same operations as those shown in FIG.

First, the switch 203 is turned on by the clock φH (3j) output from the horizontal scanning circuit 145, and the no-signal voltage of the pixel held in the hold capacitor 211 is applied to the gate of the drive transistor 152. Is done. Next, the switch 206 is turned on by the clock φH (3j + 1) output from the horizontal scanning circuit 145, and the gate of the driver transistor 152
Reset to _CP . Thereafter, the switch 204 is turned on (on) by the clock φH (3j + 2) output from the horizontal scanning circuit 145, and the signal voltage of the pixel held in the hold capacitor 212 is applied to the gate of the driver transistor 152. At this time, the drive pulses of the switches 203, 206 and 204 are combined by the OR circuit 215 to become φ _K (j), and the horizontal selection transistor 153 is conductive (on) during the non-signal readout period, the reset period, and the signal readout period. Becomes By the above operation, the non-signal voltage, reset, and signal voltage of the pixel are read out to the horizontal signal line 154 as a pair.

In the above operation, the signal potential V ₂ is applied from the hold capacitor 212 via the switch 204 even before the no-signal potential V ₁ is applied from the hold capacitor 211 via the switch 203. Prior to this, the gate capacitance of the driver transistor 152 has been reset to V _CP (hereinafter, V _CP = 0 V for simplicity). Therefore, the gate potential V _G of the driver transistor 152,
V when the potential V ₁ is applied from the hold capacitor 211
_G (1) and V _G (2) when the potential V ₂ is applied from the hold capacitor 212 are as follows.

V _G (1) = V ₁ / (1 + α), V _G (2) = V ₂ / (1 + α). Thus, the difference between the no-signal voltage and the signal voltage is as follows.

V _G (2) −V _G (1) = (V ₂ −V ₁ ) / (1 + α). Therefore, irrespective of the value of α, ΔV _T commonly appearing in V ₁ and V ₂ is canceled. Will be.

As described above, between the read operation of the no-signal voltage and the signal read operation, the driver transistor 152
Is reset, so that more accurate signal processing can be performed.

After the signal voltage from the amplification type photoelectric conversion element is held in the first hold capacitor, the non-signal voltage is held in the second hold capacitor, and the signal voltage is held in the first hold capacitor and the second hold capacitor. It is preferable from the viewpoint of signal processing accuracy that the signal voltage and the non-signal voltage are output as a set of independent voltages to the common signal line via the impedance conversion circuit in the order of the non-signal voltage and the signal voltage. However, the present invention is not limited to this.

[0059]

As described in detail above, according to the present invention,
In an amplification type solid-state imaging device employing an impedance conversion (current amplification) transistor for reading a signal from a vertical signal line to a horizontal signal line, the no-signal voltage and the signal voltage from the amplification-type photoelectric conversion element correspond to the first hold capacitance and the signal voltage. Each of the signals is held in the second hold capacitor, and is transmitted as an independent set of signals to the same common signal line via an impedance conversion circuit. In addition to canceling the coarse FPN caused by the variation of the threshold value between the horizontal read means and the vertical FPN caused by the non-uniformity of the horizontal read means provided for each vertical signal line, the horizontal read means is not only canceled. The shading due to the non-uniformity of the hold time is also suppressed, and a video signal of extremely high image quality can be obtained.

In addition, a clamp,
A transistor for resetting the level of the vertical signal line is not required as compared with an image pickup apparatus of a sample-and-hold type. In addition, a blank signal voltage and a signal voltage are output as a pair for each pixel signal, and the same horizontal column pixel signal can be read multiple times while suppressing FPN and shading. An imaging device can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of an amplification type solid-state imaging device according to the present invention.

FIG. 2 is a timing chart showing the timing of each signal in the device of FIG.

FIG. 3 is a block diagram showing an example of a circuit for processing an output of the apparatus of FIG. 1;

FIG. 4 is a block diagram showing another example of a circuit for processing the output of the device of FIG. 1;

FIG. 5 is a circuit diagram showing another embodiment of the amplification type solid-state imaging device of the present invention.

6 is a timing chart showing the timing of each signal in the device of FIG.

FIG. 7 is a circuit diagram illustrating a conventional horizontal pixel.

FIG. 8 is a circuit diagram illustrating a conventional vertical pixel.

FIG. 9 is a circuit diagram showing another example of a conventional pixel.

FIG. 10 is a block diagram schematically showing the circuits of FIGS. 7 to 9;

FIG. 11 is a circuit diagram showing an example of a conventional amplification type solid-state imaging device.

12 is a timing chart showing the timing of each signal in the device of FIG.

FIG. 13 is a circuit diagram showing another example of a conventional amplification type solid-state imaging device.

FIG. 14 is a circuit diagram showing still another example of the conventional amplification type solid-state imaging device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 signal detection unit 1a photodiode 1b driving MOS-FET 1c load MOS-FET 2a, 2b pair of sample MOS-FETs 4a, 4b pair of V / I conversion MOS-FETs 5a, 5b pair of access MOS -FETs 6a, 6b A pair of setting MOS-FETs 8 Shift register 9 Bright signal common signal line 10 Dark signal common signal line 11 Setting power supply 12 Clock pulse input terminal 13 Start pulse input terminal 14 Transmission between chips Pulse output terminal 131 photoelectric conversion unit 132 amplification unit 140 vertical signal line 141 first vertical scanning circuit 142 second vertical scanning circuit 145 horizontal scanning circuit 152 driver transistor 153 horizontal selection transistor 154 common signal line 155, 156, 157 transistor 201, 02,203,204 selection switch 205, 206, reset switch 211 and 212 hold capacity 213 OR circuit

Claims (11)

[Claims] 1. A plurality of amplifying photoelectric conversion elements, a plurality of vertical signal lines to which the plurality of amplifying photoelectric conversion elements are respectively connected, an impedance conversion circuit, A common signal line to be read through the read switch circuit; and first and second hold capacitors for holding a voltage of the vertical signal line. An amplification type solid-state imaging device, wherein voltages of one hold capacitor and the second hold capacitor are output to the common signal line via the impedance conversion circuit as a set of independent voltages. 2. The first and second hold capacitors are connected to the vertical signal line via first and second switching elements, respectively, and the first hold capacitor and an input terminal of the impedance conversion circuit are connected to the vertical signal line. And a fourth switching element connected to the second hold capacitor and the input terminal of the impedance conversion circuit, wherein the read switch circuit is in a conductive state. The third and fourth switching elements are turned on in a period independent of each other, and the voltages of the first hold capacitor and the second hold capacitor are set as independent sets of voltages via the impedance conversion circuit. 2. The amplification type solid-state imaging device according to claim 1, wherein the signal is output to a common signal line. 3. A signal reading period for reading a voltage corresponding to a signal charge of the amplification type photoelectric conversion element from the amplification type photoelectric conversion element, a discharge period for discharging the signal charge of the amplification type photoelectric conversion element, and There is a non-signal readout period for reading out a voltage corresponding to a no-signal after the discharge period, and the second switching element is in a conductive state during the signal readout period, and the voltage from the amplification type photoelectric conversion element is The second switching capacitor is held as a signal voltage, the first switching element is in a conductive state during the no-signal reading period, and the voltage from the amplifying photoelectric conversion element is held as a no-signal voltage in the first holding capacitor. Done,
The amplification type solid-state imaging device according to claim 2. 4. An order in which the voltage from the amplification type photoelectric conversion element is held in the first hold capacitor and the second hold capacitor, and the order in which the voltage held in the first hold capacitor and the second hold capacitor is changed. The amplification type solid-state imaging device according to any one of claims 1 to 3, wherein the order of outputting the independent voltage to the common signal line via the impedance conversion circuit is different from each other. 5. A period in which the third switching element conducts and a period in which the fourth switching element conducts,
4. The amplifying solid-state imaging device according to claim 2, wherein a period in which the third switching element is continuous without overlapping each other is earlier than a period in which the fourth switching element is conductive. 6. A reset power supply connected to the input terminal of the impedance conversion circuit via a fifth switching element, the reset power supply being connected before the third switching element and the fourth switching element are turned on. The amplifying solid-state imaging device according to claim 2, wherein the fifth switching element is turned on, and a reference potential is applied to the input terminal of the impedance conversion circuit. 7. A sixth switching element connected in parallel with the fifth switching element between the input terminal of the impedance conversion circuit and the reset power supply, wherein the third switching element is in a conductive state. Between a certain period and a period when the fourth switching element is in a conductive state,
7. The amplifying solid-state imaging device according to claim 6, wherein the sixth switching element conducts. 8. The semiconductor device further comprising first clamp means and a first sample hold circuit connected to the common signal line, wherein the first clamp means is configured to control the voltage of the set of voltages from the common signal line. Clamping the voltage of the first hold capacitor; the first sample and hold circuit samples and holds the voltage of the second hold capacitor, whereby the difference between the voltage of the first hold capacitor and the voltage of the second hold capacitor is determined. And outputting a voltage corresponding to
8. The amplification type solid-state imaging device according to any one of items 1 to 7. 9. The semiconductor device further comprises first and second sample-and-hold circuits connected to the common signal line, and an arithmetic circuit, wherein the first sample-and-hold circuit detects the voltage of the set of voltages from the common signal line. The second sample-and-hold circuit samples and holds the voltage of the first hold capacitor, the second sample-hold circuit samples and holds the voltage of the second hold capacitor, and the arithmetic circuit is held by the first and second sample-hold circuits And outputting the difference between the applied voltages.
8. The amplification type solid-state imaging device according to any one of items 1 to 7. 10. The plurality of amplifying photoelectric conversion elements are arranged in a matrix, and output voltages of the first hold capacitor and the second hold capacitor as independent sets of voltages to the common signal line. The amplifying solid-state imaging device according to any one of claims 1 to 9, wherein the operation of performing is performed for each of the plurality of amplifying photoelectric conversion elements arranged in a row direction and is repeated for each row. 11. The first hold capacitor and the second hold capacitor.
The amplification type solid-state imaging device according to claim 10, wherein the operation of outputting the voltage of the hold capacitance as a set of independent voltages to the common signal line is repeated a plurality of times for each row.