JPH09284658A - Solid-state image pickup element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To remove the fixed pattern noise of a pixel and also the fixed pattern noise of shading which occurs in a horizontal scanning circuit. SOLUTION: This solid-state image pickup element is provided with a plurality of pixels arrayed in a matrix-shape, longitudinal signal lines 35 where the pixels 32 of the same column are commonly connected and a horizontal scanning circuit 53 outputting a signal from the pixels 32 which are outputted from the longitudinal signal lines to an order output terminal at every row. One longitudinal signal line 35 is connected to a first signal holding circuit 51 holding the first signal from the pixels 32 before pixel resetting in the horizontal scanning line 53 and a second signal holding circuit 52 holding the second signal from the pixels 32 after pixel resetting and difference between the first and the second signals is outputted from an output part which is connected to a horizontal signal line 40. In this case, the layout of the first signal holding circuit 51 and the layout of the second signal holding circuit 52 are formed to be symmetrical about the horizontal signal line 40 and a CDS circuit 47 executing the correlative double sampling of the first and the second signals is connected to the output circuit 46 of the horizontal signal line 40 in configuration.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an amplification type solid-state imaging device. More specifically, it relates to removing fixed pattern noise of pixels and shading fixed pattern noise generated in a horizontal scanning circuit.

[0002]

2. Description of the Related Art In recent years, in accordance with a demand for higher resolution of a solid-state imaging device, an amplification type solid-state imaging device which has no smear and can realize fine pixels has been developed instead of a CCD solid-state imaging device. In this amplification type solid-state imaging device, in order to give each pixel an amplification effect of an optical signal, a pixel is formed by an active element (so-called MOS type transistor) having a MOS structure or the like, and charges accumulated in the pixel by photoelectric conversion are stored. It is configured to read the signal as a current modulation of the transistor.

As described above, in the amplification type solid-state image pickup device, since the pixels are formed by the active elements (MOS type transistors), the variations of the active elements are directly added to the video signal. Since this variation has a fixed value for each pixel, it appears as fixed pattern noise (hereinafter referred to as FPN) in the captured image.

This FPN has a property that not the variation in the sensitivity to the incident light but the variation in the threshold value of the pixel is added to the signal amount according to the incident light.

[0005]

[Problems to be Solved by the Invention]
Or the amplified solid-state image according to the comparative example of FIG.
This will be described using the element 1. In FIG. 8, 2 is a unit pixel
The light receiving element that constitutes the (cell), the pixel MOS transistor in this example.
A plurality of pixel MOS transistors 2 are arranged in a row.
It is arranged in rows. 4 is a pixel MOS transistor for each row
A vertical selection line connected to the control electrode of the switch
3 is a vertical scanning signal to the vertical selection line 4, that is, a vertical scanning pulse
φV [φV ₁・ ・ ・ ΦV_m, ΦV_{m + 1},, ...]
Vertical scanning circuit. Of pixel MOS transistor 2
One main electrode, that is, the source, is connected to the vertical signal line 5 for each column.
The other main electrode, that is, its drain is connected to the power source V._DContact
Continued.

A first load capacitance element 8 holding a signal voltage (charge) is connected to each vertical signal line 5 via a first operation MOS switch 7, and the connection point thereof is a first horizontal MO.
It is connected to the first horizontal signal line 10 via the S switch 9. Further, the second operation M is applied to the vertical line signal 5 of the same column.
The second load capacitance element 8'is connected via the OS switch 7 ', and its connection point is connected to the second horizontal signal line 11 via the second horizontal MOS switch 9'. Each load capacitance element 8, 8 'is connected between the vertical signal line 5 and the ground potential.

The first operation pulse φ _OPS is applied to the gate of the first operation MOS switch 7, and the second operation MOS switch 7 is operated.
A second operation pulse φ _OPN is applied to the switch 7 '. First horizontal MOS switch 9 and second horizontal MOS
The gates of the switches 9'are commonly connected to the horizontal shift register 12, and the horizontal shift register 12 sequentially supplies the horizontal MOS switches 9 and 9'with horizontal scanning signals, that is, horizontal scanning pulses φH [φH ₁ , ... φH _n. , ΦH _{n + 1} ,
...] is supplied.

Although not shown, in order to reset the load capacitance elements 9 and 9'and the vertical signal line 5 to the initial voltage, the vertical signal line 5 on the first operation MOS switch 7 side of the load capacitance element 8 is reset. Reset MOS switch is connected. That is, the source of this reset MOS switch is connected to the vertical signal line 5, and its reset bias voltage V
_RB is applied, and the reset pulse φ _VRST is supplied to its gate.

By the first operation MOS switch 7, the first load capacitance element 8 and the first horizontal MOS switch 9,
A first signal holding circuit 19 for holding a signal voltage (charge) of a pixel before pixel reset, which will be described later, is configured, and includes a second operation MOS switch 7 ', a second load capacitance element 8', and a second load capacitance element 8 '.
The horizontal MOS switch 9'constitutes a second signal holding circuit 20 for holding a signal from a pixel after pixel reset, which will be described later, a so-called noise signal. Furthermore, the first
And second signal holding circuits 19 and 20, and first and second signal holding circuits
The horizontal signal lines 10 and 11 and the horizontal shift register 12 constitute a so-called horizontal scanning circuit 21.

At the output ends of the first and second horizontal signal lines 10 and 11, there are provided an operational amplifier 13 using an inverting amplifier, for example, a differential amplifier, a detection capacitance element 14, and a reset switch 15. The charge detection circuits 16 and 16 'are connected. That is, the horizontal signal lines 10 and 11 are connected to the inverting input terminals of the operational amplifiers 13 of the respective charge detection circuits 16 and 16 ', and the predetermined bias voltage V _B is applied to the non-inverting input terminals of the horizontal signal lines 10 and 11. The bias voltage V _B is for determining the potentials of the horizontal signal lines 10 and 11. In parallel with the operational amplifier 13, that is, between the inverting input terminal and the output terminal of the operational amplifier 13, the detection capacitance element 14 is provided.
Is connected to the detection capacitance element 14, and the horizontal signal line 10,
11 and a reset MOS for resetting the detection capacitance element 14
The switch 15 is connected in parallel. A reset pulse φ _R is applied to the gate of the reset MOS switch 15.

Then, the first charge detection circuit 16 and the second charge detection circuit 16
The respective output ends of the charge detection circuit 16 ', that is, the signal output end t _S and the noise output end t _N are connected to the differential amplifier 17 for subtraction processing.

In the amplification type solid-state image pickup device 1 of FIG. 8, a signal output from the main electrode of the pixel MOS transistor 2 in accordance with the signal charge accumulated by the incident light (that is, the signal before pixel reset = photoelectric conversion). (Signal + fixed pattern noise of pixel) is sent from the vertical signal line 5 to the first load capacitance element 8 via the first operation MOS switch 7 and is retained (stored). Further, similarly, after resetting the same pixel MOS transistor 2, a signal that emerges from the main electrode of the pixel MOS transistor 2 (that is, a signal after pixel reset =
Only the fixed pattern noise of the pixel) is sent from the vertical signal line 5 to the second load capacitance element 8'through the second operation MOS switch 7'and held (stored).

The signal before the pixel reset and the signal after the pixel reset held in the first load capacitance element 8 and the second load capacitance element 8 ', respectively, are the first horizontal MOS switch 9 and the second horizontal MOS switch 9.
By turning on the horizontal MOS switch 9'of the above, the first charge detection circuit 16 and the second charge detection circuit 1 are passed through the first horizontal signal line 10 and the second horizontal signal line 11, respectively.
6'is output to the output terminals t _S and t _N , and
The FPN is removed by the subtraction processing of the differential amplifier 17, and the output is obtained from the output terminal t _out .

However, in the amplification type solid-state image pickup device 1 having such a structure, two output circuits for outputting signals before and after pixel reset, that is, two charge detection circuits are required, and the pixel MOS transistor is required. Although the FPN generated from 2 can be removed, when a shading of different magnitude occurs in the two signals due to a slight difference in the layout of the first and second signal holding circuits 19 and 20,
There is a problem that shading remains without being removed even after the subtraction processing by the differential amplifier 17.

That is, more specifically, the first operation MOS switch 7, the first load capacitance element 8 and the first horizontal MOS switch 9 which handle the signal before the pixel reset, and the first operation MOS switch which handles the signal after the pixel reset. The second operation MOS switch 7 ′, the second load capacitance element 8 ′, and the second horizontal MOS switch 9 ′ have different layout locations from each other, and the different layouts make it necessary for each operation pulse φ. _OPS and φ _OPN , horizontal scan pulse φH _n and φH
_{Since n + 1} cannot be said to be completely equivalent, shading that tends to occur in the case of an amplification type solid-state imaging device with a large number of pixels is
As shown in FIG. 9, the difference in shading between the signal obtained from the output end t _S (signal by photoelectric conversion + pixel fixed pattern noise) and the signal obtained from the output end t _N (only pixel fixed pattern noise) is Shading is left in the output signal of the output terminal t _out that cancels the FPN.

As described above, in the above-described comparative example, the signal before the pixel reset and the signal after the pixel reset are output from different circuits, and their outputs are subjected to subtraction processing to perform the FPN of the pixel.
However, in the method of eliminating the above, there is a problem that the shading generated in the horizontal scanning circuit remains in the output in which the FPN is canceled.

In view of the above points, the present invention provides an amplification type solid-state image pickup device capable of removing fixed pattern noise of pixels and shading generated in a horizontal scanning circuit.

[0018]

An amplification type solid-state imaging device according to the present invention has a layout of a first signal holding circuit for holding a signal before pixel reset in a horizontal scanning circuit and a signal after pixel reset. The layout of the second signal holding circuit is such that it is formed on both sides of the horizontal signal line.

In this structure, the layout of the first signal holding circuit and the layout of the second signal holding circuit are formed on both sides of the horizontal signal line so that the layout of both circuits is symmetrical. Then, the difference between the first signal obtained through the first signal holding circuit and the second signal obtained through the second signal holding circuit yields an output signal from which the fixed pattern noise of the pixel and the fixed pattern noise of shading are removed. To be

The amplification type solid-state image pickup device according to the present invention includes a first signal holding circuit for holding the first signal from the pixel before reset centering on one horizontal signal line in the horizontal scanning circuit. The layout and the layout of the second signal holding circuit that holds the second signal from the pixel after reset are formed line-symmetrically, and the correlated double sampling circuit is connected to the output side of the horizontal signal line.

In this configuration, the two signals output from the output circuit through the same horizontal signal line, that is, the signal before the pixel reset and the signal after the pixel reset are passed through the correlated double sampling circuit, and An output signal from which fixed pattern noise and shading generated in the horizontal scanning circuit are removed can be obtained.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION The amplification type solid-state imaging device according to the present invention outputs a plurality of pixels arranged in a matrix, a vertical signal line in which pixels in the same column are commonly connected, and a vertical signal line. A horizontal scanning circuit that sequentially outputs signals from pixels to the output terminals row by row, and one vertical signal line that holds a first signal from a pixel before pixel reset in the horizontal scanning circuit The signal holding circuit and the second signal holding circuit that holds the second signal from the pixel after pixel reset are connected, and the difference between the first and second signals is output from the output unit connected to the horizontal signal line. Which is an amplification type solid-state image sensor,
The layout of the first signal holding circuit and the layout of the second signal holding circuit are formed on both sides of the horizontal signal line.

According to the present invention, in the amplification type solid-state imaging device, the layout of the first signal holding circuit and the layout of the second signal holding circuit are formed line-symmetrically with respect to the horizontal signal line.

According to the present invention, in the amplification type solid-state image pickup device, a circuit of one horizontal signal line is connected to a correlated double sampling circuit for performing correlated double sampling of the first signal and the second signal. To do.

According to the present invention, in the amplification type solid-state image pickup device, the length of the wiring connected to the switch means in the first signal holding circuit from the drive circuit and the length connected to the switch means in the second signal holding circuit. The length of the wiring from the drive circuit is set to be equal to each other.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of an amplification type solid state image pickup device according to the present invention. This example is an XY address type solid-state image pickup device having so-called fixed pattern noise (FPN), and variations in individual pixels and lateral nonuniformity of the horizontal scanning circuit are the main factors of the image pickup device. The FPN and shading are removed by sequentially outputting the outputs before and after resetting the pixels to the solid-state imaging device forming the FPN and performing correlated double sampling.

That is, in FIG. 1, reference numeral 32 denotes a pixel transistor which constitutes a unit pixel (cell), for example, a pixel MOS transistor, and a plurality of pixel MOS transistors 32.
Are arranged in a matrix. Reference numeral 33 is a vertical scanning circuit composed of a shift register or the like for controlling and selecting the pixel MOS transistors 32 in the same row, and 34 is vertical selection in which the control electrodes, that is, gates of the pixel MOS transistors 32 in the same row are connected in common. Shows a line. A vertical selection pulse φV [φV is sequentially supplied to the vertical selection line 34 of each row from the vertical scanning circuit 33.
₁ , ... φV _m , φV _{m + 1} , ...] are applied.

One of the main electrodes, for example, the source of the pixel MOS transistors 32 in the same column is connected to the vertical signal line 35, and the other main electrode, for example, the drain thereof is connected to the power supply line 36 to which the power supply V _D is supplied. .

The vertical signal line 35 has a signal (photoelectric signal) corresponding to the signal charge accumulated in the pixel MOS transistor before pixel reset via the first operation switch (eg, MOS switch) 37 controlled by the operation pulse φ _OPS. The first to hold the signal due to the conversion + the fixed pattern noise of the pixel)
Load capacitance element 38 is connected. That is, the first load capacitance element 38 is connected between the vertical signal line 35 and the first potential in this example, the ground potential. In addition, the first load capacitance element 3
A first horizontal switch (for example, MO) which is controlled by a horizontal shift register 42 between 8 and one horizontal signal line 40.
S switch) 39 is connected.

Further, the same vertical signal line 35 is subjected to a second operation switch (for example, a MOS switch) 37 'controlled by an operation pulse φ _OPN to _output a signal having no signal charge (pixel fixed pattern) after pixel reset. A second load capacitance element 38 'holding only noise) is connected. That is, the second load capacitance element 38 is also connected between the vertical signal line 35 and the ground potential. A second horizontal switch (eg, MOS switch) 39 'controlled by the horizontal shift register 42 is connected between the second load capacitance element 38' and the horizontal signal line 40.

The gate of the first horizontal switch 39 is sequentially fed with the horizontal scanning pulse φHS from the horizontal shift register 42.
[ΦHS ₁ , ... φHS _n , φHS _{n + 1} , ...] Is applied, and the horizontal scanning pulse φHN [φH from the horizontal shift register 42 is sequentially applied to the gate of the second horizontal switch 39 ′.
_{N 1, ‥‥ φHN n, φHN} n + 1, ‥‥ ] is applied.

The first operation switch 37, the first load capacitance element 38, and the first horizontal switch 39 constitute a first signal holding circuit 51 for holding the signal of the pixel MOS transistor before pixel reset, The above-mentioned second operation switch 37 ', second load capacitance element 38' and second
Pixel M after pixel reset by horizontal switch 39 'of
A second signal holding circuit 52 that holds the signal of the OS transistor is formed. Further, the first and second signal holding circuits 51 and 52, the horizontal signal line 40, and the horizontal shift register 42 constitute a so-called horizontal scanning circuit 53.

The layout of the first operation switch 37, the first load capacitance element 38, and the first horizontal switch 39 which form the first signal holding circuit 51, and the second layout which forms the second signal holding circuit 52. The layout of the second operation switch 37 ', the second load capacitance element 38', and the second horizontal switch 39 'is formed line-symmetrically on the upper and lower sides with one horizontal signal line 40 as the center. It

Although not shown, in order to reset the load capacitance elements 38 and 38 'and the vertical signal line 35 to the initial voltage, the vertical signal line 35 on the first operation switch 37 side of the load capacitance element 38 is reset. Reset switch (eg MOS
Switch) is connected. That is, the source of the reset switch is connected to the vertical signal line 35, the drain thereof is supplied with the reset bias voltage V _RB , and the gate thereof is supplied with the reset pulse φ _VRST .

An output circuit, that is, an operational amplifier 43 using an inverting amplifier such as a differential amplifier, a detection capacitor element 44, and a reset switch 45 are provided at the output end of one horizontal signal line 40. A correlated double sampling (CDS) circuit 4 which is connected to the charge detection circuit 46 and further performs correlated double sampling at the output end of the charge detection circuit 46.
7 is connected.

In the charge detection circuit 46, the operational amplifier 4 is provided.
The horizontal signal line 40 is connected to the inverting input terminal of No. 3, and a predetermined bias voltage V _B is applied to its non-inverting input terminal.
A detection capacitor element 44 and a reset switch (for example, a reset MOS switch) 45 are connected in parallel to the operational amplifier 43, that is, between the inverting input terminal and the output terminal of the operational amplifier 43. The reset switch 45 resets the horizontal signal line 40 and the detection capacitance element 44, and a reset pulse φ _R is applied to its gate.

FIG. 3 is a sectional view showing the semiconductor structure of the unit pixel (ie, pixel MOS transistor) 32. In FIG. 3, reference numeral 71 is a semiconductor substrate of the first conductivity type, for example, p-type, 72 is a photoelectrically converted signal charge, and in this example, a hole 7
A p-type well region for accumulating 0, 73 is a second conductivity type, that is, n
This is the well region of the mold. An n-type source region 74 and a drain region 75 are formed in the p-type well region 72, and on the p-type well region 72 between the regions 74 and 75, for example, a thin film of a thin film capable of transmitting light via the gate insulating film 77. An annular gate electrode 76 made of crystalline silicon is formed. The holes 70 accumulated by photoelectric conversion in the p-type well region 72 immediately below the gate electrode 76 control the channel current (drain current) during the read operation, and the amount of change in the channel current becomes a signal output.

Next, the operation of the above amplification type solid-state image pickup device 31 will be described.

Output from the vertical scanning circuit 33 to the vertical selection line 34.
Applied vertical selection pulse φV [φV ₁・ ・ ・ ΦV_m, Φ
V_{m + 1},,,,,], by the selected pixel in the same row
The MOS transistor 32 is in an operating state (so-called reading
State). As a result, the pixel MOS transistor 3
Depending on the signal charge accumulated by photoelectric conversion from the two main electrodes
Pixel signals (that is, signals before pixel reset) are vertical signal lines
35, and the pixel signal is output to the first operation switch 3
By the operation of shutting off → conducting → shutting off 7, the first load capacitance element
It is held by the child 38. In addition, the pixel MOS transistors in the same column
After resetting the signal charge accumulated in the transistor 32,
Similarly, a signal from the main electrode of the pixel MOS transistor 32
Pixel signals without charge (that is, signals after pixel reset)
It is output to the direct signal line 35, and the pixel signal thereof is output in the second operation line.
The operation of shutting off the switch 37 '→ conducting → shutting off the second
It is held by the load capacitance element 38 '.

The first load capacitance element 38, which holds the signal before the pixel reset, is connected to the horizontal signal line 40.
When the horizontal switch 39 is turned on by the horizontal scanning pulse φHS from the horizontal shift register 42, the signal before pixel reset is output as the signal charge to the horizontal signal line 40 that has been reset in advance, and the charge detection circuit 4
At 6, the charge is demodulated to a signal voltage and output as a signal voltage to the output terminal t ₀ .

Further, after the horizontal signal line 40 is reset again by the reset switch 45 of the charge detection circuit 46, the second load capacitance element 38 'in which the signal after pixel reset is held is similarly the horizontal signal line. The second horizontal switch 39 ′ connected to 40 is turned on by the horizontal scanning pulse φHN from the horizontal shift register 42, so that the signal after pixel reset is output to the horizontal signal line 40 as a signal charge to detect the charge. The circuit 46 demodulates the charge into a signal voltage and outputs it as a signal voltage to the output terminal t ₀ .

In this way, the signal voltages before the pixel reset and after the pixel reset, which are sequentially output to the output terminal t ₀ , are transferred to the CD.
By performing correlated double sampling by the S circuit 47,
The FPN (fixed pattern noise) of the pixel and the fixed pattern noise of shading generated in the horizontal scanning circuit 53 are removed.

Details of the CDS circuit 47 shown in FIG. 1 are shown in FIG.
Shown in The CDS circuit 47 includes a first sample and hold circuit 55 of one system, second and third sample and hold circuits 56 and 57 of another system, and a differential amplifier 58. The output terminal of the sample hold circuit 55 is connected to the non-inverting input terminal of the differential amplifier 58, and the second and third sample hold circuits 56 and 5 of another system are connected.
7 are connected in series, and the output end of the third sample hold circuit 57 in the subsequent stage is connected to the inverting input terminal of the differential amplifier 58.

Each sample hold circuit 55, 56, 57
Are the MOS switch 61 and the capacitive element 6 for the memory, respectively.
2 and a source follower circuit 65 including a MOS transistor 63 and a load resistor 64. And
MOS switch 61 of the first sample hold circuit 55
Is controlled by the first sample pulse φSHS, the MOS switch 61 of the second sample hold circuit 56 is controlled by the second sample pulse φSHN, and the MOS switch 61 of the third sample hold circuit 57 is controlled by the first sample pulse φSHS. It is controlled by φSHS.

In the CDS circuit 47, the charge detection circuit 4
Two different signals output from the same terminal 6 having different phases, that is, a signal before and after pixel reset, respectively, are sample and hold circuits of different systems, that is, a sample and hold circuit 55 of one system and a sample and hold circuit of another system. 56,57
After sampling at, by passing it through the differential amplifier 58,
The difference between the signals before and after pixel reset is output. That is, the signal before pixel reset is sampled by the sample pulse φSHS in the first sample hold circuit 55, and enters the non-inverting input (+) of the differential amplifier 58,
The signal after the pixel reset is sampled by the sample pulse φSHN in the second sample and hold circuit 56 in the previous stage, and in order to match the phase with the signal before the pixel reset, the third sample and hold circuit 5 in the subsequent stage is again provided.
At 7, the sampled pulse φSHS is sampled and enters the inverting input (−) of the differential amplifier 58, and the differential signal before and after pixel reset is obtained from the output terminal t _out of the differential amplifier 58.

FIG. 4 shows drive timings and output waveforms in the amplification type solid-state imaging device of this embodiment. In a certain horizontal blanking period HBL (on the left side of FIG. 4), the vertical selection pulse φV _m output to select the m-th row from the vertical scanning circuit 42 in FIG. 1 to the vertical selection line 34 changes to a high voltage, The pixel MOS transistor 32 in the m-th row is selected.

As a result, the pixel m of the selected m-th row is
Since the S transistor 32 outputs a signal before pixel reset (Sig signal) to the vertical signal line 35, the operation pulse φ _OPS is given to the control electrode of the first operation switch 37 to the load capacitance element 38 before pixel reset. Hold the signal.

Thereafter, in order to reset the pixel MOS transistor 32, in this amplification type solid-state image pickup device, a pixel reset pulse φV _sub which stands in the negative direction is applied to the substrate, and the signal of the selected pixel MOS transistor 32 in the m-th row is applied. Reset the charge.

After the pixel MOS transistor 32 is reset, the signal after the pixel reset (Noise signal) appearing on the vertical signal line 35 is changed to the second signal in the same manner as the signal before the reset.
The operation pulse φ _OPN is applied to the control electrode of the operation switch 37 ′ and held in the second load capacitance element 38 ′.

By this series of operations, the pixel MO of the m-th row is
The signals before and after the resetting of the S-transistor 32 are held in the first load capacitance element 38 and the second load capacitance element 38 ', respectively, so that they are output from the horizontal shift register 42 in the horizontal video period T _A. Horizontal scanning pulse φHS [φ
HS ₁ , ... φHS _n , φHS _{n + 1} ,…] and φHN
[ΦHN ₁ , ... φHN _n , φHN _{n + 1} , ...] Are alternately applied with a reset pulse φ _R for resetting the horizontal signal line 40 interposed therebetween, and the horizontal switches 39 and 39 ′ are sequentially turned on. Accordingly, the signal after the pixel reset (Noise signal) and the signal before the pixel reset (S
ig signal) is alternately output.

C, which is controlled by sample pulses φSHS and φSHN for correlated double sampling of the alternately output pixel reset signal and the pixel reset signal obtained here.
By supplying the signal to the DS circuit 47, the difference between the signals before and after the pixel reset is output from the output terminal t _out of the CDS circuit 47.

As a result, a signal from which the fixed pattern noise of pixels and the fixed pattern noise of shading generated in the horizontal scanning circuit or the like are removed is output from the output terminal t _out of the amplification type solid-state image pickup device of this embodiment.

The principle of removing shading generated in the FPN of pixels and the horizontal scanning circuit according to the present embodiment is as follows.
It is described by the following formula. The signal level before the horizontal n-th pixel reset is S ^S _n , the signal level after the pixel reset is S ^N _n , the pixel signal according to photoelectric conversion is Sig, the fixed pattern noise of the pixel is FPN, the number of horizontal pixels of the image sensor If the horizontal shading of N, 1H (one horizontal scanning period) is linear and the amount is ΔS _h ,

[0055]

[Equation 1]

The output OUT of the CDS circuit 47 represented by
Is

[0057]

[Equation 2]

Therefore, the shading component other than the pixel signal corresponding to the photoelectric conversion is small because it is divided by twice the number of pixels (2N), and if the shading is linear in the horizontal direction, which shading component is the pixel? This is an offset amount common to signals, and linear shading is completely removed.

According to the above-described embodiment, the layout of the first signal holding circuit 51 which holds the signal before the pixel reset on both sides of the one horizontal signal line 40, sandwiching the horizontal signal line 40 at the center,
That is, the first operation switch 37, the first load capacitance element 38
And the layout of the first horizontal switch and the layout of the second signal holding circuit 52 that holds the signal after the pixel reset, that is, the second operation switch 37 ', the second load capacitance element 38', and the second horizontal switch. The layout of the switch 39 'is formed line-symmetrically to each other, and the CDS circuit 47 is connected to the output end of the charge detection circuit 46 of the horizontal signal line 40, whereby fixed pattern noise generated in the pixel and It is possible to effectively remove the fixed pattern noise of shading generated in the horizontal scanning circuit or the like.

Further, in the comparative example, since the signals before and after the pixel reset are output from the separate charge detection circuits 16 and 16 'and the subtraction processing is performed, the charge detection circuits 16 and 1 are set.
While a total of three differential amplifiers including the differential amplifier 13 in 6'and the differential amplifier 17 for the subtraction processing are required,
In the present embodiment, only one differential amplifier 45 in the charge detection circuit 46 and two differential amplifiers 58 in the CDS circuit 47 are required, and one differential amplifier can be omitted. It can be simplified.

By providing the CDS circuit 47, reduction random noise is removed, and as a result, the S / N of the signal is reduced.
The ratio improves.

In the comparative example, the gain is corrected and subtracted in order to match the gains of the noise signal and the pixel signal.
In this embodiment, since only one horizontal signal line is required, gain correction is unnecessary.

FIG. 5 shows another embodiment of the present invention. This embodiment is a case where the invention is applied to an amplification type solid-state image pickup device of a field readout system. FIG. 5 shows the vertical signal line 3 in the nth column.
Although only the horizontal scanning circuit section connected to FIG. 5 is shown, the other configuration, that is, the configuration and connection relationship of the pixel MOS transistor 32, the vertical scanning circuit 33, and the like are the same as those in FIG.

The embodiment shown in FIG. 5 has two horizontal scanning circuit components for reading out a mixed signal of two vertical pixels on each vertical signal line 35.
Group, that is, the first and second horizontal scanning circuit constituent parts 81 [8
1a, 81b] are connected in parallel to the horizontal signal line 40, the charge detection circuit 46 is connected to the horizontal signal line 40, and the CDS circuit 47 is further connected to the output terminal thereof.

That is, the first horizontal scanning circuit configuration section 81a
Connects the first load capacitance element 38a to the vertical signal line 35 via the first operation switch 37a, and connects the connection point to the horizontal signal line 40 via the first horizontal switch 39a. In parallel to the second operation switch 37'a
The second load capacitance element 38'a is connected to the horizontal signal line 40 via the second horizontal switch 39'a.

By the first operation switch 37a, the first load capacitance element 38a, and the first horizontal switch 39a, for example, a first signal holding circuit 51a for holding the signal before the pixel reset of the pixel MOS transistor in the (m + 1) th row. And a second operation switch 37'a, a second load capacitance element 38'a, and a second horizontal switch 39'a hold a signal after pixel reset of the pixel MOS transistor in the (m + 1) th row. Signal holding circuit 52a. The operation pulse φ _OPS1 is applied to the control electrode, that is, the gate of the first operation switch, and the operation pulse φ _OPN1 is applied to the control electrode, that is, the gate of the second operation switch.

The second horizontal output circuit component 81b is connected to the vertical signal line 35 in the same column as described above and the third operation switch 37b.
Is connected to the third load capacitance element 38b, and the connection point is connected via the third horizontal switch 39b to the horizontal signal line 40.
And the fourth operation switch 3 connected in parallel.
The fourth load capacitance element 38'b is connected via 7'b,
The connection point is connected to the horizontal signal line 40 via the fourth horizontal switch 39'b.

A third signal holding circuit for holding the signal of the m-th row pixel MOS transistor 32 before pixel reset by the third operation switch 37b, the third load capacitance element 38b and the third horizontal switch 39b. 51b is formed, and the fourth operation switch 37′b, the fourth load capacitance element 38′b, and the fourth horizontal switch 39′b hold the signal after the pixel reset of the pixel MOS transistor in the m-th row. 4 signal holding circuit 52b is configured. The operation pulse φ _OPS2 is applied to the control electrode or gate of the third operation switch, and the operation pulse φ _OPN2 is applied to the control electrode or gate of the fourth operation switch.

Then, the first and third horizontal switches 39
The control electrodes or gates of a and 39b are commonly connected to the horizontal shift register 42, the common horizontal scanning pulse φHS _n is applied to them, and the second and fourth horizontal switches 39'a and 39'b are applied. The control electrodes or gates of the above are commonly connected to the horizontal shift register 42 so that the common horizontal scanning pulse φHN _n is applied.

In the amplification type solid-state image pickup device 83 of the field reading system, the horizontal blanking period HB is set.
The read operation is performed twice in each of the first half period and the second half period of K.

That is, in the first half period of the horizontal blanking period, the vertical selection pulse φV _m is applied and the pixel MOS of the m-th row is
The transistor is selected. Then, the first operation pulse φ _{OP S1} turns off the first operation switch 37a → conducts →
The cutoff operation is performed, and the signal before the pixel reset of the pixel MOS transistor 32 in the m-th row is held in the first load capacitance element 38a.

Next, after the pixel reset pulse φV _sub is applied to the substrate in the pixel reset period to reset the signal charges accumulated in the pixel MOS transistors in the m-th row,
Second operation switch 3 by second operation pulse φ _OPN1
7'a performs the operation of shutting off → conducting → shutting off, and the second load capacitance element 38'a holds the signal of the pixel MOS transistor 32 of the m-th row after the pixel reset.

Next, in the latter half period of the horizontal blanking period HBK, the vertical selection pulse φV _{m + 1} is applied to select the pixel MOS transistor of the m + 1th row. Then, by the third operation pulse φ _OPS2 , the third operation switch 37b
Cut off → conduct → cut off, and the third load capacitance element 3
The signal before the pixel reset of the pixel MOS transistor 32 of the m + 1th row is held in 8b.

In the next pixel reset period, the pixel reset pulse φV _sub is applied to the substrate and the pixel MOS of the (m + 1) th row
After resetting the signal charge accumulated in the transistor 32, the fourth operation pulse φ _OPN2 causes the fourth operation switch 37′b to perform the operation of shut off → conductive → off, and the fourth load capacitance element 38′b. Further, the signal after the pixel reset of the pixel MOS transistor 32 in the (m + 1) th row is held.

Next, during the horizontal video period T _A , the first horizontal scanning pulse φHS from the horizontal shift register 42
When the horizontal switch 39a and the third horizontal switch 39b of FIG.
a and the second pre-pixel reset signals of the m-th row and the m + 1-th row held in the third load capacitance element 38b are added and output to the horizontal signal line 40, and the added pixel reset The previous signal is input to the charge detection circuit 46 and demodulated.

Further, the second horizontal switch 39'a is driven by the horizontal scanning pulse φHN from the horizontal shift register 42.
And the fourth horizontal switch 39'b becomes conductive, the m-th row and m + held in the second load capacitance element 38'a and the fourth load capacitance element 38'b, respectively.
The two signals after pixel reset in the first row are added and output to the horizontal signal line 40, and the added signals after pixel reset are input to the charge detection circuit 46 and demodulated.

Then, the signal voltages before the pixel reset and after the pixel reset, which are sequentially output to the output terminal of the charge detection circuit 46, are correlated double-sampled by the CDS circuit 47, so that in the field reading system, the F
Shading of the PN component and the horizontal scanning circuit can be removed.

FIG. 6 shows still another embodiment of the amplification type solid state image pickup device of the present invention. Amplification-type solid-state imaging device 85 of this example
Arranges the first signal holding circuit 51 and the second signal holding circuit 52 with symmetrical layouts on both sides of the horizontal signal line with the horizontal signal line as the center, and from the charge detection circuit 46 through the first signal holding circuit 51. The subtraction processing is performed on the obtained signal before pixel reset and the signal after pixel reset obtained from the charge detection circuit 46 'through the second signal holding circuit 52.

That is, the first horizontal signal line 86 and the second horizontal signal line 87 are arranged side by side in the center. On one side of the two horizontal signal lines 86 and 87, the vertical signal line 3
5 is connected to the first operation switch 37, the first load capacitance element 38 connected to the operation switch 37, and the first load capacitance element 38 connected to the first horizontal signal line 86. The first signal holding circuit 51 including the horizontal switch 39 of FIG.

The vertical signal lines 35 are arranged on the other side of the two horizontal signal lines 86 and 87 so as to be line symmetrical with the layout of the first signal holding circuit 51.
A second operation switch 37 'connected to the second operation switch 37' and a second load capacitance element 38 'connected to the second operation switch 37'.
And the load capacitance element 38 'and the second horizontal signal line 87.
A second signal holding circuit 52 including a second horizontal switch 39 'connected between them is arranged.

The first horizontal signal line 86 is connected to the first charge detection circuit 46 including the operational amplifier 43, the detection capacitance element 44 and the reset switch 45, and the second horizontal signal line 87 is connected to the operational amplifier 43, It is connected to a second charge detection circuit 46 'composed of the detection capacitance element 44 and the reset switch 45, and the first and second charge detection circuits 46, 46' are connected.
Is connected to each input terminal of the subtraction circuit 88 formed of an external differential amplifier, for example. Since other configurations are the same as those in FIG. 1, the corresponding portions are denoted by the same reference numerals, and the duplicate description will be omitted.

The amplification type solid state image pickup device 85 of this embodiment is
Similar to the comparative example shown in FIG. 8, the signal before pixel reset is held in the first load capacitance element 51, and the signal after pixel reset is held in the second load capacitance element 52. Then, by connecting the horizontal switches 39 and 39 'to each other, the signal before the pixel reset is output to the first charge detection circuit 46 through the first horizontal signal line 86, and the second horizontal signal line 8
The signal after the pixel reset is output to the second charge detection circuit 46 'through 7, the subtraction circuit 88 performs the subtraction process on the signal, and the output signal from which the FPN is removed is obtained from the output terminal t _out . In particular, according to the amplification type solid-state image pickup device 85, the first and second signal holding circuits 51 and 52 having the line-symmetrical layouts on both sides with the two horizontal signal lines 86 and 87 as a center are provided. Since the signals before and after reset obtained from the respective charge detection circuits 46 and 46 'have the same gradient of shading, the fixed pattern of shading is obtained from the output signal obtained through the subtraction circuit 88. Noise is also removed at the same time.

On the other hand, as described above, one of the causes of shading largely depends on the waveforms of the operation pulses φ _OPS and φ _OPN entering the first and second operation MOS switches. That is, for example, operating pulses φ _OPS and φ
_OPN is applied, but because of the layout, for example, the wiring length from the drive circuit to the operation switch is different,
The example operation pulse phi _OPS waveform through the long wiring accent, for example operation pulse phi _OPS waveform through a short, no rounding than operation pulse phi _OPS. When the waveform of the operation pulse φ _OPS at the cutoff of the operation switch is gentle, the slope of the shading is gentle, while when the waveform of the operation pulse φ _OPN is sharp, the shading is low. The inclination of becomes large. The same applies to the waveforms of the horizontal scanning pulses φHS and φHN.

FIG. 7 shows still another embodiment of the amplification type solid-state image pickup device of the present invention in consideration of the above point. It should be noted that the figure shows only the main part of the horizontal scanning circuit. In this embodiment, as shown in FIG. 7, a drive circuit for supplying operation pulses φ _OPS and φ _OPN, that is, a drive circuit 91 including, for example, an external CMOS inverter and the first and second operation switches 3 are provided.
The lengths of the wirings 92, 92 'up to 7, 37' are formed to have the same length. Further, the wiring 9 from the horizontal shift register 42 to the respective horizontal switches 39, 39 '
The lengths of 3,93 'are also formed to be the same.

The other structure is the same as that of FIG. It is also possible to apply the configuration of the comparative example of FIG.
Although the drive circuit 91 is an external type in FIG. 7, it may be an on-chip type in which the drive circuit 91 is arranged in the chip of the image sensor.

In this way, the wirings 92, 93 'from the drive circuit 91 to the first and second operation switches 37, 37' are provided.
By making the lengths equal to each other, the operation switches 37, 3
The waveforms of the operation pulses φ _OPS and φ _OPN entering _7'can be made as similar as possible, and as a result, the occurrence of shading can be reduced. In addition, the horizontal shift register 42 to the first and second horizontal switches 39, 3
By making the lengths of the wirings 93 and 93 ′ up to 9 ′ the same, it is possible to reduce the occurrence of shading.

Although the pixel MOS transistor 32 of the above-described embodiment has the pixel structure of the n-channel MOS transistor, it may be applied to the pixel structure of the p-channel MOS transistor in which the n-type / p-type impurity is inverted. it can.

[0088]

According to the amplification type solid-state imaging device of the present invention, the layout of the first signal holding circuit for holding the signal before pixel reset on both sides of the horizontal signal line and the signal after pixel reset are provided. By forming the layout of the second signal holding circuit to hold, both layouts can be formed symmetrically. Therefore, by outputting the difference between the signal before the pixel reset and the signal after the pixel reset, both the fixed pattern noise of the pixel and the fixed pattern noise of the shading generated in the horizontal scanning circuit or the like can be removed.

According to the amplification type solid-state image pickup device of the present invention, the layout of the first signal holding circuit and the layout of the second signal holding circuit are formed line-symmetrically with respect to the horizontal signal line, so that the pixel When the difference between the first signal before reset and the second signal after pixel reset is output, both the fixed pattern noise of the pixel and the fixed pattern noise of shading generated in the horizontal scanning circuit and the like can be removed.

According to the amplification type solid-state image pickup device of the present invention, one horizontal signal line is used and the layout of the first signal holding circuit and the layout of the second signal holding circuit are arranged symmetrically on both sides of the horizontal signal line. And the fixed pattern noise of the pixel and the horizontal scanning circuit are generated by performing the correlated double sampling of the first signal and the second signal output from the output circuit through the horizontal signal line sequentially. The fixed pattern noise of shading can be removed.

In this case, a differential amplifier for subtracting signals before and after pixel reset output from different terminals as in the comparative example is omitted. Since the correlated double sampling circuit is used, low-frequency random noise can be removed, and the S / N ratio of the pixel signal is improved. Since there is only one horizontal signal line, there is no need for gain correction for matching the signal and noise gains as in the comparative example.

According to the amplification type solid-state image pickup device of the present invention, the length of the wiring connected to the switch means in the first signal holding circuit from the drive circuit and the switch means in the second signal holding circuit are increased. When the lengths of the wirings to be connected from the drive circuit are set to be equal to each other, the waveforms of the drive patterns applied to the respective signal holding circuits have the same dullness, and the first and second obtained through the output circuit. The fixed pattern noise of the pixel and the fixed pattern noise of the shading generated in the horizontal scanning circuit can be removed by outputting the difference between the signals.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of an amplification type solid-state imaging device according to the present invention.

FIG. 2 is a configuration diagram of a CDS circuit according to the present invention.

FIG. 3 is a sectional view showing an example of a semiconductor structure of a pixel MOS transistor.

FIG. 4 is a drive timing chart and output waveform (horizontal synchronization) diagram of the amplification type solid-state imaging device according to the present invention.

FIG. 5 is a configuration diagram showing another embodiment of the amplification type solid-state imaging device according to the present invention.

FIG. 6 is a configuration diagram showing another embodiment of the amplification type solid-state imaging device according to the present invention.

FIG. 7 is a configuration diagram showing another embodiment of the amplification type solid-state imaging device according to the present invention.

FIG. 8 is a configuration diagram of an amplification type solid-state imaging device according to a comparative example.

FIG. 9 is an explanatory diagram of signal waveforms in a comparative example.

[Explanation of symbols]

31 amplification type solid-state imaging device, 32 pixel MOS transistor, 33 vertical scanning circuit, 34 vertical selection line, 35
Vertical signal line, 37, 37 'operation switch, 38, 3
8'load capacitance element, 39, 39 'horizontal switch, 4
0,86,87 horizontal signal line, 42 horizontal shift register, 46 charge detection circuit, 47 CDS circuit, 91 drive circuit, 92, 92 ', 93, 93' wiring

[Procedure amendment]

[Submission date] May 30, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Name of invention

[Correction method] Change

[Correction contents]

Title of invention Solid-state imaging device

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0001

[Correction method] Change

[Correction contents]

[0001]

TECHNICAL FIELD The present invention relates to a solid-state image sensor . More specifically, it relates to removing fixed pattern noise of pixels and shading fixed pattern noise generated in a horizontal scanning circuit.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction contents]

Although not shown, in order to reset the load capacitance elements 8, 8 ′ and the vertical signal line 5 to the initial voltage on the vertical signal line 5 on the first operation MOS switch 7 side of the load capacitance element 8. Reset MOS switch is connected. That is, the source of this reset MOS switch is connected to the vertical signal line 5, and its reset bias voltage V
_RB is applied, and the reset pulse φ _VRST is supplied to its gate.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction contents]

In view of the above points, the present invention provides a solid-state image pickup device capable of removing fixed pattern noise of pixels and shading generated in a horizontal scanning circuit.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction contents]

[0018]

A solid-state image sensor according to the present invention
The child has a layout of a first signal holding circuit that holds a signal before pixel reset in the horizontal scanning circuit and a layout of a second signal holding circuit that holds a signal after pixel reset, with a horizontal signal line interposed therebetween. The structure is formed on both sides.

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction contents]

The solid-state image pickup device according to the present invention has a layout of a first signal holding circuit for holding a first signal from a pixel before reset centering on one horizontal signal line in a horizontal scanning circuit. The layout of the second signal holding circuit for holding the second signal from the pixel after reset is formed line-symmetrically, and the correlated double sampling circuit is connected to the output side of the horizontal signal line.

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0022

[Correction method] Change

[Correction contents]

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION A solid-state image sensor according to the present invention includes a plurality of pixels arranged in a matrix, a vertical signal line in which pixels in the same column are commonly connected, and a pixel output from the vertical signal line. And a horizontal scanning circuit for sequentially outputting the signal of each row to the output terminal for each row, and one vertical signal line for holding the first signal from the pixel before pixel reset in the horizontal scanning circuit. The circuit and the second signal holding circuit for holding the second signal from the pixel after pixel reset are connected, and the difference between the first and second signals is output from the output unit connected to the horizontal signal line. In the solid-state imaging device , the layout of the first signal holding circuit and the layout of the second signal holding circuit are formed on both sides of the horizontal signal line.

[Procedure amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0023

[Correction method] Change

[Correction contents]

According to the present invention, in the above solid-state image pickup device , the layout of the first signal holding circuit and the layout of the second signal holding circuit are line-symmetrical with respect to the horizontal signal line.

[Procedure amendment 10]

[Document name to be amended] Statement

[Name of item to be corrected] 0024

[Correction method] Change

[Correction contents]

The present invention provides the above solid-state image pickup device, wherein
A circuit having a horizontal signal line is connected to a correlated double sampling circuit for performing correlated double sampling of the first signal and the second signal.

[Procedure amendment 11]

[Document name to be amended] Statement

[Name of item to be corrected] 0025

[Correction method] Change

[Correction contents]

According to the present invention, in the above solid-state image pickup device , the length of the wiring connected to the switch means in the first signal holding circuit from the drive circuit and the length of the wiring connected to the switch means in the second signal holding circuit. The length of the wiring from the drive circuit is set to be equal to each other.

[Procedure amendment 12]

[Document name to be amended] Statement

[Correction target item name] 0031

[Correction method] Change

[Correction contents]

Further, the same vertical signal line 35 is subjected to a second operation switch (for example, a MOS switch) 37 'controlled by an operation pulse φ _OPN to _output a signal having no signal charge (pixel fixed pattern) after pixel reset. A second load capacitance element 38 'holding only noise) is connected. That is, this second load capacitance element 38 'is also connected between the vertical signal line 35 and the ground potential. A second horizontal switch (eg, MOS switch) 39 'controlled by the horizontal shift register 42 is connected between the second load capacitance element 38' and the horizontal signal line 40.

[Procedure amendment 13]

[Document name to be amended] Statement

[Correction target item name] 0061

[Correction method] Change

[Correction contents]

By providing the CDS circuit 47, the differential
Generated from amplifier 45 and pixel MOS transistor 32
The low frequency component of the random noise is removed, and as a result,
The signal S / N ratio is improved.

[Procedure Amendment 14]

[Document name to be amended] Statement

[Correction target item name] 0083

[Correction method] Change

[Correction contents]

On the other hand, as described above, the shading
One of the causes is the first and second operating MOS switches.
Operation pulse φ entering the switch_OPS, Φ_OPNGreat for the waveform of
Dependent. That is, for example, from an external drive circuitpad
Operation pulse φ in different system through (terminal)_OPS, Φ
_OPNIs applied, but due to the layout, for example, drive
Since the wiring length from the circuit to the operation switch is different,
For example, an operation pulse φ that passes through a long wiring_OPSWaveform of
For example, operating pulse φ_OPSWaveform is dynamic
Work pulse φ_OPSMore than not. Operation switch bracket
Operation pulse at turn-off φ_OPSWaveforms fall slowly
Being gentle, the gradient of shading is gentle
In contrast, operating pulse φ_OPNWaveform has a sharp fall
In case of, the inclination of shading becomes large. This
That is, regarding the waveforms of the horizontal scanning pulses φHS and φHN.
However, the same can be said.

[Procedure Amendment 15]

[Document name to be amended] Statement

[Correction target item name] 0088

[Correction method] Change

[Correction contents]

[0088]

According to the solid-state image pickup device of the present invention, the layout of the first signal holding circuit for holding the signal before pixel reset on both sides of the horizontal signal line and the signal after pixel reset are held. By forming the layout of the second signal holding circuit, both layouts can be formed symmetrically. Therefore, by outputting the difference between the signal before the pixel reset and the signal after the pixel reset, both the fixed pattern noise of the pixel and the fixed pattern noise of the shading generated in the horizontal scanning circuit or the like can be removed.

[Procedure Amendment 16]

[Document name to be amended] Statement

[Correction target item name] 0089

[Correction method] Change

[Correction contents]

According to the solid-state image pickup device of the present invention, the layout of the first signal holding circuit and the second signal holding circuit centering on the horizontal signal line are used.
When the difference between the first signal before pixel reset and the second signal after pixel reset is output, the fixed pattern noise of the pixel and the horizontal scanning circuit are formed by forming the layout of the signal holding circuit of FIG. It is possible to remove the fixed pattern noise of shading that occurs due to the above.

[Procedure amendment 17]

[Document name to be amended] Statement

[Correction target item name] 0090

[Correction method] Change

[Correction contents]

According to the solid-state image pickup device of the present invention, one horizontal signal line is used and the layout of the first signal holding circuit and the layout of the second signal holding circuit are formed on both sides of the horizontal signal line in line symmetry. Then, the first signal and the second signal output from the output circuit sequentially through the horizontal signal line are subjected to correlated double sampling by the correlated double sampling circuit,
The fixed pattern noise of pixels and the fixed pattern noise of shading generated in the horizontal scanning circuit and the like can be removed.

[Procedure amendment 18]

[Document name to be amended] Statement

[Correction target item name] 0092

[Correction method] Change

[Correction contents]

According to the solid-state image sensor of the present invention, the first
When the length of the wiring connected to the switch means in the signal holding circuit from the driving circuit and the length of the wiring connected to the switch means in the second signal holding circuit from the driving circuit are set to be equal to each other. The waveforms of the drive patterns applied to the respective signal holding circuits are the same, and the fixed pattern noise of the pixel and the horizontal scanning circuit are output by outputting the difference between the first and second signals obtained through the output circuit. Together with the fixed pattern noise of shading that occurs in
Can be removed.

Claims (4)

[Claims] 1. A plurality of pixels arranged in rows and columns, a vertical signal line in which pixels in the same column are commonly connected, and a signal from the pixel output from the vertical signal line is sequentially output for each row. A horizontal scanning circuit for outputting to a first signal holding circuit for holding a first signal from a pixel in the horizontal scanning circuit before pixel reset and a pixel after pixel reset. An amplification type solid-state imaging device, which is connected to a second signal holding circuit for holding a second signal and outputs a difference between the first and second signals from an output section connected to a horizontal signal line. An amplification type solid-state imaging device, wherein the layout of the first signal holding circuit and the layout of the second signal holding circuit are formed on both sides of the horizontal signal line. 2. The layout of the first signal holding circuit and the layout of the second signal holding circuit are formed symmetrically with respect to the horizontal signal line. Amplification type solid-state image sensor. 3. The output circuit for one horizontal signal line is provided with the first circuit.
3. The amplification type solid-state imaging device according to claim 2, further comprising: a correlated double sampling circuit that performs correlated double sampling of the signal of FIG. 2 and the second signal. 4. The length from the drive circuit of the wiring connected to the switch means in the first signal holding circuit, and the second
2. The amplification type solid-state imaging device according to claim 1, wherein the length of the wiring connected to the switch means in the signal holding circuit from the drive circuit is set to be equal to each other.