JPH0723303A - Solid state image pickup element - Google Patents

Abstract

PURPOSE:To eliminate the necessity of a voltage buffer having high speed and large capacity, to suppress power consumption and to attain the FPN correction of a CMD image pickup element or the like by connecting the output terminal of the CMD image pickup element to one input terminal of a differential amplifier and the input terminal of a frame memory through a preamplifier. CONSTITUTION:Since reset voltage is impressed to all gate lines of the CMD image pickup element 220 in each horizontal flyback time by a control signal outputted from a timing generating circuit 224 at t=t1, the exposure time of each picture element becomes > one horizontal effective scanning period. Thereby a signal output based upon incident light is regarded as a dark time output. A clock signal is turned to 'H' by a control signal, from the circuit 224 at t=t2 and a normal image pickup state is set up. Dark time output signals for all picture elements are read out from the element 220 by impressing reset potential to the gate lines of all the picture elements over > one frame period and stored in the frame memory 225 as a dark time FPN signal through the preamplifier 212. Then the element 220 executes image pickup operation by a control signal from the circuit 224 to read out the signals of respective picture element obtain a video signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a charge modulation device (CM).
D: Charge Modulation Device
The present invention relates to a solid-state image pickup device using an image pickup element such as e) as a constituent element of a pixel, and particularly to a solid-state image pickup device having an FPN correction function.

[0002]

2. Description of the Related Art Conventionally, there are known various solid-state image pickup devices including an image pickup device having a MIS type light receiving / accumulating portion. There is a solid-state image pickup device using an image pickup device having an amplification function.

As an example of this solid-state image pickup device, Japanese Patent Laid-Open No. 61-84059 and 19 proposed by the applicant of the present application.
International El held in 1986
electron Device Meeting (IED
M), pp. 353-356, 'A New M
OS Image Sensor Operation
g in a Non-Destructive Re
In addout Mode ', a solid-state image pickup device using a CMD image pickup element is disclosed.

FIG. 11 shows a circuit configuration of a conventional solid-state image pickup device using the above-mentioned CMD image pickup device and will be described. First, CMDs 101-11 and 101-1 that form each pixel
2, ..., 101-mn are arranged in a matrix, and each drain has a common video bias V _DD (> 0).
Is applied.

The gate terminals of the CMDs arranged in the X direction are row lines 102-1, 102-2, ..., 102-m.
, And the source terminals of the CMDs arranged in the Y direction are column lines 103-1, 103-2, ..., 103.
-N respectively.

The column lines 103-1 and 103-2,
, 103-n are column selection transistors 10 respectively.
, 104-n and anti-selection transistors 105-1, 105-2, ..., 105-n to the signal line 106 and the reference line 107 grounded to GND, respectively. Connect in common. The signal line 106 is connected to a current-voltage conversion type preamplifier 112 whose input is virtually grounded, and a negative video signal is read out in time series from the output terminal 109 of the preamplifier 112.

Also, the row lines 102-1, 102-2,
, 102-m are connected to the vertical scanning circuit 110 to apply signals φ _G1 , φ _G2 , ..., φ _Gm , respectively, and the column selection transistors 104-1, 104-2, ..., 104-n and anti-selection are performed. Transistors 105-1, 105-2, ..., 10
The gate terminals of 5-n are connected to the horizontal scanning circuit 111, and apply the respective signals φ _S1 , φ _S2 , ..., φ _Sn and their inverted signals. Each CMD is formed on the same substrate, and a substrate voltage V _{SUB (} not shown) is applied to the substrate.

Next, FIG. 12 is a signal waveform diagram for explaining the operation of the solid-state image pickup device using the CMD image pickup device shown in FIG. Row lines 102-1, 102-2, ...
Clock signals φ _G1 , φ _G2 , ..., φ applied to 102-m
_Gm is composed of a read gate voltage V _RD , a reset voltage V _RST , an overflow voltage V _OF , and a storage voltage V _INT . In a non-selected row, the storage voltage V _INT is stored during the horizontal effective period of the video signal, and the horizontal blanking period is stored. Overflow voltage V _OF is, read gate voltage V _RD during the horizontal effective period of the video signal in the selected row, and reset voltage V during the horizontal retrace period.
Become _RST .

Further, the column selecting transistors 104-1,
The signals φ _S1 , φ _S2 , ..., φ _Sn applied to the gate terminals of 104-2 ,.
These signals are for selecting 3-2, ..., 103-n.

In the applied signals φ _S1 , φ _S2 , ..., φ _Sn , the low level of the voltage value indicates that the column selection transistor 104-
, 104-n are turned off, anti-selection transistors 105-1, 105-2, ..., 105-n are turned on, and high level is column selection transistors 104-1, 10.
, 104-n are turned on and the anti-selection transistors 105-1, 105-2, ..., 105-n are turned off. Then, the optical signal of each CMD pixel is sequentially read out to the signal line 106, amplified by the preamplifier 112, and output. In FIG. 12, H
-BLANK is a signal whose low level indicates the timing of the horizontal blanking period of the video signal.

However, in the present solid-state image pickup device, a so-called fixed pattern noise (fixed pattern noise) in which a characteristic variation for each pixel appears in a signal output.
Oise: hereinafter abbreviated as FPN) is large and is a main noise source of the present solid-state imaging device. The main cause of this FPN is
It has been reported that variations in the characteristics of transistors forming pixels and the effect of this FPN can be significantly improved by performing offset correction of the dark output (reference: "FPN suppression driving method for CMD image sensor"). ”, Proceedings of National Congress of Television Society, 3-7, 19
90).

As a solid-state image pickup device having the offset correction function, the applicant of the present application discloses two methods.
First of all, there is a solid-state imaging device having a configuration as shown in FIG. 13 disclosed in Japanese Patent Laid-Open No. 64-39171.

This solid-state image pickup device forms an optical image from a subject on a photoelectric conversion surface of an image sensor 2 through a lens 1. The shutter 3 behind the lens 1 is installed to realize a state in which no light is incident on the photoelectric conversion surface of the image sensor 2. Of course, it may be provided in front of the lens 1.

With the shutter 3 closed,
Since no light is incident on the photoelectric conversion surface of the image sensor 2, the electrical output of the image sensor 2 should be zero (black level), but the FPN is output from the image sensor 2.

This FPN output is stored in the frame memory 4, and the output signal from the image sensor 2 obtained when an actual subject is imaged and the signal corresponding to the FPN stored in the frame memory 4 are read out. Are simultaneously supplied to the differential amplifier 5 to obtain a difference signal between them. As a result, the FP is detected from the image pickup output signal of the subject from the image sensor 2.
An output signal from which the N signal is removed is obtained.

In FIG. 13, the clock signal generating circuit 6 makes the pixels of the image sensor 2 correspond to the addresses of the frame memory 4 at the time of storing the FPN signal and at the time of reading the FPN signal.
Generate a clock signal that is applied simultaneously to the.

The process circuit 7 includes the image sensor 2
Is a circuit for removing the FPN from the output signal of the above and processing a signal corresponding to only the optical image by a normal video signal.
Is a switch that switches between the case of storing a signal corresponding to FPN in the frame memory 4 and the case of capturing and outputting a normal subject.

However, in the above-mentioned solid-state image pickup device having the FPN correction function, the mechanical light shielding member, that is, the shutter 3 is required, which increases the scale, weight and cost of the system.

Therefore, Japanese Patent Laid-Open No. 4-1 by the applicant of the present invention
Japanese Patent No. 62886 discloses a solid-state imaging device capable of suppressing the influence of FPN on a video signal without using a mechanical light shielding member such as a shutter.

FIG. 14 shows an outline of this solid-state image pickup device.
The CMD image pickup device 20 in this solid-state image pickup device is shown in FIG.
Since it is the same as that shown in, the description of the configuration is omitted.

The output of the CMD image pickup device 20 is connected to the preamplifier 12, and one output terminal of the differential amplifier 26 and the input terminal of the frame memory 25 are connected to the output of the preamplifier 12. The output terminal of the frame memory 25 is connected to the other input terminal of the differential amplifier 26. Of the read signal voltage power supply terminal V ₁ , the reset signal voltage power supply terminal V ₂ and the overflow signal voltage power supply terminal V ₃ of the CMD image sensor 20, the power supply terminal V
₁ and the power supply terminal V ₂ are connected to the power supply 21 to apply the read signal voltage V _RD and the reset signal voltage V _RST , respectively, and the power supply terminal V ₃ is connected to the power supply through the power supply switching switch circuit 27. , Either the reset signal voltage V _RST or the overflow signal voltage V _OF is applied to the power supply terminal V ₃ .

The switching control of the switch circuit 27, the operation of the CMD image pickup device 20 and the operation of the frame memory 25 are configured to be performed by signals from the timing signal generating circuit 24.

Next, the operation of the solid-state image pickup device will be described. The control signal from the timing signal generation circuit 24 operates the power supply switching switch circuit 27 to apply the reset voltage V _RST to the overflow signal voltage power supply terminal V ₃ of the image sensor 20.

In this case, the period in which the overflow signal is applied to each pixel of the CMD image sensor 20 is a period in which no pixel signal is read out, that is, the horizontal blanking period, and therefore the gate of each pixel of the CMD image sensor 20 is The reset signal voltage is generated every horizontal blanking period, and the exposure time of each pixel is one horizontal effective scanning period or less.

Therefore, since the signal output by the incident light is 1 / the number of scanning lines in one field, it is C in the NTSC standard.
When the MD image pickup device 20 is operated, it becomes 0.4% or less, which can be regarded as dark output. Power supply terminal V ₃ is 1
By setting the reset voltage V _RST for the frame period or longer, the dark output signals for all pixels are read from the CMD image sensor 20, amplified by the preamplifier 12 to a predetermined voltage amplitude, and held in the frame memory 25 as a dark FPN signal. .

Then, the control signal from the timing signal generating circuit 24 activates the power supply switching switch 27, and the overflow signal voltage V _OF near the read signal voltage is applied to the overflow signal voltage power supply terminal V ₃ of the CMD image pickup device 20. Then, the CMD image pickup device 20 is changed to the one shown in FIG.
The signal output of each pixel is read out in the same manner as in the conventional examples 1 and 12, and the video signal can be obtained from the output of the preamplifier 12.

At this time, by the reference signal from the timing signal generation circuit 24, the frame memory 25 causes the pixel signal read from the CMD image sensor 20 to be the same as the pixel signal in dark F
The PN signal is sequentially read and input to the differential amplifier 26 together with the video signal from the CMD image sensor 20. By taking the difference of these signals by the differential amplifier 26,
A video signal from which the dark FPN signal has been removed can be obtained from its output terminal.

The CMD used in this solid-state imaging device
A scanning circuit as shown in FIG. 15 is used as the vertical scanning circuit 110 of the image sensor 20, and it operates at the timing as shown in FIG.

That is, the gate pulse level generating circuit 2
08 applies the output from the switching transistor 201 and the shift register 206 of the read voltage V _RD connected to apply the inverted clock signal / φ ₂ ^V to the gate for each bit for each row line. The switching transistor 202 having the overflow voltage V _{OF and} the switching transistor 20 having the reset voltage V _RST configured to apply the inverted output of the output from the shift register unit 206 to the gate.
3, a switching transistor 204 for switching the accumulated voltage V _INT connected so as to apply the inverted clock signal / φ ₂ ^V to the gate, and a control transistor 205 for controlling each of the above transistors It is composed of.

Each unit circuit 206 of the shift register
As shown in the figure, for example, a clocked CMOS configuration is available, and 207-1, 207-2,
, 207-m are unit circuits for each row line of the shift register and the gate pulse level generating circuit.

The solid-state image pickup device having the FPN correction function configured as described above does not require a mechanical light-shielding member when storing the FPN signal, and thus is a light-weight, compact and inexpensive solid-state image pickup device. .

[0032]

However, in the above-described conventional solid-state image pickup device having the FPN correction function, when the dark FPN signal is stored in the frame memory, the CMD is stored.
There is a problem that the power supply voltage connected to the overflow signal voltage power supply terminal V ₃ of the image pickup device 20 needs to be switched between the overflow signal voltage V _OF near the read signal voltage and the reset signal voltage V _RST .

A capacitive load corresponding to all the pixels inside the CMD image pickup device 20 is connected to the overflow signal voltage power supply terminal V ₃ of the CMD image pickup device 20, and the power supply voltage for driving this load is externally supplied at high speed. High-speed and large-capacity voltage buffer is indispensable for switching with
Generally, the power consumption of such a voltage buffer is extremely large.

Therefore, if the solid-state image pickup device having the FPN correction function is to be put into practical use, the scale of the drive circuit increases and a problem occurs in terms of power consumption. Therefore, the present invention provides a solid-state imaging device that does not require a high-speed and large-capacity voltage buffer, and that suppresses an increase in power consumption, and a solid-state imaging device having a FPN correction function for a solid-state imaging device similar to this. The purpose is to

[0035]

In order to achieve the above object, the present invention includes transistors each of which has a source / drain current modulated as a component by the amount of charge generated and accumulated by light irradiation, as a matrix, A plurality of pixels arranged in a plurality of pixels, a read signal for reading the source / drain current corresponding to the accumulated charge of each pixel on the periphery thereof, and a reset signal for discharging all the accumulated charges of the pixel, An input provided to the logic control terminal from the outside, which includes driving means for selectively applying to the gate of the pixel an overflow signal for discharging a part of the accumulated charge after the pixel is reset and before the next reading Depending on the state, a driver that selectively applies other DC voltage to the gate of the pixel during the period when the overflow potential is applied. A solid-state image sensor including: a first means for holding all pixel signal output of the solid-state image sensor; and an output of the solid-state image sensor and a means for holding all pixel signal output A second means of obtaining
Timing signal generating means for generating a control signal to be applied to a logic control terminal for driving a driving means for selectively applying another direct current voltage to the gate of the pixel during a period in which the overflow potential of the solid-state imaging device is applied. Provided is a solid-state imaging device including the following.

[0036]

By operating the solid-state image pickup device having the above-described structure, the reset signal is set at each timing at which the overflow signal voltage should be applied during the normal image pickup operation in accordance with the input to the logic control terminal input to the image pickup device. When the signal of each pixel is read after being applied to the gate of the pixel,
The exposure time of the signal of the solid-state image sensor is one horizontal scanning period or less, which can be regarded as equivalent to a dark state, a high-speed and large-capacity voltage buffer is not required, and an increase in power consumption is suppressed.

[0037]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a circuit configuration diagram of a vertical scanning circuit unit of a solid-state image pickup device as a first embodiment according to the present invention.

In this solid-state image pickup device, 31 and 32 are a P-channel type MOS transistor and an N-channel type MOS transistor which form a COMS inverter.
A clock pulse whose low level is the read voltage V _RD and whose high level is the reset voltage V _RST is applied to the source of the P-channel MOS transistor 31.

On the other hand, the source of the N-channel MOS transistor 32 is the drain of the N-channel MOS transistor 33 for switching the overflow voltage V _OF and the N-channel MO transistor for switching the accumulated voltage V _INT.
It is commonly connected to the drain of the S-transistors 34. The gate of the V _OF N-channel type MOS transistor 33 for switching, the clock signal φ _B ^{V, V} _INT
N-channel MOS transistor 34 for switching
Inverted clock signal of clock signal φ ₂ ^V /
φ ₂ ^V is applied.

Further, the P-channel type MOS transistor 3
The output SR _i of the i-th unit circuit 17 of the shift register is applied to each gate of the 1- and N-channel type MOS transistors 32, and the start pulse φ is applied to the i-th unit circuit 17 of the shift register. _ST ^V , scanning clock signal φ ₁ ^V , inverted clock signal / φ ₂ ^V , scanning clock signal φ ₁ ^V , and inverted clock signal / φ
₂ ^V is input.

Further, P which constitutes the COMS inverter
Channel type MOS transistor 31 and N channel type M
The reset voltage V is applied to the drain of the OS transistor 32.
The drain of the P-channel MOS transistor 30 for _RST switching is connected to the P-channel MO transistor 30.
Clock signal phi _A ^V to the gate of the S transistor 32 is applied.

Next, the operation of the vertical scanning circuit thus constructed will be described with reference to the timing chart shown in FIG. The normal imaging operation corresponding to the left half surface of FIG. 2, that is, the clock signal φ _A ^V is constantly supplied with a high level, and the clock signal φ _B ^V is supplied with the clock signal φ ₂ ^V.
And a case where pulses of the same timing are supplied will be described.

First, at time t ₁₁ , the clock signal φ
_In synchronization with the rise of ₁ ^V , the output SR _i of the i-th unit circuit 17 of the shift register switches from the high level to the low level, the P-channel MOS transistor 31 forming the CMOS inverter is turned on, and the CMD pixel array after the read voltage V _RD is applied to the gate lines, the reset voltage V synchronized with the clock signal phi ₂ ^V
_RST is applied from the V _RD / V _RST line.

Then, at time t ₁₂ , the clock signal φ
_When the output SR _i of the i-th unit circuit 17 of the shift register changes from low level to high level in synchronization with the rise of ₁ ^V , the N-channel type MOS transistor 32 forming the CMOS inverter is turned on. In FIG. 1, at point A (the connection point between the source of the N-channel MOS transistor 32 and the drains of the N-channel MOS transistors 33 and 34), an overflow voltage V _OF synchronized with the high level of the clock signal φ _B ^V is generated. Clock signal / φ
_The accumulated voltage V _INT synchronized with the high level of ₂ ^V is switched and applied by the N-channel MOS transistors 33 and 34. Therefore, N of the CMOS inverter
When the channel type MOS transistor 32 is turned on, the accumulated voltage V is applied to the gate line of the CMD pixel array.
_INT and the overflow voltage V _OF are applied alternately.

Next, the reset signal voltage V _RST is supplied to the gate of each pixel of the CMD image pickup device in each horizontal blanking period, which corresponds to the right half surface of FIG. 2, to read the dark output signal from the CMD image pickup device. in operation mode, and is always low level is supplied to the clock signal phi _B ^V, and the inverted clock signal / phi ₂ ^V and the pulse at the same timing of the clock signal phi ₂ ^V is supplied to the clock signal phi _a ^V The case where there is is explained.

First, at time t ₂₁ , the clock signal φ
_When the output SR _i of the i-th unit circuit 17 of the shift register changes from the high level to the low level in synchronization with the rise of ₁ ^V , the P-channel type MOS transistor 31 forming the CMOS inverter is turned on and the CMD pixel After the read voltage V _RD is applied to the gate line of the array, the reset voltage V _RST synchronized with the clock signal φ ₂ ^V is applied.
Is applied from the V _RD / V _RST line.

Then, at time t ₂₂ , when the output SR _i of the i-th unit circuit 17 of the shift register changes from the low level to the high level in synchronization with the rising of the clock signal φ ₁ ^V , the CMOS inverter is formed. The N-channel type MOS transistor 32 is turned on. In FIG. 1, at point A (the connection point between the source of the N-channel MOS transistor 32 and the drains of the N-channel MOS transistors 33 and 34), an inverted clock signal / φ ₂ ^V
The accumulated voltage V _INT synchronized with the high level is output by the N-channel MOS transistor 34.

On the other hand, the clock signal φ _B ^V is always at the low level, the N-channel MOS transistor 33 is always off, and the overflow voltage V _OF is not output. Furthermore, since the clock signal phi _A ^V is supplied the clock signal of the inverted clock signal / phi ₂ ^V and the same timing, the i-th unit circuit of the shift register 1
When the output SR _{i of} 7 is at high level, the accumulated voltage V _INT and the reset voltage V _RST are alternately applied to the gate line of the CMD pixel array in synchronization with the inverted clock signal / φ ₂ ^V.

Next, referring to FIG. 3, using the solid-state image pickup device having the above-described structure and the vertical scanning circuit for driving,
A method of removing the influence of so-called FPN that appears in the signal output will be described. FIG. 4 is a schematic timing chart of the drive signal sent from the timing signal generation circuit 224 shown in FIG. 3 to the CMD image sensor 220.

The output terminal of the CMD image pickup device 220 is connected to the preamplifier 212, and the output thereof is the differential amplifier 22.
6 and one of the input terminals of the frame memory 225.

The output terminal of the frame memory 225 is
It is connected to the other input terminal of the differential amplifier 226.
Further, signals from the power supply 221 and the timing signal generation circuit 224 are connected to the CMD image pickup device 220, and DC voltage and timing signals necessary for the operation of the image pickup device are supplied. The operation of the frame memory 225 is also controlled by a signal from the timing signal generation circuit 224.

Next, the operation of the solid-state image pickup device of this embodiment will be described with reference to FIG. At t = t ₁ ,
The clock signal φ _A ^V in the circuit example shown in FIG. 1 is clocked by the control signal from the timing signal generation circuit 224, while the clock signal φ _B ^V is always at the low level. At this time, since the reset potential V _RST is applied to all the gate lines of the CMD image pickup device 220 every horizontal blanking period as shown in the right half surface of FIG. 2, the exposure time of each pixel is 1 horizontal effective. It is less than the scanning period. Therefore,
Signal output by incident light is 1 / the number of scanning lines in one field
Therefore, when the image pickup device 220 is operated in accordance with the NTSC standard, the output becomes 0.4% or less, which can be regarded as a dark output. After that, at t = t ₂ , the clock signal φ _A ^V in the circuit example shown in FIG. 1 is always at the high level by the control signal from the timing signal generation circuit 224, while the clock signal φ _B ^V is clocked. , The operation in the normal imaging state is performed. When performing the operation of applying the reset potential V _RST every horizontal retrace line period, it is necessary to change the clock signals φ _A ^V and clock signal φ _B ^{V from} the normal image pickup operation. The supply of these clock signals to the vertical scanning circuit can be realized, for example, by changing the clock signal itself supplied from the timing signal generation circuit 224 to the image pickup element 220.

As another method, from the timing signal generating circuit 224, for example, a low level is applied during a normal image pickup operation, and a high level is applied when an operation of applying a reset potential V _RST every horizontal blanking period is performed. A reset operation control signal φ _CNT is input to the solid-state image sensor 220, and a drive pulse generation circuit as shown in FIG. 5 is formed in the solid-state image sensor 220 to switch between the above two types of operations. It becomes possible.

By applying the reset potential V _RST to the gate lines of all the pixels for one frame period or more by configuring and driving as described above, the dark output signals of all the pixels are read from the solid-state image sensor 220. , Preamplifier 2
The frame memory 22 is amplified by 12 to a predetermined voltage.
5 is held as an FPN signal in the dark.

Then, by the control signal from the timing signal generating circuit 224, the solid-state image pickup device 220 is driven in the same manner as in the conventional example, the normal image pickup operation is performed, and the signal of each pixel is sequentially read. A video signal can be obtained from the output of the preamplifier 212.

At this time, according to the reference signal from the timing signal generation circuit 224, the frame memory 225 successively outputs the dark-time FPN signal of the same pixel as the pixel signal read from the solid-state image pickup device 220, and the solid-state image pickup device 220 outputs. Is input to the differential amplifier 226 together with the video signal of. By taking the difference signal of these input signals by the differential amplifier 226, the video signal from which the influence of the dark FPN signal has been removed can be obtained from its output terminal.

The solid-state image pickup device of the present embodiment does not correct the variation in the dark charge amount, but as described in Japanese Patent Laid-Open No. 4-162886, the main cause of FPN is not the variation in the dark charge amount. Therefore, it has the same FPN removal effect as the solid-state imaging device shown in the first conventional example.

Further, since the solid-state image pickup device of this embodiment does not require a mechanical light shielding member, it is possible to provide a solid-state image pickup device having a lightweight and inexpensive structure. Further, the solid-state imaging device of the present invention has the same FPN removal effect as the solid-state imaging device shown in the second conventional example,
By providing a switch for applying the reset voltage V _RST to all pixels for capturing PN for each gate line, a high-speed and large-capacity switch for driving a large capacitive load and switching the power supply voltage at a high speed is provided. The advantage is that no voltage buffers or switches are needed.

Next, a solid-state image pickup device as a second embodiment according to the present invention will be described. The second embodiment further improves the first embodiment and solves the following problems.

First, in order to perform the FPN removal for each unit circuit unit of the vertical scanning circuit corresponding to each gate line, it is necessary to additionally provide a switch in addition to the configuration required for the normal image pickup operation. , The circuit scale increases. That is, when a sensor having a large number of pixels is formed, not only the yield problem becomes conspicuous but also the problem arises that the circuit layout becomes practically difficult when the unit unit of the vertical scanning circuit having a narrow pitch is formed.

Second, as shown in FIG. 4, the first
When the method of the embodiment is adopted, in order to output and hold the FPN in the dark, a normal video signal output cannot be obtained for one field period, and in addition, in order to perform the operation, the following field is used. However, since the signal integration time of the pixels connected to each line is not constant, there arises a problem that a normal video signal output cannot be obtained.

These problems are solved by the second embodiment. Specifically, the phase condition of the pulse driving the shift register unit included in the unit of the vertical scanning circuit is controlled to be changed between the normal operation and the FPN signal acquisition.
The same FPN suppression effect as that of the first embodiment is realized, and further, in order to hold the dark FPN, a normal video signal cannot be obtained for one field period. , In the subsequent field, the disadvantage that a normal video signal cannot be obtained because the signal integration times of the pixels connected to each line are not aligned is solved, and a normal video signal is obtained from the next field following the operation. Since the vertical scanning circuit does not further increase in circuit scale, the unit unit of the vertical scanning circuit with a narrow pitch does not cause a yield problem and a decrease when a multi-pixel sensor is configured. In order to eliminate the disadvantage of the first embodiment of the present invention that the circuit layout becomes practically difficult even when configuring the above.

FIG. 6 shows a vertical scanning circuit of a solid-state image pickup element used in a solid-state image pickup device as a second embodiment. Here, members having the same functions as those of the vertical scanning circuit unit of the first embodiment shown in FIG. 1 among the constituent members of FIG. 6 are designated by the same reference numerals, and the description thereof will be omitted.

In FIG. 6, the difference from the circuit shown in FIG. 1 is that the switch transistor for applying the reset potential V _RST for each horizontal blanking period is omitted. The operation of the vertical scanning circuit portion shown in FIG. 6 is shown in FIG.
A description will be given using the timing chart shown in FIG.

In FIG. 7, the operation of the left half surface is exactly the same as the operation of the vertical scanning circuit portion in the case of the first embodiment, and the description thereof will be omitted. The right half of Fig. 7 shows the gate of each pixel.
This is the timing when the dark voltage FPN signal is read by applying the read voltage V _RD after applying the reset voltage V _RST to the line.

Since the output SR _i of the i-th unit circuit of the shift register transits in synchronization with the rising edge of the clock signal φ ₁ ^V , during the normal image pickup operation, the pixel after transition from the non-selected state to the selected state The read voltage V _RD for reading the signal is applied. After that, the reset voltage V _RST for resetting the signal charge of the pixel for which reading has been completed is applied to the gate line of the pixel during the subsequent horizontal blanking period.

On the other hand, when reading the dark FPN signal shown on the right half of FIG. 7, the phase condition of the clock signal supplied to the shift register is different from that in the normal image pickup operation, so that the horizontal blanking period is entered. By the way, the output SR _i of the i-th unit circuit of the shift register transits. Therefore, when the state of the unit circuit changes from the non-selected state to the selected state, the reset voltage V is applied to the corresponding gate line.
_{After RST} is applied during the horizontal blanking period, the read voltage V _RD for reading the signal from the pixel is applied and the signal from the pixel is read.

Therefore, the exposure time of each pixel is one horizontal effective scanning period or less, and the signal output by the incident light is one-hundredth of the number of scanning lines in one field. Therefore, the image sensor is operated according to the NTSC standard. In case of 0.4% or less,
It can be regarded as dark output.

In the solid-state image pickup device having the vertical scanning circuit configured and driven as described above, the signal appears in its signal output.
A method of removing the influence of so-called FPN will be described with reference to FIG.

FIG. 9 is a schematic timing chart of the drive signal sent from the timing signal generation circuit 424 shown in FIG. 8 to the CMD image sensor 420. In the configuration shown in FIG. 8, only the timing signal generation circuit 424 and the solid-state image pickup element 420 are different from the configuration diagram showing the example of the solid-state image pickup device of the first embodiment shown in FIG.
The other components are equivalent to the configuration shown in FIG. 3, and therefore the same reference numerals are given and the description thereof is omitted.

The output terminal of the CMD image pickup device 420 is connected to the preamplifier 212, and the output thereof is the differential amplifier 22.
6 and one of the input terminals of the frame memory 225.

The output terminal of the frame memory 225 is
The other input terminal of the differential amplifier 226 is connected so that the output is applied. Further, signals from the power source 221 and the timing signal generation circuit 424 are CMD image sensor 420.
And a DC voltage and a timing signal necessary for the operation of the image pickup device are supplied. The operation of the frame memory 225 is also controlled by a signal from the timing signal generation circuit 424.

Next, the operation of the solid-state image pickup device of this embodiment will be described with reference to the timing chart of FIG.
At time t = t ₁ , the timing signal generation circuit 424
Control signals from the clock signal φ ₁ ^V and the clock signal φ ₂ ^V in the circuit example shown in FIG. 1 are changed from those in the normal imaging operation. For example, the clock signal φ ₁ ^V and the clock signal φ ₂ ^V are changed. The phase relationship of the ^V clock is reversed.

At this time, the reset potential V _RST is applied to the gate line selected by the vertical scanning circuit of the CMD image sensor 420 for each horizontal blanking period as shown in the right half surface of FIG.
Is applied, the read potential V _RD is applied,
The exposure time of each pixel from which the signal is read is one horizontal effective scanning period or less.

Therefore, the signal output by the incident light is one-hundredth of the number of scanning lines in one field. Therefore, when the image pickup device 420 is operated according to the NTSC standard, it is 0.4% or less,
It can be regarded as dark output. After this, time t = t ₂
6, the control signal from the timing signal generation circuit 424 causes the clock signal φ in the circuit example shown in FIG.
The phases of ₁ ^V and the clock signal φ ₂ ^V return to the normal phase relationship similar to those of the conventional example and the first embodiment of the present invention, and the operation in the normal imaging state is performed.

It should be noted that the read potential V is set every horizontal retrace period.
_When performing the operation of applying the reset potential V _RST prior to the application of _RD , the clock signal φ ₁ ^V
It becomes necessary to change the phase of and φ ₂ ^V. In order to supply these clock signals to the vertical scanning circuit, the image sensor 420
In addition, for example, it can be realized by changing the clock signal itself supplied from the timing signal generation circuit 424.

As another method, when the timing signal generating circuit 424 performs an operation of applying the reset potential V _RST prior to the reading of a signal at a low level during each normal image pickup operation and every horizontal blanking period, for example. Is high
The reset operation control signal φ _CNT that becomes a level is input to the solid-state image sensor 420, and by forming a drive pulse generation circuit as shown in FIG. It is possible to switch.

Here, for simplification, the case where the phase relationship between the clock signal φ ₁ ^V and the clock signal φ ₂ ^V is reversed between the normal read and the FPN signal read has been described, but of course the phase of the clock signal is reversed. The relationship is not limited to this. The point is that the state transition of the clock signal that determines the state transition of the output of the shift register unit circuit of the vertical scanning circuit is changed after the state of the clock signal transits during the normal signal readout and the signal readout of the selected pixel is performed. The phase is set so that the accumulated charge of the selected pixel is reset, while the signal is read out of the selected pixel after the accumulated charge of the selected pixel is reset during dark FPN signal reading. Setting the phase of the state transition of the clock signal. Further, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications and applications can be made without departing from the scope of the invention.

[0079]

As described above, according to the solid-state image pickup device of the present invention,
By using a CMD solid-state image pickup device and a solid-state image pickup device similar to this, no mechanical light-shielding means is required, a high-speed and large-capacity voltage buffer is not necessary, and an increase in power consumption is prevented. It has the FPN correction function of the CMD image sensor and a solid-state image sensor similar to this.

Further, the solid-state image pickup device of the present invention is
In addition to the fact that a normal video signal cannot be obtained for one field period in order to hold PN, the signal integration time of the pixels connected to each line is not uniform in the subsequent field because the operation is performed. In order to eliminate the disadvantage that a normal video signal cannot be obtained, the configuration is such that a normal video signal from the next field following the operation is obtained.
Further, since the circuit scale of the vertical scanning circuit does not increase, when a multi-pixel sensor is constructed, the yield problem and the deterioration are not caused, and even when the unit unit of the vertical scanning circuit with a narrow pitch is constructed, the circuit is It has an FPN correction function for a CMD image sensor and a solid-state image sensor similar thereto, which solves the disadvantage of the first embodiment of the present invention that the layout becomes practically difficult.

As described in detail above, according to the present invention, a high-speed and large-capacity voltage buffer is not required, and an increase in power consumption is suppressed, and an FPN of a CMD image pickup device and a solid-state image pickup device similar to the CMD image pickup device. A solid-state imaging device having a correction function can be provided.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a vertical scanning circuit portion of a solid-state image sensor used in a solid-state image sensor according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the solid-state imaging device shown in FIG.

FIG. 3 is a diagram showing a configuration example of a solid-state imaging device as a first embodiment according to the present invention.

4 is a timing chart showing a schematic drive signal sent from a timing signal generation circuit of the solid-state imaging device shown in FIG.

5 is a diagram showing a configuration of a drive pulse generation circuit for driving a vertical scanning circuit of the solid-state imaging device shown in FIG.

FIG. 6 is a diagram showing a configuration of a vertical scanning circuit portion of a solid-state imaging device used in a solid-state imaging device as a second embodiment according to the present invention.

FIG. 7 is a timing chart for explaining the operation of the solid-state image sensor shown in FIG.

FIG. 8 is a diagram showing a configuration example of a solid-state imaging device as a second embodiment according to the present invention.

9 is a schematic timing chart of drive signals sent from the timing signal generation circuit of the solid-state imaging device shown in FIG.
It is a chart.

10 is a diagram showing a configuration of a drive pulse generation circuit for driving the vertical scanning circuit shown in FIG.

FIG. 11 is a diagram showing a configuration example of a solid-state imaging device using a conventional CMD solid-state imaging device.

12 is a timing chart for explaining the operation of the conventional CMD solid-state imaging device shown in FIG.

13 is a diagram showing a configuration example for solving the problem of the solid-state imaging device using the conventional CMD solid-state imaging device shown in FIG.

FIG. 14 is a diagram showing another configuration example for solving the problem of the solid-state imaging device using the conventional CMD solid-state imaging device shown in FIG.

15 is a diagram showing a configuration example of a vertical scanning circuit of a solid-state image pickup element used in the solid-state image pickup device shown in FIG.

FIG. 16 is a timing chart when driving a conventional CMD solid-state imaging device.

[Explanation of symbols]

1, 222 ... Lens, 2 ... Image sensor, 3 ... Shutter, 4, 25, 225 ... Frame memory, 5, 26, 2
26 ... Differential amplifier, 6 ... Clock signal generation circuit, 7 ... Process circuit, 12, 212 ... Preamplifier, 17 ... Unit circuit, 20, 220 ... CMD image pickup device, 21 ... Power supply, 2
4, 224 ... Timing signal generating circuit, 27 ... Power supply switching switch circuit, 30, 31 ... P-channel type MOS
Transistor, 32 ... N-channel type MOS transistor, 33 ... V _OF switching N-channel type MOS transistor, 34 ... V _INT switching N-channel type M
OS transistor, 221 ... Power supply.

Claims (7)

[Claims] 1. A plurality of pixels arranged in a matrix, each including a transistor whose source / drain current is modulated by the amount of charge generated and accumulated by light irradiation as a constituent element, and each of the pixels in the periphery thereof. A read signal for reading the source / drain current corresponding to the accumulated charge of the pixel, a reset signal for discharging all the accumulated charge of the pixel, and one of the accumulated charges before the next read after resetting the pixel. A driving means for selectively applying an overflow signal for discharging the pixel to the gate of the pixel, and in accordance with an input state given to the logic control terminal from the outside, during the period when the overflow potential is applied, A solid-state image sensor including a driving unit that selectively applies the DC voltage of the solid-state image sensor to the gate of the pixel; A first means for holding a signal output, a second means for receiving an output of the solid-state image sensor and an output of a means for holding the all-pixel signal output, and an image signal; and an overflow potential of the solid-state image sensor. Is provided with timing signal generating means for generating a control signal to be applied to a logic control terminal for driving a driving means for selectively applying another DC voltage to the gate of the pixel. Solid-state imaging device. 2. The solid-state imaging device according to claim 1, wherein
A switch for outputting other DC voltage for each unit stage of each vertical scanning circuit is provided as driving means for selectively applying other DC voltage to the gate during a period when the overflow potential of the solid-state imaging device is applied. A solid-state imaging device characterized by the above. 3. The solid-state imaging device according to claim 2, wherein
A circuit for generating a clock for controlling other switches for outputting a DC voltage for each unit stage of each vertical scanning circuit of the solid-state imaging device according to claim 2, based on a control signal from the timing signal generating means. Is formed on the same substrate as the solid-state imaging device. 4. The solid-state imaging device according to claim 1, wherein
2. A solid-state image pickup device, wherein the phase of a clock for driving a shift register unit included in a unit stage of a vertical scanning circuit of the solid-state image pickup device according to claim 1 is changed and controlled by a control signal of a timing signal generating means. 5. The solid-state imaging device according to claim 4,
The state transition of the clock that determines the state transition of the output of the shift register unit circuit included in the unit stage of the vertical scanning circuit of the solid-state imaging device according to claim 4, the state of the clock transits, and the signal reading of the selected pixel is performed. And the first phase condition such that the accumulated charge of the selected pixel is reset, and the signal of the selected pixel is read after the accumulated charge of the selected pixel is reset. A solid-state imaging device, characterized in that any one of two phase conditions of a second phase condition in which a clock state transitions is controlled by a control signal of a timing signal generating means. 6. The solid-state imaging device according to claim 4,
5. A solid-state imaging device, wherein the phase of a two-phase clock driving a shift register unit included in a stage of a vertical scanning circuit of a solid-state imaging device according to claim 4 is reversed by a control signal of a timing signal generating means. 7. The solid-state imaging device according to claim 5,
A circuit for reversing a phase of a two-phase clock driving a shift register unit included in a stage of a vertical scanning circuit of the solid-state image pickup device according to claim 5 on the same substrate as the solid-state image pickup device is controlled by a control signal of a timing signal generating means. A solid-state imaging device characterized by being formed.