JP2001008109A - Solid state image pickup element, its driving method and camera system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state image pickup element preventing an electronic shutter(ES) scanning circuit from generating a difference in ES stages at the time of executing ES operation, a method for driving the image pickup element and a camera system. SOLUTION: Relating to the XY address type image pickup element for executing ES operation, dummy stages 23', 24' are added to both of a vertical scanning circuit 23 and an ES scanning circuit 24 so as to form the same number of stages as the total number of scanning lines of a video signal and a dummy pixel 28 is added to an image pickup area so that ES scanning pulses are continuously outputted from the dummy stage 24' at least for a vertical video period after the end of vertical scanning by the circuit 23.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image sensor, a method of driving the same, and a camera system, and more particularly to an XY address (scanning) type image sensor such as a MOS or CMOS image sensor and a method of driving the same. It relates to the camera system used.

[0002]

2. Description of the Related Art FIG. 1 shows a conventional example of an XY address type image pickup device.
0 is shown. Here, for the sake of simplicity of the drawing, as for the configuration of the unit pixel, only the pixels 101m and n in the m-th row and the n-th column are shown as an example. The pixels 101m and 101n include a photodiode 102, a readout transistor 103, an amplification transistor 104, a vertical selection transistor 105, X
It comprises a Y address transistor 106 and a reset transistor 107. A scanning system 108 in the row direction (vertical direction) and a scanning system 109 in the column direction (horizontal direction) are provided as peripheral circuits.

A scanning system 108 in the row direction includes a vertical scanning circuit 110 for performing read scanning, an electronic shutter scanning circuit 111 for performing electronic shutter scanning, and these scanning circuits 110 and 110.
An OR gate 112 that performs a logical operation on the read scan pulse and the electronic shutter scan pulse output from 111 is configured. A column-directional scanning system 109 is connected to a vertical signal line 113 wired for each column and selects a column of signal output from a pixel. And a horizontal scanning circuit 115.

Next, the basic operation of the XY address type image pickup device according to the conventional example having the above configuration will be described with reference to the pixel 1 in the m-th row and the n-th column.
The case of 01m, n will be described as an example.

The product of the vertical scanning pulse Vm in the m-th row and the horizontal reading scanning pulse H ^R n in the n-th column is obtained by the XY address transistor 106, and the result is given to the gate of the reading transistor 103. This allows
Advance before the pixel 101 m, to the gate of the amplifying transistor 104 is reset by the horizontal read scanning pulse H ^R n-1 of n-1, photoelectrically converted signal charges (here, electrons) in the photodiode 102 is read.

At the time of reading out the signal charges, the vertical scanning pulse Vm is at the selected state level, so that the vertical selection transistor 105 connected to the source of the amplification transistor 104 is conducting. As a result, the signal amplified by the amplification transistor 104 passes through the horizontal selection transistor 114 in a conductive state by the horizontal scanning pulse Hn from the horizontal scanning circuit 115, and further passes through the horizontal signal line 116.
Is output from the output terminal 117 via the.

[0007] When performing an electronic shutter, before the m-th row readout scanning is performed (forward by time of the shutter speed), unnecessary signal charges from the photodiode 102 by the electronic shutter scanning pulse V ^s m is read However, since the vertical selection transistor 105 is conductive only during the invalid period of the signal period of one pixel, the signal output of the pixel on which the read-out scanning is being performed is performed. Since no signal is output from the row where the scanning is performed, a normal video signal can be obtained without the signal of the row where the electronic shutter is being performed being overlaid on the signal of the reading row.

FIG. 11 and FIG. 12 show an XY according to a conventional example.
5 is a timing chart for explaining the operation of the address type imaging device. In these figures, VD is a vertical synchronization signal, and HD is a horizontal synchronization signal. φVS and φV1,
φV2 is a start pulse and a clock pulse of the vertical scanning circuit 110. φSS and φS1, φS2 are a start pulse and a clock pulse of the electronic shutter scanning circuit 111.

Vm-1, Vm and Vm + 1 are vertical read scanning pulses, which maintain a selected state throughout the horizontal video period for row selection. Vk-1, Vk, and Vk + 1 are electronic shutter scanning pulses for performing read reset for the electronic shutter, and the signal output of the row is m-
Only in a very short period of one pixel period, the pixel is intermittently selected during the horizontal video period so as not to be mixed with the signals output from the pixels of each row of 1, m, and m + 1.

[0010]

However, in the XY address type imaging device according to the above-mentioned conventional example, as shown in FIG. 13, the electronic shutter scanning pulse V ^sm (V ^s1 , V s
^s2 ,..., ^Vsm ,..., ^VsM ) are stopped during the vertical video period. The total number of vertical pixels in the imaging area is
Since there is no need to output signals during the vertical blanking period,
The number of rows is smaller than the number of vertical scanning lines including the vertical blanking period.

For this reason, the electronic shutter scanning circuit 1 whose number of stages is determined according to the total number of vertical pixels of the image pickup area.
In 11, scanning is started prior to the vertical scanning circuit 110 to control the shutter speed, and as a result, the power supply current flowing to the electronic shutter scanning circuit 111 is different or a vertical scanning pulse is electrostatically applied to the imaging region. Since the influence changes, an offset or a step in signal amplitude occurs in the image signal of the image sensor.

The effect on such a video signal is caused by the electronic shutter scan pulse V ^sm (V ^s1 , V ^s2,.
( ^Vsm ,..., ^VsM ) stop at a timing corresponding to a period during which a step appears in a horizontal band that moves up and down according to the shutter speed, as shown in FIG. Hereinafter, this is referred to as an electronic shutter step.

Regarding the effects of the current flowing through the electronic shutter scanning circuit 111 and the vertical scanning pulse on the image pickup area,
The mechanism can be explained as follows.

When the current flowing through the electronic shutter scanning circuit 111 changes, the power supply connected to the image sensor and the G
The potential of the ND line fluctuates considerably, and its power supply and GN
This appears as an offset step or a signal amount step of the video signal passing through the signal output circuit of the image sensor commonly connected to D.

As for the scanning pulse Vm, the vertical selection line 11 is wired so as to cross the imaging region and is connected to the gate of the vertical selection transistor 105 and the like.
8 is supplied with the scanning pulse Vm, P-We corresponding to the vertical selection line 118 and GND of the imaging area in terms of capacitance.
11 and the like, the discontinuity of the scanning pulse Vm becomes a potential variation such as GND in the imaging region, causing a gain variation and an offset variation of the amplifying transistor 104, and an offset level difference and a signal amount of the video signal. Appears as a step.

As is apparent from the above description, in the electronic shutter operation, the electronic shutter scanning circuit 111 starts scanning earlier by the time corresponding to the shutter speed before the vertical scanning circuit 110 performs scanning. In many cases, the scanning circuit 111 finishes scanning the imaging region during the video period. At the time when the scanning is completed, the current flowing through the vertical scanning circuit 110 decreases, or the vertical selection line 1
Since there is no electronic shutter scan pulse applied to 18,
Before and after the scanning of the electronic shutter scanning circuit 110, the amplitude and level of the video signal output of the image sensor are affected to a considerable extent. A step is generated.

That is, the vertical scanning circuit 110 relating to the reading of pixel signals operates continuously during the vertical video period and outputs a vertical scanning pulse, and the start and end of the scanning do not occur during the video period ( On the other hand, since the electronic shutter scanning circuit 111 starts the electronic shutter scanning earlier by the shutter speed before the vertical scanning circuit 110, the electronic shutter scanning starts and ends. It may occur during a video period, and such an operation has affected a video signal output from the image sensor.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has as its object to provide a solid-state imaging device in which an electronic shutter scanning circuit does not generate an electronic shutter step when performing an electronic shutter operation. An object, a driving method thereof, and a camera system are provided.

[0019]

In order to achieve the above object, according to the present invention, each pixel of an image pickup area having a plurality of pixels arranged in a matrix is vertically scanned in units of rows.
Prior to the selection of each row by the vertical scanning, in a solid-state imaging device that sequentially outputs an electronic shutter scanning pulse and performs an electronic shutter operation by performing a reset operation of pixels of each row, at least during a vertical video period after the end of vertical scanning. The electronic shutter scanning pulse is continuously output.

In the solid-state image pickup device which performs the electronic shutter operation, the electronic shutter scan pulse is continuously output at least during the vertical video period even after the end of the vertical scan. The output of the electronic shutter pulse does not stop during the vertical video period. In other words, the electronic shutter pulse is output at least in all the horizontal scanning periods within the vertical video period. As a result, at least in the video period, the current flowing through the electronic shutter scanning circuit does not change, and the influence of the vertical scanning pulse on the imaging region electrostatically does not change. A step can be prevented from occurring.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic configuration diagram showing an XY address type imaging device according to the first embodiment of the present invention. Here, for the sake of simplicity of the drawing, as for the configuration of the unit pixel, only the pixels 11m and n in the m-th row and the n-th column are shown as an example. It is.

In FIG. 1, a pixel 11m,
n is a photodiode 12 which is a photoelectric conversion element, an NchMOS transistor (reading transistor) 13 functioning as a gate for reading out signal charges from the photodiode 12, and an NchMOS functioning as an amplifying element
A transistor (amplification transistor) 14, an NchMOS transistor (vertical selection transistor) 15 functioning as a switch for vertically selecting a pixel, an NchMOS transistor (XY address transistor) 16 for specifying addresses in the horizontal and vertical directions, and a switch for resetting the pixel And an NchMOS transistor (reset transistor) 17 functioning as a transistor.

In the pixels 11m and n having the above configuration, the cathode of the photodiode 12 is connected to the source of the readout transistor 13. The gate of the amplification transistor 14 and the source of the reset transistor 17 are connected to the drain of the read transistor 13, respectively. The drain of the reset transistor 17 is connected to the power supply VDD. The drain of the vertical transistor 15 is connected to the source of the amplification transistor 14.

The source of the vertical transistor 15 is connected to a vertical signal line 18. Vertical select transistor 15
Is connected to a vertical selection line 19 wired so as to cross the imaging region. Read transistor 1
The source of the XY address transistor 16 is connected to the gate of No. 5. The drain of the XY address transistor 16 is connected to the horizontal selection line 20, and the gate is connected to the vertical selection line 19.

A vertical scanning system 21 is provided around the imaging area.
And a horizontal scanning system 22. Vertical scanning system 2
Reference numeral 1 denotes a vertical scanning circuit 23 that performs read scanning, an electronic shutter scanning circuit 24 that performs electronic shutter scanning, and an OR gate 25 that performs a logical operation on the read scanning pulse and the electronic shutter scanning pulse output from these scanning circuits 23 and 24. It is configured. The horizontal scanning system 22 is connected to a vertical signal line 18 wired for each column, and selects a column from which a signal output from a pixel is output. The horizontal selection transistor 26 supplies a horizontal scanning pulse to the horizontal selection transistor 26 sequentially. The scanning circuit 27 is configured.

In this embodiment, in addition to the image pickup area where the signal is output during the image period, the number of vertical pixels of the image pickup element according to the conventional example and the image Dummy stages 23 'and 24' are added to the vertical scanning circuit 23 and the electronic shutter scanning circuit 24 by the number of stages corresponding to the difference in the total number of signal scanning lines, and the dummy pixels 2 corresponding thereto are added.
8 is added. Each scanning pulse output from the dummy stages 23 'and 24' is O
The signal is supplied to the dummy vertical selection line 30 through the R gate 29.

FIG. 2 is a timing chart for explaining the operation of the XY address type image pickup device according to the first embodiment having the above configuration. In this timing chart, the start pulse .phi.VS, .phi.SS, a vertical scanning pulse V ^R m (V ^{R
1, V R 2, ...,} V R m, ..., V R M) and the electronic shutter scan pulse ^{V S m (V S 1,} V S 2, ..., V S m, ..., V S M) is a conventional The timing relationship is the same.

Further, the timing chart of FIG. 2 shows an example in which the total number of lines in the image pickup area to which a signal is output in the video period is M lines, and i-line pixels are added as dummy pixels 28. I have. At this time, from the vertical scanning circuit 23, a vertical scanning pulse ^{V R 1, V R 2,} ...,
^{V R m, ..., V R} M, V R M + 1, ..., V R M + i are output sequentially. Also, from the electronic shutter scanning circuit 24, the electronic shutter scanning pulse ^{V S 1, V S 2,} ..., V S m, ..., V S M, V S
^{M + 1, ..., V S} M + i is output to the order.

As described above, the XY according to the first embodiment
In the address type image pickup device, dummy stages 23 'and 24' are added to the vertical scanning circuit 23 and the electronic shutter scanning circuit 24 and a dummy pixel 28 is added so that the number of stages is equal to the total number of scanning lines of the video signal. As a result, FIG.
As can be seen from the timing charts, both the vertical scanning circuit 23 and the electronic shutter scanning circuit 24 output the scanning pulse of the first row in synchronization with the respective start pulses φVS, φSS, and the last row M + i of the dummy stage.
When the scanning is completed up to this point, the next vertical scanning period is started, so that scanning is continuously and again started from the first row.

[0030] Thus, the electronic shutter scanning pulse is outputted from the electronic shutter scanning circuit ^{24 V S m (V S 1} , V
^{S 2, ..., V S m} , ..., V S M, V S M + 1, ..., V S M + i) is to be always outputted to all of the horizontal scanning period, thus the electronic shutter scanning circuit 24 Current flowing through the electronic shutter scanning circuit 24 is not different for each horizontal scanning period, so that irregular potential fluctuations flowing from the power supply of the electronic shutter scanning circuit 24 to the output circuit of the image sensor are suppressed.

Furthermore, since the electronic shutter scanning pulse V ^S m applied without interruption in the imaging area in the video period, the offset step or amount of signal level difference due to the presence or absence of the scan pulse to the output signal from the pixel is suppressed. As a result, since the influence of the current and the electronic shutter scanning pulse flowing through the electronic shutter scanning circuit 24 V ^S m has on the imaging area is the continuous, electronic shutter step in question in the prior art (FIG. 14
) Are removed very well.

FIG. 3 is an XY diagram according to a second embodiment of the present invention.
FIG. 2 is a configuration diagram illustrating an address type imaging device. Here, for the sake of simplicity of the drawing, as for the configuration of the unit pixel, only the pixel 31m, n in the m-th row and the n-th column is shown as an example, but it is needless to say that the other pixels have exactly the same configuration. It is.

In FIG. 3, a pixel 31m in an m-th row and an n-th column is provided.
n is a photodiode 32, a readout transistor 33, an amplification transistor 34, a vertical selection transistor 35, an XY address transistor 36, and a reset transistor 3 as in the case of the imaging device according to the first embodiment.
7.

In the pixels 31m and n having the above-described configuration, the cathode of the photodiode 32 is connected to the source of the readout transistor 33. The gate of the amplification transistor 34 and the source of the reset transistor 37 are connected to the drain of the read transistor 33, respectively. The drain of the reset transistor 37 is connected to the power supply VDD. The drain of the vertical transistor 35 is connected to the source of the amplification transistor 34.

The source of the vertical transistor 35 is connected to a vertical signal line 38. Vertical select transistor 35
Are connected to a vertical selection line 39 wired so as to cross the imaging region. Read transistor 3
The source of the XY address transistor 36 is connected to the gate of No. 5. The drain of the XY address transistor 36 is connected to the horizontal selection line 40, and the gate is connected to the vertical selection line 39.

A vertical scanning system 41 is provided around the imaging area.
And a horizontal scanning system 42. And the first
As in the case of the XY address type imaging device according to the embodiment, the vertical scanning system 41 includes a vertical scanning circuit 43, an electronic shutter scanning circuit 44, and an OR gate 45,
The horizontal scanning system 42 includes a horizontal selection transistor 46 and a horizontal scanning circuit 47.

In this embodiment, the vertical scanning system 41 further includes a vertical scanning circuit 43 and an electronic shutter scanning circuit 44.
Is connected to one (or a plurality of) self-running cyclic scanning circuits 48 and 49 at the final stage (M-th stage), and outputs a signal corresponding to the dummy pixel 50 during the video period. In this case, a configuration is added in which the imaging region is added. Each scanning pulse output from the self-propelled scanning circuits 48 and 49 is O
The data is supplied to a dummy vertical selection line 52 through an R gate 51.

The self-propelled scanning circuits 48 and 49 receive the respective scanning pulses of the vertical scanning circuit 43 and the electronic shutter scanning circuit 44 and start operating. The self-propelled scanning circuit 49 on the electronic shutter scanning circuit 44 side operates as follows. As shown in the timing chart of FIG. 4, an electronic shutter scanning pulse V ^S M + 1 is generated during a period in which an electronic shutter step occurs in an XY address type image sensor according to a conventional example.

However, if the self-propelled scanning circuits 48 and 49 are left as they are, the scanning pulse continues to be output. Therefore, as is apparent from the timing chart of FIG. A stop pulse φSR is applied to stop the operation. Similarly, the self-propelled scanning circuit 48 on the side of the vertical scanning circuit 43 is stopped by giving the self-propelled stop pulse φSR at an appropriate timing.

In the timing chart of FIG. 4, the start pulses φVS, φSS and the vertical scanning pulse V ^Rm (V
^{R 1, V R 2, ...} , V R m, ..., V R M) and the electronic shutter scan pulse ^{V S m (V S 1,} V S 2, ..., V S m, ..., V S M) is conventionally It has the same timing relationship as. The vertical scanning pulse V ^R output from the self-propelled scanning circuits 48 and 49
The ^{M + 1, V S M +} 1, will occur continuously by the number of stages of the XY address type image pickup difference number of vertical pixels and the video signal total number of scanning lines of the device according to the conventional example.

As described above, the XY according to the second embodiment
The address type image pickup device, as well as add a self-propelled scanning circuit 49 to the vertical scanning circuit 43 and the electronic shutter scanning circuit 24, by adding the dummy pixels 50, the electronic shutter scanning pulse V ^S m (V ^S 1, V ^S 2,…,
^{V S m, ..., V S} M, V S M + 1) for is to be always outputted to all of the horizontal scanning period, for the same reason as in the first embodiment, to suppress the electronic shutter step be able to.

That is, since the current flowing through the electronic shutter scanning circuit 44 does not differ for each horizontal scanning period, irregular potential fluctuations from the power supply of the electronic shutter scanning circuit 44 to the output circuit of the image sensor are suppressed. . Furthermore, since the electronic shutter scanning pulse V ^S m applied without interruption in the imaging area in the video period, the offset step or amount of signal level difference due to the presence or absence of the scan pulse is suppressed in the output signal from the pixel. As a result, since the influence of the current and the electronic shutter scan pulse V ^S m flowing through the electronic shutter scanning circuit 44 is applied to the imaging area is continuous, the electronic shutter step is very well removed.

FIG. 5 is a circuit diagram showing a specific circuit example of the electronic shutter scanning circuit 44 and a one-stage self-propelled scanning circuit 49 connected to the last stage thereof.

In FIG. 5, the electronic shutter scanning pulse V
^{S 1, V S 2, ...} , V S m, ..., circuits at the respective stages to V ^S M is
It comprises a general dynamic shift register comprising switching transistors 61 and 63 and CMOS inverters 62 and 64. Then, the logical product of the output of each stage of the shift register and the horizontal synchronizing signal HD and the read timing pulse is obtained by the AND gate 65, and the logical product output of the AND gate 65 is used as the electronic shutter scan pulses V ^S1 and V ^S. 2, ..., V ^S m, ..., V ^S M.

On the other hand, self-propelled scanning circuit 49 for generating an electronic shutter scanning pulse V ^S M + 1 is a typical dynamic shift register composed of switching transistors 61 and 63 and CMOS inverters 62 and 64 as a basic configuration, which In addition to the above, an OR gate 66 for calculating the logical sum of the output of the own stage and the output of the last stage of the vertical scanning circuit 44, and the CMOS inverter 6 in response to the free-running stop pulse φSR
Stop transistor 6 that connects the input terminal 2 to GND
7 and a stop transistor 69 that connects the input terminal of the CMOS inverter 54 to a power supply in response to the self-running stop pulse φSR inverted by the inverter 68.

The self-propelled scanning circuit 49 having the above configuration continuously outputs pulses in response to the output of the preceding stage, that is, the output of the last stage of the vertical scanning circuit 44. The output pulse is supplied to the AND gate 65 in the same manner as the output of each stage of the vertical scanning circuit 44.
Logical product of the horizontal synchronizing signal HD and read timing pulse taken at the logical product output of the AND gate 65 becomes the electronic shutter scanning pulse V ^S M + 1. Also, when self-running stop pulse φSR is given, CMO
When the input terminal of the S inverter 62 is grounded and the input terminal of the CMOS inverter 54 is pulled up to a power source, the self-running is stopped.

FIG. 6 is a timing chart showing a detailed timing relationship from when the self-propelled scanning circuit 49 starts outputting a pulse to when it stops. In this timing example, the self-propelled scanning circuit 49 outputs the electronic shutter scanning pulse V ^S
A case is shown in which three self-propelled stop pulses φSR are generated and then stopped after three M + 1s are output. The start pulse φSS rises and the electronic shutter scanning pulse V ^S 1 is output so that the scanning of the first row starts again from the next horizontal scanning period in which the self-propelled scanning circuit 49 stops.

Next, a third embodiment of the present invention will be described. The third embodiment is structurally applied to an XY address type imaging device according to a conventional example having the configuration shown in FIG. That is, the electronic shutter scanning circuit is devised without changing the structure of the XY address type image pickup device according to the conventional example, thereby preventing the electronic shutter level difference. The drive timing is shown in FIG. 7 and FIG.

FIG. 7 is a timing chart of the vertical synchronization. In this timing chart, VD is a vertical synchronization signal, and HD is a horizontal synchronization signal. .phi.V1, vertical clock pulse in the vertical scanning circuit 110 of φV2 FIG 10, .phi.VS its vertical scanning start pulse, V ^R 1, V ^R
2, ..., V ^R M is a vertical scanning pulse. φS1, φS2
Clock pulses, .phi.SS electronic shutter scanning start pulse in the electronic shutter scanning circuit 111, V ^S 1,
^{V S 2, ..., V S} M is the electronic shutter scanning pulse.

When the vertical scanning start pulse φVS rises, the vertical scanning pulse rises in each horizontal scanning period from V ^R 1 to control the pixel readout row. On the other hand, since the shutter speed of the electronic shutter is determined by the time difference from the vertical scanning start pulse φVS, the electronic shutter scan start pulse φSS is kept at an appropriate position in accordance with the desired shutter speed. Electronic shutter scanning pulse by the electronic shutter scanning start pulse φSS stood for each order horizontal scanning period from V ^S 1, to reset the signal charge accumulated in the pixels.

Here, features of the third embodiment will be described. One is the electronic shutter scan pulse V
^{S 1, V S 2, ...} , V S M is, so as not to be output for a horizontal scanning period, a dummy scanning start pulse as an electronic shutter scanning start pulse φSS when the opportunity arises which the electronic shutter scanning circuit 111 has finished scanning To stand up.

The other one is that the electronic shutter scanning pulses V ^S1 , V ^S2 ,..., V ^S M output from the electronic shutter scanning circuit 111 by the dummy scanning start pulse and the original electronic shutter scanning start pulse. Is to insert a dummy scan stop pulse as the clock pulses φS1 and φS2 of the electronic shutter scanning circuit 111 immediately before the electronic shutter scan start pulse rises so as not to be output.

FIG. 8 is a timing chart showing an enlarged portion of the dummy scanning stop pulse in the time axis direction so that the phase relationship can be understood. The specific circuit configuration of the electronic shutter scanning circuit 111 is shown in FIG.
It is assumed that the circuit configuration is the same as that of the electronic shutter scanning circuit 44 in the second embodiment shown in FIG.

Such a switching transistor 6
1 and 63 and CMOS inverters 62 and 64 generate a clock pulse φ.
The shift register normally operates in a state where the phases of S1 and φS2 are not different. However, if the phases of the clock pulses φS1 and φS2 are overlapped, a pulse to be scanned disappears due to a phenomenon called so-called racing,
As a result, the electronic shutter scanning circuit 111 is reset.

Conversely, utilizing this phenomenon, the electronic shutter scan pulse V ^S 9 in FIG.
By setting a dummy scan stop pulse in which the phases of the clock pulses φS1 and φS2 are superimposed before overlapping with ^S 1,
The electronic shutter scanning circuit 111 can be reset. As a result, the electronic shutter scanning pulse is always output from the electronic shutter scanning circuit 111 during all horizontal scanning periods, and the electronic shutter step does not occur.

As described above, the XY according to the third embodiment
In the address type imaging device, when the electronic shutter scanning circuit 11 makes one round of scanning of the imaging area, the electronic shutter scanning circuit 1
11. A dummy scan start pulse is applied to the electronic shutter 11 and the electronic shutter scanning circuit 111 is reset immediately before the next electronic shutter scan is started. As a result, the output is continuously performed without interruption, so that the electronic shutter step can be removed for the same reason as in the first embodiment.

In particular, in the case of the third embodiment, the intended purpose can be achieved only by changing the drive timing of the electronic shutter scanning circuit 111, and the conventional XY address type image pickup device can be used as it is. There is an advantage that an XY address type imaging device capable of preventing a shutter step beforehand can be provided at low cost.

Although the electronic shutter scanning circuit including the dynamic shift register having the circuit configuration shown in FIG. 5 has been described with reference to the case where the lacing of the shift register is used, the present invention is not limited to this. Also, the present invention can be applied to an electronic shutter scanning circuit having a circuit configuration capable of causing racing by a clock pulse or the like.

As a modification of the third embodiment, FIG.
It is possible to use the reset transistors 67 and 69 for resetting the self-propelled scanning circuit 49 having the circuit configuration shown in FIG.

FIG. 9 is a schematic diagram showing an example of a camera system according to the present invention. In FIG. 9, incident light (image light) from a subject (not shown) is formed on an imaging surface of an XY address type imaging device 72 by an optical system including a lens 71 and the like. As the XY address type imaging device 72,
The XY address type imaging device according to the above-described first, second or third embodiment of the present invention or its modification is used.

The XY address type image pickup device 72 is driven based on various timing signals output from a drive circuit 73 including a timing generator and the like. X
The imaging signal output from the Y-address type imaging device 72 is
After being subjected to various signal processing in the signal processing circuit 74, the signal is output as a video signal.

In the camera system having the above configuration, XY
By using the XY address type image pickup device according to the first, second or third embodiment of the present invention or its modification as the address type image pickup device 72, the image pickup device can suppress the electronic shutter step. In addition, it is possible to provide a good imaging screen without an electronic shutter step.

[0063]

As described above, according to the present invention,
In the solid-state imaging device performing the electronic shutter operation, the driving method thereof, and the camera system, the electronic shutter scan pulse is continuously output at least during the vertical image period even after the end of the vertical scan, so that at least the vertical image period is not changed. Since the electronic shutter pulse is output in all the horizontal scanning periods, it is possible to suppress the occurrence of the offset and the step of the signal amplitude in the image signal of the image sensor, and as a result, it is possible to reliably prevent the step of the electronic shutter. Become.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing an XY address type solid-state imaging device according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the XY address type solid-state imaging device according to the first embodiment.

FIG. 3 is a schematic configuration diagram illustrating an XY address type solid-state imaging device according to a second embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the XY address type solid-state imaging device according to the second embodiment;

FIG. 5 is a circuit diagram showing specific circuit examples of an electronic shutter scanning circuit and a free-running scanning circuit.

FIG. 6 is a timing chart for explaining the operation of the self-propelled scanning circuit.

FIG. 7 is a timing chart (part 1) according to a third embodiment of the present invention.

FIG. 8 is a timing chart (part 2) according to the third embodiment of the present invention.

FIG. 9 is a schematic configuration diagram showing a camera system according to the present invention.

FIG. 10 is a schematic configuration diagram showing an XY address type solid-state imaging device according to a conventional example.

FIG. 11 is a timing chart according to a conventional example (part 1).
It is.

FIG. 12 is a timing chart according to a conventional example (part 2).
It is.

FIG. 13 is a timing chart according to a conventional example (part 3).
It is.

FIG. 14 is a diagram illustrating an electronic shutter step that occurs on an imaging screen.

[Explanation of symbols]

11m, n, 31m, n: pixels, 23, 43: vertical scanning circuit, 24, 44: electronic shutter scanning circuit, 23 ', 2
4 ': dummy stage, 27, 47: horizontal scanning circuit, 2
8, 50: dummy pixel, 48, 49: self-propelled scanning circuit

Claims (6)

[Claims] An imaging region having a plurality of pixels arranged in a matrix; a vertical scanning circuit for sequentially outputting vertical scanning pulses to vertically scan each pixel in the imaging region in row units; Prior to the selection of each row, the electronic shutter scan pulse is sequentially output to reset the pixels in each row, and the electronic shutter scan pulse is continuously output at least during the vertical video period after the vertical scanning by the vertical scanning circuit is completed. A solid-state imaging device comprising an electronic shutter scanning circuit. 2. The solid-state imaging device according to claim 1, wherein said vertical scanning circuit and said electronic shutter scanning circuit have the same number of stages as the total number of scanning lines of a video signal. 3. The electronic shutter scanning circuit has a self-propelled scanning circuit connected to a final stage thereof, and stops the self-propelled scanning circuit immediately before the next vertical scanning starts. The solid-state imaging device according to claim 1. 4. When the electronic shutter scanning circuit makes one round of scanning of the image pickup area, a dummy scan start pulse is applied to the electronic shutter scanning circuit, and the electronic shutter scanning circuit immediately before the next electronic shutter scanning starts. 2. The solid-state imaging device according to claim 1, wherein reset is performed. 5. Each row of an image pickup area having a plurality of pixels arranged in a matrix is vertically scanned on a row-by-row basis, and an electronic shutter scan pulse is sequentially output prior to selection of each row by the vertical scanning. A solid-state imaging device that performs a reset operation of the pixel described in (1), wherein the electronic shutter scanning pulse is continuously output at least during a vertical video period after the end of vertical scanning. 6. An imaging region having a plurality of pixels arranged in a matrix, a vertical scanning circuit for sequentially outputting vertical scanning pulses and vertically scanning each pixel of the imaging region in row units, and the vertical scanning circuit. Prior to the selection of each row, the electronic shutter scan pulse is sequentially output to reset the pixels in each row, and the electronic shutter scan pulse is continuously output at least during the vertical video period after the vertical scanning by the vertical scanning circuit is completed. A camera system using a solid-state imaging device having an electronic shutter scanning circuit.