JPH06113215A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To obtain a solid-state image pickup device formed such that the scanning mode is switched with a simple control and the difference from the image quality due to the scanning mode is not caused. CONSTITUTION:The device is provided with 1st and 2nd vertical scanning circuits 5L, 5R in which picture elements 1 are arranged in a 2-dimensional array and the picture elements arranged in the row direction are scanned via a vertical selection line. Furthermore, each scanning unit of the 1st vertical scanning circuit 5L corresponds to each vertical selection line of an odd numbered order and each scanning unit of the 2nd vertical scanning circuit 5R corresponds to each vertical selection line of an even numbered order. A clock group driving each of the vertical scanning circuits 5L, 5R is controlled to select the scanning mode by a control clock generating circuit 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device capable of supporting both interlaced scanning and non-interlaced scanning.

[0002]

2. Description of the Related Art A conventional two-line mixed interlaced scanning system (hereinafter simply referred to as interlaced scanning), which is generally used as a standard television system, is applied to an XY address type image sensor. As disclosed in Japanese Patent Laid-Open No. 58-53830,
A configuration is known in which an interlace circuit is provided between a vertical scanning circuit and a vertical selection line. FIG. 24 shows a configuration example thereof. The image sensor of this configuration example includes a pixel composed of photoelectric conversion elements arranged in a two-dimensional array, a horizontal scanning circuit for column selection, a horizontal selection switch 3 connected to a horizontal selection line 3, and an output signal line 4. , A vertical scanning circuit 5 for row selection, and an interlace circuit 6.
Then, for the pixels in the two columns in the vertical direction,
Bits correspond to each other, and the interlace circuit 6 controlled by the control signals F1 and F2 selects the vertical selection lines V1, V2, V3, ...

By the way, recently, video cameras have been actively used for industrial or measurement purposes. In addition to standard television interlaced scanning, sequential scanning in which each vertical selection line can be independently selected, There is an increasing need for an image sensor that is compatible with so-called non-interlaced scanning.

However, non-interlaced scanning cannot be performed with an image sensor having a configuration compatible with the standard television system as shown in FIG. Therefore, there has been proposed a configuration of a vertical scanning circuit capable of supporting two types of scanning modes, interlaced scanning and non-interlaced scanning. For example, Japanese Patent Application Laid-Open No. 63-292773 discloses a structure in which a scanning mode control circuit is provided between a vertical scanning circuit and a vertical selection line. FIG. 25 shows the configuration. Figure
Compared with the configuration shown in 24, only the configuration of the scanning mode control circuit 7 that connects the vertical scanning circuit 5 and the vertical selection lines V1, V2, V3, ... That is, the gates of the _three selection MOS transistors Q ₁ , Q ₂ , and Q ₃ are connected to the output terminals of the vertical scanning circuit 5, and the MOS transistor Q ₁ is driven by the drive bias B1.
To the vertical selection lines V1, V3, V5, ..., and the MOS transistor Q ₂ uses the drive bias B2 as the vertical selection lines V2, V5.
4, V6, to ..., MOS transistor Q ₃ are drive bias B3 vertical selection lines V1, V3, V5, which is configured to sequentially transfer ..., hence the drive bias B1, B2, B3 The scanning mode can be controlled by applying a suitable combination. Further, based on the completely same idea, the output of the vertical scanning circuit 5 directly outputs the vertical selection lines V1, V2, V3, ... As shown in FIG.
It is also possible to use the scan mode control circuit 8 configured to drive the.

[0005]

By the way, when a video camera system capable of capturing images in two kinds of scanning modes of interlace and non-interlace is constructed by using the image sensor having the construction shown in FIGS. There is a problem that the relationship between the timing of vertical scanning and the timing of horizontal scanning is broken at the time of switching. That is, it is necessary to change the clock frequency for vertical scanning or horizontal scanning when switching the scanning mode. For example, when the clock frequency for horizontal scanning is fixed and the data rate of the output from the image sensor is the same between both scanning modes, that is, when the frame rates are the same, the frequency of the clock that drives the vertical scanning circuit during non-interlaced scanning. Must be halved for interlaced scanning. Then, it is necessary to provide a timing control circuit including a frequency control of a clock therefor inside or outside the image sensor.

Further, in the image sensor having the structure shown in FIGS. 25 and 26, the number of selection MOS transistors connected to the vertical selection lines V1, V2, V3, ... That is, odd-numbered vertical selection lines V3, V5
V7, ... Two for the even-numbered vertical selection lines V2, V
One MOS transistor is connected to 4, V6, .... Therefore, in this configuration, the parasitic capacitance of the vertical selection line is different for each line, which causes a horizontal stripe-shaped fixed pattern noise. This phenomenon appears differently in interlaced scanning and non-interlaced scanning. During interlaced scanning, two vertical selection lines with different parasitic capacitances are always selected as a pair, so the effect of the difference in parasitic capacitance is mitigated to a large extent, but during non-interlaced scanning, each vertical selection line is independent. Therefore, the influence of the difference in parasitic capacitance will be affected properly. As a result, there is a difference in image quality between the scanning modes.

Furthermore, the image sensor having the structure shown in FIG. 26 has a problem that the load of the buffer circuit for driving the vertical selection line included in the vertical scanning circuit 5 varies depending on the scanning mode. In the case of interlaced scanning, the vertical scanning circuit has two vertical selection lines for one bit, but in the case of non-interlaced scanning, there is one vertical selection line.
The difference in the load of the buffer circuit causes a difference in the bias applied to the pixels, resulting in a difference in image quality depending on the scanning mode.

The present invention has been made in order to solve the above-mentioned problems in the conventional solid-state image pickup device capable of switching the scanning modes, and the scanning modes can be switched by simple control, and a difference in image quality occurs depending on the scanning modes. It is an object of the present invention to provide a solid-state imaging device configured so as not to have it.

[0009]

In order to solve the above problems, the present invention provides a plurality of photoelectric conversion elements arranged in a two-dimensional array and the photoelectric conversion elements arranged in a column direction. Corresponding to a horizontal selection line group provided correspondingly, a horizontal scanning circuit for scanning photoelectric conversion elements arranged in the column direction through the horizontal selection line group, and the photoelectric conversion elements arranged in the row direction In the solid-state imaging device, the solid-state imaging device includes: a vertical selection line group provided in a row, and first and second vertical scanning circuits that scan the photoelectric conversion elements arranged in a row direction through the vertical selection line group. Each of the first and second vertical scanning circuits is composed of a plurality of stages of scanning units, and one scanning unit of the first vertical scanning circuit is provided for each odd-numbered vertical selection line of the vertical selection line group. Corresponding to the pair 1 and the second drop Each scanning unit of the scanning circuit is made to correspond to each even-numbered vertical selection line of the vertical selection line group in a one-to-one correspondence, and a clock group for driving the first and second vertical scanning circuits is controlled. Then, a control clock generating means for switching the scanning mode is provided.

As described above, the first and second vertical scanning circuits are provided, and the control clock generating means controls the clock groups input to both the vertical scanning circuits to switch between interlaced scanning and non-interlaced scanning. Moreover, it is not necessary to change the frequency of the drive clock of the vertical scanning circuit when switching the scanning modes, and it is possible to realize a solid-state imaging device in which there is no difference in image quality between scanning modes.

[0011]

EXAMPLES Next, examples will be described. FIG. 1 is a diagram showing a schematic configuration of a first embodiment of a solid-state imaging device according to the present invention, in which the same or corresponding members as those of the conventional example shown in FIGS. The description is omitted. The present invention, as shown in the embodiment of FIG. 1, is characterized by the absence of a scanning mode control circuit and the provision of two vertical scanning circuits as compared with the conventional example shown in FIGS. Is.

Next, the structure of the first and second vertical scanning circuits 5L and 5R, which are the main features of the present invention, will be specifically described. The first and second vertical scanning circuits 5L and 5R
Have the same circuit configuration and are different only in the connection to the vertical selection line group. That is, the first vertical scanning circuit 5L is connected to the odd-numbered vertical selection lines L1, L2, ...
The second vertical scanning circuit 5R includes even-numbered vertical selection lines R1 and R.
2, ... are respectively connected. First, prior to the description of these vertical scanning circuits, constituent columns of a shift register used in a conventional vertical scanning circuit will be described with reference to FIG. This configuration example is a system in which two units of clocked inverters constitute one unit 9, and a schematic conceptual diagram of this is shown in FIG. FIG. 4 shows the operation timing. The clock has two phases of Φ1 and Φ2, and when the start pulse ΦST is applied to the input of the first stage unit 9, the output terminals SR1 and SR of each shift register unit 9 are synchronized with the rising of the clock Φ1.
2, SR3, ..., Sequential output is performed. Note that in FIG. 2, / Φ1, / Φ2 is Φ1,
The inverted clock of Φ2 is shown.

Next, the first and second embodiments of the present invention will be described.
FIG. 5 shows a part of a configuration example of a scanning circuit used for the vertical scanning circuits 5L and 5R. Unit 19 that constitutes this scanning circuit
Is a pulse shift unit 19A with two clocked inverter stages similar to the conventional shift register shown in FIG.
And an output pulse generation unit 19B that generates a pulse by detecting the rising transition of the shift pulse of the unit 19A.
It consists of and. In FIG. 5, the second-stage unit is shown as a representative, and SR2.5 indicates the first-stage output terminal of the two-stage clocked inverter that constitutes the pulse shift unit 19A. FIG. 6 shows the operation timing. The clock has three phases of Φ0, Φ1, and Φ2.
By applying the start pulse ΦST to the input of the first-stage pulse shift unit 19A, the output terminals S1, S2, S3, ... Of the output pulse generation units 19B sequentially output in synchronization with the rising of the clock Φ1. It has become so. It is clear that when Φ0 is the same clock as Φ1 in FIG. 6, the output is the same as the output shown in the timing chart (FIG. 4) of the conventional shift register shown in FIGS. 2 and 3.

On the other hand, the shift register of this embodiment can operate in different operation modes other than the operation mode shown in FIG. FIG. 7 shows an example of the operation timing. The difference from the operation mode shown in the timing chart of FIG.
Of the phase clocks Φ0, Φ1, and Φ2, pulses are applied to the clocks Φ0 and Φ2 at the same timings as in the operation mode of FIG. 6, but the clock Φ1 has a period twice that of the clock Φ0 unlike the operation mode of FIG. That is, the high level of the clock Φ0 is applied as the clock Φ1 in the pulse lost every cycle. By applying such clocks Φ0, Φ1, and Φ2, the pulse shift unit 19A is driven by the clocks Φ1 and Φ2, so the pulse shift cycle is the cycle of the clock Φ1:
T ₁ = 2 · T ₂ = 2 · T ₀ (T ₂ : cycle of clock Φ2, T ₀ : cycle of clock Φ0), and output pulse generation unit that detects rising transition of shift pulse and generates pulse Since 19B is driven by the clock Φ0 and the output of the pulse shift unit 19A, the output terminal S of each output pulse generation unit 19B of the shift register.
1, S2, S3, ... The effective pulse width of the selection pulse is the period of the clocks Φ0 and Φ2: T ₀ = T ₂ =
It becomes T _1/2 .

Next, a case where the operation mode of the shift register shown in FIGS. 6 and 7 is applied to the vertical scanning circuit of the embodiment shown in FIG. 1 will be described. FIG. 8 shows a configuration example of a solid-state image pickup device in the case where the operation mode of the shift register is applied to the embodiment shown in FIG. In FIG. 8, only terminals related to the skeleton of the operation are shown, but in order to drive the field index pulse FI for identifying the first field and the second field and the first and second vertical scanning circuits 5L, 5R. Of the basic clocks Φ1 and Φ2, and the vertical scanning start pulse ΦST are provided, and the field index pulse FI, the clocks Φ1, Φ2, and the start pulse ΦST input to the circuit 21 are the first And pulse groups Φ0-L, Φ1-L, Φ2-L, and ΦST input to the second vertical scanning circuits 5L and 5R.
-L and Φ0-R, Φ1-R, Φ2-R, ΦST-R, respectively, and are input to the first and second vertical scanning circuits 5L and 5R, respectively.

Next, the operation at the time of interlace scanning in the solid-state image pickup device configured as described above will be described with reference to the timing chart shown in FIG. In the interlaced mode, in the scanning circuit control clock generation circuit 21, the basic clock Φ1 remains Φ0-L, Φ1-L,
And Φ0-R, Φ1-R, and the basic clock Φ2 is output as Φ2-L and Φ2-R. Further, in the first field in which the field index pulse FI is at the low level, the start pulse ΦST-L input to the first vertical scanning circuit 5L is the second pulse
Start pulse ΦST− input to the vertical scanning circuit 5R of
It is controlled so as to precede the R by one cycle of the basic clock Φ1. As a result, the first vertical scanning circuit 5
Since the pulse shifting L and the second vertical scanning circuit 5R has a phase difference of one cycle of the basic clock Φ1, the selected row, that is, the vertical selection line is L1, L2 and R1, L.
3 and R2, ... are selected in this order.

On the other hand, the field index pulse FI
In the second field in which is a high level, in the scanning circuit control clock generation circuit 21, the start pulse ΦST-L input to the first vertical scanning circuit 5L and the start pulse ΦST-L input to the second vertical scanning circuit 5R are input. Pulse ΦST-R
Are controlled so that their phases are the same and are output. Therefore, the pulses for shifting the first vertical scanning circuit 5L and the second vertical scanning circuit 5R have the same timing, and the selected rows, that is, the vertical selection lines are L1 and R1 and L2 and R.
2, L3 and R3, ... are selected in this order. By driving the vertical selection lines as described above, the most general interlaced scanning, that is, two-row mixed reading in which the combination of two vertical pixels added in each field is different is realized.

Next, the operation during non-interlaced scanning will be described with reference to the timing chart shown in FIG. The basic clocks Φ1 and Φ2 for driving the first and second vertical scanning circuits 5L and 5R and the vertical scanning start pulse ΦST are input to the scanning circuit control clock generation circuit 21, and in the circuit 21, the first and second vertical scanning circuits 5L and 5R are input. Pulse groups Φ0-L, Φ1-L, Φ2-L, and ΦST-L input to the vertical scanning circuits 5L and 5R of
And Φ0-R, Φ1-R, Φ2-R, ΦST-R, respectively, and the first and second vertical scanning circuits 5 respectively.
Input to L and 5R. In non-interlaced mode, the basic clock Φ1 remains Φ0-L and Φ
It is output as 0-R, and the basic clock Φ2 is output as it is as Φ2-L and Φ2-R. However, unlike the interlaced scanning described above, Φ1-L and Φ1-R are supplied in a form in which the high level of the basic clock Φ1 is lost in each cycle. Moreover, Φ1-L and Φ1-R
Is a half cycle of each cycle, that is, the basic clock Φ
The timing is such that the phase is shifted by one cycle of 1. By applying such a pulse group to the first and second vertical scanning circuits 5L and 5R, each vertical scanning circuit 5
Since the pulse shift unit 19A constituting the L and 5R shift registers is driven by Φ1-L to Φ1-R and Φ2-L to Φ2-R, the pulse shift cycle is Φ1-L to Φ1-R. : T ₁ = 2 · T ₂ = 2 ·
T ₀ , on the other hand, the output pulse generation unit 19B which detects the rising transition of the shift pulse and generates a pulse is Φ0-L to Φ0-R and the pulse shift unit 19A.
, The width of the selection pulse output from the unit unit of the shift register is Φ0−L, Φ.
Cycle of 0-R and Φ2-L, Φ2-R: T ₀ = T ₂ = T ₁
/ 2. Therefore, the selected row, that is, the vertical selection line is L
1, R1, L2, R2, L3, R3, ... By driving the vertical scanning circuit as described above, it is possible to perform so-called non-interlaced reading, in which signals of all pixels of the image sensor are read independently and sequentially without being mixed with signals of adjacent pixels in the vertical direction. .

Next, a second embodiment will be described. First
In the embodiment, an output pulse generation unit 19 that receives the output of the pulse shift unit 19A and generates a row selection pulse
By partially changing B, the interlaced scanning and the non-interlaced scanning can be performed as in the first embodiment, and at the same time, the electronic shutter function can be realized.

Next, FIG. 11 shows a part of the configuration example of the scanning circuit used for the first and second vertical scanning circuits 5L and 5R in the present embodiment. The shift register unit 29 constituting this scanning circuit has a pulse shift unit 29A with two clocked inverter stages similar to the conventional shift register shown in FIG. 2, and detects the rising and falling transitions of the shift pulse to generate a pulse. The output pulse generating unit 29B for generating the output pulse generating unit 29B is shown in FIG. FIG. 12 shows the operation timing. The clock has three phases of Φ0, Φ1, and Φ2.
By applying the start pulse ΦST to the input of the first-stage pulse shift unit 29A, the output terminals S1, S2, S3, ... Of the output pulse generation units 29B are sequentially output in synchronization with the rising and falling edges of the clock Φ1. It is designed to output. In Figure 12, Φ0 is Φ1
If the clock is the same as that in the first embodiment shown in the timing chart of FIG. 6, the clock Φ2 rises even at the trailing edge of the shift pulses SR1, SR2 ,. From the time until the rise of the clock Φ1, the output is made.

On the other hand, the shift register of this embodiment can operate in different operation modes other than the operation mode shown in FIG. FIG. 13 shows an example of the operation timing. Figure
The difference from the operation mode shown in the 12 timing diagram is 3
Of the phase clocks Φ0, Φ1, and Φ2, pulses are applied to the clocks Φ0 and Φ2 at the same timing as the operation mode shown in FIG. 12, but the clock Φ1 is twice the clock Φ0 unlike the operation mode of FIG. The cycle is
The high level of the clock Φ0 is lost every one cycle, and a pulse is applied as the clock Φ1. By applying such clocks Φ0, Φ1, and Φ2,
Since the pulse shift unit 29A is driven by the clocks Φ1 and Φ2, the pulse shift cycle becomes the cycle of the clock Φ1: T ₁ = 2 · T ₂ = 2 · T ₀ , while the rising and falling transitions of the shift pulse are changed. The output pulse generation unit 29B that detects and generates a pulse has a clock Φ.
0 and the output of the pulse shift unit 29A, the output terminal S of each output pulse generation unit 29B
1, S2, S3, ... The effective pulse widths of the selection pulses are shift pulses SR1, SR2, SR3 ,.
Φ2 cycle clock Φ0 in a rising transition of the _{·: T 0 = T 2 =} T 1/2 , and the shift pulse SR
At the falling transitions of 1, SR2, SR3, ..., Outputs are made twice from the rising edge of the clock Φ2 to the rising edge of the clock Φ0 and from the falling edge of the clock Φ0 to the rising edge of the clock Φ1. It has become so.

Next, when the shift register having the operation mode shown in FIGS. 12 and 13 is applied to the vertical scanning circuit of the first embodiment shown in FIG. 1 to form the solid-state image pickup device of the second embodiment. Will be described. The solid-state imaging device of the second embodiment has a so-called electronic shutter function,
The shutter speed information is included in the duty ratio of the pulse that shifts in the vertical scanning circuit, and the pixel configuration is such that the rising and falling of the pulse are detected to read out or reset the pixel. The technique utilizing the rising edge and the falling edge of the shift pulse, which the applicant of the present application has already disclosed in JP-A-3-127567, is also used in the present invention.

The configuration example of the solid-state image pickup device using the shift register having the operation modes of FIGS. 12 and 13 is the same as that of the first and second vertical scanning circuits 5L and 5R except for the internal configuration.
This is the same as the first embodiment shown in FIG. 8, so the second embodiment will be described using FIG. Field index pulse FI for identifying the first field and the second field
The basic clocks Φ1 and Φ2 for driving the first and second vertical scanning circuits 5L and 5R, and the vertical scanning start pulse ΦST are input to the scanning circuit control clock generating circuit 21, and the first and second Second vertical scanning circuit 5
Pulse groups Φ0-L, Φ1-L, Φ input to L and 5R
2-L, ΦST-L and Φ0-R, Φ1-R, Φ2-R,
.PHI.ST-R is processed and input to the first and second vertical scanning circuits 5L and 5R, respectively.

Next, the operation during interlace scanning in the solid-state image pickup device configured as described above will be described with reference to FIGS.
This will be described with reference to the timing chart shown in FIG. Figure 14 and Figure
Reference numeral 15 is a division of what is originally integral, and the timings shown by the dotted lines show the same timing. In the interlaced mode, in the scanning circuit control clock generation circuit 21, the basic clock Φ1 remains Φ0-L,
.PHI.1-L, .PHI.0-R, .PHI.1-R, and the basic clock .PHI.2 is outputted as .PHI.2-L, .PHI.2-R as it is. Furthermore, the field index pulse F
In the first field where I is low level, the first
Start pulse ΦST− input to the vertical scanning circuit 5L of
L is controlled so as to be input before the start pulse ΦST-R input to the second vertical scanning circuit 5R by one cycle of the basic clock Φ1. As a result, the pulse that shifts in the first vertical scanning circuit 5L and the second vertical scanning circuit 5R has a phase difference of one cycle of the basic clock Φ1, and is generated by detecting the rising transition of the shift pulse. The pulses S1-L and S2- from the rising edge of the clock Φ1 to the rising edge of the clock Φ0.
L, S3-L, ... S1-R, S2-R, S3-R select rows, that is, vertical select lines are L1, L2 and R.
The order is 1, L3, R2, .... Further, the pulse generated by detecting the falling transition of the shift pulse extends from the rising edge of the clock Φ2 to the rising edge of the clock Φ1 to the vertical selection lines L1, L2 and R1, L3 and R.
It is output so as to select in the order of 2, ...

Therefore, the period from the rising edge of the clock Φ1 to the rising edge of the clock Φ1, that is, one horizontal scanning period, is read from the pixel during the period from the rising edge of the clock Φ1 to the rising edge of the clock Φ2. If the image sensor is configured to use the period from the rising edge of the clock Φ2 to the rising edge of the clock Φ1 for resetting the pixel data, only during the period when the start pulse ΦST is at the high level,
The exposure time for obtaining a pixel signal is shortened as compared with the first embodiment.

On the other hand, the field index pulse FI
In the second field in which is a high level, the scanning circuit control clock generation circuit 21 causes the start pulse ΦST-L input to the first vertical scanning circuit 5L and the start pulse ΦST-L input to the second vertical scanning circuit 5R. The input signals are controlled so that the phases of ΦST-R are the same. Therefore, the pulses for shifting in the first vertical scanning circuit 5L and the second vertical scanning circuit 5R have the same timing, and the rising edge of the clock Φ1 generated from the rising edge of the clock Φ1 generated by detecting the rising transition of the shift pulse. The selected rows selected by the row selection pulse during the rising, that is, the vertical selection lines are L1 and R1, L2 and R2, L3 and R3.
The order is ... Further, the row selection pulse generated by detecting the falling transition of the shift pulse has vertical selection lines L1 and R1, L2 and R2, L3 and R from the rising edge of the clock Φ2 to the rising edge of the clock Φ1.
It is output to select in the order of 3, ...

Therefore, the field index pulse F
As in the first field where I is low,
In the cycle from the rising edge of the clock Φ1 to the rising edge of the clock Φ1, that is, in one horizontal scanning period, the high level period of the clock Φ1 is for reading data from the pixel, and the low level period of the clock Φ1 is for the pixel data. If the image sensor is configured to be used for resetting, the exposure time for obtaining the pixel signal will be shortened as compared with the first embodiment only during the period when the start pulse ΦST is at the high level. Note that a specific configuration example of the unit of the vertical scanning circuit for realizing this function will be described later with reference to FIGS. 19, 20, and 21.

By driving the vertical scanning circuit as described above, the most general interlaced scanning, that is, the two-row mixed reading in which the combination of the vertical two pixels added in each field is different, and the image is realized. By changing the width of the start pulse applied from the outside to the sensor, the exposure time for outputting the image signal can be shortened compared to the normal field cycle, so that an on-chip electronic shutter can be realized. .

Next, the operation during non-interlaced scanning will be described with reference to the timing charts shown in FIGS. 16 and 17 are originally integrated, but
The timing shown by the dotted line is the same timing. The basic clocks Φ1 and Φ2 for driving the first and second vertical scanning circuits 5L and 5R and the vertical scanning start pulse ΦST are input to the scanning circuit control clock generating circuit 21, and in the circuit 21, the first and second Vertical scanning circuit 5
Pulse groups Φ0-L, Φ1-L, Φ input to L and 5R
2-L, ΦST-L and Φ0-R, Φ1-R, Φ2-R,
.PHI.ST-R is processed and input to the first and second vertical scanning circuits 5L and 5R, respectively. In the non-interlaced mode, the basic clock Φ1 is directly output as Φ0-L and Φ0-R, and the basic clock Φ2 is directly output as Φ2-L and Φ2-R. However, unlike the interlaced scanning described above, Φ1-L and Φ1-R are supplied in a form in which the high level of the basic clock Φ1 is lost in each cycle. Moreover,
Φ1-L and Φ1-R have a timing shifted by a half cycle of each cycle, that is, by one cycle of the basic clock Φ1.

By applying such a pulse group to the first and second vertical scanning circuits 5L and 5R, the pulse shift unit 29A constituting the shift register of each vertical scanning circuit 5L and 5R has the Φ1-L or Φ1. Since it is driven by -R and Φ2-L or Φ2-R, the pulse shift cycle is Φ1-L or Φ1-R: T ₁ = 2 · T ₂ =
2 · T _0. On the other hand, the output pulse generating unit for generating a pulse by detecting the rising transition of the shift pulse 29
Since B is driven by Φ0-L or Φ0-R and the output of the pulse shift unit 29A, the width of the selection pulse generated by detecting the rising transition of the shift pulse is
Period of Φ0-L or Φ0-R and Φ2-L or Φ2-R:
T ₀ = T ₂ = T _1/2 . Therefore, the rows selected by the selection pulse generated by detecting the rising transition of the shift pulse, that is, the vertical selection lines are L1, R1, L2, R.
The order is 2, L3, R3, .... The selection pulse generated by detecting the falling transition of the shift pulse is
From the rise of Φ2-L or Φ2-R, Φ0-L or Φ
The vertical selection lines are L1, R1, L2, R2, L from the rising edge of 0-R and from the falling edge of Φ0-L or Φ0-R to the rising edge of Φ1-L or Φ1-R.
It is output so as to be selected in the order of 3, R3, ....

Therefore, during the period from the rising edge of the clock Φ1 to the rising edge of the clock Φ1, that is, in one horizontal scanning period, the high level period of the clock Φ1 is used for reading data from the pixel, and the low level of the clock Φ1 is read. If the image sensor is configured to use the period of 1 to reset the pixel data, the exposure time for obtaining the pixel signal can be shortened as compared with the first embodiment only during the period when the start pulse ΦST is at the high level. Become. In addition,
A specific configuration example of the unit of the vertical scanning circuit for realizing this function will be described later with reference to FIGS. 19, 20, and 21.

By driving the vertical scanning circuit as described above, so-called non-interlaced reading is realized in which the signals of all the pixels of the image sensor are read independently and sequentially without being mixed with the signals of adjacent pixels in the vertical direction. Moreover, by changing the width of the start pulse applied to the image sensor from the outside, the exposure time for outputting the image signal can be shortened compared to the normal exposure cycle. It will be possible.

A scanning circuit control clock generation circuit 21 for switching each scanning mode in each embodiment described above.
Can be realized by a simple logic circuit, for example,
With the configuration as shown in FIG. 18, it can be formed on the same substrate as the sensor without increasing the area. Especially as in CMD image sensor, CMOSFET
In the case where the scanning circuit according to (1) is built in, the clock driver can also be configured by CMOSFET. Therefore, it is possible to configure the control clock generation circuit described above by CMOSFET and form it together with the clock driver on the same substrate as the sensor. It's extremely easy. In addition, in FIG.
Is a signal for controlling the scanning mode. By setting it to a low level for interlaced scanning and a high level for non-interlaced scanning, the scanning mode can be easily switched from the outside.

Next, a unit of a vertical scanning circuit when the present invention is applied to an image sensor using a CMD light receiving element which is an amplification type solid-state image pickup element will be described. When a video signal is output from the CMD light receiving element, the signals applied to the common gate line of each row of the CMD light receiving elements arranged in a two-dimensional array include a storage voltage VSS, an overflow voltage VOF, a read voltage VRD, and a reset voltage V.
A pulse in which four RST voltages are combined in time series is required. First, the case of the most general reading method will be described. In the non-selected row, the storage voltage VSS is applied during the horizontal effective period of the video signal, and the overflow voltage VOF is applied during the horizontal blanking period. In the selected row, the read voltage VRD and the horizontal return voltage are applied during the horizontal effective period of the video signal. The reset voltage VRST is required during the line period. In order to apply the above signals to the gate of the CMD light receiving element, a circuit having a configuration in which the selected / non-selected theoretical output of two binary values is obtained from each scanning stage, and the level level as shown in FIG.
A vertical scanning circuit including a mix circuit is used. Figure
In 19, 31 is a pulse shift unit, 33 is a level
It is a mix circuit. In this configuration, clock Φ1
The high level corresponds to the effective period of the video signal, and the low level corresponds to the horizontal blanking period.

However, the configuration example of the general vertical scanning circuit of the CMD image sensor shown in FIG. 19 is premised on that the width of the clock pulse for shifting in the pulse shift unit is one clock, and the present invention Assuming that the width of the clock pulse that shifts in the pulse shift unit is 1 clock or more, as shown in FIG. 20, the pulse shift unit 31 and C
Between the level mix circuit 33 having a terminal Gi for outputting a pulse applied to the gate line of the MD light receiving element,
It is necessary to provide the output pulse generation unit 32.
It is to be noted that the pulse shift unit 31, the output pulse generation unit 32, and the output pulse generation unit 32 having the configuration shown in FIG.
It is a part of the configuration of the vertical scanning circuit of the first embodiment shown in FIG. With this configuration, as shown in FIG. 21, if the pulse phase is set such that the effective period of the video signal is included in the high level period of the pulse of the clock Φ1,
It is clear that a video signal in interlaced scanning can be obtained as well as a video signal in non-interlaced scanning by the same selection sequence as in the conventional example.

Next, FIG. 22 shows a configuration in which a level mix circuit is connected to the pulse shift unit and the output pulse generation unit of the vertical scanning circuit of the second embodiment shown in FIG.
It will be described based on. In FIG. 22, 31 is a pulse shift unit, 42 is an output pulse generation unit, 33 is a level
It is a mix circuit. In this case, since the pulse waveform applied to the gate line of the CMD light receiving element is as shown in FIG. 23, the pulse phase is set so that the valid period of the video signal is included in the high level period of the clock pulse Φ1. For example, a video signal in interlaced scanning can be obtained by the same selection sequence as in the conventional example, and a video signal in non-interlaced scanning can also be obtained.
It is obvious that the electronic shutter function can be realized because the exposure time of the D light receiving element can be controlled.

This level mix circuit has a circuit configuration disclosed as a conventional example in Japanese Patent Application No. 4-56076 filed by the present applicant, but is disclosed as an embodiment of the invention in the same application. It is clear that the same effect can be obtained by the same connection in the level mix circuit that generates the above-mentioned four-valued pulse including the circuit configuration.

In the above embodiment, it goes without saying that as the output pulse generation unit, it is possible to use a circuit configuration using static logic including a circuit using dynamic logic of another configuration.

[0039]

As described above on the basis of the embodiments,
According to the solid-state imaging device of the present invention, it is possible to obtain the video signal in the conventional interlaced scanning as well as the video signal in the non-interlaced scanning, and to obtain the clock signal to be added to the scanning circuit control clock generation circuit at the time of switching the scanning mode. It is possible to realize a solid-state image pickup device that does not need to be changed, has no difference in image quality between scanning modes, and has an electronic shutter function in both scanning modes.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a schematic configuration of a first embodiment of a solid-state imaging device according to the present invention.

FIG. 2 is a circuit configuration diagram showing a configuration example of a general shift register.

FIG. 3 is a conceptual diagram schematically showing the shift register shown in FIG.

FIG. 4 is a timing diagram illustrating an operation of the shift register shown in FIG.

FIG. 5 is a diagram showing a part of a vertical scanning circuit of the first embodiment.

6 is a timing chart for explaining the operation of the vertical scanning circuit shown in FIG.

FIG. 7 is a timing chart for explaining another operation mode of the vertical scanning circuit shown in FIG.

8 is a diagram showing a specific configuration example of the first embodiment shown in FIG.

9 is a timing chart for explaining an operation during interlace scanning of the first embodiment shown in FIG.

FIG. 10 is a timing chart for explaining the operation during non-interlaced scanning according to the first embodiment shown in FIG. 8.

FIG. 11 is a diagram showing a part of a vertical scanning circuit according to a second embodiment.

FIG. 12 is a timing chart for explaining the operation of the vertical scanning circuit shown in FIG. 11.

FIG. 13 is a timing chart for explaining another operation mode of the vertical scanning circuit shown in FIG. 11.

FIG. 14 is a diagram showing part of the timing for explaining the operation during interlaced scanning of the solid-state imaging device of the second embodiment.

FIG. 15 is a diagram showing another portion of the timing for explaining the operation during interlace scanning of the solid-state imaging device of the second embodiment.

FIG. 16 is a diagram showing a part of the timing for explaining the operation of the solid-state imaging device of the second embodiment during non-interlaced scanning.

FIG. 17 is a diagram showing another portion of the timing for explaining the operation of the solid-state imaging device of the second embodiment during non-interlaced scanning.

FIG. 18 is a circuit diagram showing a configuration example of a scanning circuit control clock generation circuit.

FIG. 19 is a diagram showing a configuration example of a general vertical scanning circuit used in a CMD image sensor.

FIG. 20 is a diagram showing a configuration example of a vertical scanning circuit in an embodiment in which the present invention is applied to a CMD image sensor.

FIG. 21 is a timing chart for explaining the operation of the vertical scanning circuit shown in FIG. 20.

FIG. 22 is a diagram showing another configuration example of the vertical scanning circuit in the embodiment in which the present invention is applied to a CMD image sensor.

23 is a timing chart for explaining the operation of the vertical scanning circuit shown in FIG. 22.

FIG. 24 is a configuration diagram showing a configuration example of a conventional solid-state imaging device.

[Fig. 25] Fig. 25 is a configuration diagram illustrating a configuration example of a conventional solid-state imaging device capable of switching scan modes.

[Fig. 26] Fig. 26 is a configuration diagram illustrating another configuration example of a conventional solid-state imaging device capable of switching scan modes.

[Explanation of symbols]

 1 Pixel 2 Horizontal scanning circuit 3 Horizontal selection switch 4 Output signal line 5L First vertical scanning circuit 5R Second vertical scanning circuit 19 Shift register unit 19A Pulse shift unit 19B Output pulse generation unit 21 Scan circuit control clock generation circuit

Claims (6)

[Claims] 1. A plurality of photoelectric conversion elements arranged in a two-dimensional array, a horizontal selection line group provided corresponding to the photoelectric conversion elements arranged in a column direction, and the horizontal selection line group. Via a horizontal scanning circuit for scanning the photoelectric conversion elements arranged in the column direction, a vertical selection line group provided corresponding to the photoelectric conversion elements arranged in the row direction, and the vertical selection line group. In a solid-state imaging device having first and second vertical scanning circuits for scanning photoelectric conversion elements arranged in a row direction, each of the first and second vertical scanning circuits includes a plurality of scanning units. Each scanning unit of the first vertical scanning circuit is made to correspond one-to-one to each odd-numbered vertical selection line of the vertical selection line group, and
Each scanning unit of the second vertical scanning circuit is made to correspond to each even-numbered vertical selection line of the vertical selection line group in a one-to-one correspondence, and further, the first and second vertical scanning circuits are driven. A solid-state imaging device comprising: a control clock generation unit that controls a clock group to switch scanning modes. 2. The control clock generating means includes the first
2. The solid-state imaging device according to claim 1, wherein the scanning mode is switched by changing a frequency of a part of a clock group for driving the second vertical scanning circuit. 3. The control clock generation means includes the first
2. The solid-state imaging device according to claim 1, wherein the scanning mode is switched by changing a phase relationship of a part of a clock group for driving the second vertical scanning circuit. 4. The solid-state imaging device according to claim 2,
A solid-state imaging device, wherein the frequency of a clock whose frequency changes is half the frequency of other clocks. 5. The solid-state imaging device according to claim 3,
A solid-state imaging device, wherein a phase difference between clocks whose phase relationship changes is ½ of a cycle of the clock. 6. A CMD is used as the photoelectric conversion element,
2. The solid-state imaging device according to claim 1, wherein the control clock generating means is formed on the same substrate as the photoelectric conversion element array together with the first and second vertical scanning circuits.