JPH06339073A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To obtain a solid-state image pickup element provided with a shutter function by a single vertical scanning circuit. CONSTITUTION:A solid-state image pickup element is provided with a light receiving part 6 composed by two-dimensionally arraying photoelectric conversion elements, and vertical and horizontal scanning circuits 4 and 5 for successively reading the optical storage electric charge signals of the photodetector part 6. The vertical scanning circuit 4 is constituted of a shift register 1, a means 2 shifting a control signal CONT by the output of the shift register 1 and discriminating the timing of a reading and a reset by the level of a shifted control signal and a means 3 combining the output of the shift register 1 and the output of the reading/reset discimination means 2 and outputting the line selection signals of the reading and the reset.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an XY address type solid-state image pickup device having a simple structure and a shutter function.

[0002]

2. Description of the Related Art Conventionally, as a multifunctional solid-state image pickup device, there has been a device in which a shutter function is provided on the device itself, which is used in a wide range of applications such as photographing a high-speed moving object and flicker countermeasures. In the XY address type solid-state imaging device, the shutter operation can be performed by shifting the timings of signal reset and read operations. In order to realize such an operation, conventionally, there is known a method in which two vertical scanning circuits for reset and read operations are individually provided as shown in, for example, Proceedings 4-7 of the National Conference of the Television Society of 1987. Has been.

Next, the configuration of a solid-state image pickup device in which two vertical scanning circuits are individually provided to perform a shutter operation will be described with reference to FIG. In FIG. 19, 501 is a vertical scanning circuit for signal sweeping, 502 is a horizontal scanning circuit, and 50 is a horizontal scanning circuit.
Reference numeral 3 denotes a signal reading vertical scanning circuit, and 504 is a light receiving unit in which photoelectric conversion elements are two-dimensionally arranged in a matrix as pixels.
In order to perform the shutter operation in the solid-state image pickup device having such a configuration, the signal scanning vertical scanning circuit 501 is operated in advance of the signal reading vertical scanning circuit 503 to perform the scanning scanning.

For example, a signal scanning vertical scanning circuit 501
However, assuming that the signal reading vertical scanning circuit 503 is operated by n lines in advance, first, each pixel of the light receiving section 504 arranged two-dimensionally outputs the signal sweeping vertical scanning circuit 501. The light accumulation signal is sequentially reset by the pulse and the output pulse of the horizontal scanning circuit 502. Then, after a lapse of the period of n lines, the light accumulation signal of each pixel is read by the output pulse of the signal reading vertical scanning circuit 503 and the horizontal scanning circuit 502. By the above operation, each pixel signal is read out after the light accumulation time of n lines, which means that the shutter operation is performed in the shutter time nH for the cycle of n lines.

During this operation, each vertical scanning circuit 501
, 503 shows the timing of the scanning pulse output.
Shown in. Here, φ _V is a clock for operating the vertical scanning circuits 501 and 503 and having a period of 1 horizontal scanning period (1H), and 501-1, 501-2, 501-3 are vertical scanning for signal sweeping. Output pulse of circuit 501, 503-1, 503-2, 50
3-3 is an output pulse of the signal reading vertical scanning circuit 503, which includes output pulses 501-1 and 503-1 and output pulses 501-2 and 5-3.
03-2, output pulses 501-3 and 503-3 are applied to respective horizontal lines for controlling resetting and reading, which are connected to pixel rows arranged in the same row.

As described above, in the XY address type solid-state image pickup device, the shutter operation becomes possible by realizing the vertical scanning pulse trains having the shifted phases.

[0007]

However, an XY having a shutter function by using the conventional vertical scanning method.
Attempts to realize an address-type solid-state image pickup device cause the following problems. That is, when two vertical scanning circuits for signal sweeping and for signal reading are respectively provided as shown in FIG. 19, the chip area increases and the cost of the solid-state imaging device increases.

The present invention has been made to solve the above-mentioned problems in the conventional XY address type solid-state image pickup device having a shutter function, and it is possible to reduce the rate of increase in the chip area and suppress the increase in cost. An object of the present invention is to provide a solid-state image pickup device having a simple structure and a shutter function.

[0009]

In order to solve the above problems, the present invention provides a light receiving section in which photoelectric conversion elements are two-dimensionally arranged in a matrix as pixels, and light accumulation in each pixel of the light receiving section. In a solid-state imaging device including horizontal and vertical scanning circuits for sequentially addressing and reading charge signals, a means for causing the vertical scanning circuit to sequentially shift and output pulses at the timings of reading and reset, and the pulse. Means for identifying the timing of the read and reset by the shift pulse output from the shift output means and the control signal, and timing of the read and reset by the outputs from the pulse shift output means and the read / reset identifying means Readout that sequentially selects the corresponding pixel rows of the light receiving unit in synchronization with the pulse shifted by And it constitutes at the item and means for generating a reset signal.

In the solid-state image pickup device thus constructed, the read signal and the reset signal outputted from the read signal and reset signal generating means constituting the vertical scanning circuit are synchronized with the pulse shifted at the read and reset timings. Select each pixel row of the light receiving part,
At each selection time point, the reading operation and the resetting operation of the light accumulation charge signal are performed. Therefore, it is possible to realize an XY address type solid-state image sensor having a shutter function that does not require a plurality of vertical scanning circuits, reduces an increase in chip area, and suppresses an increase in cost.

[0011]

EXAMPLES Next, examples will be described. Figure 1 (A)
FIG. 3 is a conceptual diagram showing a vertical scanning circuit 4, which is a main part of a basic embodiment of a solid-state image sensor according to the present invention. In FIG. 1A, reference numeral 1 is a shift register, 2 is an identification means for identifying the timing of reading and resetting using a control signal CONT, and a control signal C
ONT is shifted by the output of the shift register 1,
The timing of reading and resetting is identified by the level of the shifted control signal CONT. Reference numeral 3 is a means for combining the output of the shift register 1 and the output of the read / reset identification means 2 in order to output a row selection signal for read and reset. FIG. 1B is a block diagram showing a solid-state imaging device configured by using the vertical scanning circuit 4 shown in FIG.
Reference numeral 5 is a horizontal scanning circuit, and 6 is a light receiving section in which photoelectric conversion elements are two-dimensionally arranged.

In the solid-state image pickup device having the above-described structure, the read / reset identification means 2 in the vertical scanning circuit 4 changes the level of the control signal CONT shifted by the output of the shift register 1 to, for example, the control signal CONT being "H". When it is "level", it is recognized as "read", and when it is "L" level, it is recognized as "reset", and the signals necessary for each read and reset operations are output. Then, in the combination means 3, the output of the shift register 1 and the output signal from the read / reset identification means 2 are combined and output as a read signal and a reset signal. By this read signal and reset signal, each pixel row of the light receiving unit is selected in synchronization with the pulse shifted at the read and reset timings, and the read operation and reset operation of the photo-accumulated charge signal are performed at each selection time point. As a result, the shutter function can be provided without providing a plurality of vertical scanning circuits.

Next, a concrete embodiment will be described.
FIG. 2 is a circuit configuration diagram showing a configuration of a vertical scanning circuit which is a main part of a first specific example of a solid-state image pickup device having a shutter function according to the present invention. In FIG. 2, 10 is a shift register used in the vertical scanning circuit, which is 10-0, 10
Reference numerals -1, 10-2, ... Show shift register units constituting each stage of the shift register 10. The shift register 10 has a function of shifting a start pulse φ _VST by a drive pulse φ _V having a horizontal scanning period as one cycle. Reference numeral 12 is a circuit for identifying read / reset by using a control signal CONT which is shifted by the output of the shift register 10, and each shift register unit 10-0, 10
-1, 10-2, ..., Each stage of the identification circuit 12 includes transfer gates 13-1, 13-2, 13-3, ... And two inverters 14-1, 14-. 2, 14-3, ..., 15-1, 15-2, 15-3, ...
・ It consists of and.

Reference numeral 16 denotes the output and read of the shift register 10.
It is a circuit that combines the outputs of the reset identification circuit 12,
2-input AND17-1 and 17 for reset timing signal generation
-2, 17-3, ... and 2 for generating read timing signals
It is composed of inputs AND18-1, 18-2, 18-3, .... 2-input AND17 for reset timing signal generation
1, 17-2, 17-3, ... Inverters 14-1, 14 of the output / readout / reset identification circuit 12 from the output terminals 11-1, 11-2 ,. Outputs of -2, 14-3, ... are input respectively, and 2-input AND 18-1, 18-2, 18-3, ... for generating a timing signal for reading are connected to the output terminal 11 of the shift register 10. -1, 11-2, ..., and inverters 15-1, 15-2, 15 of read / reset identification circuit 12
-3, ... Outputs are input respectively.

Next, the operation of the vertical scanning circuit thus configured will be described based on the timing chart shown in FIG. In this vertical scanning circuit, during one vertical scanning period, two pulses that are at the “H” level for one cycle of the driving pulse φ _V are used as the start pulse φ _VST of the shift register 10 to shift the shift register 10. . 2 here
One of the "H" level pulses corresponds to the reset timing and the other corresponds to the read timing. In the start pulse φ _VST shown in FIG. 3, t _{0 to} t
_{When the} timing of becoming "H" level for _one period is reset, t
Timing the ₆ ~t ₇ period "H" level corresponds respectively to read.

When such a start pulse φ _VST is input, each shift register unit 10 of the shift register 10
-0, 10-1, 10-2, ... Output terminals 11-0, 11-1, 11-2, ...
The pulses indicated by 11-0, 11-1, 11-2, ... And the same as those of these output terminals in FIG. The control pulse CONT is recognized as reset when the level of the control signal CONT in the read / reset discrimination circuit 12 is “L” level, and read when the level is “H” level. Since the control signal CONT in 12 is shifted by the output of the shift register 10, the outputs of the inverters 15-1, 15-2, 15-3, ... In FIG. It becomes like the signal shown by 1, 15-2, 15-3, ....

Therefore, the two-input AND 17-1 and 17- for generating the reset timing signal in the combinational circuit 16
The output of 2,17-3, respectively _{t 2 ~t 3, t 3 ~t} 4,
period t ₄ ~t ₅ "H" level and becomes the reset signal 19
1, 19-2, 19-3 are generated. The output of the read timing signal generating two inputs AND18-1,18-2,18-3 is a period "H" level of _{t 8 ~t 9, t 9 ~t} 10, t 10 ~t 11 respectively Readout signals 20-1, 20-2, 20-3 are generated. And these reset signals 19-1, 19-2, ...
.. and read signals 20-1, 20-2, ... Are given to the row selection lines of the light receiving section to sequentially select pixel rows and perform reset and read operations of each pixel.

As described above, according to the vertical scanning circuit having the configuration shown in FIG. 2, the shutter operation having the light accumulation time corresponding to the phase difference between the pulses shifted at the reset and read timings is performed. Can be done, XY
It can be applied to a solid-state image sensor that reads out signals by an address method.

In the first embodiment, the shift register uses the pulse which is at "H" level for one cycle of the driving pulse for transmitting information, but of course "L".
It is apparent that the level portion can be used for information transmission, and the information transmission level for read / reset identification can be different from that of the above-mentioned embodiment also for the control signal.

FIG. 4 is a circuit configuration diagram showing a modification of the vertical scanning circuit of the first embodiment shown in FIG. 2, and the same or corresponding members as those of the vertical scanning circuit shown in FIG. Is shown. In this modification, the shift operation of the control signal CONT of the read / reset identification circuit 12 is thinned out, and the number of elements can be reduced. In this modification, the control signal CO
Although the shift operation of NT is shown in two steps,
Further, the shift operation can be thinned out.

Next, as a second concrete example, the present invention is an amplification type photoelectric conversion element CMD (Charge Modulat).
A vertical scanning circuit when applied to a solid-state imaging device using an ion device) as a light receiving element will be described. When a video signal is output from the CMD light receiving element, as the signal applied to the common gate line of each row of the CMD light receiving elements arranged in a two-dimensional array, as shown in FIG. 5, the accumulated voltage V _INT and the overflow voltage V Pulses φ _G1 , φ _G2 , ... Combining four voltages of _OF , read voltage V _RD, and reset voltage V _RST in time series are required.

Next, the case of the most general reading method using a gate application signal in which such four voltages are combined in time series will be described. In the non-selected row, the accumulated voltage V _INT is applied during the horizontal effective period of the video signal, and the overflow voltage V _OF is applied during the horizontal retrace period. In the selected row, the read voltage V _RD is applied during the horizontal effective period of the video signal. The reset voltage V _RST is required during the horizontal blanking period. In order to apply such a signal to the gate of the CMD light receiving element, a vertical scanning circuit including a circuit having a configuration in which a binary logic output of selection / non-selection is obtained from each scanning stage and a level mix circuit are provided. Used.

As a level mix circuit, there is a structure as shown in FIG. In FIG. 6, the clock V
_When the "L" level of _CK1 is the horizontal effective period of the video signal,
The "H" level corresponds to the horizontal blanking period. Also RD
The / RS signal is a signal that becomes the reset voltage V _RST while the level of the clock V _CK1 is “H” and becomes the read voltage V _RD during the period of “L”.

FIG. 7 is a diagram showing the operation timing of the level mix circuit shown in FIG. S is a selection / non-selection signal, and "L" level is selected and "H" level is non-selected. The read voltage V _RD or the reset voltage V _RST appears at the output while the selection / non-selection signal S is at the “L” level, while it is output at the time when the selection / non-selection signal S is at the “H” level. Overflow voltage V _OF or storage voltage V
_INT appears, and the gate line application signal G having four levels is obtained. When this gate line application signal G is applied to the common gate line of the CMD light receiving element, the light accumulation period of that row is the period of t _{1 to} t ₂ in FIG. 7. Therefore, the variable shutter operation can be realized by controlling the timing of the selection / non-selection signal S input to the level mix circuit.

FIG. 8 is a circuit configuration diagram showing a vertical scanning circuit of the second specific example. In FIG. 8, 100 is a shift register used in the vertical scanning circuit, and 100-0, 10
0-1, 100-2, ... are shift register units of each stage constituting the shift register 100. The shift register 100 has a function of shifting the start pulse phi _VST by the drive pulse phi _V to 1 cycle horizontal scanning period. 110 uses the control signal CONT that is shifted by the output of the shift register 100 to read /
In the circuit for identifying the reset timing, each stage of the identifying circuit 110 corresponding to each shift register unit 100-0, 100-1, 100-2, ... Includes a transfer gate for shifting the control signal CONT. 130-1, 130-2,
130-3, ... and two inverters 140-1, 140-2, 14
0-3, ... and 150-1, 150-2, 150-3, ... And when a CMD light receiving element is used as a pixel, the period during which the read operation and the reset operation are performed as described above. Is different within one horizontal scanning period, the control signal C
Transfer gates 160-1, 160-2, 160-3 for switching and outputting a clock φ _RD that gives a read period and a clock φ _RS that gives a reset period depending on the ONT level.
, And 170-1, 170-2, 170-3, and so on. In this embodiment, a CMOS switch is used as the transfer gate for shifting the control signal CONT, unlike the first embodiment shown in FIG. 2, but of course the same configuration as in the first embodiment can be used. This is also possible, and the same applies to the transfer gate for switching the clocks φ _RD and φ _RS .

Reference numeral 120 denotes a circuit that combines the output of the shift register 100 and the output of the read / reset identification circuit 110. Each stage of the combination circuit 120 has an output of the shift register 100 and an output of the read / reset identification circuit 110. 2-input NAND 180-1, 180-2, 180-
It consists of 3, ... And the combination circuit 12
The output of 0 is input to the above-mentioned level mix circuit LM and is configured to obtain output signals G ₁ , G ₂ , G ₃ , ....

FIG. 9 is a timing chart for explaining the operation of the vertical scanning circuit shown in FIG. φ _VST is a start pulse of the shift register 100, which is at “H” level at the timing corresponding to the reset and read operations. The control signal CONT recognizes reset at "L" level and read at "H" level. φ _RD is the light receiving element of CMD,
The clock is at the "H" level during the horizontal valid period in which the read operation is performed, and the φ _RS is the clock at the "H" level during the horizontal blanking period during which the reset operation is performed.
S ₀ , S ₁ , S ₂ , and S ₃ are shift register units 100-0 and 100-1 at the respective stages of the shift register 100 shown in FIG.
, 100-2, 100-3 output. C ₁ , C ₂ , C
Reference numeral ₃ is a control signal for shifting in the read / reset discrimination circuit 110 shown in FIG. 8 by the output of the shift register 100. D _1, D _2, D ₃ is the output of the read-reset discrimination circuit 110, the output D _1, D _2, D
₃ , the clock φ _RD is output when the control signals C ₁ , C ₂ and C ₃ that shift in the read / reset identification circuit 110 are “H” level, and the clock φ _RS is output when the control signals C ₁ , C ₂ and C ₃ are “L” level. Is output.

M ₁ , M ₂ and M ₃ are outputs of the combinational circuit 120 shown in FIG. 8, and at the reset timing, they are sequentially set to the “L” level only during the horizontal retrace period which is the reset period of the CMD light receiving element. At the read timing, the level becomes “L” sequentially only during the horizontal effective period which is the read period of the CMD light receiving element. G ₁ , G ₂ and G ₃ are output signals when the outputs M ₁ , M ₂ and M ₃ of the combination circuit 120 are input to the level mix circuit LM, and CM
In order to operate the D light receiving element, a 4-level gate line application signal is applied to the common line of each row.

As described above, according to the vertical scanning circuit of the second embodiment having the configuration shown in FIG. 8, the shutter having the light accumulation time corresponding to the phase difference between the pulses shifted at the reset and read timings. You can take action.

In the second embodiment, similar to the first embodiment, the shift register uses the "H" level pulse for transmitting information, but of course the "L" level portion. It can be used for information transmission, and the control signal is recognized as read at "H" level and reset at "L" level. This level is the same as that of this embodiment. It is clear that it is possible to make them different. Further, like the first embodiment, the shift operation of the control signal may be thinned out to reduce the number of elements.

Next, a third specific example will be described. In this embodiment, switching between one-row interlaced scanning and non-interlaced scanning is possible, and there is field accumulation and frame accumulation in one-row interlaced scanning. Is applied. Also in this embodiment, a vertical scanning circuit using a CMD as a light receiving element will be described.

First, the circuit configuration of the shift register used in the vertical scanning circuit of this embodiment will be described with reference to FIG. This shift register is a unit of the shift register with two stages of clocked inverters surrounded by broken lines in FIG.
200-0, 200-1, 200-2, ...
This shift register is shown using symbols as shown in FIG. In Figures 10 and 11, / φ _V2A , / φ
_V1A , / φ _V2B , and / φ _V1B represent inverted clocks of the clocks φ _V2A , φ _V1A , φ _V2B , and φ _V1B , respectively.

12, 13 and 14 are timing charts for explaining the operation of the shift register having the above structure.
The clock used for this shift register has two phases.
As shown in 12, 13, and 14, the shift operation is changed by controlling this two-phase clock. Start pulse φ to the first stage unit 200-0 of the shift register
By applying _VST , clock φ _V1A or φ
Each shift register unit is synchronized with the fall of _V1B
Outputs 200-0, 200-1, 200-2, ... S ₀ , S ₁ ,
S ₂ , ... Appears.

In FIG. 12, the clocks φ _V1A and φ _V1B and the clocks φ _V2A and φ _V2B are clocked by the same clock, so that the sequentially shifted outputs S ₀ , S ₁ ,
S ₂ , ... Appears. In FIGS. 13 and 14, the clock φ
_{By fixing V1B} and φ _V2B or clocks φ _V1A and φ _V2A to “L” level, the input and output levels of the shift register unit to which those clocks are input become the same, and as shown in FIGS. The output shifted every two units appears.

FIG. 15 is a circuit configuration diagram showing a vertical scanning circuit of a third embodiment using the shift register shown in FIGS. In FIG. 15, reference numeral 200 denotes the shift register having the configuration shown in FIGS. 10 and 11 that shifts a pulse by a drive pulse having a horizontal scanning period as one cycle.
The shift operation can be changed by controlling the drive pulse. Reference numeral 210 denotes a circuit for identifying the timing of read / reset by using the control signal CONT which is shifted by the output of the shift register 200. The transfer gate and the two inverters for shifting the control signal CONT are shown in FIG. Similar to the modification of the first embodiment shown, the number of elements is reduced by providing every two stages. Further, when a CMD light receiving element is used as a pixel, two clock lines are provided for giving a read and reset period in one horizontal scanning period, and clocks φ _RDA and φ _RDB and clocks φ _RSA and φ _RSB are respectively set. It is designed to be applied.

The lines to which the clocks φ _RDA and φ _RSA are applied are connected to the transfer gates of odd-numbered stages whose output is switched according to the level of the control signal CONT. On the other hand, the lines to which the clocks φ _RDB and φ _RSB are applied are connected to the transfer gates in even stages. Therefore, when the timing of reading is recognized by the control signal CONT, the clock φ
_The clock φ _RDB appears at the output in the even-numbered stages, and when the reset timing is recognized, the clock φ _RSA appears at the odd-stage and the clock φ _RSB appears at the even-numbered stages.

Reference numeral 220 is a circuit that combines the output of the shift register 200 and the output of the read / reset identification circuit 210, and is composed of a 2-input NAND to which the respective outputs are input. The LM to which the output of the 2-input NAND is input is a level mix circuit having the same configuration as that of the second embodiment.

Next, the operation of the vertical scanning circuit thus configured will be described. In the case of non-interlaced scanning, the same operation as in the second embodiment shown in FIG. 8 may be performed.
Therefore, the shift register 200 has clocks φ _V1A and φ _V1B and clocks φ _V2A and φ _V2A and φ _V1A as shown in FIG.
_{Make V2B the} same so that the outputs from the shift register units at each stage are sequentially shifted. In the read / reset discrimination circuit 210, the clocks φ _RDA and φ _RDB for giving the read period are pulsed which are at the “H” level during the horizontal effective period as in the second embodiment, and the clock φ _RSA for giving the reset period, φ _RSB is a pulse that is at “H” level during the horizontal retrace period. By setting in this way, the vertical scanning circuit shown in FIG. 15 performs the same operation as the second embodiment shown in FIG. 8 and performs non-interlaced scanning.

Next, regarding one-line interlaced scanning,
Description will be made based on the timing chart of FIG. The one-row interlaced scanning is a scanning method in which pixel signals of odd-numbered rows are read out in one field and pixel signals of even-numbered rows are read out in the other field to form one frame. Figure
In 16, the field from which the signals in the odd rows are read is the A field, and the field from which the signals in the even rows are read is the B field. Also, from the reset timing start pulse that determines the light accumulation time of the signal read out in the A field to the reset timing start pulse that determines the light accumulation time of the signal read out in the B field is the RSA field, and the signal read out in the B field The RSB field is from the reset timing start pulse that determines the light accumulation time to the reset timing start pulse that determines the light accumulation time of the signal read in the A field.

Φ _VST is a start pulse of the shift register 200, which becomes “H” level at the timing corresponding to the reading and resetting. The control signal CONT recognizes reading at "H" level and reset at "L" level. The clock φ _RDA is a clock signal which is at “H” level during a horizontal effective period which is a read period of the CMD light receiving element in the A field, and is always at “L” level in the B field. Clock φ
_{The RDB} is a clock signal similar to the A field of the clock φ _{RDA in} the B field, and is always at the “L” level in the A field. The clock φ _RSA is a clock signal which becomes “H” level during the horizontal retrace period which is the reset period of the CMD light receiving element in the RSA field.
In the B field, the level is always "L". Clock φ
_RSB is the RSB field and _RSA of clock φ RSA
The clock signal is the same as that of the field, and is always at the “L” level in the RSA field.

S _{0 to} S ₄ are outputs of the shift register 200. Here, the clocks φ _V1B and φ _V2B are clock signals, and the clock φ _V1A is the same as that shown in FIG. 14 for the driving pulse of the shift register 200. And φ _V2A are always set to the “L” level so that the shift register outputs S ₁ and S ₂ , and S ₃ and S ₄ have the same timing.

M _{1 to} M ₄ are outputs of the combination circuit 220. At the read timing, the output of the read / reset identification circuit 210 becomes the clock φ _{RDA in} the odd stages and the clock φ _{RDB in the} even stages. In the A field, φ _RDA is a clock that is at the “H” level during the horizontal effective period which is the reading period of the CMD light receiving element, so that the odd-numbered output M ₁ , M ₃ ,
... become "L" level during the horizontal effective period when the output of the shift register 200 becomes "H" level. On the other hand, φ
_RDB is always at "L" level, so combinational circuit 22
The outputs M ₂ , M ₄ , ... Of even-numbered stages of 0 are always at "H" level. In field B, φ _RDA is always "L"
Since the level, φ _RDB, is a clock signal, the outputs M ₁ , M ₃ , ... Of the odd-numbered stages of the combinational circuit 220 are always "H".
, And the outputs M ₂ , M ₄ , ... Of even-numbered stages are at "L" level during the horizontal effective period when the shift register output is at "H" level.

On the other hand, at the reset timing,
Similar to the read timing, in the RSA field, the odd-numbered stage outputs M ₁ , M ₃ , ... Of the combinational circuit 220.
When the output of the shift register 200 becomes "H" level, it becomes "L" level during the horizontal blanking period which is the reset period of the CMD light receiving element, and the outputs M ₂ , M ₄ , ...
Is always at "H" level. On the other hand, in the RSB field, the outputs M ₁ , M ₃ , ... Of odd-numbered stages are always at “H” level, and the outputs M ₂ , M ₄ , ... Of even-numbered stages are the outputs of the shift register 200. When it goes to H level, it goes to "L" level during the horizontal blanking period.

G _{1 to} G ₄ are the outputs of the level mix circuit LM, and the outputs M _{1 to} M ₄ of the combination circuit 220.
Is inputted, a 4-level signal for operating the CMD light receiving element is output and applied to the common line of each row.

As described above, according to the vertical scanning circuit having the structure shown in FIG. 15, it is possible to perform the shutter operation having the light accumulation time corresponding to the phase difference between the pulses shifted at the reset and read timings. Therefore, by controlling the clock, the one-row interlaced scanning and the non-interlaced scanning can be switched.

In the third embodiment, as in the first and second embodiments, the "H" and "L" information levels may be different from those shown in the third embodiment. Obviously, it is possible to further reduce the number of elements by further thinning out the shift operation of the control signal. Further, in the configuration of the vertical scanning circuit shown in FIG.
Although the output load of the shift register units in each stage is not uniform, the output load can be made uniform by providing dummy transistors.

Next, a fourth specific example will be described. In this embodiment, the present invention is applied to a solid-state image pickup device that is capable of switching between two-row mixed interlaced scanning and non-interlaced scanning, which is generally used as a standard television system. A vertical scanning circuit when a CMD is used as an element will be described. FIG. 17 is a circuit configuration diagram of the vertical scanning circuit of the fourth embodiment. In FIG. 17, reference numeral 300 denotes a shift register that shifts the start pulse φ _VST by a drive pulse having a horizontal scanning period as one cycle. Like the third embodiment shown in FIG. 15, the shift operation is controlled by the drive pulse. It is configured to be able to change. 310 is a control signal C that is shifted by the output of the shift register 300.
This is a circuit for discriminating between reading and resetting using the ONT, and a transfer gate for shifting the control signal CONT and two inverters are provided in every two stages. Note that the transistor denoted by the reference symbol MD is
This is a dummy transistor provided to make the output load of the shift register units of each stage uniform. Further, in the read / reset identification circuit 310, when a CMD light receiving element is used as a pixel, a transfer gate for switching and outputting a clock that gives a read and reset period in one horizontal scanning period is output according to the level of the control signal CONT. It is provided in steps.

The clock line for giving the reading period is of one system and is connected to the transfer gates of all stages so that the clock φ _RD is applied. On the other hand, there are four clock lines that give the reset period, and each line has clocks φ _RS1 and φ every 4 stages.
_RS2 , _φRS3 , and _φRS4 are applied.
Therefore, when the read timing is recognized by the control signal CONT, the clock φ
_{When RD} appears in the output and it is recognized as the reset timing, the clock φ _RS1 is output in every 4th stage 1, 5, 9, ...
However, the clock φ _RS2 is 3, ₂ , 10, ...
7, 11, ... Clock φ _RS3 is 4, 8, 12, ...
_-In stages, clock φ _RS4 appears at the output.

Reference numeral 320 is a circuit that combines the output of the shift register 300 and the output of the read / reset identification circuit 310, and each stage of the combination circuit 320 is configured by a 2-input NAND to which the respective outputs are input. There is. Then, the output of the combination circuit 320 is input to the level mix circuit LM configured similarly to the second embodiment.

Next, the operation of the vertical scanning circuit shown in FIG. 17 will be described. Figure for non-interlaced scanning
The same operation as in the second embodiment may be performed by considering the same as in the third embodiment shown in FIG. Therefore, the shift register 30
0 means clocks φ _V1A and φ _V1B and clocks φ _V2A and φ
_{Make V2B the} same so that the outputs from the shift register units at each stage are sequentially shifted. In the read / reset identification circuit 310, a clock φ _RD that gives a read period is a clock pulse that becomes “H” level during the horizontal effective period, and clocks φ _RS1 and φ that give a reset period.
_RS2 , φ _RS3 , and φ _RS4 are clock pulses that are at “H” level during the horizontal retrace line period. By setting in this way, the vertical scanning circuit shown in FIG. 17 becomes the second scanning circuit shown in FIG.
The same operation as that of the embodiment is performed, and non-interlaced scanning is performed.

Next, the two-row mixed interlaced scanning will be described with reference to the timing chart shown in FIG. In this timing chart, 1, 2 rows, 3, 4
The fields in which the signals of rows ... Are mixed are referred to as A fields, and the fields in which the signals of rows 2, 3 rows, 4, 5 ... are mixed are referred to as B fields. Also, from the reset timing start pulse that determines the light accumulation time of the signal read in the A field to the reset timing start pulse that determines the light accumulation time of the signal read in the B field is the RSA field, and the opposite period is RSB. It is in the field.

Φ _V1A and φ _V1B are drive pulses for the shift register 300. In the A field, φ _V1B is not shown in FIG. 18, but only φ _V2B is a clock signal, and is also shown in FIG. 18 like φ _V1A . However, φ _V2A is always at “L” level, while in the B field, only φ _V1A and φ _V2A are clock signals, and φ _V1B and φ _V2B are always at “L” level, so that the shift timing changes for each field. There is. It should be noted that in the present embodiment, φ is only used for one cycle so that the shift operation is performed even at the time of switching fields.
_V1A, phi _V2A and phi _V1B, and is configured to phi _V2B overlap. φ _VST is a start pulse, which is a pulse that becomes "H" level at the timing of reading and resetting.
In this embodiment, the period during which the reset timing is at the "H" level is 2H. CONT is a control signal for identifying the read and reset timings. In this embodiment, the "H" level is recognized as read,
The "L" level is recognized as a reset.

Φ _RD is a pulse which is at "H" level during the horizontal effective period which is the read period of the CMD light receiving element.
φ _RS1 , φ _RS2 , φ _RS3 , and φ _RS4 are 2H cycle pulses that are at “H” level during the horizontal blanking period that is the reset period of the CMD light receiving element. In the RSA field, φ _RS1 , φ _RS2, and φ _RS3 And φ _RS4 are in the same phase,
In the RSB field, φ _RS1 and φ _RS4 and φ _RS2 and φ
_RS3 and the same phase.

S _{0 to} S ₄ are outputs of the shift register 300, and S ₁ is set in the A field by the clock control.
And S ₂ , S ₃ and S ₄ , ... Have the same timing, and in the B field, S ₂ and S ₃ , S ₄ and S ₅ , ... Not shown in FIG. 18 have the same timing. .

M _{1 to} M ₄ are outputs of the combination circuit 320. At the read timing, the output becomes "L" level during the period in which both the shift register output and the clock φ _RD are at "H" level, so in the A field, M ₁
And M ₂ , M ₃ and M ₄ , ...
In the field, combinations of M ₂ and M ₃ , M ₄ and M ₅ , ... Not shown in FIG. 18 sequentially become “L” level during the horizontal effective period which is the reading period of the CMD light receiving element. On the other hand, at the reset timing, the shift register output and clocks φ _RS1 , φ _RS2 , φ _RS3 , φ
_Since either _RS4 is at "L" level while both are at "H" level, in the RSA field, M ₁ and M ₂ ,
The combination of M ₃ and M ₄ , ..., And in the RSB field, the combination of M ₂ and M ₃ , M ₄ and M ₅ , ... It becomes the middle "L" level.

G _{1 to} G ₅ are outputs of the level mixing circuit LM, and outputs M ₁ and M _{1 of} the combinational circuit 320.
By inputting M ₂ , M ₃ , ... To the level mix circuit LM, a 4-level signal for operating the CMD light receiving element is output and applied to the common line of each row.

As described above, by using the vertical scanning circuit having the configuration shown in FIG. 17, the shutter operation having the light accumulation time corresponding to the phase difference between the pulses shifted at the reset and read timings is performed. It is possible to switch between the two-row mixed interlaced scanning and the non-interlaced scanning by controlling the clock. Further, in the two-row mixed interlaced scanning, since the light accumulation time of each row is the same even if the fields are different, field flicker due to the difference in light accumulation time between fields does not occur.

In the fourth embodiment, as in the first to third embodiments, the "H" and "L" information transmission levels can be different from those in the present embodiment. It is also clear that the shift operation of the control signal can be further thinned to reduce the number of elements.

Further, as can be seen from the third and fourth embodiments, the clock lines for providing the read and reset periods in the read / reset discrimination circuit are set to 2 systems and 4 systems, respectively. Control only, non-interlaced, 2-line mixed interlaced, 1
A vertical scanning circuit capable of switching each scan of the row interlace can be configured.

[0060]

As described above on the basis of the embodiments,
According to the present invention, a single vertical scanning circuit generates a read signal and a reset signal that select a pixel row in synchronization with a pulse that shifts at the timing of signal read and reset and perform a signal read operation and a signal reset operation. The XY address type solid-state having a shutter function capable of switching interlaced / non-interlaced scanning by clock control, which has a simple structure to reduce the rate of increase in chip area and suppresses cost increase. An image sensor can be provided.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing a basic embodiment of a solid-state image sensor according to the present invention.

FIG. 2 is a circuit configuration diagram showing a vertical scanning circuit according to a first specific example of the present invention.

FIG. 3 is a timing chart for explaining the operation of the vertical scanning circuit of the first embodiment shown in FIG.

FIG. 4 is a circuit configuration diagram showing a modification of the vertical scanning circuit of the first embodiment shown in FIG.

FIG. 5 is a diagram showing a signal applied to a common gate line of each row in a solid-state imaging device using a CMD light receiving element.

FIG. 6 is a circuit configuration diagram showing a configuration example of a level mix circuit.

7 is a timing chart for explaining the operation of the level mix circuit shown in FIG.

FIG. 8 is a circuit configuration diagram showing a vertical scanning circuit according to a second specific example of the present invention.

FIG. 9 is a timing chart for explaining the operation of the vertical scanning circuit of the second embodiment shown in FIG.

FIG. 10 is a diagram showing a configuration of a shift register used in a vertical scanning circuit according to a third specific example of the present invention.

11 is a diagram showing symbols of the shift register shown in FIG. 10.

FIG. 12 is a timing chart for explaining the operation of the shift register shown in FIGS. 10 and 11.

FIG. 13 is a timing chart for explaining the operation of the shift register shown in FIGS. 10 and 11.

14 is a timing chart for explaining the operation of the shift register shown in FIGS. 10 and 11.

FIG. 15 is a circuit configuration diagram showing a vertical scanning circuit of a third embodiment.

16 is a timing chart for explaining the operation of the vertical scanning circuit of the third embodiment shown in FIG.

FIG. 17 is a circuit configuration diagram showing a vertical scanning circuit of a fourth specific example of the present invention.

FIG. 18 is a timing chart for explaining the operation of the vertical scanning circuit of the fourth embodiment shown in FIG.

FIG. 19 is a block diagram showing a configuration example of a conventional solid-state imaging device having a shutter function.

20 is a diagram showing the timing of output scanning pulses of the vertical scanning circuit in the conventional solid-state imaging device shown in FIG.

[Explanation of symbols]

 1 shift register 2 read / reset identification means 3 combination means 4 vertical scanning circuit 5 horizontal scanning circuit 6 light receiving section

Claims (1)

[Claims] 1. A light receiving part, in which photoelectric conversion elements are two-dimensionally arranged in a matrix as pixels, and horizontal and vertical scanning circuits for sequentially addressing and reading a light accumulated charge signal of each pixel of the light receiving part. In the solid-state imaging device, the vertical scanning circuit sequentially shifts and outputs pulses at the timings of reading and resetting, and the reading by the shift pulse and the control signal shifted and output from the pulse shift output means. And means for identifying the reset timing, and the outputs from the pulse shift output means and the read / reset identifying means, sequentially corresponding pixel rows of the light receiving unit in synchronization with the pulse shifted at the read and reset timings. And a means for generating a read signal and a reset signal to be selected. Solid-state image sensor.