JPH1098653A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device in which a storage time of a photoelectric conversion element in a field A is made equal to that in a field B in the case of interlace scanning for two-row additive mixture in the solid-state image pickup device of the X-Y address type provided with photoelectric conversion elements arranged in a 2-dimension array. SOLUTION: The device is provided with a photoelectric conversion element group where photoelectric conversion elements 6 are arranged in a 2-dimension array, a 1st vertical scanning circuit 8 connecting to horizontal selection lines 7-1,... arranged in common to odd number rows of the photoelectric conversion element group, and a 2nd vertical scanning circuit 9 connecting to horizontal selection lines 7-2,... arranged in common to even number rows of the photoelectric conversion element group. Each vertical scanning circuit is configured with a vertical shift register 1(2) and a focal plane shutter circuit 3(4), and the focal plane shutter operation is conducted for each picture element row after the end of the read operation to make the storage time of a field A equal to that of a field B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a vertical and horizontal scanning circuit for arranging photoelectric conversion elements in a two-dimensional array, and for sequentially reading out signals from the photoelectric conversion elements at the periphery of the photoelectric conversion element group. In addition, the present invention relates to an XY address type solid-state imaging device that performs interlaced scanning with addition and mixing of two rows.

[0002]

2. Description of the Related Art Conventionally, photoelectric conversion elements arranged in a two-dimensional array and a vertical and horizontal scanning circuit for reading out signals of the photoelectric conversion element group are provided, and interlaced scanning is performed by adding and mixing two rows. As an XY address type solid-state imaging device, one having a configuration as shown in FIG. 13 is known, and interlaced scanning of two rows mixed in the solid-state imaging device having such a configuration is described in a timing chart of FIG. It is performed as shown. In FIG. 13, reference numeral 101 denotes a photoelectric conversion element arranged in a two-dimensional array.
Horizontal scanning circuit 102 for sequentially reading the signals from 101
And a vertical scanning circuit 103.
Each unit stage of the vertical scanning circuit 103 is arranged so as to correspond to two photoelectric conversion elements arranged in the horizontal direction, and the output of each unit stage of the vertical scanning circuit 103 is used for two adjacent horizontal conversion units when performing interlaced scanning. Switch for selecting selection lines at the same time
Interlace circuit 10 consisting of 104-1, 104-2, ...
4 photoelectric conversion elements arranged in a two-dimensional array
Are connected to the 101 horizontal selection line groups 105-1, 105-2, 105-3,...

[0003] The interlace circuit 104 has a field index pulse φ input to the interlace circuit 104.
Since the FDX is configured to determine a pair of two adjacent horizontal selection lines, the read operation and the reset operation are performed at the same timing on the selected two adjacent horizontal selection lines. It has become.
The pair of horizontal selection lines selected at the time of interlaced scanning is, for example, in the A field, the horizontal selection line group 105-1 connected to the photoelectric conversion elements arranged in a two-dimensional array.
.., 105-2, 105-3, 105-4, 105-5, 105-6,... Are selected and read out two rows at a time. On the other hand, in the B field, the combination of the selected horizontal selection line pair changes, and only the first horizontal selection line 105-1 is read independently, and then the horizontal selection line group 105-2 is read out.
As in 105-3, 105-4, 105-5, 105-6, and 105-7, two rows are sequentially selected simultaneously and signals are read out.

[0004]

When interlaced scanning is performed using such an interlaced circuit, attention is paid to an even-numbered horizontal selection line that does not directly correspond to the output of each unit stage of the vertical scanning circuit. , A field readout, that is, when the field index pulse φFDX is “L”, the readout is performed at the same timing as the horizontal selection line of the odd row one row before. However, when the field index pulse φFDX becomes “H” in the reading of the B field, the reading is performed at the same timing as the odd-numbered horizontal selection line one row after. That is, the accumulation operation time of the horizontal selection lines 105-1, 105-3, 105-5,... Corresponding to the odd-numbered photoelectric conversion elements is 1 V for both the A field and the B field (1 V is 1 V).
(Corresponding to the vertical scanning period), but the horizontal selection lines 105-2, 105-4, 105-6,... Corresponding to the photoelectric conversion elements in the even-numbered rows.
Storage operation time is (1V-1) for the A field.
H) <1H corresponds to one horizontal scanning period>, and (1V + 1H) in the case of the B field.

[0005] Therefore, when two-row mixed reading is performed in interlaced scanning, a signal having an accumulation time of 1 V and a signal of (1 V-1 H) are added in the A field. In the B field, the accumulation time is 1 V
Is added to the signal of (1V + 1H), and the accumulation time is longer in the B field by 2H period than in the A field. This means that even when a subject with a uniform light quantity is imaged, the output signal differs for each field, which causes flicker. In the case of a single-chip color camera equipped with a color filter,
Similarly, the color signal will be different for each field.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem in the conventional solid-state imaging device of the two-row addition mixed interlace scanning system, and an XY address in which photoelectric conversion elements are arranged in a two-dimensional array. When performing interlaced scanning with two-line addition and mixing in a solid-state imaging device of
An object of the present invention is to provide a solid-state imaging device in which the accumulation time in the field and the accumulation time in the B field are equal.

[0007]

In order to solve the above-mentioned problems, the invention according to claim 1 includes a plurality of photoelectric conversion elements arranged in a two-dimensional array and a plurality of photoelectric conversion elements arranged in a peripheral portion of the photoelectric conversion element group. An X- scan circuit having a horizontal scanning circuit for scanning the photoelectric conversion element group in the horizontal direction and a vertical scanning circuit for scanning in the vertical direction, and performing interlaced scanning of two-row addition and mixing.
In a Y-address type solid-state imaging device, a first vertical scanning circuit connected to a horizontal selection line commonly disposed in each of odd-numbered rows of the photoelectric conversion element group, and an even-numbered row of the photoelectric conversion element group. A second vertical scanning circuit connected to a commonly disposed horizontal selection line, wherein the first and second vertical scanning circuits include a shift register and a shutter circuit, and the input of the shift register and the The configuration is such that the storage times of the photoelectric conversion elements in the A field and the B field are equalized by the shutter function of the shutter circuit.

According to a second aspect of the present invention, in the solid-state imaging device according to the first aspect, the shutter circuit is reset by a focal plane type shutter operation for each row after a read operation of the photoelectric conversion element is completed. Make up. According to a third aspect of the present invention, in the solid-state imaging device according to the first or second aspect, the sum of the storage operation times of the two horizontal selection lines that are selected and added and mixed is equal in the A field and the B field. It is characterized by being constituted. Claim 4
According to another aspect of the present invention, in the solid-state imaging device according to the first or second aspect, the storage operation times of the two horizontal selection lines that are selected and added and mixed are equal to each other. is there.

[0009]

Next, an embodiment will be described. FIG. 1 is a conceptual diagram showing the first embodiment. In this embodiment, for example, the present invention is applied to a solid-state imaging device having a MOS type photoelectric conversion element such as a CMD as a pixel, and in FIG. 1, reference numeral 1 denotes a left side of a photoelectric conversion element group. , A first vertical shift register for shifting a read pulse, a second vertical shift register similarly arranged on the right side, and 3 at each stage of the first vertical shift register 1 for performing a shutter operation. A correspondingly provided focal plane type shutter circuit, 4 is a focal plane type shutter circuit similarly provided in the second vertical shift register 2, 5 is a horizontal scanning circuit for performing horizontal scanning, and 6 is light receiving. The photoelectric conversion elements 7-1, 7-3, and 7-5 constituting the unit are odd-numbered horizontal selection lines connected to the first vertical shift register 1, and 7-2, 7
Reference numerals -4 and 7-6 denote even-numbered horizontal selection lines connected to the second vertical shift register 2. The first vertical scanning circuit 8 is composed of a first vertical shift register 1 and an associated focal plane type shutter circuit 3, and the second vertical scanning circuit 9 is composed of the second vertical shift register 2 and the focal plane shutter circuit 3. And a plane-type shutter circuit 4.

A first vertical shift register 1 for shifting a read pulse in a first vertical scanning circuit 8
Each of the unit stages 10 has a clocked C as shown in FIG.
It is composed of two stages of MOS inverters, and a unit stage of the first vertical shift register 1 is provided so as to correspond to two photoelectric conversion elements arranged in the vertical direction. First
, A two-phase driving clock φ1 and φ2 for sequentially shifting the read pulse and their respective inverted clocks / φ1 and / φ2 are input to the first stage of the first vertical shift register 1. φVST
3, the output terminal of each unit stage of the first vertical shift register 1 is synchronized with the falling edge of the drive clock φ1 as shown in FIG.
The read pulses are sequentially shifted as indicated by 1, S1-2, S1-3,....
Here, one cycle of the drive clock φ1 corresponds to a 1H period. In FIG. 2, S1-0.5, S1-1.5,
.. Indicate the output of the first clocked inverter of the two-stage clocked inverter forming each unit stage of the first vertical shift register 1. The same applies to the second vertical shift register 2 disposed on the right side of the photoelectric conversion element group 6, and the driving clocks φ1 and φ2 for driving the vertical shift registers 1 and 2 are commonly used. In the same manner, the start pulse φVST
2 is input.

The respective unit stages of the first vertical shift register 1 and the second vertical shift register 2 are connected to focal plane type shutter circuits 3 and 4, respectively. Has a circuit configuration as shown in FIG. 4, for example.
In FIG. 4, the source of the P-ch transistor 11 and the source of the P-ch transistor 12 are both connected to the high power supply voltage V _DD , and the drain of the P-ch transistor 11 is connected to the source of the P-ch transistor 13. , The drain of the P-ch transistor 12 and the drain of the P-ch transistor 13 are connected.
The sources of the N-ch transistors 15 and 16 are commonly Low
Side is connected to the power supply voltage V _SS . On the other hand, the drain of the N-ch transistor 15 and the drain of the N-ch transistor 16
And the source of the N-ch transistor 14 are connected. N-
The drain of ch transistor 14 is P-ch transistors 13 and 12
And the above constituent elements constitute the unit stage 17 of the shutter circuit.

The gates of the P-ch transistor 11 and the N-ch transistor 15 constituting the unit stage 17 of the shutter circuit are connected to the output of the corresponding unit stage of the vertical shift register by the clocked inverter one stage before. Output S1-0.5
(S2-0.5), the P-ch transistor 12 and the N-ch
The gate of the transistor 14 is connected to the output S1-1 (S2-1) of each corresponding unit stage of the vertical shift register. Also, the P-ch transistor 13 and the N-ch transistor 16
Are connected to the output S1-1.5 (S2-1.5) of the clocked inverter one stage after the output of the corresponding unit stage. Note that the focal plane shutter circuit 3
The output of each unit stage 17 is taken out from the connection point of each drain of the P-ch transistor 12, the P-ch transistor 13 and the N-ch transistor 14, and is output through an inverter circuit 18 provided in each unit stage. Horizontal selection line 7 of each odd-numbered row of the conversion element group
-1, 7-3, and 7-5.

The second vertical scanning circuit 9 has the same configuration as that of the first vertical scanning circuit 8. Each output of the second vertical scanning circuit 9, that is, the output of each unit stage of the shutter circuit 4 is , The horizontal selection line 7-2 of each even-numbered row of the photoelectric conversion element group,
7-4 and 7-6, respectively.

Next, the operation of the first embodiment configured as described above will be described with reference to the timing chart shown in FIG. In FIG. 5, φVST1 and φVST2 indicate start pulses input to the first unit stages of the first and second vertical shift registers 1 and 2, and output pulses of each unit stage of the first vertical shift register 1 are shown. S
At 1-1, S1-2, and S1-3, the output pulses of each unit stage of the second vertical shift register 2 are converted to S2-1, S2-2, and S2-1.
This is indicated by S2-3. First, the reading operation of the A field will be described. At time t _10, the first stage unit stages of the vertical shift register 1 which is disposed on the left side of the array of the photoelectric conversion element group in a two-dimensional array, the readout start pulse FaiVST1 2 cycles of the driving clock .phi.1 (Clock (two periods of φ1 correspond to a 2H period). The read start pulse is sequentially shifted, from t ₁₁ to
In a period of t _12, the first vertical output of the first-stage unit stage of the shift register 1 S1-1 and the first output of the clocked inverter of the next stage unit stage S1-1.5 (first clocked inverter outputs S1 −0.5, S1-1.5,... Are not shown). Shutter circuit 3
Is the output S of the first unit unit of the first vertical shift register 1
1-1 and the output S of the clocked inverter of the next unit stage
When both 1-1.5 are "H", the N-ch transistors 14 and 16 are both "ON", and the horizontal selection line 7-1 corresponding to the output of the first unit unit of the shutter circuit 3 is "H".

In the period from t _{14 to} t ₁₅ , the first
Output S1-0.5 of the clocked inverter of the first unit unit and the output S1-1 of the first unit unit of the vertical shift register 1 of FIG.
Are both "H", the N-ch transistors 14 and 15 are both "ON", and the horizontal selection line 7-1 corresponding to the output of the first unit unit of the shutter circuit 3 is "H". However, in other periods, the N-ch transistors 14 and 15
Alternatively, the horizontal selection line 7-1 is set to "L" since neither of them is turned "ON". That is, the output of the first unit unit of the shutter circuit 3, that is, the output of the horizontal selection line 7-1 is t.
₁₁ ~t ₁₂ period "H" next to, for the rest t ₁₂ ~t ₁₄ becomes "L", the period of t ₁₄ ~t ₁₅ is "H". Thus, the horizontal selection lines 7-1, after the signal reading operation of the photoelectric conversion elements in the period of t ₁₁ ~t ₁₂ the output of the shutter circuit 3 becomes "H", t ₁₄ ~ after a lapse of 1H period
the reset operation is performed in the period of t _15, it becomes a signal to sweep out charges.

[0016] Similarly, in the second vertical shift register 2, the read start pulse φVST at t ₁₀
By inputting (corresponding to 2H period) 2 2 cycles of the clock .phi.1, after the horizontal selection line 7-2 of performing a read operation in the period of t ₁₁ ~t _12, after a lapse of 1H period t ₁₄
In the period of ~t _15, so that the reset operation is performed. In the A field, the horizontal selection lines 7-1 and 7
-2 performed simultaneously reading operation period of t ₁₁ ~t _12,
The reset operation is performed in the period of t ₁₄ ~t ₁₅ after a lapse of 1H period, a signal to sweep out charges. After that, in the same manner, the read operation is sequentially performed on the pairs of the horizontal selection lines 7-3 and 7-4 and 7-5 and 7-6, and then the reset operation is performed after a lapse of 1H period. As described above, in the A-field, the start pulses φVST1 and φVST2 are input to the first and second vertical shift registers 1 and 2 for two cycles of the clock φ1 so that the shutter circuits 3 and 4 function. The signal charge accumulated in the 1H period after the end of the read operation is swept away, and the accumulation time of the B field is shortened by 1H.

Next, the reading operation of the B field will be described. In t _20, the first readout start pulse φVST1 the vertical shift register 1 clock φ1
For one cycle (corresponding to the 1H period). In a period of t ₂₁ ~t _22, clocked inverter output S1-1.5 output S1-1 and the next stage unit stage of the first stage unit stages of the vertical shift register 1 are both "H". In the shutter circuit 3, when both the output S1-1 of the first unit stage of the first vertical shift register 1 and the output S1-1.5 of the clocked inverter of the next unit stage become "H", the N-ch transistors 14 and 16 Are both "ON", and the shutter circuit 3
The horizontal selection line 7-1 corresponding to the output of the first unit unit at “H” goes “H”. The first in a period of t ₂₂ ~t ₂₃
Since both the output S1-0.5 of the clocked inverter of the first-stage unit stage and the output S1-1 of the first-stage unit stage of the vertical shift register 1 become "H", both the N-ch transistors 14 and 15 become "ON", The horizontal selection line 7-1 corresponding to the output of the first unit unit of the shutter circuit 3 becomes "H". Thus, the horizontal selection lines 7-1 of odd rows connected to the first vertical shift register 1 performs signal read operation in a period of t ₂₁ ~t _22, reset at the period of t ₂₂ ~t ₂₃ immediately after Performs operation and sweeps out signal charges.

[0018] The second vertical shift register 2, in t ₂₁ a start pulse FaiVST2, i.e. by one cycle delay input of the first clock φ1 than the vertical shift register 1, different horizontal and A Field Interlace scanning can be performed by a combination of pairs of selection lines, and a reset operation is performed immediately after the end of the read operation, similarly to the horizontal selection lines in the odd-numbered rows.

[0019] By inputting a start pulse to the first and second vertical shift registers 1 and 2 at the timing as described above, performs a signal read operation in a period of the horizontal selection line 7-1 only t ₂₁ ~t ₂₂ , the reset operation is performed in the period of t ₂₂ ~t _23. Thereafter, reading is sequentially performed on the pairs of the horizontal selection lines 7-2 and 7-3 and 7-4 and 7-5,
Immediately after that, the reset operation is performed.

As described above, the first vertical scanning circuit 8 and the second vertical scanning circuit 9 are provided on both sides of the photoelectric conversion element group, respectively. Second vertical shift register 2
, The start pulses φVST1 and φVST2 are input for two periods of the clock φ1, and the first pulse is input in the B field.
Start pulse φVS for both vertical shift registers 1 and 2
By inputting T1 and φVST2 for one cycle of the clock φ1, in the A field, the operation of the focal plane shutter circuits 3 and 4 causes the read operation to be completed.
After the elapse of the 1H period, the reset operation is performed, and the accumulation time of the B field is shortened by the 1H period. Therefore, the sum of the accumulation times of the two horizontal selection lines that are selected and added when the interlaced scanning of the two-row mixed reading is performed is (2V-
1H) is equal to both the A field and the B field, and the difference in the accumulation time for each field can be eliminated. In particular, when the accumulation time is extremely short by performing the electronic shutter operation, the effect becomes more remarkable.

Next, a second embodiment will be described. The basic configuration of the solid-state imaging device according to the second embodiment is the same as that of the first embodiment shown in FIGS. 1, 2 and 4, except for the first field during the A-field read operation. A start pulse φVST1 for two cycles of the clock φ1 is input to the vertical shift register 1, a start pulse φVST2 for three cycles of the clock φ1 is input to the second vertical shift register 2, and the first vertical shift is performed in the B field. A start pulse φVST1 for two cycles of the clock φ1 is input to the register 1, and a start pulse φVS for one cycle of the clock φ1 is input to the second vertical shift register 2.
It is configured to input T2.

Next, the operation of the second embodiment configured as described above will be described with reference to the timing chart shown in FIG. First, the reading operation of the A field will be described. At time t _10, the first stage unit stages of the vertical shift register 1, read start pulse φV
ST1 is input for two cycles of the clock φ1. Read start pulse is sequentially shifted, t ₁₁ in the period of ~t _12, clocked inverter output S1-1.5 output S1-1 and the next stage unit stage of the first stage unit stages of the vertical shift register 1 are both It becomes "H". The shutter circuit 3
Output S1- of the first stage unit stage of the first vertical shift register 1
1 and the output S1- of the clocked inverter of the next unit unit
When both 1.5 become “H”, the N-ch transistors 14 and 16 both become “ON”, and the horizontal selection line 7-1 corresponding to the output of the first unit stage of the shutter circuit 3 becomes “H”. Also,
t ₁₄ ~t in the period of ₁₅ output of the clocked inverter of the first stage unit stages of the vertical shift register 1 S1-0.
5 and the output S1-1 of the first-stage unit are both "H", so that the N-ch transistors 14 and 15 are "ON", and the horizontal selection line 7- corresponding to the output of the first-stage unit of the shutter circuit 3 is output.
1 becomes "H". However, in the other periods, the output of the first unit unit of the shutter circuit 3 becomes “L”. That is, the horizontal selection line 7-1 corresponding to the output of the first-stage unit stage of the shutter circuit 3 for a period of t ₁₁ ~t ₁₂ becomes "H",
Thereafter a period of t ₁₂ ~t ₁₄ becomes "L", the period of t ₁₄ ~t ₁₅ is "H". Thus, the horizontal selection lines 7-1 t ₁₁ ~
performs a read operation in the period t _12, then, 1H
The reset operation is performed in the period of t ₁₄ ~t ₁₅ after a lapse of time, draining the accumulated signal charges.

On the other hand, the second vertical shift register 2 at time t _10, by the read start pulse FaiVST2 3 cycles input clock .phi.1, the t ₁₁ ~t ₁₂ with respect to the horizontal selection line 7-2 after performing the read operation period, so as to perform a reset operation in a period of t ₁₆ ~t ₁₇ after a lapse 2H period. Similarly, in the A field, the horizontal selection lines 7-3 and 7-
In the pairs of 4, 7-5 and 7-6, the read operation is sequentially performed simultaneously, but the reset operation is performed for the odd-numbered horizontal selection lines (7-1, 7-3, 7-5). The operation is performed after a lapse of 1H period after the operation is completed, and the horizontal selection lines (7
-2, 7-4, 7-6), the reset operation is performed after a lapse of 2H period after the end of the read operation.

Next, the reading operation of the B field will be described. At time t _20, the read start pulse φVST1 input two cycles of the first clock φ1 to the first stage unit stages of the vertical shift register 1. In a period of t ₂₁ ~t _22, clocked inverter output S1-1.5 output S1-1 and the next stage unit stage of the first stage unit stages of the vertical shift register 1 are both "H". When the output S1-1 of the first unit stage of the first vertical shift register 1 and the output S1-1.5 of the clocked inverter of the next unit stage both become "H", the shutter circuit 3 outputs the N-ch transistor 1
4 and 16 are turned “ON”, and the output of the first unit unit of the shutter circuit 3 becomes “H” via the inverter circuit 18. Further, in a period of t ₂₄ ~t _25, the output S of the clocked inverter of the first stage unit stages of the vertical shift register 1
Since both 1-0.5 and the output S1-1 of the first unit stage become “H”, the N-ch transistors 14 and 15 of the shutter circuit 3 are turned “ON”, and the output of the shutter circuit 3 is output via the inverter circuit 18. It becomes "H". Horizontal selection lines 7-1 corresponding to the output of the first-stage unit stage of the shutter circuit 3 for a period of t ₂₁ ~t ₂₂ and t ₂₄ ~t ₂₅ becomes "H". Accordingly, performs signal read out in the horizontal selection line 7-1 period t ₂₁ ~t _22, the reset operation is performed in the period of t ₂₄ ~t ₂₅ after the elapse of the subsequent 1H period.

On the other hand, a second start pulse φVST2 the vertical shift register 2, at time t _21, by entering one cycle of the clock .phi.1, horizontal selection lines 7-
2 the read operation is performed in the period of t ₂₃ ~t _24,
The reset operation is performed in the period that immediately after t ₂₄ ~t _25. Hereinafter, similarly, in the B field, only the horizontal selection line 7-1 is independently read out, and thereafter, 7-2 and 7-3, and so on.
The read operation is sequentially performed in pairs of 7-4 and 7-5, and the reset operation is performed in the odd-numbered horizontal selection lines (7-1, 7).
-3, 7-5) are performed after a lapse of 1H period from the end of the read operation, and the even-numbered horizontal selection lines (7-
For 2,7-4,7-6), a reset operation is performed immediately after the end of the read operation.

As described above, in the second embodiment, the first vertical shift register 1 and the second vertical shift register 2 are provided on both sides of the photoelectric conversion element group, respectively. , The start pulse φVST1 is supplied to the first vertical shift register 1 by the clock φ1.
, And the start pulse φVST2 is input to the second vertical shift register 2 for three cycles of the clock φ1, while the start pulse φVST1 is input to the first vertical shift register 1 for the clock φ1 in the B field. 2
By inputting the start pulse φVST2 for one cycle to the second vertical shift register 2 for one cycle, one cycle of the clock φ1 is selected at the same time when the interlaced scanning of the two-row mixed readout is performed by the function of the focal plane shutter circuit. Storage time for each of the two horizontal selection lines (1
V-1H), and the storage time for each field is also equal.

In the first embodiment, the configuration is such that the sum of the accumulation operation times of the two selected horizontal selection lines is equal. In the present embodiment, the selected horizontal selection line is selected. The accumulation operation time for each filter is also completely equal, and especially in a single-chip color camera equipped with a color filter, the accumulation time of the color signal for each filter is completely equal.

In each of the first and second embodiments, a shift register composed of a clocked CMOS inverter is used as a vertical shift register. However, sequential reading is performed by clock control. As long as the shift register shifts the pulse, the above-described scanning can be performed by another type. It is apparent that the operation of the above-described embodiment is also possible for the focal plane shutter circuit as long as the circuit other than the circuit shown in FIG. 4 is a focal plane shutter circuit having the same function. It is.

Next, a third embodiment will be described with reference to FIG. This embodiment has an internal amplification type photoelectric conversion element as a pixel, and recently has an APS (Active Pixel Sequential).
The present invention is applied to a solid-state imaging device in which a readout line and a reset line are separately connected like, for example, an AMI. As shown in FIG. 7, similarly to the first and second embodiments, a first vertical scanning circuit 28 and a first vertical scanning circuit 28 are provided on both sides of a photoelectric conversion element group in which photoelectric conversion elements 26 are arranged in a two-dimensional array. 2 vertical scanning circuits 29
The vertical scanning circuits 28 and 29 are composed of vertical shift resists 1 and 2 each composed of a clocked CMOS inverter for sequentially shifting read pulses, and focal plane shutter circuits 23 and 24. . The shutter circuits 23 and 24 have a configuration as shown in FIG. 8, for example. In FIG. 8, the source of the P-ch transistor 31 and the source of the P-ch transistor 32 are both connected to the high-side power supply voltage V _DD , and the drain of the P-ch transistor 31 and the P-ch
The source of transistor 33 is connected and a P-ch transistor
The drain of 32 and the drain of P-ch transistor 33 are connected. The source of the N-ch transistors 35 and 36 are connected to the power supply voltage V _SS of the Low side in common. On the other hand, N-
The drain of the channel transistor 35, the drain of the N-ch transistor 36 and the source of the N-ch transistor 34 are connected,
The drain of ch transistor 34 is P-ch transistors 33 and 32
And these components constitute each unit stage 37 of the shutter circuit. The connection point between the drain of the N-ch transistor 34 and the drains of the P-ch transistors 33 and 32 is The output of stage 37.

The gates of the P-ch transistor 31 and the N-ch transistor 35 are connected to the output S1-0.5 (S2-0.5) of the clocked inverter one stage before the output S1-1 of each unit stage of the corresponding vertical shift register. ), And the gates of the P-ch transistor 32 and the N-ch transistor 34 are connected to the corresponding unit stage S1-1 (S2-1) of the vertical shift register. Further, the gates of the P-ch transistor 33 and the N-ch transistor 36 are connected to the clocked inverter output S1-1.5 (S1
2-1.5). The output of each unit stage 37 of each shutter circuit is connected to an N-ch transistor 41 forming a transfer gate and a P-ch
N-ch transistor 43 and P-ch transistor which also constitute the source of transistor 42 and transfer gates
Connected to 44 sources.

An N-ch transistor 41 forming a transfer gate of the shutter circuit 23 of the first vertical scanning circuit 28
The drain of the P-ch transistor 42 is connected to a reset line (27-2, 27-6, 27-) corresponding to the odd-numbered row of photoelectric conversion element groups.
10) Also, N-ch transistor 43 and P-ch transistor
The drain 44 is connected to the readout lines (27-1, 27-5, 27-9) corresponding to the odd-numbered rows of photoelectric conversion element groups. The gates of the transistors 42 and 43 are connected to the inverted clock / φ3 of the clock φ3, and the gates of the transistors 41 and 44 are connected to the clock φ3. Similarly, the second vertical shift register 22 has the same configuration. Similarly, the output of the shutter circuit 24 is supplied via a transfer gate to a reset line (27-) corresponding to an even-numbered row of photoelectric conversion elements.
4, 27-8, 27-12) and readout lines (27-3, 27).
-7, 27-11). That is, the horizontal selection lines (readout lines and reset lines) corresponding to the odd-numbered photoelectric conversion elements correspond to the first vertical scanning circuit, and the horizontal selection lines (readout lines and reset lines) corresponding to the even-numbered photoelectric conversion elements correspond to the first vertical scanning circuit. It is connected to a second vertical scanning circuit.

Next, the operation of the third embodiment configured as described above will be described with reference to timing charts shown in FIGS. First, the reading operation of the A field will be described. At time t _10, the first stage unit stages of the vertical shift register 21 disposed on the left side of the array of the photoelectric conversion element group in a two-dimensional array, two cycles of the clock φ1 read start pulse FaiVST1 (clock φ1 (Corresponding to the 2H period). The read start pulse is sequentially shifted, from t ₁₁ to
In a period of t _12, the clocked inverter output S1-1.5 output S1-1 and subsequent stage units stage of the first stage unit stage of the first vertical shift register 21 are both "H" (S1
−0.5, S1-1.5,... Are not shown). In the shutter circuit 23, when the output S1-1 of the first unit unit of the first vertical shift register 21 and the output S1-1.5 of the clocked inverter of the next unit unit both become "H", the N-ch transistors 34 and 36 Are both "ON", and the output of the first unit unit of the shutter circuit 23 becomes "H" via the inverter circuit 38. Further, t ₁₄ in the period of ~t _15, since the output S1-1 of the clocked inverter output S1-0.5 and the first stage unit stage of the first stage unit stage of the first vertical shift register 21 are both "H", The N-ch transistors 34 and 35 are both “ON”, and the output of the first unit unit of the shutter circuit 23 is “H” via the inverter circuit 38. However, during the other periods, the N-ch transistors 34, 35, and 36 do not both turn “ON”, so that the output of the first unit unit of the shutter circuit via the inverter circuit 38 becomes “L”. That is, the output of the first unit unit of the shutter circuit becomes “H” during the period from t ₁₁ to t ₁₂ ,
Period of ₁₂ ~t ₁₄ becomes "L", the period of t ₁₄ ~t ₁₅ is "H".

The transfer gate connected to the output of the first unit unit of the shutter circuit is connected to the transistors 43 and 44 because the transistors 43 and 44 are "ON" while the clock φ3 is "L". Readout line
For 27-1 performs a read operation period t ₁₁ ~t _12, reads out the signal. Then, since the period of t ₁₄ ~t ₁₅ transistors 41 and 42 becomes "ON", the transistor
The reset line 27-2 connected to 41 and 42 becomes "H". Therefore, the horizontal selection line (readout line) 27-1
Performs a read operation in the period of t ₁₁ ~t _12, 1
In the period of t ₁₄ ~t ₁₅ after a lapse of H period by the horizontal selection line (reset line) 27-2 to perform a reset operation, the connected photoelectric conversion elements to the horizontal selection line 27-1 and 27-2 The reset operation is performed after a lapse of 1H period after the read operation.

[0034] Similarly, in the second vertical shift register 22 at time t _10, the read start pulse φ
VST2 for two cycles of clock φ1 (corresponding to 2H period)
By inputting, the horizontal selection line (readout line) 27
After the read operation in the period of t ₁₁ ~t ₁₂ for -3, horizontal selection lines in the period of t ₁₄ ~t ₁₅ after a lapse of 1H period (reset line) 27-4 reset operation against And sweep away the signal charge.

As described above, the horizontal selection lines 27-1 and 27-3
Performed simultaneously read operation period t ₁₁ ~t ₁₂ for the reset in a period of t ₁₄ ~t ₁₅ after a lapse of a read operation after the end of the 1H period with respect to the horizontal selection lines 27-2 and 27-4 Perform the operation. Similarly, in the A field, the read operation is sequentially performed on the pairs of the horizontal selection lines 27-5 and 27-7 and 27-9 and 27-11, and the horizontal selection lines 27-6 and 27-27 after 1H period. 8. The reset operation is sequentially performed in pairs of 27-10 and 27-12. As described above, in the A field, both the start pulses φVST1 and φVST2 for the two cycles of the clock φ1 are input to the first and second vertical shift registers 21 and 22, so that the focal plane shutter circuits 23 and 24 are input. By sweeping out the signal charges accumulated during the 1H period after the end of the read operation by the function of (1), the accumulation time of the B field is shortened by 1H.

Next, the reading operation of the B field will be described. At time t _20, the read start pulse FaiVST1 (corresponding to 1H period) 1 cycle of the clock φ1 to the first vertical shift register 21 for input. t
₂₁ in a period ~t _22, the first vertical shift register
The output S1-1 of the first unit stage and the output S1-1.5 of the clocked inverter of the next unit stage both become "H".
Output S1- of the first unit stage of the first vertical shift register 21
1 and the output S1- of the clocked inverter of the next unit unit
When 1.5 is both "H", the shutter circuit 23 turns on both the N-ch transistors 34 and 36, and the shutter circuit 23
The output of the first unit unit is “H” through the inverter circuit 38.
Becomes Further, in a period of t ₂₂ ~t _23, since the output S1-1 of the clocked inverter output S1-0.5 and the first stage unit stage of the first stage unit stage of the first vertical shift register 21 are both "H", The N-ch transistors 34 and 35 are both “ON”, and the output of the first unit unit of the shutter circuit 23 is “H” via the inverter circuit 38. In the transfer gate, during the horizontal effective scanning period, that is, during the period when the clock φ3 is “L”, the transistors 43 and 44 are
Since but a "ON", the read operation in the read line 27-1 during the period of t ₂₁ ~t _22. Immediately thereafter, t
₂₂ period ~t ₂₃ transistor 41 of shutter circuit 23 and 42
Becomes "ON", the reset line 27-2 becomes "H".
Becomes Thus, the horizontal selection lines where the first vertical shift register 21 corresponding to the photoelectric conversion elements of the first row being connected (read line) 27-1 performs a signal read operation in a period of t ₂₁ ~t _22, t ₂₂ the period ~t ₂₃ performs a reset operation in the horizontal selection line (reset line) 27-2.

[0037] The second start pulse φVST2 similarly to the vertical shift register 22, at t _21, i.e. by one cycle delay input also clocks φ1 than the first vertical shift register 21, the A field Interlaced scanning can be performed by a combination of different pairs of horizontal selection lines, and a reset operation is performed immediately after the end of the read operation similarly to the horizontal selection lines in the odd-numbered rows. Therefore, only the photoelectric conversion element group corresponding to the horizontal selection line 27-1,
read operation is performed in the period of t ₂₁ ~t _22, t ₂₂
The reset operation is performed in ~t _23. Thereafter, the read operation is sequentially performed on the pairs of the horizontal selection lines 27-3 and 27-5, 27-7 and 27-9, and immediately thereafter, the horizontal selection lines 27-4 and 27-27 are read.
The reset operation is sequentially performed in pairs of 6, 27-8 and 27-10.

As described above, in the third embodiment, the first vertical shift register is provided on both sides of the photoelectric conversion element group.
21 and a second vertical shift register 22 are provided.
In the field read operation, the first vertical shift register 21 and the second vertical shift register 22 both receive start pulses φVST1 and φVST2 for two cycles of the clock φ1. By inputting the start pulses φVST1 and φVST2 for one cycle of the clock φ1 to both the second vertical shift registers 22, the reset operation is performed after the lapse of 1H period after the end of the read operation by the operation of the focal plane shutter circuit in the A field. As a result, the accumulation time of the B field is shortened by 1H period. Therefore, when the interlaced scanning of the two-row mixed reading is performed, the sum of the accumulation times of the two selected horizontal selection lines becomes equal, and the difference in the accumulation time for each field can be eliminated. This effect is remarkable especially when the accumulation time is extremely short due to the electronic shutter operation.

Next, a fourth embodiment will be described. The basic configuration of the solid-state imaging device according to the fourth embodiment is the same as that of the third embodiment shown in FIG.
In the field read operation, a start pulse φVST1 for two cycles of the clock φ1 is input to the first vertical shift register 21 and the second vertical shift register 22
Start pulse φVST for three cycles of clock φ1
2, a start pulse φVST1 for two cycles of the clock φ1 is input to the first vertical shift register 21 in the B field, and a start pulse for one cycle of the clock φ1 is input to the second vertical shift register 22. It is configured to input φVST2.

Next, the operation of the fourth embodiment thus configured will be described with reference to the timing charts shown in FIGS. First, the reading operation of the A field will be described. The first stage unit stage of the first vertical shift register 21 at time t _10, the read start pulse FaiVST1, enter two periods of the clock .phi.1. The read start pulse is sequentially shifted, from t ₁₁ to
In a period of t _12, the clocked inverter output S1-1.5 output S1-1 and subsequent stage units stage of the first stage unit stage of the first vertical shift register 21 are both "H". In the shutter circuit 23, when both the output S1-1 of the first unit stage of the first vertical shift register 21 and the output S1-1.5 of the clocked inverter of the next unit stage become "H", the N-ch
The transistors 34 and 36 are both "ON", and the output of the first unit unit of the shutter circuit 23 is "H" via the inverter circuit 38. Further, t ₁₄ in the period of ~t _15, the output of the first output S1-0.5 and the first stage unit stage of the clocked inverter of the first stage unit stages of the vertical shift register 21 S1-1
Are both "H", the N-ch transistors 34 and 35 are "ON", and the output of the first unit unit of the shutter circuit 23 is "H" via the inverter circuit 28. However, in other periods, the output of the first unit unit of the shutter circuit 23 becomes “L”. That is, the output of the first unit unit of the shutter circuit 23 becomes “H” during the period from t ₁₁ to t ₁₂ ,
Period of ₁₂ ~t ₁₄ becomes "L", the period of t ₁₄ ~t ₁₅ is "H". Thus, t ₁₁ in the horizontal selection lines 27-1 to
performs a read operation period t _12, after the lapse of 1H period t
Horizontal selection lines 27-2 during the period of ₁₄ ~t ₁₅ would perform the reset operation.

On the other hand, the second vertical shift register 22 at time t _10, by the read start pulse FaiVST2 3 cycles input clock .phi.1, the t ₁₁ ~t ₁₂ with respect to the horizontal selection line 27-3 period reads operation, in the period of t ₁₆ ~t ₁₇ after a lapse 2H period, the reset operation is performed with respect to the horizontal selection line 27-4. Similarly, in the A field, the horizontal selection lines 27-5 and 27-
7, 27-9 and 27-11, the read operation is sequentially performed simultaneously, but the reset operation is performed on the odd-numbered horizontal select lines (27-2, 27-6) after the read operation is completed. 1
This is performed after the elapse of the H period, and the horizontal selection lines (27−
4, 27-8) is performed after a lapse of 2H period after the end of the read operation.

Next, the reading operation of the B field will be described. At time t _20, the read start pulse φVST1 input 2 cycles of the clock φ1 in the first stage unit stage of the first vertical shift register 21. In a period of t ₂₁ ~t _22, clocked inverter output S1-1.5 output S1-1 and subsequent stage units stage of the first stage unit stage of the first vertical shift register 21 are both "H". Shutter circuit
At 23, when both the output S1-1 of the first unit stage of the first vertical shift register 21 and the output S1-1.5 of the clocked inverter of the next unit stage become "H", the N-ch transistors 34 and 36 become "H". ON ”, and the output of the first unit unit of the shutter circuit 23 becomes“ H ”via the inverter circuit 38.
Further, in a period of t ₂₄ ~t _25, since the first stage unit stage clocked output of the inverter S1-0.5 the output of the first stage unit stages S1-1 of the vertical shift register 21 are both "H", N-ch transistors 34 and 35 are turned “ON”,
The output of the first unit unit of the shutter circuit 23 is an inverter circuit 38.
To “H” via Therefore, the output of the first stage unit stage of the shutter circuit 23 has a period of t ₂₁ ~t ₂₂ and t ₂₄ ~t ₂₅ to "H". Thus, the horizontal selection lines 27-1 t ₂₁ ~
performs signal read operation in a period of t _22, horizontal selection lines in the period of t ₂₄ ~t ₂₅ after the lapse of 1H period 27-2
Reset operation.

On the other hand, the start pulse φVST2 the second vertical shift register 22 at time t _21, by entering one cycle of the clock .phi.1, horizontal selection lines 27-
3 performs a read operation in the period of t ₂₃ ~t _24, the reset operation is performed to the horizontal selection line 27-4 in the period t ₂₄ ~t ₂₅ immediately thereafter, the swept signal charges accumulated. Hereinafter, similarly, in the B field, the horizontal selection line
The read operation is sequentially performed in pairs of 27-3, 27-5, 27-7, and 27-9, and the reset operation is performed by the horizontal selection lines (27-2, 27-6) corresponding to the odd-numbered photoelectric conversion elements. ) Is performed 1H after the end of the read operation, and a reset operation is performed immediately after the end of the read operation on the horizontal selection lines (27-4, 27-8) corresponding to the even-numbered rows of photoelectric conversion elements. Sweeps out the charge.

As described above, in the fourth embodiment, the first vertical shift register and the second vertical shift register are provided on both sides of the photoelectric conversion element group, respectively. , A start pulse φVST1 is input for two cycles of the clock φ1, and a start pulse φVST2 is input to the second vertical shift register for three cycles of the clock φ1, while the first vertical shift register is input in the B field. , A start pulse φVST1 for two cycles of the clock φ1, and a start pulse φVST2 in the second vertical shift register.
Is input for one cycle of the clock φ1, and the accumulation time (1V-V) of two horizontal selection lines simultaneously selected when interlaced scanning of two-row mixed reading is performed by the function of the focal plane shutter circuit.
1H) are completely equal, and the accumulation time for each field is also equal.

In the third embodiment, the configuration is such that the sum of the storage times of the two selected horizontal selection lines is equal. , The storage time of the color signal for each filter becomes completely equal, especially in a single-chip color camera equipped with a color filter. Further, even when the read line and the reset line are independently connected to the photoelectric conversion element as in the third and fourth embodiments, the accumulation time for each field can be made equal, and flicker can be reduced. Occurrence can be prevented.

In each of the third and fourth embodiments, a shift register composed of a clocked CMOS inverter is used as a vertical shift register. However, sequential reading is performed by clock control. As long as the shift register shifts the pulse, the above-described scanning can be performed by another type. In addition, the same operation as the above-described embodiment can be performed for the focal-plane shutter circuit as long as the focal-plane shutter circuit has the same function other than the circuit employed in the present embodiment. Is obvious.

In the first to fourth embodiments, the vertical scanning circuits are provided on both sides of the photoelectric conversion element group. However, even on one side, odd-numbered rows of photoelectric conversion elements and even-numbered rows of photoelectric conversion elements are provided. It is apparent that the same operation as in each of the above embodiments can be performed if the conversion elements are provided with the vertical scanning circuits independently of each other.

[0048]

As described above with reference to the embodiments, according to the present invention, the first vertical scanning connected to the horizontal selection lines commonly arranged on the odd-numbered rows of the photoelectric conversion element group, respectively. A shift circuit and a second vertical scanning circuit connected to a horizontal selection line commonly arranged in an even-numbered row by a shift register and a shutter circuit, and inputs to the shift register and a shutter function of the shutter circuit. , The accumulation times of the photoelectric conversion elements in the A field and the B field are equalized, so that there is no difference in the accumulation time between the fields, and the interlaced scanning of the two-row mixed readout without flicker can be performed. In particular, when the accumulation time is extremely short due to the shutter operation or the like, the advantage that the effect is remarkable is obtained.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram illustrating a first embodiment of a solid-state imaging device according to the present invention.

FIG. 2 is a circuit configuration diagram illustrating a configuration example of a shift register according to the first embodiment illustrated in FIG. 1;

FIG. 3 is a timing chart for explaining an operation of the shift register shown in FIG. 2;

FIG. 4 is a circuit configuration diagram illustrating a configuration example of a shutter circuit according to the first embodiment illustrated in FIG. 1;

FIG. 5 is a timing chart for explaining the operation of the first embodiment shown in FIG. 1;

FIG. 6 is a timing chart for explaining the operation of the second exemplary embodiment of the present invention.

FIG. 7 is a conceptual diagram showing a third embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration example of a shutter circuit according to the third embodiment shown in FIG. 7;

FIG. 9 is a diagram showing a part of a timing chart for explaining an operation of the third embodiment shown in FIG. 7;

FIG. 10 is a diagram illustrating the remaining part of the timing chart for describing the operation of the third embodiment illustrated in FIG. 9;

FIG. 11 is a diagram illustrating a part of a timing chart for explaining an operation of the fourth exemplary embodiment of the present invention.

FIG. 12 is a diagram showing the remaining part of the timing chart for explaining the operation of the fourth embodiment shown in FIG. 11;

FIG. 13 is a conceptual diagram illustrating a configuration example of a conventional solid-state imaging device.

14 is a timing chart for explaining the operation of the conventional example shown in FIG.

[Explanation of symbols]

1,21 First vertical shift register 2,22 Second vertical shift register 3,4,23,24 Shutter circuit 5,25 Horizontal shift register 6,26 Photoelectric conversion element 7-1,7-2, ... 7 -6, 27-1, 27-2, 27
−12 Horizontal selection line 8,28 First vertical scanning circuit 9,29 Second vertical scanning circuit 10 Shift register unit stage 11,12,13,31,32,33 P-ch transistors 14,15,16,34 , 35, 36 N-ch transistor 17, 37 Shutter circuit unit stage 18, 38 Inverter circuit 41, 43 N-ch transistor 42, 44 P-ch transistor

Claims (4)

[Claims] 1. A plurality of photoelectric conversion elements arranged in a two-dimensional array, a horizontal scanning circuit for performing horizontal scanning of the photoelectric conversion element group around the photoelectric conversion element group, and a vertical scanning circuit. A XY address type solid-state imaging device having a vertical scanning circuit for performing scanning in two lines and performing interlaced scanning with addition and mixing of two rows. A first vertical scanning circuit connected to a horizontal selection line; and a second vertical scanning circuit connected to a horizontal selection line commonly disposed on each of the even rows of the photoelectric conversion element group. The first and second vertical scanning circuits include a shift register and a shutter circuit, and the input times of the shift register and the shutter function of the shutter circuit make the accumulation times of the photoelectric conversion elements in the A field and the B field equal. A solid-state imaging device characterized by having such a configuration. 2. The solid-state imaging device according to claim 1, wherein the shutter circuit is configured to perform a reset by a focal plane type shutter operation for each row after a read operation of the photoelectric conversion element is completed. . 3. The apparatus according to claim 1, wherein the sum of the accumulation operation times of the two horizontal selection lines which are selected and added and mixed is equal in both the A field and the B field. Solid-state imaging device. 4. The solid-state imaging device according to claim 1, wherein the storage operation times of the two horizontal selection lines that are selected and added and mixed are equal to each other.