JP3353921B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device capable of coping with both interlaced scanning and non-interlaced scanning.

[0002]

2. Description of the Related Art A two-line mixed interlaced scanning system (hereinafter simply referred to as "interlaced scanning") generally used as a standard television system is applied to an XY address type image sensor. As disclosed in JP-A-58-53830,
A configuration is known in which an interlace circuit is provided between a vertical scanning circuit and a vertical selection line. FIG. 24 shows an example of the configuration. The image sensor of this configuration example includes a pixel composed of photoelectric conversion elements arranged in a two-dimensional array, a horizontal scanning circuit for column selection, a horizontal selection switch connected to a horizontal selection line, and an output signal line 4. , A vertical scanning circuit 5 for selecting a row, and an interlace circuit 6.
Then, 1 of the vertical scanning circuit 5 is applied to pixels in two columns in the vertical direction.
The bits correspond to each other, and the vertical selection lines V1, V2, V3,... Having different combinations for each field are selected by the interlace circuit 6 controlled by the control signals F1 and F2.

In recent years, video cameras have been increasingly used for industrial or measurement purposes. In addition to interlaced scanning in a standard television system, progressive scanning in which each vertical selection line can be independently selected is also available. There is an increasing need for an image sensor that can also support so-called non-interlaced scanning.

However, an image sensor having a configuration corresponding to the standard television system as shown in FIG. 24 cannot perform non-interlaced scanning. Therefore, a configuration of a vertical scanning circuit that can support two types of scanning modes, interlaced scanning and non-interlaced scanning, has been proposed. For example, Japanese Patent Application Laid-Open No. 63-292773 discloses a configuration in which a scanning mode control circuit is provided between a vertical scanning circuit and a vertical selection line. FIG. 25 shows the configuration. Figure
Compared with the configuration shown in FIG. 24, only the configuration of the scanning mode control circuit 7 that connects the vertical scanning circuit 5 and the vertical selection lines V1, V2, V3,. That is, the respective gates of _three selection MOS transistors Q ₁ , Q ₂ , Q ₃ are connected to the respective output terminals of the vertical scanning circuit 5, and the MOS transistor Q ₁ has a drive bias B ₁
The vertical selection lines V1, V3, V5, a · · ·, MOS transistor Q ₂ is the drive bias B2 vertical selection line V2, V
4, V6, to ..., MOS transistor Q ₃ are drive bias B3 vertical selection lines V1, V3, V5, which is configured to sequentially transfer ..., hence the drive bias B1, B2, B3 The scanning mode can be controlled by applying an appropriate combination. Also, based on exactly the same idea, as shown in FIG. 26, the output of the vertical scanning circuit 5 is directly output to the vertical selection lines V1, V2, V3,.
Can be used.

[0005]

By the way, when a video camera system capable of performing imaging in two types of scanning modes, interlaced and non-interlaced, using the image sensor having the configuration shown in FIGS. There is a problem that the relationship between the timing of vertical scanning and the timing of horizontal scanning is disrupted at the time of switching. That is, when switching the scanning mode, it is necessary to change the clock frequency for vertical scanning or horizontal scanning. For example, if the clock frequency for horizontal scanning is fixed and the data rate of the output from the image sensor is the same between the two scanning modes, that is, if the frame rates are aligned, the frequency of the clock that drives the vertical scanning circuit during non-interlaced scanning Must be reduced to half that of interlaced scanning. Then, it is necessary to provide a timing control circuit including a clock frequency control for the purpose inside or outside the image sensor.

In the image sensor having the structure shown in FIGS. 25 and 26, the number of selection MOS transistors connected to the vertical selection lines V1, V2, V3,... That is, the odd-numbered vertical selection lines V3, V5,
V7,... Have two even-numbered vertical selection lines V2, V
4, V6,... Are connected to one MOS transistor. Accordingly, in this configuration, the parasitic capacitance of the vertical selection line differs for each line, which causes horizontal streak-like fixed pattern noise. This phenomenon appears differently between interlaced scanning and non-interlaced scanning. In the case of interlaced scanning, two vertical selection lines having different parasitic capacitances are always selected as a pair, so the effect of the difference in parasitic capacitance is considerably reduced. However, in the case of non-interlaced scanning, each vertical selection line is independent. , The influence of the difference in the parasitic capacitance is directly affected. As a result, there is a difference in image quality between the two scan modes.

Further, in the image sensor having the configuration shown in FIG. 26, there is a problem that the load of the buffer circuit for driving the vertical selection line included in the vertical scanning circuit 5 differs depending on the scanning mode. In the case of interlaced scanning, the number of vertical selection lines for one bit of the vertical scanning circuit is two, but in the case of non-interlaced scanning, it is one.
The difference in the load of the buffer circuit causes a difference in the bias applied to the pixel, and as a result, a difference in image quality depending on the scanning mode.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems in the conventional solid-state imaging device capable of switching between scan modes. The scan mode can be switched with simple control, and the image quality differs depending on the scan mode. It is an object of the present invention to provide a solid-state imaging device configured so as not to exist.

[0009]

In order to solve the above-mentioned problems, the present invention relates to a plurality of photoelectric conversion elements arranged in a two-dimensional array and the photoelectric conversion elements arranged in a column direction. Corresponding to a horizontal selection line group provided correspondingly, a horizontal scanning circuit for scanning the photoelectric conversion elements arranged in the column direction via the horizontal selection line group, and the photoelectric conversion elements arranged in the row direction A solid state image pickup device comprising: a vertical selection line group provided as above; and first and second vertical scanning circuits for scanning photoelectric conversion elements arranged in a row direction via the vertical selection line group. Each of the first and second vertical scanning circuits is constituted by a plurality of scanning units, and each scanning unit of the first vertical scanning circuit is provided with one scanning unit for each odd-numbered vertical selection line of the vertical selection line group. And the second drop Each scanning unit of the scanning circuit is made to correspond one-to-one with each even-numbered vertical selection line of the vertical selection line group, and further controls a clock group for driving the first and second vertical scanning circuits. And a control clock generating means for switching the scanning mode.

[0010] Thus providing the first and second vertical scanning circuit, the control clock generating means, by controlling the clock group to be input to both the vertical scanning circuit, inter <br/> Les over scan scanning and non Interlaced scanning is switched,
In addition, when switching the scanning mode ,
It is not necessary to change the frequency of the driving clock input from the outside , and a solid-state imaging device having no difference in image quality depending on the scanning mode can be realized.

[0011]

Next, an embodiment will be described. FIG. 1 is a diagram showing a schematic configuration of a first embodiment of a solid-state imaging device according to the present invention. Members which are the same as or correspond to those of the conventional example shown in FIGS. Description is omitted. As shown in the embodiment of FIG. 1, the present invention is characterized in that there is no scanning mode control circuit and two vertical scanning circuits are provided as compared with the conventional example shown in FIGS. It is.

Next, the configuration of the first and second vertical scanning circuits 5L and 5R, which are the gist of the present invention, will be specifically described. The first and second vertical scanning circuits 5L and 5R
Have the same circuit configuration and differ only in how they are connected to the vertical selection line group. That is, the first vertical scanning circuit 5L supplies the odd-numbered vertical selection lines L1, L2,.
The second vertical scanning circuit 5R is connected to the even-numbered vertical selection lines R1, R
2,... Respectively. First, prior to the description of these vertical scanning circuits, a configuration column of a shift register used in a conventional vertical scanning circuit will be described with reference to FIG. This configuration example is a system in which one unit 9 is configured by two stages of clocked inverters, and this is schematically shown in FIG. 3 as shown in FIG. FIG. 4 shows the operation timing. The clock has two phases of Φ1 and Φ2. When a start pulse ΦST is applied to the input of the first stage unit 9, the output terminals SR1 and SR of each shift register unit 9 are synchronized with the rising of the clock Φ1.
2, SR3,..., Are sequentially output. In FIG. 2, / Φ1 and / Φ2 correspond to Φ1,
The inverted clock of Φ2 is shown.

Next, the first and second embodiments of the present invention will be described.
FIG. 5 shows a part of a configuration example of a scanning circuit used for the vertical scanning circuits 5L and 5R. Unit 19 that constitutes this scanning circuit
Is a pulse shift unit 19A having two stages of clocked inverters similar to the conventional shift register shown in FIG.
And an output pulse generating unit 19B for detecting a rising transition of the shift pulse of the unit 19A and generating a pulse.
It is composed of In FIG. 5, the second stage unit is representatively shown, and SR2.5 is the first stage output terminal of the two stage clocked inverter constituting the pulse shift unit 19A. FIG. 6 shows the operation timing. The clock has three phases, Φ0, Φ1, and Φ2.
When the start pulse ΦST is applied to the input of the first-stage pulse shift unit 19A, the output is sequentially output from the output terminals S1, S2, S3,... Of each output pulse generation unit 19B in synchronization with the rise of the clock Φ1. It has become so. In FIG. 6, when Φ0 is the same clock as Φ1, it is clear that the output is the same as the output shown in the timing diagram (FIG. 4) of the conventional shift register shown in FIGS. 2 and 3.

On the other hand, the shift register of this embodiment can operate in different operation modes other than the operation mode shown in FIG. FIG. 7 shows an example of the operation timing. The difference from the operation mode shown in the timing chart of FIG.
Of the phase clocks Φ0, Φ1 and Φ2, the clocks Φ0 and Φ2 are applied with pulses at the same timing as in the operation mode of FIG. 6, but the clock Φ1 is twice as long as the clock Φ0 unlike the operation mode of FIG. That is, a pulse in which the high level of the clock Φ0 is lost every cycle is applied as the clock Φ1. By applying such clocks Φ0, Φ1 and Φ2, the pulse shift unit 19A is driven by the clocks Φ1 and Φ2.
T ₁ = 2 · T ₂ = 2 · T ₀ (T ₂ : period of clock φ ₂ , T ₀ : period of clock φ ₀ ), and on the other hand, an output pulse generation unit that detects a rising transition of a shift pulse and generates a pulse Since 19B is driven by the clock φ0 and the output of the pulse shift unit 19A, the output terminal S of each output pulse generation unit 19B of the shift register is output.
The effective pulse width of the selection pulse output from 1, S2, S3,... Is the period of clocks Φ0 and Φ2: T ₀ = T ₂ =
T _1/2 .

Next, a case where the operation mode of the shift register shown in FIGS. 6 and 7 is applied to the vertical scanning circuit of the embodiment shown in FIG. 1 will be described. FIG. 8 shows a configuration example of a solid-state imaging device when the operation mode of the shift register is applied to the embodiment shown in FIG. FIG. 8 shows only the terminals related to the outline of the operation. However, in order to drive the first and second vertical scanning circuits 5L and 5R, a field index pulse FI for identifying the first field and the second field is shown. , And a scanning circuit control clock generation circuit 21 for inputting a vertical scanning start pulse ΦST. The field index pulse FI, clocks Φ1, Φ2, and start pulse ΦST input to the circuit 21 And pulse groups Φ0-L, Φ1-L, Φ2-L, and ΦST input to the second vertical scanning circuits 5L and 5R.
-L and Φ0-R, Φ1-R, Φ2-R, and ΦST-R, respectively, and are configured to be input to the first and second vertical scanning circuits 5L and 5R, respectively.

Next, the operation of the solid-state imaging device thus configured at the time of interlaced scanning will be described with reference to a timing chart shown in FIG. In the interlace mode, in the scanning circuit control clock generation circuit 21, the basic clock Φ1 is used as is Φ0-L, Φ1-L,
And Φ0-R and Φ1-R, and the basic clock Φ2 is directly outputted as Φ2-L and Φ2-R. Further, in the first field in which the field index pulse FI is at the low level, the start pulse ΦST-L input to the first vertical scanning circuit 5L becomes the second pulse.
Start pulse ΦST- inputted to the vertical scanning circuit 5R
It is controlled so as to be input earlier than R by one period of the basic clock Φ1. Thereby, the first vertical scanning circuit 5
L and the pulse that shifts through the second vertical scanning circuit 5R have a phase difference of one cycle of the basic clock Φ1, so that the selected row, that is, the vertical selection line is L1, L2 and R1, L2.
3 and R2,...

On the other hand, the field index pulse FI
Is a high level, in the scanning circuit control clock generation circuit 21, the start pulse .PHI.ST-L input to the first vertical scanning circuit 5L and the start pulse .PHI.ST-L input to the second vertical scanning circuit 5R. Pulse ΦST-R
Are output so as to be controlled to have the same phase. Therefore, the pulses for shifting between the first vertical scanning circuit 5L and the second vertical scanning circuit 5R have the same timing, and the selected row, that is, the vertical selection line is L1 and R1, and L2 and R
2, L3 and R3,... By driving the vertical selection lines as described above, the most common interlaced scanning, that is, two-row mixed reading in which the combination of two pixels in the vertical direction added for each field is different is realized.

Next, the operation at the time of non-interlace scanning will be described with reference to the timing chart shown in FIG. Basic clocks Φ1 and Φ2 for driving the first and second vertical scanning circuits 5L and 5R and a vertical scanning start pulse ΦST are input to a scanning circuit control clock generation circuit 21. Φ0-L, Φ1-L, Φ2-L, ΦST-L input to the vertical scanning circuits 5L, 5R
Φ0-R, Φ1-R, Φ2-R, and ΦST-R, respectively, and the first and second vertical scanning circuits 5 respectively.
L, 5R. In the non-interlace mode, the basic clock Φ1 remains unchanged as Φ0-L and Φ0-L.
0-R, and the basic clock Φ2 is directly output as Φ2-L and Φ2-R. However, unlike the above-described interlaced scanning, Φ1-L and Φ1-R are supplied in such a manner that the high level of the basic clock Φ1 is lost every period. Moreover, Φ1-L and Φ1-R
Is a half cycle of each cycle, that is, the basic clock Φ
The phase is shifted by one cycle of one. By applying such a pulse group to the first and second vertical scanning circuits 5L and 5R, each vertical scanning circuit
Since the pulse shift unit 19A constituting the L, 5R shift register is driven by Φ1-L to Φ1-R and Φ2-L to Φ2-R, the pulse shift period is the period of Φ1-L to Φ1-R. : T ₁ = 2 ・ T ₂ = 2 ・
T _0. On the other hand, the output pulse generating unit 19B for generating a pulse by detecting the rising transition of the shift pulse to no Φ0-L Φ0-R and the pulse shift unit 19A
, The width of the selection pulse output from the unit unit of the shift register is Φ0−L, Φ
Period of 0-R and Φ2-L, Φ2-R: T ₀ = T ₂ = T ₁
/ 2. Therefore, the selected row, that is, the vertical selection line is L
1, R1, L2, R2, L3, R3,... By driving the vertical scanning circuit as described above, the so-called non-interlaced reading can be performed independently and sequentially without mixing the signals of all the pixels of the image sensor with the signals of the adjacent pixels in the vertical direction. .

Next, a second embodiment will be described. First
In the embodiment, an output pulse generation unit 19 that receives a output of the pulse shift unit 19A and generates a row selection pulse.
By partially changing B, interlaced scanning and non-interlaced scanning can be performed as in the first embodiment, and at the same time, an electronic shutter function can be realized.

Next, FIG. 11 shows a part of a configuration example of a scanning circuit used for the first and second vertical scanning circuits 5L and 5R in this embodiment. A shift register unit 29 constituting this scanning circuit includes a pulse shift unit 29A having two stages of clocked inverters similar to the conventional shift register shown in FIG. 2 and a pulse shift unit 29A which detects rising and falling transitions of a shift pulse to generate a pulse. The output pulse generating unit 29B generates the output pulse, and FIG. 11 representatively shows the second stage unit. FIG. 12 shows the operation timing. The clock has three phases, Φ0, Φ1, and Φ2.
When the start pulse ΦST is applied to the input of the first-stage pulse shift unit 29A, the output terminals S1, S2, S3,... Of each output pulse generation unit 29B are sequentially transmitted in synchronization with the rise and fall of the clock Φ1. Output is to be made. In FIG. 12, Φ0 is Φ1
When the clock is the same as that of the first embodiment shown in the timing chart of FIG. 6, in addition to the output, the rising of the clock .PHI.2 also occurs at the falling position of the shift pulses SR1, SR2,. Is output during the period from to the rising edge of the clock Φ1.

On the other hand, the shift register of this embodiment can operate in different operation modes other than the operation mode shown in FIG. FIG. 13 shows an example of the operation timing. Figure
The difference from the operation mode shown in the timing diagram of 12 is that
Of the phase clocks Φ0, Φ1 and Φ2, the clocks Φ0 and Φ2 are applied with a pulse at the same timing as the operation mode shown in FIG. 12, but the clock Φ1 is twice the clock Φ0 unlike the operation mode of FIG. It is a cycle of
The point is that a pulse in which the high level of the clock φ0 is lost every cycle is applied as the clock φ1. By applying such clocks Φ0, Φ1, Φ2,
Since the pulse shift unit 29A is driven by the clocks Φ1 and Φ2, the pulse shift cycle is the cycle of the clock Φ1: T ₁ = 2 · T ₂ = 2 · T ₀ , while the rising and falling transitions of the shift pulse are The output pulse generation unit 29B that detects and generates a pulse is a clock Φ
0 and the output of the pulse shift unit 29A.
, S2, S3,..., The effective pulse width of the selected pulse is the shift pulse SR1, SR2, SR3,.
Φ2 cycle clock Φ0 in a rising transition of the _{·: T 0 = T 2 =} T 1/2 , and the shift pulse SR
1, SR2, SR3,... Are output twice during the period from the rise of the clock Φ2 to the rise of the clock Φ0 and twice during the period from the fall of the clock Φ0 to the rise of the clock Φ1. It has become so.

Next, the case where the shift register having the operation mode shown in FIGS. 12 and 13 is applied to the vertical scanning circuit of the first embodiment shown in FIG. 1 to constitute the solid-state imaging device of the second embodiment. Will be described. The solid-state imaging device according to the second embodiment has a so-called electronic shutter function.
The information on the shutter speed is included in the duty ratio of the pulse that shifts in the vertical scanning circuit, and has an element configuration that detects the rise and fall of the pulse to read or reset the pixel. The technique utilizing the rising and falling edges of the shift pulse, which has already been disclosed by the present applicant in Japanese Patent Application Laid-Open No. 3-127567, is also used in the present invention.

A configuration example of the solid-state imaging device using the shift registers having the operation modes shown in FIGS. 12 and 13 is the same as that of the first embodiment except for the internal configuration of the first and second vertical scanning circuits 5L and 5R.
Since this is the same as the first embodiment shown in FIG. 8, the second embodiment will be described with reference to FIG. Field index pulse FI for identifying the first field and the second field
And the basic clocks Φ1 and Φ2 for driving the first and second vertical scanning circuits 5L and 5R, and the vertical scanning start pulse ΦST are input to the scanning circuit control clock generation circuit 21. Second vertical scanning circuit 5
L, 5R pulse groups Φ0-L, Φ1-L, Φ
2-L, ΦST-L and Φ0-R, Φ1-R, Φ2-R,
.PHI.ST-R are processed and input to the first and second vertical scanning circuits 5L and 5R, respectively.

Next, the operation at the time of interlaced scanning in the solid-state imaging device thus configured will be described with reference to FIGS.
This will be described with reference to the timing chart shown in FIG. 14 and FIG.
Numeral 15 is a division of an originally integral one, and the timing indicated by the dotted line indicates the same timing. In the interlace mode, in the scanning circuit control clock generation circuit 21, the basic clock .PHI.
Φ1-L and Φ0-R and Φ1-R are output, and the basic clock Φ2 is output as it is as Φ2-L and Φ2-R. Further, the field index pulse F
In the first field where I is at a low level, the first
Start pulse ΦST- inputted to the vertical scanning circuit 5L of
L is controlled so as to be inputted one cycle of the basic clock Φ1 earlier than the start pulse ΦST-R inputted to the second vertical scanning circuit 5R. As a result, since the pulse that shifts in the first vertical scanning circuit 5L and the second vertical scanning circuit 5R has a phase difference of one cycle of the basic clock Φ1, it is generated by detecting the rising transition of the shift pulse. , The pulses S1-L and S2-L from the rising of the clock Φ1 to the rising of the clock Φ0.
L, S3-L,... S1-R, S2-R, and S3-R are selected rows, that is, vertical selection lines are L1, L2 and R
1, L3 and R2,... Also, the pulse generated by detecting the falling transition of the shift pulse changes the vertical selection lines to L1, L2 and R1, L3 and R from the rising of the clock Φ2 to the rising of the clock Φ1.
It is output so as to select in the order of 2,.

[0025] Thus, the period extending between the leading edge of the clock .phi.1 from the rising of the clock .phi.1, i.e. through the horizontal scanning period one cycle, the read data clock .phi.1 from pixels high level period, the clock [Phi 1 is low
If the image sensor is configured to use the level period for resetting the pixel data, the exposure time for obtaining the pixel signal can be reduced as compared with the first embodiment only during the period when the start pulse ΦST is at the high level. become.

On the other hand, the field index pulse FI
Is a high level, the scanning circuit control clock generation circuit 21 causes the start pulse .PHI.ST-L to be input to the first vertical scanning circuit 5L and the start pulse to be input to the second vertical scanning circuit 5R. The input is controlled so that the phase of ΦST-R becomes the same. Therefore, the pulses for shifting the first vertical scanning circuit 5L and the second vertical scanning circuit 5R have the same timing, and are generated by detecting the rising transition of the shift pulse. The selected row selected by the row selection pulse over the rising edge, that is, the vertical selection line is L1 and R1, L2 and R2, L3 and R3.
... Further, the row selection pulse generated by detecting the falling transition of the shift pulse changes the vertical selection lines from L1 to R1, L2 and R2, L3 and R from the rising of the clock Φ2 to the rising of the clock Φ1.
It is output so as to select in the order of 3,.

Therefore, the field index pulse F
As in the case of the first field where I is low level,
During a period from the rising edge of the clock Φ1 to the rising edge of the clock Φ1, that is, one horizontal scanning period, a period during which the clock Φ1 is at a high level is used to read data from a pixel, and a period during which the clock Φ1 is at a low level is referred to as pixel data. If the image sensor is configured to be used for resetting, the exposure time for obtaining the pixel signal can be reduced as compared with the first embodiment only during the period when the start pulse ΦST is at the high level. A specific configuration example of the unit of the vertical scanning circuit for realizing this function will be described later with reference to FIGS. 19, 20, and 21.

By driving the vertical scanning circuit as described above, the most common interlaced scanning, that is, two-row mixed reading in which the combination of two pixels in the vertical direction added for each field is different, is realized. By changing the width of the start pulse applied from the outside to the sensor, the exposure time for outputting an image signal can be shortened from a normal field cycle, so that an on-chip electronic shutter can be realized. .

Next, the operation at the time of non-interlace scanning will be described with reference to the timing charts shown in FIGS. FIG. 16 and FIG. 17 are those obtained by dividing the originally integral one,
The timing shown by the dotted line is the same timing. The basic clocks Φ1 and Φ2 for driving the first and second vertical scanning circuits 5L and 5R and the vertical scanning start pulse ΦST are input to a scanning circuit control clock generation circuit 21. Vertical scanning circuit 5
L, 5R pulse groups Φ0-L, Φ1-L, Φ
2-L, ΦST-L and Φ0-R, Φ1-R, Φ2-R,
ΦST-R are processed and input to the first and second vertical scanning circuits 5L and 5R, respectively. In the non-interlace mode, the basic clock Φ1 is output as Φ0-L and Φ0-R as it is, and the basic clock Φ2 is output as Φ2-L and Φ2-R as it is. However, unlike the above-described interlaced scanning, Φ1-L and Φ1-R are supplied in such a manner that the high level of the basic clock Φ1 is lost every cycle. Moreover,
.PHI.1-L and .PHI.1-R are timings shifted in phase by a half cycle of each cycle, that is, one cycle of the basic clock .PHI.1.

By applying such a group of pulses to the first and second vertical scanning circuits 5L and 5R, the pulse shift unit 29A constituting the shift register of each of the vertical scanning circuits 5L and 5R becomes Φ1-L to Φ1. -R and Φ2-L to Φ2-R, the pulse shift cycle is the cycle of Φ1-L to Φ1-R: T ₁ = 2 · T ₂ =
2 · T _0. On the other hand, the output pulse generating unit for generating a pulse by detecting the rising transition of the shift pulse 29
Since B is driven by Φ0-L or Φ0-R and the output of the pulse shift unit 29A, the width of the selection pulse generated by detecting the rising transition of the shift pulse is:
Period of Φ0-L or Φ0-R and Φ2-L or Φ2-R:
T ₀ = T ₂ = T _1/2 . Therefore, the row selected by the selection pulse generated by detecting the rising transition of the shift pulse, that is, the vertical selection line is L1, R1, L2, R
2, L3, R3,... The selection pulse generated by detecting the falling transition of the shift pulse is:
Φ0-L or Φ from the rise of Φ2-L or Φ2-R
During the rising edge of 0-R and between the falling edge of Φ0-L or Φ0-R and the rising edge of Φ1-L or Φ1-R, the vertical selection line is set to L1, R1, L2, R2, L.
3, R3,... Are output in order.

Therefore, during a period from the rise of the clock Φ1 to the rise of the clock Φ1, that is, during one horizontal scanning period, the period when the clock Φ1 is at the high level is used for reading data from the pixel and the clock Φ1 is at the low level. If the image sensor is configured to use the period for resetting the pixel data, the exposure time for obtaining the pixel signal can be reduced compared to the first embodiment only during the period when the start pulse ΦST is at the high level. Become. In addition,
A specific configuration example of the unit of the vertical scanning circuit for realizing this function will be described later with reference to FIGS. 19, 20, and 21.

By driving the vertical scanning circuit as described above, so-called non-interlaced reading is realized, in which signals of all pixels of the image sensor are read independently and sequentially without being mixed with signals of adjacent pixels in the vertical direction. In addition, by changing the width of the start pulse applied from the outside to the image sensor, the exposure time for outputting the image signal can be shortened from the normal exposure cycle. It can be realized.

The scanning circuit control clock generation circuit 21 for switching each scanning mode in each embodiment described above.
Can be realized by a simple logic circuit, for example,
With the configuration shown in FIG. 18, the sensor can be formed on the same substrate as the sensor without increasing the area. Especially CMOSFET like CMD image sensor
Since the clock driver can also be configured with a CMOSFET when the scanning circuit according to the above is built in, it is possible to configure the above-described control clock generation circuit with a CMOSFET and form the control clock generation circuit together with the clock driver on the same substrate as the sensor. Extremely easy. In FIG. 18, INT
Is a signal for controlling the scanning mode. By setting the signal to a low level in the case of interlaced scanning and to a high level in the case of non-interlaced scanning, the scanning mode can be easily switched from outside.

Next, a description will be given of a unit of a vertical scanning circuit when the present invention is applied to an image sensor using a CMD light receiving element which is an amplification type solid-state imaging element. When a video signal is output from the CMD light receiving element, the signals applied to the common gate line of each row of the CMD light receiving elements arranged in a two-dimensional array include an accumulation voltage VSS, an overflow voltage VOF, a read voltage VRD, and a reset voltage V
A pulse that combines the four voltages of the RST in a time series is required. First, the case of the most general reading method will be described. In a non-selected row, the storage voltage VSS is set during the horizontal valid period of the video signal, and the overflow voltage VOF is set in the horizontal flyback period. During the line period, the reset voltage VRST is required. In order to apply the above signal to the gate of the CMD light receiving element, a circuit having a configuration in which the above-mentioned selected / unselected binary theoretical output is obtained from each scanning stage,
A vertical scanning circuit having a mix circuit is used. Figure
In 19, 31 is the pulse shift unit, 33 is the level
It is a mix circuit. In this configuration, the clock Φ1
The high level corresponds to the effective period of the video signal, and the low level corresponds to the horizontal blanking period.

However, the configuration example of the general vertical scanning circuit of the CMD image sensor shown in FIG. 19 is based on the premise that the width of the clock pulse to be shifted in the pulse shift unit is one clock. Assuming that the width of the clock pulse to be shifted in the pulse shift unit is equal to or more than one clock, as shown in FIG.
Between a level mix circuit 33 having a terminal Gi for outputting a pulse applied to the gate line of the MD light receiving element,
It is necessary to provide the output pulse generation unit 32.
The pulse shift unit 31, output pulse generation unit 32, and the output of the output pulse generation unit 32 having the configuration shown in FIG.
Is a part of the configuration of the vertical scanning circuit of the first embodiment shown in FIG. With such a configuration, as shown in FIG. 21, if the pulse phase is set so that the valid period of the video signal is included in the high level period of the pulse of the clock Φ1,
Obviously, a video signal in interlaced scanning and a video signal in non-interlaced scanning can be obtained by the same selection sequence as in the conventional example.

Next, a configuration in which a level mix circuit is connected to the pulse shift unit and the output pulse generation unit of the vertical scanning circuit of the second embodiment shown in FIG.
It will be described based on. In FIG. 22, 31 is a pulse shift unit, 42 is an output pulse generation unit, and 33 is a level shifter.
It is a mix circuit. In this case, since the pulse waveform applied to the gate line of the CMD light receiving element is as shown in FIG. 23, the pulse phase is set so that the valid period of the video signal is included in the high level period of the clock pulse Φ1. For example, a video signal in interlaced scanning and a video signal in non-interlaced scanning can be obtained by the same selection sequence as in the conventional example.
Obviously, since the exposure time of the D light receiving element can be controlled, an electronic shutter function can also be realized.

This level mix circuit has a circuit configuration disclosed as a conventional example in Japanese Patent Application No. 4-56076 filed by the present applicant, but is disclosed as an embodiment of the invention in the same application. It is obvious that the same effect can be obtained by the same connection as long as the level mix circuit generates the above four-valued pulse, including the circuit configuration.

Further, in the above embodiment, it is needless to say that a circuit configuration using static logic, including a circuit using dynamic logic of another configuration, can be used as the output pulse generation unit.

[0039]

As described above with reference to the embodiments,
According to the solid-state imaging device of the present invention, not only a video signal in interlaced scanning as in the related art but also a video signal in non-interlaced scanning can be obtained, and a clock applied to the scanning circuit control clock generation circuit when the scanning mode is switched. There is no need to make any changes, and there is no difference in image quality depending on the scanning mode, and further, a solid-state imaging device having an electronic shutter function in both scanning modes can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a schematic configuration of a first embodiment of a solid-state imaging device according to the present invention.

FIG. 2 is a circuit configuration diagram showing a configuration example of a general shift register.

FIG. 3 is a conceptual diagram schematically showing the shift register shown in FIG.

FIG. 4 is a timing chart for explaining an operation of the shift register shown in FIG. 2;

FIG. 5 is a diagram showing a part of the vertical scanning circuit of the first embodiment.

FIG. 6 is a timing chart for explaining the operation of the vertical scanning circuit shown in FIG.

FIG. 7 is a timing chart for explaining another operation mode of the vertical scanning circuit shown in FIG. 5;

FIG. 8 is a diagram showing a specific configuration example of the first embodiment shown in FIG. 1;

FIG. 9 is a timing chart for explaining the operation at the time of interlaced scanning of the first embodiment shown in FIG. 8;

FIG. 10 is a timing chart for explaining an operation at the time of non-interlaced scanning of the first embodiment shown in FIG. 8;

FIG. 11 is a diagram illustrating a part of a vertical scanning circuit according to a second embodiment.

FIG. 12 is a timing chart for explaining the operation of the vertical scanning circuit shown in FIG. 11;

13 is a timing chart for explaining another operation mode of the vertical scanning circuit shown in FIG.

FIG. 14 is a diagram illustrating a part of timing for describing an operation at the time of interlaced scanning of the solid-state imaging device according to the second embodiment.

FIG. 15 is a diagram illustrating another portion of the timing for describing the operation at the time of interlaced scanning of the solid-state imaging device according to the second embodiment.

FIG. 16 is a diagram illustrating a part of timing for describing an operation at the time of non-interlaced scanning of the solid-state imaging device according to the second embodiment.

FIG. 17 is a diagram illustrating another portion of the timing for describing the operation at the time of non-interlaced scanning of the solid-state imaging device according to the second embodiment.

FIG. 18 is a circuit diagram illustrating a configuration example of a scanning circuit control clock generation circuit.

FIG. 19 is a diagram illustrating a configuration example of a general vertical scanning circuit used for a CMD image sensor.

FIG. 20 is a diagram illustrating a configuration example of a vertical scanning circuit in an embodiment in which the present invention is applied to a CMD image sensor.

FIG. 21 is a timing chart for explaining the operation of the vertical scanning circuit shown in FIG. 20.

FIG. 22 is a diagram illustrating another configuration example of the vertical scanning circuit in an embodiment in which the present invention is applied to a CMD image sensor.

FIG. 23 is a timing chart for explaining an operation of the vertical scanning circuit shown in FIG. 22.

FIG. 24 is a configuration diagram illustrating a configuration example of a conventional solid-state imaging device.

FIG. 25 is a configuration diagram illustrating a configuration example of a conventional solid-state imaging device capable of switching a scanning mode.

FIG. 26 is a configuration diagram illustrating another configuration example of a conventional solid-state imaging device capable of switching scan modes.

[Explanation of symbols]

 Reference Signs List 1 pixel 2 horizontal scanning circuit 3 horizontal selection switch 4 output signal line 5L first vertical scanning circuit 5R second vertical scanning circuit 19 shift register unit 19A pulse shift unit 19B output pulse generation unit 21 scanning circuit control clock generation circuit

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/335

Claims (5)

(57) [Claims] 1. A plurality of photoelectric conversion elements arranged in a two-dimensional array, a horizontal selection line group provided corresponding to the photoelectric conversion elements arranged in a column direction, and a horizontal selection line group. A horizontal scanning circuit that scans the photoelectric conversion elements arranged in the column direction via a vertical selection line group provided corresponding to the photoelectric conversion elements arranged in the row direction, and the vertical selection line group. In a solid-state imaging device having first and second vertical scanning circuits for scanning photoelectric conversion elements arranged in a row direction, the first and second vertical scanning circuits each include a plurality of scanning units. And each scanning unit of the first vertical scanning circuit is made to correspond one-to-one with each odd-numbered vertical selection line of the vertical selection line group.
A scanning unit for causing each scanning unit of the second vertical scanning circuit to correspond one-to-one with each even-numbered vertical selection line of the vertical selection line group, and for driving the first and second vertical scanning circuits; A solid-state imaging device comprising a control clock generation unit that controls a group of clocks to switch a scan mode. 2. The control clock generating means according to claim 1, wherein:
And second Rutotomoni varied similarly a part of the frequency of each of the click <br/> locking group for driving the vertical scanning circuit, peripheral
Driving the first and second vertical scanning circuits with different wave numbers
2. The solid-state imaging device according to claim 1, wherein the scanning mode is switched by further changing the phase relationship between the clocks for use . 3. The solid-state imaging device according to claim 2, wherein
A solid-state imaging device, wherein the frequency of the clock whose frequency changes is half of the frequency of the other clocks. 4. The solid-state imaging device according to claim 2 , wherein
A solid-state imaging device, wherein a phase difference between clocks whose phase relationship changes is 関係 of a cycle of the clock. 5. Using CMD as said photoelectric conversion element,
2. The solid-state imaging device according to claim 1, wherein said control clock generating means is formed on the same substrate as a photoelectric conversion element array together with said first and second vertical scanning circuits.