JPH0750918B2 - Driving device for solid-state image sensor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a drive device for a solid-state image pickup device suitable for use in a television camera for industrial measurement.

[Conventional technology]

As shown in FIG. 9, a solid-state image sensor (1) such as CCD is composed of a plurality of photodetectors (picture elements) (2) arranged at a predetermined pitch in the horizontal and vertical scanning directions. Then, at least as many photodetectors (2) as the number of effective scanning lines for one frame in the standard television signal are arranged in the vertical scanning direction.

Further, a drive device for obtaining various drive pulses such as transfer clocks for horizontal and vertical shift registers for the solid-state image pickup device (1) of this kind and gate pulses for the vertical shift register is generally of an external synchronization type. Therefore, when the horizontal and vertical synchronizing signals in the standard television signal are supplied from the outside, the interlaced signal reading is executed in synchronization with these signals.

For example, when the signal is read from the photodetector (2) of the odd line in the odd field as shown in FIG. 9 in the case of frame reading, it becomes 1 in the even field.
A signal is read from the photodetector (2) on the even-numbered line which is shifted.

When it is field reading, as shown in FIG.
In one field, the photodetectors (2) of two adjacent horizontal lines are read simultaneously, and in the next field, the horizontal lines to be read simultaneously are shifted by one horizontal line, so that interlaced signal reading is performed. It

Now, in some cases, the solid-state image sensor (1) described above may want to obtain an image output by a scanning method other than the television standard method, depending on its application.

For example, in an industrial measurement image input device, various measurement data are obtained by supplying the image pickup output of a measurement camera such as a CCD camera to the image input device, but this type of measurement data has a short measurement cycle. It is better, and it may be preferable that the previous measurement point and the current measurement point are always the same.

However, the standard system TV camera has a long measurement cycle of 1/30 seconds because it is a frame cycle.Because a field signal is obtained by interlaced scanning and a frame image is obtained from this, sampling points are obtained for each field. Is shifted in the vertical scanning direction by one horizontal scanning line.

If you change to non-interlaced scanning instead of interlaced scanning, the field period is 1/60 second, so the measurement period can be shortened to 1/2 of the conventional one, and the sampling points in each field will be the same. , Field images of the same phase are always obtained.

Therefore, non-interlaced scanning may be preferable to interlaced scanning for industrial measurement.

In addition, when changing to non-interlaced scanning, 1
It is completely unknown whether the frame consists of 524 frames, 526 frames, or even other frames. As described above, even if the number of lines per frame is different, a drive pulse corresponding to this must be output from the drive device.

[Problems to be solved by the invention]

Conventionally, when a standard television signal is supplied from the outside in this way, interlace scanning is performed in synchronization with it, and when a television signal other than the standard television signal is supplied from the outside, non-interlaced synchronization is performed. There is no externally synchronized drive such that scanning takes place.

However, in any case, it is preferable to be able to drive the solid-state image sensor in order to broaden the application.

Therefore, in the present invention, the solid-state imaging device can be driven even when external synchronization other than the standard system is input.

[Means for solving problems]

The solid-state image pickup device driving apparatus according to the present invention has, for example,
As shown in the figure, in synchronism with externally supplied horizontal and vertical synchronizing signals HD and VD, a solid state having a number of photodetectors (2) corresponding to the number of effective scanning lines for one frame of a standard television signal. In a drive device for a solid-state image pickup device which reads out a signal from the image pickup device (1), the horizontal and vertical sync signals HD and VD are interlaced based on the phase difference between the externally supplied horizontal and vertical sync signals HD and VD. Discriminating means (15) (20) for discriminating which one of the non-interlaced mode and the non-interlaced mode, and the discriminating means (15)
Based on the determination result SP of (20), when the horizontal and vertical synchronizing signals HD and VD supplied from the outside are in the non-interlace mode, the signal is read from the fixed photodetector (2) in all fields. When the horizontal and vertical sync signals HD and VD supplied from the outside generate the CCD drive signal and are in the interlace mode, different photodetectors in adjacent fields based on the horizontal and vertical sync signals HD and VD ( For reading the signal from 2)
Drive pulse generator for generating CCD drive signals (11) (12)
(13) and are provided.

[Action]

The second pulse generator (13) is modulated by the discrimination result SP of the discrimination means (15) (20). That is, in the non-interlaced mode, the vertical transfer clock is modulated in each field as shown in FIGS. 5B and 5C, and the output is read from the fixed photodetector (2) in all fields.

Since the read-out trigger pulse ROT is formed based on the vertical synchronizing signal VD, even when a television signal other than the standard television signal is externally supplied, non-interlaced scanning synchronized with it can be realized.

〔Example〕

FIG. 1 shows a driving device (10) for a solid-state image sensor according to the present invention.
An example is shown. An interline transfer CCD is exemplified as the solid-state image sensor.

The driving device (10) has a driving pulse generator (11), which has a first horizontal transfer clock (two-phase two-value or four-phase three-value clock, the former in this example) and an output reset pulse. Pulse generator (12) and a second pulse generator (13) for obtaining the readout pulse and the vertical transfer clock.

The vertical transfer clock is a two-phase binary clock like the horizontal transfer clock.

The H and trigger pulses HT obtained from the control pulse forming circuit (15) are supplied to the first and second pulse generators (12) and (13), and the second pulse generator (13) is supplied.
Further, a pulse ROT for the read-out trigger and a discrimination pulse SP for controlling the sending mode of the vertical transfer clock in the normal interlaced mode and the non-interlaced mode are supplied. The control of the sending mode will be described later.

FIG. 2 shows an example of the control pulse forming circuit (15), in which horizontal and vertical synchronizing signals HD and VD (FIG. 3A and B) which are external synchronizing signals are supplied to the input terminals (16) and (17). To be done.
A predetermined clock CK is supplied to the input terminal (18).

In the figure, (19) is a shift register, (20) is a flip-flop, (21) is a generator of a read-out trigger pulse ROT, and the read-out trigger pulse ROT is a falling edge of the vertical synchronizing signal VD in this example. Obtained 11 hours after the timing.

FIG. 3 shows a timing relationship in an odd field, and the horizontal synchronizing signal HD and the vertical synchronizing signal VD are input at the same timing. Vertical sync signal VD is a shift register (19)
Is supplied to the flip-flop (20) and delayed by a predetermined time τ.
Is supplied as a clock pulse, and the value of the horizontal synchronizing signal HD at that supply timing is loaded.

In the odd field in interlaced mode,
As shown in FIG. 3, since HD and VD have the same timing, the discrimination pulse SP which is the output pulse of the flip-flop (20) is "0" (E in the same figure).

On the other hand, the relationship between HD and VD is 4th in the even field.
As shown in FIGS. A and B, VD is shifted from HD by 0.5H (H is 1 horizontal period), so in this case, a discrimination pulse SP of "1" (D in the same figure) is obtained. Become. Thus, in the interlace mode, the polarity of the discrimination pulse SP is inverted for each field.

In the non-interlaced mode, the timing relationship between HD and VD is the same in both odd and even fields, and the relationship is as shown in FIG. 3, so the discrimination pulse SP is always "0".

Therefore, it is possible to determine whether to image in the interlace mode or the non-interlace mode based on the phase relationship between the external synchronization signals HD and VD supplied to the terminals (16) and (17). SP is supplied to the second pulse generator (13) and the vertical transfer clock is modulated so as to correspond to each mode.

Since the vertical transfer clock is a two-phase binary clock as described above, the two-phase transfer clocks V1 and V2 (B and C in FIG. 5) have opposite phases. Further, if the transfer clocks V1 and V2 are modulated by the input of the determination pulse SP so that the transfer clock V1 is “1” and V2 is “0” in the read-out period T in the odd field, in the even field, By inputting the discrimination pulse SP having a polarity different from that in the odd field, the transfer clocks V1 and V2 are modulated so that V1 becomes "0" and V2 becomes "1" (D and E in FIG. 5).

As a result, in the odd field, only the photodetector (2) whose V1 becomes “1” during the read-out period T,
The carriers stored in are transferred to the vertical shift register and the carriers are read out. In the even-numbered field, the potential levels are reversed as shown in FIGS. 5D and 5E, so that the carrier is transferred only to the photodetector (2) whose V2 is "1". Therefore, the photodetector (2) used in the odd field and the even field is shifted by one line, and the interlace mode is executed.

On the other hand, when a non-interlaced scanning television signal that provides the discrimination pulse SP having the same polarity in both the odd and even fields is input, the even field undergoes the same modulation as the odd field. Therefore, the transfer clocks V1 and V2 shown in FIGS. 5B and 5C are output irrespective of whether the field is odd or even, and the photodetector (2) used is the light used in the even field and the light used in the odd field. The detector (2) is used to enter non-interlaced mode and the sample points are fixed. The same applies to the case of simultaneous reading of two horizontal lines (field reading) as shown in FIG.

By the way, in the non-interlaced mode, it is not known whether the number of horizontal lines constituting one frame is 524, 526, or other, but the discrimination pulse SP is determined from the phase relationship between HD and VD.
If the lead-out trigger pulse ROT is formed based on the external vertical synchronizing signal VD supplied to the terminal (17), the discrimination pulse SP of the same polarity is output in each field, and 11H later than VD. Since the carrier is always read out, the non-interlaced mode can be executed regardless of the number of horizontal lines constituting one frame.

In the case of the configuration shown in FIG. 2, the determination pulse SP is formed based on the horizontal and vertical synchronization signals HD and VD, so
The interlace mode can be executed even when a television signal for interlacing other than the standard television signal of 25 lines / frame or 625 lines / frame is input as the external synchronizing signal.

FIG. 6 shows another example of the control pulse forming circuit (15),
In particular, another example of the means for forming the discrimination pulse SP will be shown.

In this example, a match detection circuit (30) for HD and VD is provided, and when both match, that is, in the case of an odd field, a match pulse SU (FIGS. 7A to 7C) is obtained. Reset. The coincidence pulse SU is further supplied to the counter (32) to count the number of 263 horizontal lines.

If the flip-flop (31) is set by the count output SC (Fig. 7D) obtained when counting the number of 263 horizontal lines, the discrimination pulse SP of "0" is obtained in the odd field and in the even field. The discrimination pulse SP of "1" can be obtained.

When an external synchronizing signal for non-interlace is supplied, as shown in FIG. 8, a coincidence pulse SU is obtained even in an even field, so that a discrimination pulse SP of "0" is outputted from the flip-flop (31) for each field. can get.

In the case of FIG. 6, since the discrimination pulse SP for odd and even fields is formed based on the count output SC of the interlace mode counter (32), one field structure of the television signal for external synchronization is formed. The number of lines must be less than 263 lines. Further, the number of odd or even lines is 1/2 of the total number of photodetectors (2) in the vertical scanning direction of the solid-state image sensor (1), and therefore must be more than this number.

Therefore, for example, if the effective total number of photodetectors (2) is 492, the number n of constituent lines of one field in the television signal for external synchronization may be any integer satisfying 246 <n <263. Good. On the other hand, in the configuration shown in FIG. 2, the number of constituent lines n in one field may be any integer.

〔The invention's effect〕

As described above, according to the present invention, the solid-state imaging device can be driven even when the external synchronization other than the standard method is input. When the external synchronization is the non-interlaced mode, the photodetector to be read is The photodetector used in the odd field or the even field is fixed and the signal is read from the photodetector in each field.

This way, an image signal can be obtained every 1/60 second, and
Since an image signal of the same sample point is obtained for each field, for example, if the present invention is applied to the industrial video camera of the industrial measurement image input device described at the beginning, the measurement cycle can be shortened and the same. The effect that the data of the sample points can be collected can be obtained.

Further, even if the number of lines per frame of the television signal for external synchronization is different, various pulses corresponding to this can be formed. Therefore, when the standard television signal is supplied from the outside, interlaced scanning synchronized with it is executed. Therefore, when a television signal other than the standard television signal is supplied from the outside, non-interlaced scanning synchronized with the television signal can be executed.

Therefore, the present invention can be used for a wide range of purposes.

[Brief description of drawings]

FIG. 1 is a system diagram showing an example of a driving device for a solid-state image pickup device according to the present invention, FIGS. 2 and 6 are system diagrams showing examples of control pulse forming circuits, FIGS. 3 to 5, and FIG. 7 and 8 are waveform diagrams for explaining the operation thereof, and FIGS. 9 and 10 are diagrams of the solid-state image pickup device for explaining the present invention. (1) is a solid-state image sensor, (2) is a photodetector, (10) is a drive unit, (11) is a drive pulse generator, (12) and (13) are first and second pulse generators, (15) is a control pulse forming circuit.

Claims (1)

[Claims] 1. A signal is read from a solid-state image sensor having a number of photodetectors corresponding to the number of effective scanning lines for one frame of a standard television signal in synchronization with externally supplied horizontal and vertical synchronizing signals. In a solid-state image sensor drive device, a determination is made based on the phase difference between the externally supplied horizontal and vertical sync signals to determine whether the horizontal and vertical sync signals are in an interlace mode or a non-interlace mode. Means, and based on the discrimination result of the discrimination means, when the horizontal and vertical synchronization signals supplied from the outside are in the non-interlaced mode, a CCD drive signal for reading out a signal from a fixed photodetector in all fields is supplied. When the horizontal and vertical synchronization signals generated and supplied from the outside are in the interlace mode, the horizontal and vertical synchronization signals are generated. Based on the issue,
A drive device for a solid-state imaging device, comprising: a drive pulse generator that generates a CCD drive signal for reading out signals from photodetectors different from each other in adjacent fields.