JP2977051B2 - Solid-state imaging device and driving method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device used in a high-speed camera system and a driving method thereof.

[0002]

2. Description of the Related Art Conventionally, in a solid-state imaging device used in a high-speed camera system, in order to realize a high frame rate, a light receiving section is divided into a plurality of blocks, and outputs of the respective blocks are taken out in parallel. It is configured to be able to.

[0003] For example, IEEE Transactions on Electron
Devices, Vol. ED-19, No. 9, 1982 pp. 1469-1477 show an image sensor having the configuration shown in FIG.
In this image sensor, the light receiving area 100 is divided into six blocks 101-1, 101-2,... 101-6, each having 32 parallel outputs. Each block is sequentially selected, but by continuously selecting only one block, the display area on the TV monitor is reduced to 1/6, but a frame rate six times higher can be obtained. The pixel output in the horizontal direction is read by a selection pulse from the shift register 102. In FIG. 17, reference numeral 103 denotes an external clock generating means, 104 denotes a block address means, 105 denotes an output selection FET, and 106 denotes a coupling matrix.

EG & G RETICON catalog RA256
8N shows a high-speed image sensor having a configuration as shown in FIG. This image sensor includes a plurality of horizontal scanning circuits 201, 202,... 207, 208, and the output terminals 211, 212,.
In the illustrated example, horizontal scanning circuits 201 and 202, 203 and 204
,... 207 and 208 form a set, and the light receiving area is divided into four blocks. Since each of the horizontal scanning circuits can scan at the same time, a frame rate four times as high can be obtained.

[0005] Also, the Technical Report of the Institute of Television Engineers of Japan, Vol.
No. 52, pp. 31-36, 1987, a paper titled “TSL Image Sensor with Variable Electronic Shutter” by Izawa et al. Describes a TSL with a shift register in which the internal state is cleared by inputting a start pulse. (Transversal Signal L
ine) An image sensor is disclosed, and it is disclosed that window processing as shown in FIG. 19 can be performed by performing high-speed scanning to a place where an image is to be displayed.

[0006]

In the conventional image sensor shown in FIG. 17, since a plurality of divided blocks of the light receiving section are divided only in the vertical direction, the TV monitor display at the maximum frame rate is horizontally long. Therefore, the light receiving area cannot be divided in the horizontal direction to obtain a higher frame rate.

In the image sensor shown in FIG.
Contrary to that shown in FIG. 17, the light receiving area cannot be divided in the vertical direction. Also, in order to place one block of horizontal scanning circuit within the horizontal range of the light receiving area of one block,
As shown in FIG. 18, it is necessary to devise a method of providing two scanning circuits in the vertical direction. In general, a scanning circuit requires additional circuits at both ends thereof. Therefore, in a configuration in which a plurality of scanning circuits are provided, layout becomes difficult when pixels are miniaturized.

On the other hand, in the conventional image pickup device shown in FIG. 19, the image output area can be freely set as compared with the conventional example shown in FIGS. 17 and 18, but high-speed scanning and normal scanning are mixed. Therefore, there is a problem that the control is complicated, and furthermore, normal scanning is performed during image output, so that the high speed of the shift register cannot be fully utilized.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems in the conventional solid-state imaging device, and has a simple configuration in which a light receiving region is divided in both horizontal and vertical directions to obtain a high frame rate. It is an object to provide an imaging device and a driving method thereof.

[0010]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention is to make all outputs of a shift register the same state when there are a plurality of transfer clock pulses supplied to the shift register. In a solid-state imaging device provided with a shift register capable of performing scanning as a light receiving pixel scanning unit, one shift register is divided into a plurality of blocks, and a start pulse is supplied independently for each of the divided blocks and all or a part of the light is received. It is configured to read information of a pixel.

In the solid-state image pickup device thus configured, a start pulse is supplied to each divided block of the shift register divided into a plurality of blocks independently for each block, whereby the light receiving pixels are partially or partially controlled by the shift register. A high frame rate can be realized when all signals are read out by scanning and only a part is repeatedly scanned.

[0012]

Next, an embodiment will be described. FIG. 1 is a circuit diagram showing a first embodiment of a shift register constituting a drive scanning unit of a light receiving unit in a solid-state imaging device according to the present invention. In this embodiment, a one-stage CMOS clocked inverter 1 and a two-stage CMOS clocked inverter 1-O
_ij , 1-E _ij (i = 1, 2, 3, j = A, B, C) in which nine stages of cascade-connected unit circuits are provided. Each unit circuit has an output terminal O _1A , O _2A ,... O _3C are provided, and are divided into three blocks A, B, and C and can be output independently.

Before starting the description of the shift register shown in FIG. 1, a unit circuit composed of two-stage CMOS clocked inverters will be described. FIG. 2 is a block diagram of the unit circuit, and FIG. 3 is a circuit diagram shown at a transistor level. The first-stage clocked inverter 1-O connects two p-MOSFETs 11 and 12 connected in series and two n-MOSFETs 13 and 14 connected in series similarly in series, and the p-MOSFET 12 and n-MOSFET An input signal IN is applied to each gate of the MOSFET 13 in common, and a p-MOSFET
Clock pulse φ ₁ , n-MOSFET
Clock pulses / phi ₁ is configured to apply to the gate of 14.

The second-stage clocked inverter 1-E
Are similarly p-MOSFETs 15, 16 and n-MOSFET 1
7, p-MOSFET16 and n-MOSF
Each gate of ET17 has a first-stage clocked inverter 1
The output end 19 of the -O is connected to the gate of the p-MOSFET 15 is configured so that the clock pulses / phi ₂ is applied to the gate of the clock pulse φ _2, n-MOSFET18. The sources of the p-MOSFETs 11 and 15 are connected to the power supply V _DD , and the sources of the n-MOSFETs 14 and 18 are connected to the power supply V _SS
It is connected to the. In addition, as a unit circuit, the input signal I
A configuration shown in FIG. 4 in which the method of applying N and the clock pulses φ ₁ , / φ ₁ , φ ₂ , / φ ₂ is changed can also be used.

Next, the operation of the unit circuit will be described with reference to the timing chart of FIG. Input pulse IN at t = t ₀
Attains an “H” level, and at t = t ₁ , the clock pulse φ ₁
Becomes "L" level, the p-MOSFET 11, n-MOSFET 13, 1 of the first-stage clocked inverter 1-O
4 conducts and the output terminal 19 of the first stage clocked inverter
(The output of the node a) becomes “L” level. Then t =
When the clock pulse φ ₂ becomes “L” level at t ₃ , 2
P-MOSFET of the clocked inverter 1-E of the stage
15, 16, and the n-MOSFET 18 are turned on, and the output OUT of the second-stage clocked inverter 1-E becomes "H" level. After the input pulse IN goes to the “L” level at t = t ₄ , when the clock pulse φ ₁ goes to the “L” level, the same operation as described above results in the output a (19) of the first-stage clocked inverter. ) Is at the “H” level. When the clock pulse φ ₂ goes to “L” level at t = t ₇ , as a result of the same operation as described above, the output OUT goes to “L” level. From the above description, it is understood that the node a, that is, the output terminal 19 of the first stage is in a floating state while the clock pulse φ ₁ is at the “H” level.

Next, the description returns to the shift register shown in FIG. Shift register start pulse φ _STj (j =
A, B, C) are input independently for each block. For example, when skipping the block A and sequentially outputting a pulse only to the block B to sequentially scan only the light receiving unit driven by the B block, only the start pulse φ _STB is activated. A method for preventing the block C from being scanned after the block B has been scanned will be described later.

Next, a start pulse φ _STj (j = A, B,
A method of inputting C) to a node in the middle of the shift register will be described. _{Reference numerals} 2-1, 2-2, and 2-3 _denote tri-state buffers. When φ _STj (j = A, B, C) is at “H” level, an input is transmitted to the output side, and “L” level is output. Sometimes the output goes into a high impedance state.
The output terminals 3-1, 3-2, 3-3 of the tristate buffers 2-1, 2-2, 2-3 are connected to a clocked inverter 1-O _1j (j = A, B, C )
And the clocked inverter 1-E _1j (j = A,
B, C) at the connection with the input end, ie, nodes a, b,
c. The input terminal of each tri-state buffer 2-1, 2-2, 2-3 has a clock pulse /
to enter the φ _1.

Next, the operation of the shift register shown in FIG. 1 will be described with reference to FIGS. FIG. 6 shows block A,
FIG. 7 is a diagram illustrating signal waveforms in the case of normal scanning in which all light receiving units driven by B and C are scanned. Synchronization with the start pulse phi _STA with a rise of the clock pulses phi ₁ to the "H" level. The tri-state buffer 2-1 _controls the period (t = t ₁ to t ₁₎ during which the start pulse φ _STA is at the “H” level.
t _4), and outputs a clock pulse / φ _1. t = t ₁ ~
At t _3, as described above, the clocked inverter 1
If the input of E _1A is in a floating state unless the output terminal 3-1 of the tri-state buffer 2-1 is connected, the node a becomes / φ ₁ = “L” level. The input of the first stage clocked inverter 1 is "H".
Since t = t _{3 to} t ₄ , the clocked inverter 1-O _1A is in a conductive state, and the node “a” is about to go to the “H” level. Since / φ ₁ = “H” level, node a attains “H” level. The output of the output terminal O _1A, when the state of the node a clock pulse phi ₂ becomes the "L" level, since incorporated into the clocked inverters 1-E _1A, the "H" level at t = t _2. Thereafter, the data is sequentially shifted in synchronization with the clock pulse. The tri-state buffer 2-2 and 2-3, always start pulse φ _STB, because it is φ _STC both the "L" level, always be in a high impedance state, it does not affect the shift operation.

FIG. 7 is a diagram showing signal waveforms when only the light receiving section driven by the block B is scanned. In this case, both the start pulses φ _STA and φ _STC are set to “L” level. Start pulse φ _STB is clock pulse φ ₁
Rises to the "H" level in synchronization with the rise of the output terminals O _1B , O _2B , and O 2.
Pulses are sequentially output from _3B . After the output appears at the output terminal O _3B, when the clock pulses φ ₁ and φ ₂ are both set to “L” level at t = t ₅ , all the clocked inverters forming the shift register are turned on, and the first stage clocked inverter is turned on. since first input is the "H" level, the outputs of all of the output terminals O _1A ~ O _3C becomes "L" level. That is, the shift operation of the shift register can be stopped by simultaneously setting the clock pulses φ ₁ and φ ₂ to the “L” level.

FIG. 8 is a circuit diagram showing a second embodiment of the shift register. This embodiment is configured by connecting the unit circuits shown in FIG.
It is divided into B and C and can be output independently.

First, the configuration and operation of the unit circuit will be described. The unit circuit is an n-MOSFE, as shown in FIG.
T21, inverter 22, p-MOSFET 23, and inverter
Made a series circuit of 24, a clock pulse phi ₂ to the gate of the n-MOSFET 21, is adapted to apply a clock pulse phi ₁ to the gate of the p-MOSFET 23. In the unit circuit having such a configuration, as shown in FIG. 10, the input signal IN becomes “H” level at t = t ₁ ,
When clock pulse φ ₂ attains an “H” level, n-MO
The SFET 21 conducts, and the node a goes to "L" level.
When the clock pulse φ ₁ goes to “L” level at t = t ₂ , the p-MOSFET 23 conducts, and the output OUT goes to “H”.
Become a level. At t = t ₃ , when the input signal IN goes to “L” level and the clock pulse φ ₂ goes to “H” level,
The n-MOSFET 21 conducts, and the node a goes to "H" level. When the clock pulse phi ₁ becomes "L" level at t = t _4, p-MOSFET23 becomes conductive, the output OUT becomes "L" level. Node a receives clock pulse φ ₂
Is in the floating state during the period of “L” level.

Next, the operation of the first stage of the shift register shown in FIG. 8 will be described with reference to the signal waveform diagrams of FIGS. 11 and 12. 25 is a tristate buffer, when the control terminal IN is at the "H" level, outputs the input clock pulses / phi _2, when the control terminal IN is at the "L" level, the output becomes a high impedance state. The output of the tristate buffer 25 is connected to the input node a 'of the inverter 22. The source of the n-MOSFET21 is connected to the power supply V _SS.

Control terminal I of tri-state buffer 25
N becomes "H" level at t = t ₁ ~t _4, and outputs the input clock pulses / phi _2. Tri-state buffer
A connection point between the n-MOSFET 21 and the inverter 22 to the output terminal 25 is connected the node a 'clock pulses phi ₂
Becomes "L" level when "H" level, so that t = t
Period of ₂ ~t ₄ becomes "H" level. When the clock pulse φ ₁ goes to “L” level at t = t ₃ , the p-MOSFE
T23 conducts, and as described in FIG.
T is at the “H” level during the period from t = t _{3 to} t ₅ . This later, the output appears in synchronization with the sequential falling edge of the clock pulse φ _1.

In the shift register of FIG. 8, a start pulse φ _STj (j =
If (A, B, C) is set to the “H” level at the timing shown in FIG. 12, the shift operation is started from that block.
Since the control terminals of the tristate buffers in the subsequent stages are at the “L” level, the output of the tristate buffer is in a high impedance state and does not affect the shift operation. To stop the shift operation of the shift register is the same concept as in the first embodiment shown in FIG. 7, if at the same time the clock pulses phi ₁ the "L" level, the clock pulse phi ₂ to the "H" level Good.

FIG. 13 is a schematic configuration diagram showing a configuration example of a solid-state imaging device using the shift register of the first embodiment shown in FIG. This solid-state imaging device includes a light receiving section 31 composed of 9 × 9 pixels, and a vertical shift register 32 and a horizontal shift register 33 composed of the shift registers shown in FIG. In this configuration example, reading can be performed with 3 × 3 pixels as one block. As the pixel, any pixel that can be XY-addressed, such as a MOS image sensor, a CMD image sensor, a SIT image sensor, and an AMI image sensor, can be used. Note that the readout circuit is appropriately changed depending on the type of the pixel.

FIG. 14 is a diagram showing the pulse timing when the entire screen of the light receiving section is read. The start pulse φ _STB ,
φ _STC , φ _STb , φ _STc are set to “L” level. During a period in which one row of the light receiving section 31 is selected by the vertical shift register 32 (vertical selection period), nine pixels in the horizontal direction are sequentially scanned by the horizontal shift register 33 so that pixel signals of the entire screen are output to the output line. The signals are read out in time series via 34, and a signal output Sig is obtained.

FIG. 15 is a diagram showing pulse timing when only the 3 × 3 pixels at the center of the light receiving section 31 are repeatedly scanned. In this case, the waveforms of the start pulse and each clock pulse are selected as shown in the figure so that pulses are sequentially output only from the block B of the vertical shift register 32 and the block b of the horizontal shift register 33. In this case, the timings of the start pulse and each clock pulse are obtained by applying the signal waveform for divided scanning of the shift register of the first embodiment shown in FIG. 7 to the vertical and horizontal shift registers 32 and 33.

FIG. 16 shows an example of a selected area of the light receiving section 31. Figure
When the vertical shift register and the horizontal shift register are operated at the pulse timing shown in FIG. 14, it corresponds to the whole area selection shown in (F), and when operated at the pulse timing shown in FIG. Corresponds to the selection area indicated by.
By simply controlling the waveforms of the start pulse and the clock pulse to the vertical and horizontal shift registers, the size and position of the selected region can be set variously, not limited to the illustrated example.

In the above configuration example, the description has been given of the case where the invention is applied to an area sensor. However, it is needless to say that the present invention can be applied to a line sensor.

[0030]

As described above with reference to the embodiments,
According to the present invention, since a start pulse is supplied to each divided block of a plurality of divided shift registers independently for each block, only a part of the light receiving pixels can be repeatedly scanned, and a high frame rate can be obtained. realizable. Further, the size and position of the scanning selection area of the light receiving pixels can be arbitrarily set within the range of the divided block by selecting start pulses to be supplied independently.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a shift register used in a solid-state imaging device according to the present invention.

FIG. 2 is a block diagram showing a unit circuit constituting the shift register shown in FIG. 1;

FIG. 3 is a diagram illustrating a circuit configuration at a transistor level of the unit circuit illustrated in FIG. 2;

FIG. 4 is a diagram showing another configuration example of the unit circuit.

FIG. 5 is a diagram showing signal waveforms for explaining the operation of the unit circuit shown in FIG. 3;

FIG. 6 is a diagram showing signal waveforms when normal scanning is performed by the shift register shown in FIG. 1;

FIG. 7 is a diagram showing signal waveforms when performing a division scan by the shift register shown in FIG. 1;

FIG. 8 is a circuit diagram showing a second embodiment of the shift register.

FIG. 9 is a circuit diagram showing a unit circuit constituting the shift register shown in FIG. 8;

10 is a diagram showing signal waveforms for describing the operation of the unit circuit shown in FIG.

11 is a circuit configuration diagram illustrating a first-stage portion of the shift register illustrated in FIG. 8;

12 is a diagram illustrating signal waveforms for describing an operation of a first-stage portion illustrated in FIG. 11;

13 is a diagram illustrating a configuration example of a solid-state imaging device using the shift register illustrated in FIG. 1;

FIG. 14 is a diagram illustrating signal waveforms when normal scanning is performed in the solid-state imaging device illustrated in FIG. 13;

FIG. 15 is a diagram illustrating signal waveforms when performing divided scanning in the solid-state imaging device illustrated in FIG. 13;

FIG. 16 is a diagram illustrating an example of a division selection area of the light receiving unit.

FIG. 17 is a block diagram illustrating a configuration example of a conventional image sensor.

FIG. 18 is a circuit configuration diagram illustrating another configuration example of a conventional image sensor.

FIG. 19 is a diagram for explaining window processing by another conventional image sensor.

[Explanation of symbols]

 1 First-stage CMOS clocked inverter 2-1, 2-2, 2-3 Tri-state buffer 11 p-MOSFET 12 p-MOSFET 13 n-MOSFET 14 n-MOSFET 15 p-MOSFET 16 p-MOSFET 17 n-MOSFET 18 n −MOSFET 21 n-MOSFET 22 inverter 23 p-MOSFET 24 inverter 25 tri-state buffer 31 light receiving section 32 vertical shift register 33 horizontal shift register

Claims (4)

(57) [Claims] 1. A solid-state imaging device comprising a shift register capable of setting all outputs of the shift register to the same state in a state where a plurality of transfer clock pulses are supplied to the shift register as scanning means of a light receiving pixel. Divide one shift register into multiple blocks,
A solid-state imaging device characterized in that a start pulse is supplied independently for each divided block to read out information on all or some of the light receiving pixels. 2. A start pulse supplied independently for each divided block is input to a predetermined node of each divided block of a shift register via a tri-state buffer, and a timing at which the node is in a floating state is provided. 2. The solid-state imaging device according to claim 1, wherein a tri-state buffer is activated and a start pulse is applied to said node. 3. A drive of a solid-state imaging device having a shift register capable of making all outputs of the shift register the same state in a state where there are a plurality of transfer clock pulses to be supplied to the shift register as scanning means of a light receiving pixel. In the method, one shift register is divided into a plurality of blocks, a start pulse is supplied independently for each divided block, and a pulse waveform of a start pulse supplied for each divided block and a transfer clock pulse supplied commonly to the divided blocks And reading out information of all or some of the light receiving pixels by controlling the driving of the solid-state imaging device. 4. A start pulse supplied independently for each divided block is input to a predetermined node of each divided block of a shift register via a tri-state buffer, and a timing at which the node is in a floating state is provided. 4. The driving method for a solid-state imaging device according to claim 3, wherein a tri-state buffer is activated, and a start pulse is applied to the node.