JP3704763B2 - Solid-state imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device, and more particularly to an XY address type solid-state imaging device typified by an amplification-type solid-state imaging device capable of reading pixel information obtained by photoelectric conversion in units of pixels.
[0002]
[Prior art]
For example, an amplification type solid-state imaging device which is an XY address type solid-state imaging device includes a vertical scanning circuit that scans a plurality of pixels (photoelectric conversion elements) arranged in rows and columns and a horizontal scanning circuit that scans in units of columns. In order to control the operation of these scanning circuits, many clock pulses are required. FIG. 15 shows a schematic configuration of a conventional amplification type solid-state imaging device.
[0003]
In FIG. 15, the gate electrodes (control electrodes) of a large number of pixel transistors 111 arranged in rows and columns are connected to the vertical selection line 112 in units of rows, and each source electrode is connected to the vertical signal line 113 in units of columns, so that vertical selection is performed. A vertical scanning circuit 114 that drives the line 112 and a horizontal scanning circuit 116 that sequentially outputs a signal output from each pixel transistor 111 through the vertical signal line 113 to the output terminal 115 for each column are provided.
[0004]
The vertical scanning circuit 114 includes a reset shift register 117 that performs an electronic shutter operation, a read shift register 118, and a vertical selection line driver 119. The vertical scanning circuit 114 includes a clock pulse (φV1P, φV1N, φV2P, φV2N) for controlling the vertical selection line 112 at an appropriate timing, and other timing pulses (read start pulse φVS, electronic shutter start pulse φSS). , Read timing pulse φVOP, electronic shutter timing pulse φSOP).
[0005]
On the other hand, the horizontal scanning circuit 116 includes a signal holding circuit 120 that stores and holds an output signal from the pixel transistor 111 and a horizontal shift register 121. The horizontal scanning circuit 116 receives a signal holding operation pulse φOP, clock pulses φH1 and φH2 of the horizontal shift register 121, and a start pulse φHS. These clock pulses are generated by a timing generator (not shown) provided outside the image sensor.
[0006]
[Problems to be solved by the invention]
As described above, the conventional amplification type solid-state imaging device is configured to take in various clock pulses generated outside the element, and therefore requires a large number of terminals for inputting clock pulses. There is a problem that not only the circuit configuration of an IC to be driven is complicated, but also the imaging system including the drive circuit is hindered from being downsized.
[0007]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a solid-state imaging device capable of contributing to downsizing of an imaging system by reducing terminals for inputting clock pulses. It is in.
[0008]
[Means for Solving the Problems]
  In the solid-state imaging device according to the present invention, they are arranged in a matrix.TheA plurality of photoelectric conversion elements;A read shift register that generates a read pulse for reading signals generated by the plurality of photoelectric conversion elements and a reset shift register that generates a reset pulse for resetting the photoelectric conversion elements are independently provided.A vertical scanning circuit for scanning a plurality of photoelectric conversion elements in units of rows;,A horizontal scanning circuit that outputs a horizontal scanning pulse for sequentially reading out signals output from photoelectric conversion elements in a row scanned by the vertical scanning circuit among a plurality of photoelectric conversion elements, and a plurality of photoelectric conversion elements, vertical scanning Same as circuit and horizontal scanning circuitSemiconductorIn a vertical scanning circuit and a horizontal scanning circuit which are formed on a chip and receive a vertical scanning clock, a horizontal scanning clock and a scanning start pulse inputted from the outsideRead pulse, reset pulseAnd a clock generator for generating a clock signal necessary for generating the horizontal scanning pulse.
[0009]
  In the solid-state imaging device having the above configuration, it is necessary for the scanning operation of the vertical scanning circuit and the horizontal scanning circuit.Read pulse, reset pulseAnd a clock generator that generates a clock signal necessary for generating a horizontal scanning pulse is the same as a plurality of photoelectric conversion elements, a vertical scanning circuit, and a horizontal scanning circuitSemiconductorIt is formed on a chip (on-chip), and only a vertical scanning clock, a horizontal scanning clock, and a scanning start pulse are externally supplied to this clock generator. Thus, only three terminals for inputting clock pulses are required.
[0010]
  AndScan start pulse commanding start of scanning of vertical scanning circuitBut, Including a read start pulse for starting the operation of the read shift register and a reset start pulse for starting the operation of the reset shift registerThus, the readout shift register determines the readout position in the vertical direction based on the readout start pulse, and starts readout of the pixel signal from that position. On the other hand, the reset shift register starts resetting the pixel (photoelectric conversion element) based on the reset start pulse. Here, the time interval between the read start pulse and the reset start pulse included in the scan start pulse corresponds to the shutter speed of the electronic shutter.
[0012]
  In the present inventionOtherIn the solid-state imaging device, an imaging unit including a plurality of photoelectric conversion elements that are arranged in a matrix and outputs a photoelectrically converted signal when a vertical scanning pulse is given thereto, and the plurality of vertical scanning pulses by sequentially outputting the plurality of the vertical scanning pulses. And a horizontal scanning pulse for sequentially reading out signals output from the photoelectric conversion elements in a row scanned by the vertical scanning circuit among the plurality of photoelectric conversion elements. A horizontal scanning circuit to output;The plurality of photoelectric conversion elements, the vertical scanning circuit, and the horizontal scanning circuit are formed on the same semiconductor chip and input from the outside.A clock generator for receiving a vertical scanning clock, a horizontal scanning clock, and a scanning start pulse, and generating a clock signal necessary for generating the vertical scanning pulse and the horizontal scanning pulse in the vertical scanning circuit and the horizontal scanning circuit; The start pulse includes a normal scan start pulse generated in a horizontal blanking period and a high-speed scan start pulse generated in a horizontal effective period, and the clock generator generates the normal scan start pulse generated in a horizontal blanking period. A clock signal for normal scanning by the vertical scanning circuit is generated, and a clock signal for high-speed scanning by the vertical scanning circuit is received when the high-speed scanning start pulse generated within a horizontal effective period is received. Is generated.
[0013]
In the solid-state imaging device configured as described above, the clock generator includes the normal scan start pulse generated within the horizontal blanking period and the high-speed scan start pulse generated within the horizontal effective period. In response to this single scan start pulse, a clock signal for normal scanning and a clock signal for high-speed scanning are generated.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a configuration diagram showing an embodiment of the present invention applied to an amplification type solid-state imaging device. In FIG. 1, a large number of pixel transistors (in this example, NchMOS transistors) 11 that are photoelectric conversion elements are arranged in a matrix, and the gate electrodes (control electrodes) of the pixel transistors 11 are arranged in the imaging region in the horizontal direction. Connected to the vertical selection line 12 in units of rows, each source electrode is connected to a vertical signal line 13 arranged in the vertical direction in the imaging region in units of columns, and each drain electrode is connected to the power source VD via the power source line 14. It is connected. Each vertical selection line 12 is supplied with a vertical scanning pulse φV (...) From a vertical scanning circuit 18 including a reset shift register 15 for performing an electronic shutter operation, a read shift register 16 and a vertical selection line driver 17 including a logic gate. ..., φVm, φVm + 1, ...). A specific circuit configuration of the vertical scanning circuit 18 will be described later.
[0015]
On the other hand, the horizontal scanning circuit 19 includes a horizontal shift register 20 and a signal holding circuit 21. The signal holding circuit 21 has one end connected to the NchMOS transistor 22 which is an operation switch in which the drain electrode is connected to one end of the vertical signal line 13 and the signal holding operation pulse φOP is applied to the gate electrode, and the source electrode of the MOS transistor 22. The capacitor 23, which is a signal holding element whose other end is grounded, the drain electrode is connected to one end of the capacitor 23, the source electrode is connected to the horizontal signal line 25, and the horizontal scanning pulse φH from the horizontal shift register 20 is connected to the gate electrode. (..., .Phi.Hn, .phi.Hn + 1,...) Is provided with an NchMOS transistor 24 which is a horizontal switch.
[0016]
In the horizontal scanning circuit 19, the signal output from the pixel transistor 11 selected by the vertical scanning pulse φV is held in the capacitor 23 from the vertical signal line 13 through the MOS transistor 22 which is an operation switch. When the horizontal scanning pulse φH is output from the horizontal shift register 20 in accordance with the horizontal scanning timing and the MOS transistor 24 which is a horizontal switch is sequentially turned on, the signal held in the capacitor 23 is transmitted through the MOS transistor 24 to the horizontal signal line. 25 to the output terminal 26.
[0017]
The clock generator 27 is formed on the same chip as each pixel transistor 11, vertical scanning circuit 18, horizontal scanning circuit 19, etc., and a horizontal clock pulse φHCK which is a horizontal scanning clock given from the outside of the image sensor, a vertical scanning clock. Clock pulses (φV1P, φV1N, φV2P, φV2N, φVOP, φSOP, φH1, φH2, φHS required for the scanning operation of the vertical scanning circuit 18 and the horizontal scanning circuit 19 based on the vertical clock pulse φVCK and the scanning start pulse φSCK. ). Then, the vertical scanning circuit 18 and the horizontal scanning circuit 19 output a vertical scanning pulse φV and a horizontal scanning pulse φH with appropriate timing according to these clock pulses.
[0018]
FIG. 2 is a block diagram showing an example of the configuration of the vertical scanning circuit 18 and shows the configuration in the vicinity of the input of the scanning start pulse φSCK (φVS, φSS) of the vertical scanning circuit 18. In FIG. 2, the reset shift register 15 and the read shift register 16 provided independently are constituted by transfer type dynamic shift registers. Specifically, the reset shift register 15 has a half bit shift register 31 provided at the input stage of the scan start pulse φSCK, and a plurality of unit bit shift registers 32 (for the number of rows) connected in cascade thereafter. Has been. On the other hand, the read shift register 16 has a configuration in which only the unit bit shift register 33 is cascade-connected in the same number as the unit bit shift register 32 of the reset shift register 15.
[0019]
3 and 4 show specific circuit configurations of the half-bit shift register 31 and the unit bit shift registers 32 and 33. FIG. The half-bit shift register 31 includes a transfer gate 34 in which an Nch MOS transistor Q1 and a Pch MOS transistor Q2 are connected in parallel to each other, and a CMOS inverter 35 in which an Nch MOS transistor Q3 and a Pch MOS transistor Q4 are connected in series between a power supply and the ground. The scan start pulse φSCK is input in synchronism with φV2N and φV2P of the vertical scan clock provided to the gate electrodes of the MOS transistor Q1 and the MOS transistor Q2.
[0020]
On the other hand, the unit bit shift registers 32 and 33 have a configuration in which half-bit shift registers 31 are connected in two stages in series. That is, a transfer gate 36 in which an NchMOS transistor Q5 and a PchMOS transistor Q6 are connected in parallel, a CMOS inverter 37 in which an NchMOS transistor Q7 and a PchMOS transistor Q8 are connected in series between a power supply and the ground, and similarly an NchMOS transistor A transfer gate 38 made up of Q9 and PchMOS transistor Q10 and a CMOS inverter 39 made up of NchMOS transistor Q11 and PchMOS transistor Q12 are arranged. The gate electrodes of MOS transistor Q5 and MOS transistor Q6 are connected to φV1N and φV1P of the vertical scanning clock. Is given, the output signal of the previous stage is inputted, and the MOS transistor Q9 and the MOS transistor Q10 When φV2N and φV2P of the vertical scanning clock are supplied to each gate electrode, a signal is output to the next stage.
[0021]
  As a result, the reset shift register 15 is supplied with only φV2N and φV2P of the vertical scanning clock to the first half-bit shift register 31 provided in the input stage, and therefore φV2N and φV2P of the vertical scanning clock. The shift operation is started with a scan start pulse φSCK suitable for the phase. On the other hand, a read shift register16Is constituted by the unit bit shift register 33 from the head, so that the shift operation is started with the scan start pulse φSCK adapted to the phases of the vertical scan clocks φV1N and φV1P. Of the vertical scanning clocks φV1N, φV1P, φV2N, and φV2P, φV1N and φV1P are clock signals generated at the first timing in the horizontal blanking (HBLK) period, and φV2N and φV2P are in the horizontal blanking period. The clock signal is generated at a second timing different from the first timing (see FIG. 5).
[0022]
As described above, the reset shift register 15 for generating the vertical scanning pulse φV (..., ΦVm, φVm + 1,...) Is provided with the half-bit shift register 31. Since the read shift register 16 can change the phase at which the scan start pulse is received, the shift registers 15 and 16 can be started independently. That is, both the readout timing and the shutter speed of the electronic shutter can be controlled only by inputting a single scan start pulse φSCK.
[0023]
In this example, the half-bit shift register 31 is provided on the reset shift register 15 side. However, the half-bit shift register 31 may be provided on the read shift register 16 side instead of the reset shift register 15 side. Of course, it is possible to obtain the effect.
[0024]
Referring again to FIG. 2, the vertical selection line driver 17 including the logic gate includes an AND gate 41 having two inputs of the output of the unit bit shift register 33 of the read shift register 16 and the vertical operation pulse φVOP, and the reset shift register 15. AND gate 42 having two inputs of the output of unit bit shift register 32 and start operation pulse φSOP, OR gate 43 having two inputs of each output of AND gates 41 and 42, and the logic of the output of OR gate 43 An inverting inverter 44 is provided for each row. The output of each inverter 44 is a vertical scanning pulse φV (φV1, φV2, φV3,...).
[0025]
FIG. 5 is a timing chart showing drive timing of the vertical scanning circuit 18 of FIG. Here, the first pulse P1 of the scan start pulse φSCK is an electronic shutter (reset) start pulse φSS for starting the reset shift register 15, and the next pulse P2 is a read start pulse for starting the read shift register 16. φVS. That is, the scan start pulse φSCK is a pulse signal in which the electronic shutter start pulse φSS and the read start pulse φVS are multiplexed.
[0026]
As described above, φV1N, φV1P, φV2N, and φV2P are clock pulses common to the reset shift register 15 and the read shift register 16, and φVOP and φSOP are the vertical selection lines 12 during pixel readout and electronic shutter operation, respectively. Are the timing pulses for determining the timing of the operation, and φV 1, φV 2, and φV 3 are vertical scanning pulses applied to the vertical selection line 12. ΦSUB is a pulse applied to the substrate to perform pixel reset and electronic shutter operation (pixel reset).
[0027]
In the timing chart of FIG. 5, the time interval between the pulse P1 and the pulse P2 of the scan start pulse φSCK (in this example, equivalent to 2H (H: horizontal scanning period)) corresponds to the shutter speed of the electronic shutter. The pulse P3 of the vertical scanning pulse V1 whose timing is determined by the pulse P1 performs a pixel reset operation for the electronic shutter, and the pulse P4 whose timing is determined by the pulse P2 performs a reading operation and a pixel reset operation. As described above, the electronic shutter (reset) start pulse (φSS) P1 is inserted in the scan start pulse φSCK at a timing different from that of the read start pulse (φVS) P2 in the horizontal blanking period. The normal scan start and the reset scan start can be controlled by a single control signal (scan start pulse φSCK). As is clear from this timing chart, the pulse width of the pulse P3 is determined by the pulse width of the pulse φSOP, and the pulse width of the pulse P4 is determined by the pulse width of the pulse φVOP.
[0028]
The pulse P1 of the scan start pulse φSCK is the vertical scan clock because the half bit shift register 31 to which the vertical scan clocks φV2N and φV2P are added as shift pulses starts the reset shift register 15 connected to the head of the start pulse input. It stands at the timing synchronized with φV2N and φV2P. At this timing, the read shift register 16 does not start. On the other hand, the pulse P2 of the scan start pulse φSCK stands at a timing synchronized with the vertical scan clocks φV1N and φV1P in order to start the read shift register 16 to which the shift register 33 is connected from the head. At this timing, the reset shift register 15 does not start.
[0029]
That is, by adopting the circuit configuration of FIG. 2 as the vertical scanning circuit 18, whether to synchronize with the clock pulses φV1N and φV1P or with the clock pulses φV2N and φV2P even if the terminals of the scanning start pulse φSCK are common. Thus, the read shift register 16 and the reset shift register 15 can be started independently.
[0030]
FIG. 6 is a block diagram illustrating an example of the configuration of the clock generator 27. In FIG. 6, a horizontal clock pulse φHCK given from the outside of the imaging device is supplied to the horizontal shift register 20 as a first-phase horizontal clock pulse φH1 through inverters 51 and 52, and each P input of the shift registers 53 and 55. And the N input of the shift register 54, and further supplied to the horizontal shift register 20 through the inverter 56 as the horizontal clock pulse φH2 of the second phase, and the N inputs of the shift registers 53 and 55 and the P input of the shift register 54 become. Also, the vertical clock pulse φVCK given from the outside of the image sensor is input to the first-stage shift register 53 via the inverter 47.
[0031]
The shift registers 53, 54, and 55 are connected in cascade, and the output 1B of the second stage becomes one input of each of the NAND gate 59 and the NOR gate 60 via the inverter 58, and the output 1C of the third stage becomes the NAND gate 59 and Each other input of the NOR gate 60 is used. The output of the NAND gate 59 is supplied to the horizontal shift register 20 as a horizontal start pulse φHS via the inverter 61, and the output of the NOR gate 60 is connected in cascade as a clock generator start pulse CS, for example, 100 stages of shift registers 62.₁~ 62₁₀₀First stage shift register 62₁Will be input.
[0032]
This 100 stage shift register 62₁~ 62₁₀₀, The odd-stage shift register 62₁62_Three, ..., 62₉₉The horizontal clock pulse φHCK that has passed through the inverters 51 and 52 has N input, and the horizontal clock pulse φHCK that has passed through the inverter 56 has P input.₂62_Four, ..., 62₁₀₀The horizontal clock pulse φHCK passed through the inverters 51 and 52 has a P input, and the horizontal clock pulse φHCK passed through the inverter 56 has an N input. Then, an odd-stage shift register 62₁62_Three, ..., 62₉₉Each output of the inverter 63 has one stage.₁, 63_Three, ..., 63₉₉Are derived as reference pulses T1, T3,...₂62_Four, ..., 62₁₀₀Each output of is a two-stage inverter 64₂, 64_Four, ..., 64₁₀₀And 65₂, 65_Four, ......, 65₁₀₀Are derived as reference pulses T2, T4,..., T100.
[0033]
FIG. 7 shows shift registers 53-55 and 62.₁~ 62₁₀₀It is a circuit diagram which shows the specific circuit structure of these. These shift registers include a PchMOS transistor Q13 whose source electrode is connected to a power supply, an NchMOS transistor Q14 whose source electrode is grounded, and a PchMOS transistor Q15 and an NchMOS connected in series between the drain electrodes of the MOS transistors Q13 and Q14. The gate common connection point of the MOS transistors Q13 and Q14 is an input (I) end, and the drain common connection point of the MOS transistors Q15 and Q16 is an output (O) end. The gate electrodes of the MOS transistors Q15 and Q16 serve as P and Q input terminals.
[0034]
FIG. 8 shows a timing chart of each clock of the clock generator 27 described above. The clocks φH1 and φH2 necessary for driving the horizontal shift register 20 are obtained by passing the horizontal clock pulse φHCK through the two-stage inverters 51 and 52 and the first-stage inverter 56, and the horizontal clock necessary for starting the horizontal shift register 20 is obtained. The start pulse φHS is obtained by phase-shifting the trailing edge of the vertical clock pulse φVCK with three stages of shift registers 53, 54, and 55 and passing it through a NOR gate 59 and the like.
[0035]
That is, by passing the vertical clock pulse φVCK through the three-stage shift registers 53, 54, and 55, the phase-shifted pulses 1 A, 1 B, and 1 C are obtained, and among these pulses 1 B and 1 C are passed through the NAND gate 59, A start pulse φHS of the horizontal shift register 20 synchronized with the trailing edge of the vertical clock pulse φVCK is obtained. Similarly, by passing the pulses 1B and 1C through the NOR gate 60, a clock generator start pulse CS synchronized with the leading edge of the vertical clock pulse φVCK is obtained.
[0036]
FIG. 9 shows a configuration of a timing generation circuit that generates various timing pulses based on an arbitrary combination of reference pulses T1 to T100. This logic circuit includes an S (set) R (reset) flip-flop 71 assembled with NAND gates, and inverters 72 to 75 connected to input / output terminals thereof. In the logic circuit (a), the reference pulses T1 and T20 are used as the S and R inputs of the SR flip-flop 71, thereby generating the timing pulse φV1a that is the basis of the clock pulse of the vertical scanning circuit 18.
[0037]
Similarly, in the logic circuit (b), the reference pulses T50 and T70 are used as the S and R inputs of the SR flip-flop 71, so that the timing pulse φV2a is obtained. In the logic circuit (c), the reference pulses T1 and T100 are used as the SR flip-flop 71. In the logic circuit (d), the timing pulse φSOP is generated by setting the reference pulses T50 and T100 as the S and R inputs of the SR flip-flop 71 in the logic circuit (e). By using the reference pulses T1 and T40 as the S and R inputs of the SR flip-flop 71, the timing pulse φOP is generated. The timing relationship of the input / output pulses is shown in the timing chart of FIG.
[0038]
As described above, the clock generator 27 generates a large number of reference pulses T1 to T100 whose phases are shifted by half a bit based on the horizontal clock pulse φHCK and the vertical clock pulse φVCK. By generating a desired timing pulse based on the combination of pulses, for example, the wiring of the output line of each reference pulse in FIG. 6 is made of the first-layer aluminum wiring and the input line of each reference pulse in FIG. If the wiring is formed with the second-layer aluminum wiring, the timing pulse phase (timing) can be easily and freely changed by simply changing the contact position of the first-layer and second-layer aluminum wiring. Can be changed.
[0039]
FIG. 11 is a block diagram showing another embodiment of the present invention. In the figure, the same parts as those in FIG. In the present embodiment, most of the configuration is the same as that of FIG. 1, but only the configuration of the clock generator 27 is different. In the amplification type solid-state imaging device to which the present embodiment is applied, a part of the effective pixel area is used as an image frame, and a video signal can be output from an arbitrary image frame in the effective pixel area. The rows are scanned by the vertical scanning circuit 18 by high-speed idling (high-speed scanning). This high speed idling is completed within the vertical blanking period.
[0040]
According to the amplification type solid-state imaging device having such a configuration, the vertical scanning circuit 18 controls the reading start position and the reset start position based on the scanning start pulse φSCK, thereby changing the size of the image frame or cutting out the image frame. By controlling the position, the aspect ratio can be changed and camera shake correction can be performed. Hereinafter, a specific configuration for realizing this will be described.
[0041]
A specific configuration of the clock generator 27 will be described below. In addition to the configuration of the previous embodiment, the clock generator 27 has a configuration in which a high-speed pre-feed pulse generation circuit that generates a pulse for high-speed feed of the vertical scanning circuit 18 for changing the aspect ratio and correcting camera shake is incorporated. ing. An example of the configuration of this high-speed idle feed pulse generation circuit is shown in FIG. A horizontal clock pulse φHCK, a vertical clock pulse φVCK, and a scan start pulse φSCK are input from the outside of the image sensor to the high-speed idle feed pulse generation circuit.
[0042]
In FIG. 12, the scan start pulse φSCK is inverted by the inverter 81 and becomes one input of each of the NAND gate 82 and the NOR gate 83. The vertical clock pulse φVCK becomes the other input of the NOR gate 83 and the one input of the NOR gate 84. The output of the NOR gate 83 becomes one input of the NAND gate 85. The outputs of the NAND gate 85 and the NOR gate 84 become the set input and reset input of the SR flip-flop 86. The Q output of the SR flip-flop 86 and its inverted output become the other inputs of the NAND gates 82 and 85, respectively. The output of the NAND gate 82 becomes each preset (PR) input of the cascaded four-stage binary counters 87 to 90.
[0043]
The horizontal clock pulse φHCK is inverted once by the inverter 91 and supplied to the first-stage binary counter 87 as a reverse-phase clock, and inverted twice by the inverters 92 and 93 and supplied as a positive-phase clock. In the binary counters 87 to 90, the Q outputs of the first stage, the second stage, the third stage, and the fourth stage are divided by 1/2 divided output O1N, 1/4 divided output O2N of the horizontal clock pulse φHCK, 1/8 frequency-divided output O3N and 1/16 frequency-divided output O4N.
[0044]
These frequency-divided outputs O1N to O4N are four inputs of the NAND gate 94. The output of the NAND gate 94 becomes the input of the shift register 95. The shift register 95 uses the output of the inverter 91 as the P input and the output of the inverter 93 as the N input. The output of the shift register 95 becomes the input of the shift register 96 in the next stage. The shift register 96 uses the output of the inverter 91 as an N input and the output of the inverter 93 as a P input. The output of the shift register 96 becomes the other input of the NOR gate 84 via the inverter 97. As the shift registers 95 and 96, for example, the circuit configuration shown in FIG. 8 can be used.
[0045]
In the binary counters 87 to 90, the quarter-divided output O2N of the second stage is one input of each of the NAND gates 98 and 99. The 1/8 frequency-divided output O3N at the third stage is the other input of the NAND gate 98, and the 1/8 frequency-divided output O3X of the opposite phase is the other input of the NAND gate 99. Each output of the NAND gates 98 and 99 becomes one input of each of the NAND gates 100 and 101. As other inputs of these NAND gates 100 and 101, timing pulses φV1a and φV2a generated by the timing generation circuit of FIG.
[0046]
The timing pulses φV1a and φV2a are inverted by the inverters 102 and 103, thereby being inverted as the clock pulses φV1Ps and φV2Ps, and further inverted by the inverters 104 and 105, whereby the reset shift register 15 is obtained as the clock pulses φV1Ns and φV2Ns. Given to. On the other hand, the outputs of the NAND gates 100 and 101 are directly supplied to the read shift register 16 as clock pulses φV1N and φV2N by being directly inverted by the inverters 106 and 107 as clock pulses φV1P and φV2P.
[0047]
FIG. 14 shows an example of a specific circuit configuration of the binary counter. In FIG. 14, the source electrode of the Pch MOS transistor Q21 is connected to the power supply, the source electrode of the Nch MOS transistor Q22 is grounded, the gate electrodes of these MOS transistors Q21 and Q22 are connected in common, and the drain electrode is between them. PchMOS transistor Q24 and NchMOS transistor Q24 are connected in series. NchMOS transistors Q25 and Q26 are connected in series between the common drain connection point of MOS transistors Q25 and Q26 and the ground. The gate electrode of the MOS transistor Q25 is a preset (PR) input terminal. The clock CK is applied to the gate electrode of the MOS transistor Q24, and the opposite phase clock is applied to the gate electrodes of the MOS transistors Q23 and Q26.
[0048]
Further, the NchMOS transistor Q27 whose source electrode is connected to the power source and the PchMOS transistor Q28 whose source electrode is grounded are provided at the subsequent stage. The gate electrodes of these MOS transistors Q27 and Q28 are connected to the MOS transistors Q23, Q23 of the previous stage. It is connected to the drain common connection point of Q24. A Pch MOS transistor Q29 and an Nch MOS transistor Q30 are connected in series between the drain electrodes of the MOS transistors Q27 and Q28. The clock CK is applied to the gate electrode of the MOS transistor Q29, and the opposite phase clock is applied to the gate electrode of the MOS transistor Q30.
[0049]
Further, an inverter including a Pch MOS transistor Q31 and an Nch MOS transistor Q32 connected in series between the power source and the ground is provided at the subsequent stage. The drain common connection point of the previous-stage MOS transistors Q29 and Q30 is connected to the gate electrodes of the first-stage MOS transistors Q21 and Q22, and is also connected to the gate electrodes of the MOS transistors Q31 and Q32. The drain outputs of the MOS transistors Q29 and Q30 become the Q output, and are inverted by the inverter composed of the MOS transistors Q31 and Q32 to become the anti-phase output of the Q output.
[0050]
Next, the circuit operation of the high-speed pre-feed pulse generation circuit configured as described above will be described with reference to the timing chart of FIG. In this timing chart, the scan start pulse φSCK is a high-speed scan start pulse Q1 to Q3 for starting a high-speed scan of the vertical scanning circuit 18 generated within the horizontal effective period, and a timing chart of FIG. And a normal scanning start pulse (φVS) P2 for starting normal scanning of the vertical scanning circuit 18 generated within the horizontal blanking (HBLK) period.
[0051]
Since the scan start pulse φSCK is also used as the reset shift register 15 and the read shift register 16 of the vertical scan circuit 18 as described above, the normal scan start pulses P1 and P2 enter the generation circuit. In order to prevent this, the NAND gate 82 is gated using the vertical clock pulse φVCK. As a result, the pulses other than the normal scanning start pulses P1 and P2 of the vertical scanning circuit 18, that is, the high-speed scanning start pulses Q1 to Q3 generated in the horizontal effective period are input, thereby setting the SR flip-flop 86 of the generation circuit. Then, the output of the NAND gate 82 becomes an enable pulse XFS that allows generation of a high-speed pre-feed pulse (high-speed scan start pulse).
[0052]
With this enable pulse XFS, the binary counters 87 to 90 obtain pulses O1N, O2N, O3N, and O4N obtained by dividing the horizontal clock pulse φHCK by 1/2, 1/4, 1/8, and 1/16. A high speed idle feed pulse is generated based on the divided pulse. In other words, the divided pulses O1N, O2N, O3N, and O4N are logically calculated using the timing pulses φV1a and φV2a generated by the timing generation circuit of FIG. 10 and the NAND gates 100 and 101, and used for reading including a shake correction operation. Clock pulses φV1P, φV1N, φV2P, φV2N of the shift register 16 are generated.
[0053]
In this way, a predetermined number of clock pulses φV1P, φV1N, φV2P, and φV2N are generated in response to the occurrence of one high-speed scan start pulse (Q1 to Q3) in the scan start pulse φSCK. High-speed scanning is executed a number of times corresponding to the number of start pulses (three in this example). According to this, since the number of high-speed scans can be controlled by a single control signal (scan start pulse φSCK), camera shake correction can be realized with a simple configuration.
[0054]
The clock pulses φV1Ps, φV1Ns, φV2Ps, and φV2Ns of the reset shift register 15 are generated from the timing pulses φV1a and φV2a that do not mix the high-speed idle feed pulses. As described above, the clock generator 27 independently generates the clock pulses φV1P, φV1N, φV2P, and φV2N of the read shift register 16 and the clock pulses φV1Ps, φV1Ns, φV2Ps, and φV2Ns of the reset shift register 15. By giving each register independently, the read operation and the reset operation can be performed independently.
[0055]
On the other hand, the output YA is obtained by taking the logical product of the divided pulses O1N, O2N, O3N, and O4N by the NAND gate 94, and this is used as the other input of the NOR gate 84 through the shift registers 95 and 96 and the inverter 97. This is because the SR flip-flop 86 is returned to the reset state, the enable pulse XFS is extinguished, and the operations of the binary counters 87 to 90 are stopped. As a result, the number of idle feed lines of the vertical scanning circuit 18 is determined in accordance with the number of times the scanning start pulse φSCK is raised.
[0056]
【The invention's effect】
  As explained above, the vertical scanning circuit and the horizontal scanning circuitScanning operationrequired forI.e. required to generate vertical and horizontal scan pulsesA clock generator for generating a clock signal is formed on the same chip as the plurality of photoelectric conversion elements, the vertical scanning circuit, and the horizontal scanning circuit (on-chip). By providing only the scanning start pulse, only three terminals for inputting the clock pulse are required, so that the circuit configuration of an IC or the like for driving the image sensor can be simplified and the imaging system including the drive circuit can be reduced in size. It can contribute to the development.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a vertical scanning circuit.
FIG. 3 is a circuit diagram showing an example of a configuration of a half-bit shift register.
FIG. 4 is a circuit diagram showing an example of a configuration of a unit bit shift register.
FIG. 5 is a timing chart showing driving timing of the vertical scanning circuit.
FIG. 6 is a block diagram illustrating an example of a configuration of a clock generator.
FIG. 7 is a circuit diagram illustrating an example of a configuration of a shift register.
FIG. 8 is a timing chart of each clock of the clock generator.
FIG. 9 is a block diagram illustrating an example of a configuration of a timing generation circuit.
FIG. 10 is a timing chart of input / output of a timing generation circuit.
FIG. 11 is a configuration diagram showing another embodiment of the present invention.
FIG. 12 is a block diagram showing an example of the configuration of a high-speed pre-feed pulse generation circuit.
FIG. 13 is a timing chart of the high-speed pre-feed pulse generation circuit.
FIG. 14 is a circuit diagram showing an example of the configuration of a binary counter.
FIG. 15 is a block diagram showing a conventional example.
[Explanation of symbols]
11 Pixel transistor
12 Vertical selection line
13 Vertical signal line
15 Reset shift register
16 Read shift register
17 Vertical selection line driver
18 Vertical scanning circuit
19 Horizontal scanning circuit
20 Horizontal shift register
25 Horizontal signal line
27 Clock generator
31 Half-bit shift register
32,33 unit bit shift register

Claims (9)

A plurality of photoelectric conversion elements arranged in a matrix;
Has a shift register for resetting for generating a reset pulse for resetting the shift register and the photoelectric conversion elements for reading generates a read pulse for reading a signal generated by the photoelectric conversion element independently, the plurality of photoelectric A vertical scanning circuit for scanning the conversion elements row by row ;
A horizontal scanning circuit for outputting a horizontal scanning pulse for sequentially reading out signals output from the photoelectric conversion elements in a row scanned by the vertical scanning circuit among the plurality of photoelectric conversion elements;
The vertical scanning circuit is formed on the same semiconductor chip as the plurality of photoelectric conversion elements, the vertical scanning circuit, and the horizontal scanning circuit, and receives a vertical scanning clock, a horizontal scanning clock, and a scanning start pulse input from the outside. And a clock generator for generating a clock signal necessary for generating the readout pulse, the reset pulse and the horizontal scanning pulse in the horizontal scanning circuit ,
The scan start pulse for instructing the start of scanning of the vertical scanning circuit includes a read start pulse for starting the operation of the read shift register and a reset start pulse for starting the operation of the reset shift register. A solid-state imaging device. The read shift register and the reset shift register include a first unit circuit that operates in synchronization with a first clock signal that determines the generation timing of the read pulse, and a second unit that determines the generation timing of the reset pulse . A plurality of unit bit shift registers configured in series with a second unit circuit that operates in synchronization with a clock signal are connected in cascade,
One of the read shift register and the reset shift register has a half-bit shift register constituted by the input stage second unit circuit, for the read adapted to the phase to the first clock signal A shift operation is started by inputting the start pulse or the reset start pulse adapted to the phase of the second clock signal to the unit bit shift register in the first stage via the half-bit shift register,
The other of the read shift register and the reset shift register directly applies the reset start pulse suitable for the phase to the second clock signal or the read start pulse suitable for the phase to the first clock signal. the solid-state imaging device according to claim 1, wherein the starting the shift operation by inputting to the unit bit shift register of the first stage. An imaging unit including a plurality of photoelectric conversion elements that are arranged in a matrix and output a photoelectrically converted signal when a vertical scanning pulse is given;
A vertical scanning circuit that scans the plurality of photoelectric conversion elements in units of rows by sequentially outputting the vertical scanning pulses;
A horizontal scanning circuit for outputting a horizontal scanning pulse for sequentially reading out signals output from the photoelectric conversion elements in a row scanned by the vertical scanning circuit among the plurality of photoelectric conversion elements;
The vertical scanning circuit is formed on the same semiconductor chip as the plurality of photoelectric conversion elements, the vertical scanning circuit, and the horizontal scanning circuit, and receives a vertical scanning clock, a horizontal scanning clock, and a scanning start pulse input from the outside. And a clock generator for generating a clock signal necessary for generating the vertical scanning pulse and the horizontal scanning pulse in the horizontal scanning circuit,
The scan start pulse includes a normal scan start pulse generated in a horizontal blanking period and a high-speed scan start pulse generated in a horizontal effective period,
The clock generator generates a clock signal for normal scanning by the vertical scanning circuit when receiving the normal scanning start pulse generated within a horizontal blanking period, and the high-speed scanning start generated within a horizontal effective period When a pulse is received, a clock signal for high-speed scanning by the vertical scanning circuit is generated. The solid-state imaging device according to claim 3 , wherein the clock generator generates a predetermined number of high-speed scanning pulses in response to a single high-speed scanning start pulse. The solid-state imaging device according to claim 3 , wherein the high-speed scanning is completed within a vertical blanking period. The imaging unit can output a video signal from an arbitrary image frame in the effective pixel region, with a part in the effective pixel region as an image frame.
The solid-state imaging device according to claim 3 , wherein the vertical scanning circuit scans a pixel row outside the image frame by the high-speed scanning. The vertical scanning circuit includes a read shift register that generates a read pulse for reading a signal generated by the photoelectric conversion element,
The solid-state imaging device according to claim 3 , wherein a reading operation by the reading pulse is realized by applying a pulse signal to a substrate on which the imaging unit is formed. The vertical scanning circuit includes a reset shift register that generates a reset pulse for resetting the photoelectric conversion element,
The solid-state imaging device according to claim 7 , wherein a reset operation by the reset pulse is realized by applying a pulse signal to the substrate on which the imaging unit is formed. The read shift register starts operation upon receiving a read start pulse included in the scan start pulse,
The solid-state imaging device according to claim 8, wherein the reset shift register starts an operation upon receiving a reset start pulse included in the scan start pulse.

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