JP2676897B2 - Liquid crystal display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device that displays images by arranging liquid crystal display elements in an XY matrix, for example.

[Summary of the Invention]

The present invention relates to a liquid crystal display device, in which a non-interlaced video signal is simultaneously supplied to signals of two horizontal scanning periods for first and second signal lines corresponding to an odd field and an even field of an interlaced video signal. By supplying the converted signals, a non-interlaced video signal can be satisfactorily displayed.

[Conventional technology]

For example, it has been proposed to display a television image using a liquid crystal (see Japanese Patent Application Laid-Open No. 59-220793).

That is, FIG. 6 shows an active matrix type liquid crystal panel, in which (1) is an input terminal to which a video signal of a television is supplied, and a signal from this input terminal (1) is, for example, from an N-channel FET. Line L in the vertical (Y-axis) direction through the switching elements M ₁ , M ₂ ... M _m
It is supplied to ₁ , L ₂ … L _m . Note that m is a number corresponding to the number of pixels in the horizontal (X-axis) direction. Further, an m-stage shift register (2) is provided, and clock signals Φ _1H and Φ _2H of m times the horizontal frequency are supplied to the shift register (2), and a clock signal from each output terminal of the shift register (2) is provided. signal [phi _IH, drive pulses are sequentially scanned by the [phi _2H signal phi _H1,
φ _H2 ... Φ _Hm is supplied to the control terminal of the switching element M ₁ ~M _m. The low potential (V _SS ) and the high potential (V _DD ) are supplied to the shift register (2), and drive pulses of these two potentials are formed.

Also each example N-channel FE each line L ₁ ~L _m
Switching element consisting of T M ₁₁ , M ₂₁ … M _n1 , M ₁₂ , M ₂₂ …
One end of M _n2 , ... M _1m , M _2m, ... M _nm is connected. Note that n is a number corresponding to the number of horizontal scanning lines. This switching element M
The other ends of _{11 to} M _nm are connected to the target terminal (3) through the liquid crystal cells C ₁₁ , C ₁₂ ... C _nm , respectively.

Further, an n-stage shift register (4) is provided, and horizontal frequency clock signals Φ _1V and Φ _2V are supplied to the shift register (4), and clock signals Φ _1V from the respective output terminals of the shift register (4). , the drive pulse signal phi _V1 sequentially scanned by Φ _2V, φ _V2 ... Φ _Vn is the horizontal (X
Through the gate lines G ₁ , G ₂ ... G _{n in the} (axis) direction, each row (M _{11 to} M _1m ) of the switching elements M _{11 to} M _{nm in} the X axis direction, (M ₂₁ to
It is supplied to the control terminals for each M _2m ) ... (M _{n1 to} M _nm ). Note that _VSS and _VDD are also supplied to the shift register (4) in the same manner as the shift register (2).

That is, in this circuit, the shift register (2),
In (4), clock signals Φ _1H and Φ as shown in FIGS.
_2H , Φ _1V and Φ _2V are supplied. And from the shift register (2) phi for each pixel period, as shown in FIG C _H1
~ Φ _Hm is output from the shift register (4).
As shown in, φ _V1 to φ _Vn are output every horizontal period. Further, the input terminal (1) is supplied with a signal as shown in FIG.

When φ _V1 and φ _H1 are output, the switching elements M ₁ and M _{11 to} M _1m are turned on, and the input terminal (1) → M ₁
→ C ₁ → M ₁₁ → L ₁₁ → The current path of the target terminal (3) is formed, and the potential difference between the signal supplied to the input terminal (1) and the target terminal (3) is supplied to the liquid crystal cell C _11. . Therefore, a charge corresponding to the potential difference due to the signal of the first pixel is sampled and _{held in} the capacity of the cell C11. The light transmittance of the liquid crystal is changed according to this charge amount. The same operation is sequentially performed for the cells C _{12 to} C _nm , and at the time when the next field signal is supplied, each cell C ₁₁
The charge amount of ~ C _nm is rewritten.

Thus, the liquid crystal cell C ₁₁ -C _nm light transmittance is changed corresponding to each pixel of the video signal, which displays the television image is repeated sequentially.

Further, in the case of performing display using liquid crystal, an AC drive is generally used in order to extend the reliability and the life. For example, in the display of a television image, a signal obtained by inverting a video signal for each field or frame is supplied to the input terminal (1). In a liquid crystal display device, a signal is inverted every horizontal period in order to prevent shooting in a vertical direction of display.
That is, as shown in FIG. 7E, the input terminal (1) is supplied with a signal inverted every horizontal period and inverted every field or frame.

By the way, in such an apparatus, a television image generally used for display is a so-called interlace scanning type video signal, and an adjacent horizontal scanning line is 1
They are displayed alternately every vertical period. Therefore, the applicant of the present application has previously proposed a device that allows such an interlaced video signal to be displayed well (see Japanese Patent Laid-Open No. 59-158178).

That is, in FIG. 8, the switching elements M _{1 to} M _m , M
Two sets of matrix circuits each consisting of _{11 to} M _nm and liquid crystal cells C _{11 to} C _nm are provided (indicated by letters o and e), and are arranged alternately in the vertical direction for each row line as shown in the figure. To be done. The control terminals of the switching elements M _{1 to} M _m and M _{11 to} M _nm are connected in common to each other and are connected to the shift registers (2) and (4). Further, the signal input terminals of the switching elements M _{1o to} M _mo and M _{1e to} M _me are connected in common, and the input terminals (1o) and (1
e) connected to.

By supplying an odd field signal and a predetermined potential and an even field signal and a predetermined potential to these input terminals (1o) and (1e), respectively, a good interlaced video signal can be displayed. .

[Problems to be solved by the invention]

However, it has been demanded that the above-mentioned device further display a non-interlaced video signal from a computer or the like. However, like the device described above,
Switching element M _11o ~M _nmo, when the control terminal of the M _11e ~M _nme is connected to a common gate line G ₁ ~G _n is for example a signal in the odd-numbered horizontal scanning period of the video signal noninterlaced The signal in the even horizontal scanning period and the input terminal (1
o) and (1e) are selected and supplied, no signal (noise) appears on the liquid crystal cell C _{11o to} C _nmo , C on either one of the scanning lines.
_{11e to} C _nme , and good display cannot be performed. It should be noted that providing the gate lines G _{1 to} G _n independently has many inconveniences in terms of aperture ratio and the like in terms of configuration.

Further, in the above device, the drive of the shift register (2) is sufficiently high even when applied to a non-interlaced video signal.

The present application has been made in view of such points.

[Means for solving the problem]

The present invention relates to an active matrix type liquid crystal panel having first and second signal lines (L _{1o to} L _mo , L _{1e to} L _me ) provided for odd and even fields of an interlaced video signal. And a synchronizing means (line memories (6o) and (6e)) for synchronizing the signals of the non-interlaced video signal in the sequential two horizontal scanning periods, and the signals read from the synchronizing means are the above-mentioned. The liquid crystal display device is characterized in that the liquid crystal display device is supplied to the first and second signal lines.

[Action]

According to this, the synchronized signals of two horizontal scanning periods are sequentially supplied to the first and second signal lines corresponding to the odd field and the even field, respectively, so that the respective signal lines are turned on when the switching element is turned on. Signal is supplied to the non-interlaced video signal, and the non-interlaced video signal can be satisfactorily displayed.

〔Example〕

In FIG. 1, a non-interlaced video signal is supplied to an input terminal (1), and this signal is supplied to line memories (6o) and (6e) via a switch (5) which is switched every horizontal scanning period. It is supplied alternately. Further, to the line memories (6o) and (6e), the write clock signal Φ having a frequency corresponding to each pixel of the non-interlaced video signal is supplied during the period when the signal from the switch (5) is supplied. _W is supplied and half of it is supplied
The read clock signal Φ _R having the frequency of is supplied.

This allows line memories (6o) and (6e) to
As shown in B and C of FIG. 2 with respect to the input signal as shown in FIG. 2A, the signals of the two horizontal scanning periods are sequentially synchronized and the signal whose time axis is doubled is read out. Then, these signals are supplied to the input terminals (1o) and (1e) of the device shown in the above problem. The same applies to the device described above.

Therefore, according to this device, the synchronized signals for two horizontal scanning periods are sequentially supplied to the first and second signal lines corresponding to the odd field and the even field, respectively, so that the signals are respectively supplied when the switching element is turned on. A signal is supplied to the line, and a non-interlaced video signal can be displayed well.

Further, according to this example, since the signals supplied to the input terminals (1o) and (1e) are expanded on the time axis, the shift register (2) is equivalent to a conventional interlaced video signal. A low speed one can be used.

Note that this example can be applied to both a liquid crystal panel on-chip and a line memory for synchronizing signals, or an external device.

On the other hand, FIG. 3 shows an example of a liquid crystal display device which is entirely configured by on-chip. In this figure, the same parts as those of the device shown in the above-mentioned subject are designated by the same reference numerals, and the description thereof will be omitted.

That is, in the figure, non-interlaced video signals are commonly supplied to the input terminals (1o) and (1e).

On the other hand, drive pulse signal φ _H1 from shift register (2)
To [phi] _Hm each switching element _M a1o ~M _amo and M _A1e
~ M _ame through switching elements M _1o ~ M _mo and M _1e ~ M _me
Is supplied to the control terminal of. With the control signal H _o from the terminal (7o) is supplied to the control terminal of the element _M a1o ~M _amo,
Control signal from the terminal (7e) to the control terminal of the element M _A1e ~M _ame
H _e is supplied.

Each buffer amplifier and the output of the element _M a1o ~M _amo is
B _{a1o to} B _amo , switching elements M _{b1o to} M _bmo , buffer amplifiers B _{b1o to} B _bmo are supplied to lines L _{1o to} L _mo , and elements are supplied.
The outputs of M _{a1e to} M _ame are buffer amplifiers B _a1e to
B _ame , Switching element M _b1e ~ M _bme , Buffer amplifier B _b1e
Is the line L _1e ~L _me supplied through ~B _bme. Further elements
The load signal H _x from the terminal (8) is supplied to the control terminals of M _{b1o to} M _bmo and M _{b1e to} M _bme . Other configurations are similar to those of the device shown in the assignment.

In this device, terminals (7o) and (7e) are applied to the drive pulse signals φ _{H1 to} φ _Hm as shown in FIG. 4A.
Inverted every horizontal scanning period of the input signal as shown in Fig B each of the control signal H _o and H _e (except H _o = ▲
▼) is supplied. As a result, the elements M _{a1o to} M _amo and M
Each of _A1e ~M _ame alternately to the drive pulse signal for each horizontal scanning period as shown in Figure C and D is taken out.
On the other hand, a load signal H _x corresponding to every other horizontal blanking period is supplied to the terminal (8) as shown in FIG.

Therefore, in this device, input terminals (1o) and (1e)
When a non-interlaced video signal as shown in FIG. 5A is supplied to the device, as shown in B and C of FIG. 5, the signal in the first horizontal scanning period [1] is transmitted by the elements M _{1o to} M _mo . It is sampled [S1] and held [H1] in the next horizontal scanning period [2], and the signal of this period [2] is applied to the element M.
Sampling [S2] and holding [H2] at _{1e to} M _me . Then, as shown in FIG. 6D, when the load signal H _x in every other horizontal blanking period is supplied, the held [H1] and [H2] signals are transferred to the lines L _{1o to} L _mo and L _1e.
~ Supplied to L _me .

That is, in this apparatus, the signals in the two horizontal scanning periods [1] and [2] are synchronized and supplied to the first and second lines (signal lines).

Thus, according to this device, the first and second signal lines corresponding to the odd field and the even field are sequentially connected to the two lines.
By supplying the synchronized signals during the horizontal scanning period, the signals are supplied to the respective signal lines when the switching elements are turned on, and the non-interlaced video signal can be displayed well. is there.

In the above device, when displaying an interlaced video signal, by supplying an odd field signal and a predetermined potential, and an even field signal and a predetermined potential to the input terminals (1o) and (1e), respectively, The same display as the conventional one can be displayed.

Further, in the above-mentioned device, when applied only to the non-interlaced video signal, the input terminal (1o),
It is not necessary to divide it into (1e), and it is also possible to connect them in common to have only one terminal.

It should be noted that this device is applied to a single liquid crystal display device in which sampling means, a gate circuit, a shift register and the like are integrated on a chip.

〔The invention's effect〕

According to the present invention, the synchronized signals for two horizontal scanning periods are sequentially supplied to the first and second signal lines corresponding to the odd-numbered field and the even-numbered field, respectively. Since the signal is supplied to the line, the non-interlaced video signal can be displayed well.

[Brief description of the drawings]

FIG. 1 is a block diagram of an example of the present invention, FIG. 2 is a diagram for explaining the same, FIG. 3 is a block diagram of another example, and FIGS. 4 and 5 are diagrams for explaining the same. 6 to 8 are views for explaining a conventional device. L is a vertical signal line, G is a gate line, M is a switching element, B is a buffer amplifier, C is a liquid crystal cell, and (1) and (3).
(7o), (7e) and (8) are terminals, (2) and (4) are shift registers, (5) is a switch, and (6o) and (6e) are memories.

Claims (1)

(57) [Claims] 1. An active matrix type liquid crystal panel having first and second signal lines provided for an odd field and an even field of an interlaced video signal, and two horizontal lines of a noninterlaced video signal in sequence. Synchronization means for synchronizing the signals in the scanning period, and the signals read from the synchronization means are the first
And a liquid crystal display device characterized by being supplied to the second signal line.