JP2930318B2 - Liquid crystal display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device that displays images by arranging liquid crystal display elements in an XY matrix, for example.

[Summary of the Invention]

The present invention relates to a liquid crystal display device, which samples a video signal whose polarity is inverted every predetermined period with a pulse signal corresponding to a horizontal pixel and holds the sampled signal. By shifting the potential at the timing of polarity reversal, the dynamic range of the circuit is effectively used, and a good image is displayed with a simple mechanism.

[Conventional technology]

For example, it has been proposed to display a television image using a liquid crystal (see Japanese Patent Application Laid-Open No. 59-220793).

That is, in FIG. 5, (1) is an input terminal to which a video signal of a television is supplied, and a signal from this input terminal (1) is a switching element M ₁ , M _2. Mm are supplied to lines L ₁ , L ₂ ... L _m in the vertical (Y-axis) direction. Note that m is horizontal (X
This is a number corresponding to the number of pixels in the (axis) direction. Further, an m-stage shift register (2) is provided, and clocks Φ _1H and Φ _2H of m times the horizontal frequency are supplied to the shift register (2), and clock signals from each output terminal of the shift register (2) are provided. Drive pulse signals φ _H1 , φ _H2 ... Φ _Hm sequentially scanned by Φ _1H , Φ _2H are switching elements M _{1 to} Mm
Is supplied to each control terminal. Shift register (2)
_Are supplied with a low potential (V _ss ) and a high potential (V _DD ).
A drive pulse of one potential is formed.

Also, for example, an N-channel FET is connected to each of the lines L _{1 to} Lm.
Switching elements M ₁₁ made _{of, M 21 ··· M n1, M} 12, M 22 ·
.. M _n2 ,... M _1m , M _2m .
Note that n is a number corresponding to the number of horizontal scanning lines. The liquid crystal cell C ₁₁ and the other end of the switching element M ₁₁ ~Mnm respectively, C ₂₁
... Connected to the target terminal (3) through Cnm.

Further, an n-stage shift register (4) is provided, and horizontal shift clock signals Φ _1V and Φ _V2 are supplied to the shift register (4). A clock signal Φ _1V from each output terminal of the shift register (4) is provided. , [phi drive pulse signals are sequentially scanned by _{V2 φ V1, φ V2 ··· φ} Vn is horizontal gate lines G ₁ of (X-axis) direction, G ₂ switching elements through ··· Gn M ₁₁ ~Mnm of X each column in the axial direction (M ₁₁ ~Mnm),
(M ₂₁ ~M _2m) are supplied to the control terminal of each ··· (M _n1 ~Mnm). Note that V _ss and V _DD are supplied to the shift register (4) as well as the shift register (2).

That is, in this circuit, the shift register (2),
(4) includes clock signals Φ _1H , Φ 1 as shown in FIGS.
_2H , Φ _1V and Φ _2V are supplied. And from the shift register (2) for each pixel period, as shown in FIG C phi _IH
~ Φ _Hm is output from the shift register (4).
As shown in FIG. 7, φ _V1 to φ _Vn are output every one horizontal period. Further, the input terminal (1) is supplied with a signal as shown in FIG.

When φ _{V1 to} φ _Vn are output, the switching elements M ₁ and M _{11 to} M _1m are turned on, and the input terminal (1) → M ₁
Potential difference is supplied _{→ L 1 → M 11 → C} 11 → the target terminal (3) the signal current path is supplied is formed in the input terminal to the liquid crystal cell C ₁₁ (1) of the target terminal (3) . Thus the capacity of the cell C _11, charge corresponding to the potential difference due to the signal in the first pixel is sampled and held. The light transmittance of the liquid crystal is changed according to the charge amount. It similar to this is successively performed for the cell C ₁₂ ~Cnm, the following additional fields each cell at the time the signal is supplied C ₁₁
The charge amount of ~ Cnm is rewritten.

In this manner, the light transmittance of the liquid crystal cell C ₁₁ ~Cnm is changed corresponding to each pixel of the video signal, which displays the television image is repeated sequentially.

Further, in the case of performing display using liquid crystal, an AC drive is generally used in order to extend the reliability and the life. For example, in the display of a television image, a signal obtained by inverting a video signal for each field or frame is supplied to the input terminal (1). In a liquid crystal display device, a signal is inverted every horizontal period in order to prevent shooting in a vertical direction of display.
That is, the input terminal (1) is supplied with a signal that is inverted every horizontal period and inverted every field or frame as shown in FIG. 6E.

By the way, in such a device, the time width of the drive pulse signals Φ _{1H to} Φ _Hm output from the shift register (2) is For example, in the case of the NTSC system, there is about 100 nsec. On the other hand, for example, when applied to a high-definition television, the time of the horizontal effective screen period is about 1/2, and the number of horizontal pixels is about 3 times.
It is shortened to 6.

Meanwhile the signal which is passed through the switching element M ₁ ~Mm the period of the drive pulse signal phi _IH to [phi] _Hm is fed through a line L ₁ to L m to the switching element M ₁₁ ~Mnm, in this case the line M ¹ ~ the Lm exist wiring capacitance of 10 to number 10 pF, so the signal is a switching element M ₁₁ ~M charges this capacitor
nm.

In this case, the above-described charging requires a signal supply time of 10
If it is about 0 nsec, it can rise to the signal potential, but if this time is shortened to 1/6, charging will not be performed sufficiently when the signal is at a high potential (white or black), and blurring with insufficient contrast etc. There is a possibility that only a display image can be obtained. In the case of high-definition television, the wiring capacity is further increased.

[Problems to be solved by the invention]

On the other hand, the input video signal is supplied with drive pulses φ _{1H to} φ _Hm
Parallelized by sampling each period, by supplying the parallelized signals to the temporary line L ₁ to L m in an arbitrary load period, the line L ₁ as to L m charge is sufficiently performed A way to do that is being considered.

That is, in FIG. 7, the video signal supplied to the input terminal (1) is a CMOS element M _a1 ,
M _{a2 to} M _am , and drive pulse signals φ _{H1 to} φ _Hm and ▼ to ▲ are supplied from the shift register (2) to the control terminals of these elements M _{a1 to} M _am , respectively.

The signals from these elements M _{a1 to} M _am are supplied to the non-inverting inputs of buffer amplifiers B _a1 , B _a2, ... B _am constituting the respective holding means, and these buffer amplifiers B _{a1 to} B _am
Is fed back to the inverting input. Signals from these buffer amplifiers B _a1 .about.B _am is supplied to the CMOS device M _b1, M _b2 ··· M _bm constituting each loading means, these elements
Horizontal blanking pulses (H _BLK and ▲) from the terminal (5) are applied to the control terminals M _{b1 to} M _bm as load pulses, respectively.
▼ is supplied.

Signals from these devices _Mb1 ~M _bm are supplied to the noninverting input of the amplifier B _b1, B _b2 ··· B _bm as a buffer circuit, respectively, the outputs of these buffer amplifiers B _b1 .about.B _bm the inverting input Will be returned. Signals from these buffer amplifiers B _b1 .about.B _bm are supplied to the vertical (Y-axis) direction of the line L ₁ to L m, respectively. Further, the following configuration is the same as the device described in the related art.

Therefore, in this device, for example, when a video signal as shown in FIG. 8A is supplied to the terminal (1), the element _Ma1
To M _am are conducted as shown in FIG. B, and the video signals during this conduction period are sampled and buffer amplifiers B _{a1 to} B _am
Is held by On the other hand, the elements M _{b1 to} M _bm are shown in FIG.
It is conducting a horizontal blanking timing as shown in, respectively held signal buffer amplifier B _b1
BB _bm are supplied (loaded) to the lines L _{1 to} Lm.
Thereafter, an image is displayed in the same manner as in the related art.

By the way, in this device, the buffer amplifiers B _{a1 to} B _am
And B _{b1 to} B _bm are amplifiers having a gain of 1, for example, TFT
Is configured as shown in FIG. In the figure, a differential amplifier composed of NMOS elements N ₁ and N ₂ is provided. A signal is input (Vin) to the gate of one of the elements N _{2 and} the element N ₂
The drains of N ₁ and N ₂ are connected to each other via a current mirror circuit of the PMOS elements P ₁ and P ₂ and are connected to a power supply terminal of _VDD . The drain of the element N ₂ is connected to the gate of the PMOS device P _3, together with the elements P ₃ and a drain connected to the power supply terminal of the V _DD, the source of the element P ₃ is connected to the gate of the NMOS device N _3, the drain of the element N ₃ is connected to the power supply terminal of the V _DD. The source of the element P ₃ is connected to the drain and gate of NMOS device N _4, with the source of the element N ₄ is connected to the drain of the PMOS device P _4, the gate and the source of the element P ₄ is PM
Is connected to the gate of the OS element P _5, the source of the element P ₅ is V
Connected to power supply terminal of _SS . The source and the drain of the element P ₅ of the element N ₃ are connected to each other, this connection point element N ₁
And a signal is output (Vout) from this connection point. Furthermore, the source of the element P ₃ is the NMOS element N ₅
Is connected to the gate, the drain of the element N ₅ is connected to the power supply terminal of the V _DD, the source of element N ₅ is connected to the drain of device N ₂ through the capacitor C. Element
N _{6 to} N ₈ are bias power supply flows, and the current of the constant power supply I flows through the element N ₉ constituting the current mirror circuit.

Therefore, in this circuit, the element N ₁ , N ₂ N ₈ P ₁ P ₂ constitutes the first stage high gain amplifier, the element P ₃ P ₄ N ₄ N ₆ constitutes the next stage amplifier and level shift, and the element The output buffer is composed of N ₃ P ₅ . Incidentally element N ₅ N ₇ and the capacitor C is a phase compensation circuit.

However, in the above-described device, the polarity of the signal supplied to the input terminal (1) is inverted every predetermined period as described above. Therefore, the above-described buffer amplifiers B _{a1 to} B _am , B
In _b1 .about.B _bm, for example a very wide dynamic range for the passage of the whole of the polarity inversion signal, as shown in FIG. 10 is required, is not easy circuit design and formation of the elements.

Generally, in a buffer amplifier, V
_A predetermined cutoff voltage V _A exists on the _SS side, and a saturation voltage V _B exists on the V _DD side.The power supply voltages V _DD , V _SS supplied to the buffer amplifier are added to the dynamic range with these V _A , V _B. Required voltage. For this reason, if the dynamic range is widened, | V _DD −V _SS | becomes extremely large, and a high breakdown voltage is required for each element, which may make circuit design and element formation more difficult.

This application has been made in view of the above points.

[Means for solving the problem]

The present invention relates to a plurality of first signal lines L ₁ , L ₂ ,..., L _m arranged in parallel in the vertical direction and a plurality of second signal lines G arranged in parallel in the horizontal direction. ₁ , G ₂ ... G _n and selection elements M ₁₁ , M _12, ... At respective intersections of the first and second signal lines.
A liquid crystal display device provided with liquid crystal cells C ₁₁ , C _12, ... C _nm provided via M _nm, and an input video signal (input terminal (1)) whose polarity is inverted at a predetermined cycle A plurality of horizontal switch means (CMOS elements Ma ₁ , Ma ₂ ... _Mam ) for supplying the signals to each of the first signal lines; B _a1 , B _a2 ... B _am , B _b1 , B
_b2 ... B _bm and the timing at which the polarity of the input video signal is inverted (φ ₁ , φ
₂ ) means (switches 6 _aD , 6 _bD , 6 _bS , 6 _bS ) for shifting predetermined potentials (V _DD1 , V _DD2 , V _SS1 , V _SS2 ) at the same time. A liquid crystal display device characterized in that each of the means for shifting the potential is constituted by a TFT.

[Action]

According to this, the dynamic range of the circuit can be apparently expanded by shifting the power supply potential of the circuit at the timing of the polarity inversion, and signal processing can be performed by a normal circuit without using a high withstand voltage element or the like. Can be.

〔Example〕

In FIG. 1, the power supply V of the buffer circuits (amplifiers) B _{a1 to} B _am and B _{b1 to} B _bm of the device shown in the above-described problem
_DD and V _SS lines are switches (6a _D ) (6b _S )
And (6b _D ) and (6b _S ). One fixed contact of these switches (6a _D ) (6a _D ) is connected to V _DD1 , the other fixed contact is connected to V _DD2 , and one fixed contact of the switches (6a _S ) (6b _S ) Is connected to V _SS1 and the other fixed contact is connected to V _SS2 . And these switches (6a _D) (6a _S) and (6b _D) (6b _S) is controlled by a control signal phi ₁ and phi ₂ of the terminal (7a) and (7b) respectively.

In this device, a buffer circuit (amplifier) B _{a1 to} B _am , B
_b1 .about.B _bm is intended to be constituted by a TFT as a as shown in FIG. 9 described above. Similarly, the switches (6a _D ) (6a _S ) and (6b _D ) (6b _S ), and other switch means are similarly TF.
It is configured using a switch element of T.

Therefore, in this device, the buffer amplifiers B _{a1 to} B _am , B
_b1 .about.B characteristics of _bm can be a as shown in FIG. 2 for example, by Setsu換Ru control signal phi _1, the phi ₂ in accordance with the polarity of the input signal, better even signal processing in a narrow circuit dynamic range Can be done.

In this way, according to this device, the dynamic range of the circuit can be apparently expanded by shifting the power supply potential of the circuit at the timing of the polarity inversion, and signal processing can be performed by a normal circuit without using a high withstand voltage element or the like. Is what you can do.

Further in the above apparatus, the signal phi ₁ and phi ₂ are formed as shown in Figure 3, for example. That is, with respect to the input video signal and the horizontal blanking pulse (H _BLK ) as shown in FIGS. 7A and 7B, the signals φ ₁ and φ ₂ have their entire phases inverted and the signal φ ₁ has the pulse (H _BLK ) Is switched at the trailing edge, and φ ₂ is switched at the leading edge of the pulse (H _BLK ).

Thus, the signals sampled and held by the switching elements M _{a1 to} M _am are converted into the switching elements M _{b1 to} M _b.
when it is loaded is synchronized to the signal line L ₁ to L m at _bm, the dynamic range of each buffer amplifier B _a1 .about.B _am and B _b1 .about.B _bm can be tailored to the signal supplied.

Incidentally signal supplied to the buffer amplifier B _b1 .about.B _bm, since the period of the pulse (H _LAK) is held, the signal φ
₂ there is no harm to the simple reverse-phase signals phi _1.

Although the above description has assumed that the polarity inverted every one horizontal period of the input video signal, the signal phi ₁ and phi ₂ becomes as shown in FIG. 4 when this was a field by field. That together are switched at the leading edge of the signal phi ₁ and phi ₂ vertical blanking period (V _BLK) In this case, the time signal phi ₁ and phi ₂ of the phase is intended to be in phase.

〔The invention's effect〕

According to the present invention, the dynamic range of the circuit can be apparently expanded by shifting the power supply potential of the circuit at the timing of the polarity inversion, and the signal processing is performed by a normal circuit without using a high withstand voltage element or the like. Now you can do it.

[Brief description of the drawings]

FIG. 1 is a block diagram of an example of the present invention, FIGS. 2 to 4 are diagrams for explaining the same, and FIGS. 5 to 10 are diagrams for explaining a conventional apparatus. L ₁ to L m vertical signal lines, G ₁ ~Gn gate lines, M _a1 ~M _am, M _b1
MM _bm , M ₁₁ MM nm are switching elements, B _a1 BB _am , B _b1 BB
_bm buffer amplifier, C ₁₁ ~Cnm liquid crystal cell, (1)
(3) (5) (7a) (7b) terminal and (2) (4) is a shift _{register, (6a D) (6a s} ) (6b D) (6b S) is a switch.

Claims (1)

(57) [Claims] 1. A plurality of first signal lines arranged in parallel in a vertical direction, a plurality of second signal lines arranged in parallel in a horizontal direction, and the first and second signal lines A liquid crystal display device provided with a liquid crystal cell provided at each intersection via a selection element, wherein the input video signal whose polarity is inverted at a predetermined cycle is supplied to the first video signal.
A plurality of horizontal switch means for supplying to each of the signal lines; a hold means including a buffer amplifier to which a signal from the horizontal switch means is supplied and driven by a predetermined power supply potential; Means for shifting a predetermined potential at a timing at which the polarity of the input video signal is inverted, wherein each of said horizontal switch means, hold means and potential shift means is constituted by a TFT.