JPH05300433A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To switch a scanning mode with simple control and to prevent picture quality from being made different by the scanning mode at the solid-state image pickup device which can switch the scanning mode. CONSTITUTION:This solid-state image pickup device is provided with two-dimensional array-shaped picture elements 1, vertical scanning circuit 5 to scan picture elements in a row direction through vertical selecting lines V1, V2... provided corresponding to the picture elements 1 in the row direction, and horizontal scanning circuit 2 to scan the picture elements 1 in a column direction through horizontal selecting switches 3. The vertical scanning circuit 5 is composed of the plural steps of shift register units, the vertical selecting lines are made corresponding to the respective units by 1-to-1, the input clock of the vertical scanning circuit 5 is divided into two systems A and B, the units at the odd- numbered steps are driven by the clock of the system A, the units at the even- numbered steps are driven by the clock of the system B, and the scanning mode is switched by controlling the clock groups.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device capable of supporting both interlaced scanning and non-interlaced scanning.

[0002]

2. Description of the Related Art A conventional two-row mixed interlaced scanning system (hereinafter simply referred to as interlaced scanning) generally used for standard television systems is applied to an XY address type image sensor, for example. As disclosed in Japanese Patent Publication No. 58-53830, there is known a structure in which an interlace circuit is provided between a vertical scanning circuit and a vertical selection line. FIG. 16 shows a configuration example thereof. The image sensor of this configuration example includes a pixel composed of photoelectric conversion elements arranged in a two-dimensional array, a horizontal scanning circuit for column selection, a horizontal selection switch 3 connected to a horizontal selection line 3, an output signal line 4 , A vertical scanning circuit 5 for row selection, and an interlace circuit 6. The vertical scanning circuit 5 is applied to the pixels in the two columns in the vertical direction.
, And the vertical selection lines V1, V2, V3, ... Which are different in each field are selected by the interlace circuit 6 controlled by the control signals F1 and F2.

By the way, recently, video cameras have been actively used for industrial or measurement purposes. In addition to standard television interlaced scanning, sequential scanning capable of independently selecting each vertical selection line, There is an increasing need for an image sensor that is compatible with so-called non-interlaced scanning.

However, non-interlaced scanning cannot be performed with an image sensor having a structure compatible with the standard television system as shown in FIG. Therefore, there has been proposed a configuration of a vertical scanning circuit capable of supporting two types of scanning modes, interlaced scanning and non-interlaced scanning. For example, Japanese Patent Application Laid-Open No. 63-292773 discloses a structure in which a scanning mode control circuit is provided between a vertical scanning circuit and a vertical selection line. FIG. 17 shows its configuration. Fig. 16
Compared with the configuration shown in FIG. 3, only the configuration of the scanning mode control circuit 7 that connects the vertical scanning circuit 5 and the vertical selection lines V1, V2, V3, ... That is, each of the output terminals of the vertical scanning circuit 5 has three selection MOs.
The gates of the S transistors Q ₁ , Q ₂ , and Q ₃ are connected, and the MOS transistor Q ₁ sets the drive bias B1 to the vertical selection lines V1, V3, V5, ... And the MOS transistor Q ₂ sets the drive bias B2 to the vertical. Select lines V2, V4, V
6, ..., the MOS transistor Q ₃ has a drive bias B
3 are sequentially transferred to the vertical selection lines V1, V3, V5, ...
By applying B2 and B3 in an appropriate combination,
The scanning mode can be controlled. Further, based on the completely same idea, as shown in FIG. 18, using the scanning mode control circuit 8 configured so that the output of the vertical scanning circuit 5 directly drives the vertical selection lines V1, V2, V3 ,. You can also

[0005]

By the way, when a video camera system capable of imaging in two kinds of scanning modes of interlace and non-interlace is constructed by using the image sensor having the construction shown in FIGS. There is a problem that the relationship between the timing of vertical scanning and the timing of horizontal scanning is broken at the time of switching. That is, it is necessary to change the clock frequency for vertical scanning or horizontal scanning when switching the scanning mode. For example, if the clock frequency for horizontal scanning is fixed and the data rate of the output from the image sensor is the same between both scanning modes, that is, if the frame rates are made uniform, the frequency of the clock that drives the vertical scanning circuit during non-interlaced scanning. Must be halved for interlaced scanning. Then, it is necessary to provide a timing control circuit including clock frequency control for that purpose inside or outside the image sensor.

In the image sensor having the structure shown in FIGS. 17 and 18, the number of selection MOS transistors connected to the vertical selection lines V1, V2, V3, ... That is, odd-numbered vertical selection lines V3, V5
V7, ... Two, even vertical selection lines V2, V
One MOS transistor is connected to each of 4, V6, .... Therefore, in this configuration, the parasitic capacitance of the vertical selection line is different for each line, which causes a horizontal stripe-shaped fixed pattern noise. This phenomenon appears differently in interlaced scanning and non-interlaced scanning. During interlaced scanning, two vertical selection lines with different parasitic capacitances are always selected as a pair, so the influence of the difference in parasitic capacitance is mitigated to a large extent, but during non-interlaced scanning, each vertical selection line is independent. Therefore, the influence of the difference in parasitic capacitance will be affected. As a result, there is a difference in image quality between the two scanning modes.

Furthermore, in the image sensor having the configuration shown in FIG. 18, there is a problem that the load of the buffer circuit for driving the vertical selection line included in the vertical scanning circuit 5 varies depending on the scanning mode. In the case of interlaced scanning, there are two vertical selection lines for one bit of the vertical scanning circuit, but in the case of non-interlaced scanning, there is one vertical selection line.
The difference in the load of the buffer circuit causes a difference in the bias applied to the pixel, resulting in a difference in image quality depending on the scanning mode.

The present invention has been made to solve the above-mentioned problems in the conventional solid-state image pickup device capable of switching the scanning mode. The scanning mode can be switched by simple control, and the difference in image quality depending on the scanning mode occurs. An object of the present invention is to provide a solid-state imaging device configured so as not to have it.

[0009]

In order to solve the above problems, the present invention provides a plurality of photoelectric conversion elements arranged in a two-dimensional array and the photoelectric conversion elements arranged in the row direction. A vertical selection line group provided correspondingly, a vertical scanning circuit for scanning the photoelectric conversion elements arranged in the row direction through the vertical selection line group, and the photoelectric conversion elements arranged in the column direction. In a solid-state imaging device having a horizontal selection line group provided correspondingly, and a horizontal scanning circuit for scanning photoelectric conversion elements arranged in a column direction through the horizontal selection line group, a plurality of vertical scanning circuits are provided. The unit units constituting each unit stage of the shift register are made to correspond one-to-one with each vertical selection line of the vertical selection line group, and unit units of odd-numbered stages. First group Connect to click groups are those connecting the unit unit group even-numbered stages to the second clock group, configured to switch between the scan mode by controlling the first and second clock group.

As described above, the clock group input to the vertical scanning circuit is divided into the first and second systems, the odd-numbered shift register units are driven by the first clock group, and the even-numbered shift registers are driven. By driving the unit with the second clock group, interlaced scanning and non-interlaced scanning can be switched by simple control of the clock, and it is not necessary to change the frequency of the drive clock of the shift register when switching the scanning mode. It is possible to realize a solid-state imaging device in which there is no difference in image quality depending on the mode.

[0011]

EXAMPLES Next, examples will be described. FIG. 1 is a diagram showing a schematic configuration of a first embodiment of a solid-state image pickup device according to the present invention, in which members that are the same as or correspond to those of the conventional example shown in FIGS. .. The present invention, as shown in the embodiment of FIG. 1, is compared with the conventional example shown in FIGS.
It is characterized in that there is no scan mode control circuit, one bit of the vertical scanning circuit 5 corresponds to one column of pixels 1 in the vertical direction, and the number of clocks input to the vertical scanning circuit 5 is large. ..

Next, the vertical scanning circuit 5 which is the essence of the present invention
The shift register configuration will be specifically described. First, prior to the description, a configuration column of a shift register used in a conventional vertical scanning circuit will be described with reference to FIG. This configuration example is of a widely known type in which one unit 9 is configured by two stages of clocked inverters, and this is shown in a schematic conceptual diagram as shown in FIG. FIG. 4 shows the operation timing. The clock has two phases of Φ1 and Φ2, and when the start pulse ΦST is applied to the input of the first stage unit 9, the clock Φ1
In synchronization with the output terminals S1, S2, S3 of each unit 9
The output is made more sequentially.

Next, FIG. 5 shows a configuration example of a shift register used in the vertical scanning circuit 5 in the embodiment of the present invention. In this shift register, the two-phase clocks Φ1 and Φ2 are divided into two systems of A and B, and the units 9-1, 9-3, ... of odd-numbered stages are clock groups of the A system (Φ1A, Φ2
Driven by A), while unit 9-
2, 9-4, ... are clock groups of B system (Φ1B, Φ2
It is designed to be driven by B). FIG. 6 shows a schematic conceptual diagram thereof. In FIG. 6, when the two systems of clock groups .PHI.A and .PHI.B are exactly the same, the operation is exactly the same as that of the conventional example shown in FIG.

FIG. 7 shows the operation timing of this embodiment. As can be seen from this timing chart, the clocks Φ1A, Φ1B, Φ having the same two clock groups
By applying 2A and Φ2B, the output terminals S1, S2, ... Of the units 9-1, 9-2, ... Are synchronized with the clocks Φ1A and Φ1B, as in the conventional example shown in FIG.・ More output is performed. The shift register of this embodiment is shown in FIG.
It operates in two different modes, in addition to the operating modes shown in. First, as the first case, in FIG. 5, the clocks Φ1A and Φ2A are fixed at the L level in the logic level of this embodiment, and at the same time, the clocks / Φ1A (negative logic of the clock Φ1A: the same applies hereinafter), / Φ2A (clock Φ).
The negative logic of 2A: the same applies hereinafter) is fixed to the H level, and the clocks Φ1B and Φ2B are the same clocks as the clocks Φ1 and Φ2 of FIG. In that case, odd-numbered unit 9-1,
In 9-3, ..., the two clocked inverters operate as simple inverters regardless of the clock. As a result, the odd-numbered units 9-3, 9-5, ...
Are output to the output terminals S3, S5, ... Of the even-numbered units 9-2, 9-4 ,. .. FIG. 8 shows the operation timing in that operation mode.

As the second case, the operation mode is completely opposite, that is, the clocks Φ1B and Φ2B are fixed at the L level, and the clocks Φ1A and Φ2A are the same clocks as the clocks Φ1 and Φ2 in FIG. Are connected to the output terminals S2, S4 of the units 9-2, 9-4, ...
... and the odd-numbered units 9-1 and 9-3, which are one stage before,
The output terminals S1, S3, ... Of ... Output the same signal. FIG. 9 shows the operation timing in that operation mode. As described above, the shift register of the embodiment shown in FIG. 5 has three kinds of operation modes, including the same operation mode as the conventional shift register shown in FIG.

Next, the relationship between the three types of operation modes of the shift register according to the present invention shown in FIG. 5 and the scanning mode when the shift register is applied to the vertical scanning circuit will be described. First, the interlaced scanning is performed with reference to FIGS.
It can be realized by the combination of the operation modes shown in the timing chart. By switching between these two operation modes for each field, the vertical selection line V
The combination for selecting 1, V2, V3, ... Can be changed.

FIG. 10 shows the operation timing in detail.
In the first field, a clock group of system A (Φ1A, Φ2
With the DC level of A) fixed, each unit of the shift register group indicated by A in the vertical scanning circuit 5 in FIG. 1 operates as a two-stage inverter. As a result, the same pulse is output to the vertical selection lines V2n and V2n + 1 (n ≧ 1), and the combination of vertical selection lines V1, V2 + V3, V4 + V5, ... Is read. The second
In the field, B system clock group (Φ1B, Φ2B)
Of the shift register group shown in B in the vertical scanning circuit 5 in FIG.
Operate as a stage inverter. As a result, the same pulse is output to the vertical selection lines V2n-1 and V2n (n ≧
1), V1 + V2, V3 + V4, ... Vertical combination of the selection lines is read, and the interlaced scanning output signal Sig is obtained. In the figure, FI is a pulse that is inverted every field.

On the other hand, non-interlaced scanning can be realized by the operation timing shown in FIG. FIG. 11 shows the operation timing of this scanning mode. In this scanning mode, since the A system clock group (Φ1A, Φ2A) and the B system clock group (Φ1B, Φ2B) are the same, the vertical selection lines V1, V2, V3, ... Are sequentially selected one by one. , Non-interlaced scan output signal Sig is obtained.

The clock control circuit for switching the three scanning modes described above can be realized by a simple combination of gates. For example, a NAND as shown in FIG.
With a combination of gates, it can be formed on the same substrate as the sensor with almost no increase in area. Figure
In FIG. 12, INT is a signal for controlling the scanning mode. By setting the signal to H level for interlaced scanning and L level for non-interlaced scanning, the scanning mode can be easily switched from the outside.

Further, according to this embodiment, there is no problem that the relationship between the vertical scanning timing and the horizontal scanning timing is broken when the scanning mode is switched. For example, considering the case where the scanning mode is switched from interlaced scanning to non-interlaced scanning, the frequency of the two-phase clock that drives the vertical scanning circuit is changed by doubling the effective number of bits of the shift register. The frame rate is saved automatically, without. In this case, however, the start pulse ΦST is input for each field in the interlaced scan, but it is necessary to thin out the start pulse ΦST because it is in each frame in the non-interlaced scan. However, this thinning control can be performed inside or outside the sensor by an extremely simple method, for example, by ANDing the field inversion pulse FI and the start pulse ΦST. As described above, control of the clock frequency is not required except when it is necessary to change the data rate between the scanning modes.

Further, according to this embodiment, one of the vertical scanning circuits is used.
Since the bit corresponds to one of the vertical selection lines and the parasitic capacitance of each vertical selection line is the same, there is no factor that causes horizontal stripe-shaped fixed pattern noise. Further, there is no problem that the load of the buffer circuit that drives the vertical selection line varies depending on the scanning mode. Therefore, the phenomenon that the image quality differs depending on the scanning mode does not occur.

In this embodiment, the vertical scanning circuit 5 is configured to directly drive the vertical selection lines V1, V2, ..., However, as shown in FIG. 13, the vertical scanning circuit 5 selects. The vertical selection lines V1, V2, ... Can be connected to the gate 11 and driven by the external bias B1.

Furthermore, in this embodiment, one shift register unit is constituted by two stages of clocked inverters, but the shift register unit may have a different constitution.

Further, when the configuration of the vertical scanning circuit in this embodiment is applied to the horizontal scanning circuit, a scanning circuit capable of switching between two-line mixed reading and one-line reading can be realized.

In addition, in the above embodiment, the number of shift registers is two.
Although the one configured to be driven by the clock group of the system is shown, by further increasing the clock group,
It is also possible to perform more complicated scanning.

Next, a second embodiment will be described. Figure 1
In the first embodiment shown in FIG.
When using a non-destructive readable device such as MD,
Further different scanning modes can be realized by changing the pulse width of the start pulse ΦST. in this case,
The clocks .PHI.1A, .PHI.2A, .PHI.1B and .PHI.2B are the same clocks for both A and B systems, as in the case of the non-interlaced scanning shown in FIG. 7 of the first embodiment. FIG. 14 shows an example in which the pulse width of the start pulse ΦST is set to the 2-bit width of the shift register driving clock when such a clock is applied. In this case, since two vertical selection lines are selected, two-row mixed reading is performed, but the shift register operates effectively for all bits.
The signals for the number of vertical selection lines are output while each vertical selection line is accessed twice by one scan.

In this case, since the two-row mixed reading is performed,
Although the resolution is lower than in the case of non-interlaced scanning, the random noise due to the pixels is reduced by mixing the signals of two pixels, and the jumping noise added on the signal transfer path because the signal amount is doubled. Has the effect of reducing the noise, which is advantageous in terms of S / N ratio. Moreover, if the pulse width of the start pulse ΦST is further widened to have an n-bit width,
Reading is performed for all bits of n rows mixed, and a signal with a greater noise reduction effect can be obtained.

Further, the solid-state image pickup device of this embodiment is used to
When the digital video camera with the configuration shown in 15 is configured, an output signal can be obtained at the same frame rate as the non-interlaced scanning, the resolution is the same, and the digital image capture with a higher S / N ratio than the normal non-interlaced scanning is obtained. The device can be realized. The digital image capturing device in FIG. 15 is the solid-state image pickup device 21, the preamplifier 22, the A / D converter 23, the line memory 24 for storing the captured image data, and the arithmetic device for performing the arithmetic processing of the image data in the second embodiment. (ALU) 25, D / A converter 26, process circuit 27 for performing various processes, and encoder 28. Also in this digital image capturing device, the pulse width of the start pulse ΦST will be described as a shift register driving clock of 2 bits.

As described above, the number of data output from the solid-state image pickup device of the second embodiment is almost equal to the total number of pixels, and the time required for one scanning is the same as that of the non-interlaced scanning. .. However, in order to obtain a high S / N ratio, the data is mixed in two rows, and the resolution equivalent to non-interlaced scanning cannot be obtained as it is, but the data mixed in two rows is independent of the data. Can be played. That is, as already shown in FIG. 14, the data on the first vertical selection line V1 is independently read. Since the second data is the sum of the data on the vertical selection lines V1 and V2, the second data and the first data
The data of the vertical selection line V2 can be independently obtained by obtaining the difference from the second data. If this calculation is executed for all data, one row of independent data will be obtained.

In this case, since the data to be calculated is the data read one horizontal scanning period before, in the digital image capturing device shown in FIG. 15, the line memory 24 has two horizontal scanning periods. The capacity is sufficient to store the data and the data after the calculation. Further, by configuring the arithmetic unit 25 so that the arithmetic operation can be performed at high speed, it is possible to obtain a video signal having substantially the same timing as in the case of non-interlaced scanning in almost real time.

The data flow is as follows. That is, the video output from the solid-state imaging device 21 passes through the preamplifier 22 and is A / D converted by the A / D converter 23. If data of Vn + V (n + 1) is stored in the line memory 24 during a certain horizontal scanning period, the next V (n + 1) + V (n
+2) data is fetched into the line memory 24, Vn data and Vn which have already been calculated and stored.
The arithmetic unit 25 performs arithmetic operations between + V (n + 1) data, and the resulting V (n + 1) data is stored in the line memory 24. The data is D in the D / A converter 26.
After the A / A conversion, it is processed by the process circuit 27 and the encoder 28 and output as a video signal.

Even when interlaced scanning is performed in a solid-state image pickup device using pixels that cannot be read nondestructively, it is possible to reproduce data independent of one row from data mixed in two rows. Therefore, a frame memory capable of storing several frames of data is required, and in addition, a complex and large-scale signal processing circuit is required to obtain real-time output.

In the digital image capturing device shown in FIG. 15, the case where the pulse width of the start pulse ΦST is set to the 2-bit width of the shift register drive clock has been described, but the pulse width of the start pulse ΦST is further widened to mix n rows. When reading (n ≧ 3), an image capturing device having a higher S / N ratio can be realized.

[0034]

As described above on the basis of the embodiments,
According to the present invention, there is no need to change the frequency of the drive clock of the shift register at the time of switching the scanning mode, there is no difference in image quality depending on the scanning mode, and solid-state imaging capable of supporting both interlaced scanning and non-interlaced scanning. The device can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of a first embodiment of a solid-state imaging device according to the present invention.

FIG. 2 is a circuit configuration diagram showing a configuration example of a shift register used in a conventional vertical scanning circuit.

FIG. 3 is a conceptual diagram schematically showing the shift register shown in FIG.

FIG. 4 is a diagram showing an operation timing of the shift register shown in FIG.

FIG. 5 is a circuit configuration diagram showing a configuration of a shift register used in the vertical scanning circuit according to the first embodiment of the present invention.

FIG. 6 is a conceptual diagram schematically showing the shift register shown in FIG.

FIG. 7 is a diagram showing an operation timing in a first operation mode of the shift register of the first embodiment.

FIG. 8 is a diagram showing an operation timing in a second operation mode of the shift register of the first embodiment.

FIG. 9 is a diagram showing an operation timing in a third operation mode of the shift register of the first embodiment.

FIG. 10 is a diagram showing an operation timing when interlaced scanning is performed in the first embodiment.

FIG. 11 is a diagram showing an operation timing when performing non-interlaced scanning in the first embodiment.

FIG. 12 is a circuit configuration diagram showing a configuration example of a clock control circuit for switching the scanning mode of the first embodiment.

FIG. 13 is a schematic configuration diagram showing a modified example of the first embodiment.

FIG. 14 is a timing chart for explaining the operation of the second embodiment.

FIG. 15 is a block configuration diagram showing a configuration example of a digital image capturing device using the solid-state imaging device according to the second embodiment.

FIG. 16 is a configuration diagram showing a configuration example of a conventional solid-state imaging device.

FIG. 17 is a configuration diagram showing another configuration example of a conventional solid-state imaging device.

18 is a configuration diagram showing a modified example of the conventional solid-state imaging device shown in FIG.

[Explanation of symbols]

 1 pixel 2 horizontal scanning circuit 3 horizontal selection switch 4 output signal line 5 vertical scanning circuit 9-1, 9-2, ... shift register unit 11 selection gate V1, V2, ... vertical selection line

Claims (1)

[Claims] 1. A plurality of photoelectric conversion elements arranged in a two-dimensional array, a vertical selection line group provided corresponding to the photoelectric conversion elements arranged in a row direction, and the vertical selection line group. A vertical scanning circuit that scans the photoelectric conversion elements arranged in the row direction via a horizontal selection line group provided corresponding to the photoelectric conversion elements arranged in the column direction, and the horizontal selection line group. In the solid-state imaging device having a horizontal scanning circuit that scans photoelectric conversion elements arranged in the column direction via the vertical scanning circuit, the vertical scanning circuit includes a plurality of stages of shift registers. One unit unit is formed for each vertical selection line of the vertical selection line group.
The unit units of the odd-numbered stages are connected to the first clock group, the unit units of the even-numbered stages are connected to the second clock group, and the first and second clock groups are associated with each other. A solid-state imaging device, characterized in that it is configured so that the scanning mode can be switched by controlling the.