JPH0993492A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the solid-state image pickup device capable of high speed read and uniform read by providing a low speed horizontal read section and a high speed horizontal read section and allowing the low speed read section to read different picture element signals with a delay time of one picture element or over at least. SOLUTION: A start pulse ΦHST1 is given to a 1st shift register 3 at a time t1 and a start pulse ΦHST2 is given to a 2nd shift register 4 at a time t2 . Outputs from the shift registers 3, 4 are Φ5-1 ,...Φ5-n and they are sequentially outputted and fed to gates of horizontal selector switches 5-1,..., 5-n and picture element signals of a row selected by a vertical scanning circuit 2 is outputted to horizontal read lines 7-1, 7-2 from a time t3 sequentially. A signal of a timing delayed by one picture element is read to a 2nd horizontal read line 7-2 with respect to the 1st read line. Furthermore, in the high speed read section, the signal from the low speed read section is selected and read, and since the timing of both the sections is equal to each other, no ununiformity of the signal is caused and a regular signal is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device for converting an optical image into an electric signal, such as a television camera, and more particularly to a solid-state image pickup device capable of high-speed read operation.

[0002]

2. Description of the Related Art Conventionally, for high-speed reading of an XY address type solid-state image pickup device, for example, Japanese Patent Laid-Open No. 61-2347.
The reading method disclosed in Japanese Patent No. 5 is known. FIG. 8 shows the configuration of the solid-state imaging device disclosed in this publication, and FIG. 9 shows a timing chart for explaining its operation. This conventional example is a solid-state image sensor arrayed two-dimensionally.
101 and a vertical scanning circuit 102 for selecting pixels in the vertical direction
And a horizontal shift register 103 for selecting pixels in the horizontal direction.
And horizontal selection switches 104-1, 104-2, ... 104-n for sequentially reading out pixels in the horizontal direction, and three horizontal readout lines 106-1, 106-2, 106-3 for readout. The horizontal scanning switches 105-1, 105-2, and 105-3 for converting the generated pixel signals into regular time-series signals. The solid-state image pickup device 101 may be of any type as long as it can use the XY address system. The horizontal selection switches 104-1, 104-2, ... 104-n and the horizontal scanning switches 105-1, 105-2, 105-3 are composed of MOS transistors, and the horizontal selection switches 104-1, 104-2 ,. .... The output of the horizontal shift register 103 is input to the gate of 104-n,
The clock to the gate of the horizontal scanning switches _{105-1,105-2,105-3 (Φ HH1, Φ HH2,} Φ HH3) is adapted to being input.

In this conventional example, the pixel reading section is divided into a low-speed horizontal reading section and a high-speed horizontal reading section. The low-speed horizontal reading section has a horizontal shift register 103 and horizontal selection switches 104-1, 104. -2 ... 104-
The multi-line reading method that is commonly used is used. On the other hand, the high-speed horizontal reading section is composed of horizontal scanning switches 105-1, 105-2, 105-3.

The operation of the solid-state image pickup device configured as described above is performed as follows. After a row is selected by the vertical scanning circuit 102, read pulses Φ _104-1 , ... Φ _104-n are output by the horizontal shift register 103,
The signals for three pixels in the horizontal direction are sequentially read out to the horizontal readout lines 106-1, 106-2, 106-3 via the horizontal selection switches 104-1, 104-2, ... 104-n in sequence. The signals read to the three horizontal read lines 106-1, 106-2, 106-3 are the horizontal scan switches 105-1, 105-2, 105-3.
Is converted into a regular time-series signal and becomes a video signal.
The signal read on the horizontal read line 106-1 is at time t.
_{Between 4} and t ₅ , the signal read on the horizontal read line 106-2 is between time t ₅ and t ₆ , and the signal read on the horizontal read line 106-3 is between t ₆ and t _7. During this period, the corresponding horizontal scanning switches are turned on to be converted into the regular time series signals and become the video signals. That is, after the 3-line reading is first performed in the low-speed horizontal reading unit, the 3-line reading signal is converted into the 1-line time-series signal Sig in the high-speed horizontal reading unit to be a video signal. In FIG. 9, HD is a horizontal synchronizing signal, and Φ _H1 , Φ _H2 , and Φ _HST are basic clocks and start pulses input to the horizontal shift register.

[0005]

By the way, the above-mentioned conventional reading method of the solid-state image pickup device has the following problems. That is, in the reading by the low-speed horizontal reading unit, the reading timing is simultaneous for one group because a plurality of pixel columns are divided into blocks and read at one time, whereas the reading timing by the high-speed horizontal reading unit is 1 pixel. Since it is delayed every minute, the timing of low-speed horizontal scanning and high-speed horizontal scanning differs depending on the pixel,
Even the same pixel signal is taken out as a different output for each horizontal readout line. As shown in FIG. 9, by reading the horizontal selection switch, the horizontal read lines 106-1 and 106-
Although the normal signal level is simultaneously output to 2, 106-3, a horizontal scanning switch 105- which is a high-speed horizontal reading unit.
To turn it on one pixel at a time delay At 1,105-2,105-3 (time _{t 4, t 5, t 6} ), the timing of converting a time series signal of normal different. That is, before the horizontal readout line is fully charged, the horizontal scan switch 105-
1 is turned on, whereas the horizontal scanning switch 105-3 is turned on after being fully charged. Therefore,
Since the timing when the first horizontal scanning switch is turned on is before the pixel signal is completely read out to the horizontal readout line, a time difference occurs in the signal output converted as a time-series signal. That is, there was a problem that it was modulated.

The present invention has been made in order to solve the above problems in the conventional solid-state image pickup device, and an XY address type solid-state image pickup device in which a read signal by low-speed horizontal read is arranged at a predetermined timing by high-speed horizontal read. It is an object of the present invention to obtain a normal video signal corresponding to the output of a pixel, which has no time difference and whose output is not modulated by reading.

[0007]

In order to solve the above problems, the present invention according to claim 1 provides a horizontal shift register and a horizontal shift register for reading out pixel signals of a pixel column arranged in the horizontal direction to a plurality of horizontal readout lines. An XY address system including a low-speed horizontal reading unit including a selection switch, and a high-speed horizontal reading unit including a horizontal scanning switch that arranges pixel signals read on a plurality of horizontal reading lines of the low-speed horizontal reading unit at predetermined timings. In the solid-state image pickup device, the low-speed horizontal read section is configured to read different pixel signals having a delay time of at least one pixel or more on each of the plurality of horizontal read lines,
According to a second aspect of the present invention, in the solid-state image pickup device according to the first aspect, the low-speed horizontal reading unit is at least n.
The number of horizontal shift registers (n: integer of 2 or more) is provided,
The horizontal selection switch is connected to a common horizontal shift register every (n-1).

As described above, when the pixel signal is read by the plurality of horizontal read lines of the low-speed horizontal read unit, the pixel signal is read at a delay time interval of at least one pixel on each horizontal read line. Even when arranged at a predetermined timing in the high-speed horizontal readout unit and converted into a time-series signal, the signal non-uniformity due to the readout scanning does not occur, and further, it is not modulated by the readout and corresponds to the pixel output. A regular video signal can be obtained.

According to a third aspect of the present invention, in the solid-state image pickup device according to the first aspect, the low-speed horizontal reading section is provided with one horizontal shift register and m pixels (m: 1 or more) from the output of the horizontal shift register. Control circuit for generating an output pulse having an arbitrary delay time up to the integer) and controlling the horizontal selection switch.
With this configuration, one horizontal shift register is sufficient, the circuit configuration is simple, the delay time of the output pulse can be freely adjusted, and a pulse suitable for the driving frequency can be easily generated. Is possible.

According to a fourth aspect of the present invention, in the solid-state image pickup device according to any one of the first to third aspects, the gm of a transistor forming a horizontal scanning switch of the high-speed horizontal reading section is set to the low-speed horizontal reading. It is set to be larger than the gm of the transistor that constitutes the horizontal selection switch of this section. With this configuration, the on-resistance of the transistor that forms the horizontal scanning switch of the high-speed horizontal reading unit can be reduced, and a fast switching operation can be performed.

[0011]

Next, an embodiment will be described. FIG. 1 is a circuit configuration diagram showing a first embodiment of a solid-state imaging device according to the present invention, and FIG. 2 shows a timing chart for explaining the operation thereof. The first embodiment corresponds to each invention described in claims 1, 2 and 4, and is configured as follows. That is, the solid-state imaging devices 1 arranged two-dimensionally, the vertical scanning circuit 2 that selects pixels in the vertical direction, the first and second horizontal shift registers 3 and 4 that configure the low-speed horizontal reading unit, and the horizontal selection. The switches 5-1, 5-2, ... 5-n and the horizontal scanning switches 6-1 and 6-2 that form a high-speed horizontal reading unit. The solid-state image sensor 1 may be of any type as long as it can use the XY address system. In this embodiment, two horizontal shift registers are provided, and horizontal selection switches 5-1, 5-2, ... 5-n are alternately connected to the two horizontal shift registers 3 and 4 to perform low-speed horizontal reading. It is designed to be controlled. In other words, the low-speed horizontal reading unit performs 2-line reading.

Horizontal selection switches 5-1, 5-2, ...
5-n is composed of MOS transistors, and the outputs of the horizontal shift registers 3 and 4 are input to their gates.
The horizontal scan switches 6-1 and 6-2 are also composed of MOS transistors. Here, the horizontal scan switch 6
Since -1, 6-2 have a sufficient space, the gm (voltage-current conversion rate) of the MOS transistors forming the horizontal scan switches 6-1, 6-2 is set to the horizontal selection switch 5-.
It is possible to use a MOS transistor which is 10 times or more as large as the MOS transistor constituting 1,5-2, ..., 5-n. Therefore, the on-resistance is 1/10 or less, and the time constant is 1/50.
It becomes 0 or less, and sufficiently fast switching becomes possible.
As an example, the gate length × width (L × W) of the MOS transistor forming the horizontal selection switch is 1 μm × 10 μ.
In contrast to m, the MOS that constitutes the horizontal scanning switch
The gate of the transistor can be 1 μm × 100 μm.

First and second horizontal shift registers 3, 4
The basic clocks (Φ _H1 , Φ _H2 ) are common, and only the timings of the start pulses Φ _HST1 and Φ _HST2 are different. Control signals for the horizontal scanning switches 6-1 and 6-2 (Φ
_HH1 , Φ _HH2 ) are clocks (Φ _HH1 = Φ _H2 , Φ _HH2 =) similar to the basic clocks of the horizontal shift registers 3 and 4.
Φ _H1 ).

Next, the operation of the first embodiment configured as described above will be described. First, at time t ₁ , a start pulse Φ _HST1 is applied to the first horizontal shift register 3
At time t ₂ , the start pulse Φ _HST2 is applied to the second horizontal shift register 4, respectively. The outputs of the shift registers 3 and 4 are Φ _5-1 , Φ _5-2 , ... Φ _5-n ,
The signals are sequentially output and the horizontal selection switches 5-1 and 5 are output.
The pixel signals of the row applied to the gates of −2, ..., 5-n and selected by the vertical scanning circuit 2 are horizontal selection switches 5-1, 5-2, ... 5-n from time t _3. Are sequentially output to the horizontal read lines 7-1 and 7-2. Here, a signal at a timing delayed by one pixel from the first horizontal read line 7-1 is read to the second horizontal read line 7-2.

Then, horizontal read lines 7-1 and 7-
The pixel signal read to 2 is the horizontal scanning switch 6-1 driven at the pixel reading frequency (sample rate),
6-2, the signal is converted into a regular time-series signal. That is, the signal read to the horizontal read line 7-1 is
The signal read by the horizontal scan switch 6-1 controlled by the clock Φ _HH1 between the times t ₄ and t ₅ and the signal read on the horizontal read line 7-2 by the clock Φ _HH2 between the times t ₅ and t _6. Controlled horizontal scan switch 6-
2, the signal is converted into a regular time-series signal, and thereafter, by repeating this, a 1-line type video signal Sig is obtained.

According to such a reading configuration, the high-speed horizontal reading unit sequentially reads and switches the signals of the plurality of horizontal reading lines read by the low-speed horizontal reading unit. Since the start timing and the read start timing by the high-speed horizontal reading unit are the same in every horizontal reading line, that is, the time from turning on the horizontal selection switch to turning on the horizontal scanning switch is the same for all horizontal reading lines. Since the read lines are the same, the signal nonuniformity due to the read scanning does not occur, and the output is not modulated by the read, and a normal video signal corresponding to the output of the pixel can be obtained.

At the same time that the operating frequency of the horizontal shift register becomes 1/2 of the pixel reading frequency (sample rate), the horizontal selection switches 5-1 5-2, ...
-Since the conduction time of 5-n is doubled, it becomes possible to read out sufficient signal charges to the horizontal read line. That is, there is sufficient time for the horizontal read line to be charged, and after the horizontal read line is sufficiently charged, the horizontal scan switch is turned on and the time-series signal is read.
Therefore, as in the prior art, it is possible to solve the problem that the horizontal scanning switch reads out data before the horizontal reading line is fully charged.

As described above, the signals after the high-speed horizontal reading are arranged in a time series similar to the signals read by the one-line type, even though the actual reading method is multi-line reading. No need for delay line.

Next, a second embodiment is shown in FIG. 3, and a timing chart for explaining the operation is shown in FIG. The second embodiment corresponds to each invention described in claims 1, 2 and 4, and is configured as follows. That is, the solid-state imaging devices 1 arranged in a two-dimensional manner, the vertical scanning circuit 2 for selecting pixels in the vertical direction, and the first, second and third horizontal shift registers 11, 12 constituting the low speed horizontal reading section. , 13 and horizontal selection switches 14-1, 14-2,
... 14-n and horizontal scanning switches 15-1, 15-2, 15-3 which constitute a high-speed horizontal reading section. The solid-state imaging device 1 may be of any type as long as it is an XY address system. In this embodiment, three horizontal shift registers are provided, and every two horizontal selection switches are connected to the three horizontal shift registers 11, 12 and 13 to control the low-speed horizontal read. That is, the low-speed horizontal reading unit performs 3-line reading, and the high-speed horizontal reading unit converts it into a 1-line video signal.

Horizontal selection switches 14-1, 14-2, ...
Reference numeral 14-n is a MOS transistor, and the outputs of the horizontal shift registers 11, 12, and 13 are input to their gates. The horizontal scan switches 15-1, 15-2, 15-3 are also M
It is composed of an OS transistor. Here, the horizontal scanning switches 15-1, 15-2, 15-3 are the same as in the first embodiment, and the horizontal selection switches 14-1, 14-2 ,.
The ON resistance can be reduced to 1/10 or less as compared with -n. The first, second and third horizontal shift registers 11, 12,
13 basic clocks (Φ _H1-1 , Φ _H1-2 , Φ _H2-1 , Φ _H2-2 ,
Φ _H3-1 and Φ _H3-2 ) have the same frequency and only differ in phase. In addition, start pulses Φ _HST1 , Φ _HST2 , Φ
The timing of _HST3 is also different. Horizontal scan switch 15
-1,15-2,15-3 control signal (Φ _HH1, Φ _HH2, Φ
_HH3), the basic clock and the same clock of the horizontal shift register _{11,12,13 (Φ HH1 = Φ H3-1,} Φ HH2 =
Φ _H1-1 , Φ _HH3 = Φ _H2-1 ) is used.

Next, the operation of the second embodiment will be described. At times t ₀ , t ₁ and t ₂ , start pulses Φ _HST1 , Φ _HST2 and Φ _HST3 are applied to the first, second and third horizontal shift registers 11, 12 and 13, respectively. The output of each horizontal shift register 11, 12, 13 is Φ _14-1 , Φ _14-2 , Φ
_14-3 , ... Φ _14-n , which are sequentially output and applied to the gates of the horizontal selection switches 14-1, 14-2, ... 14-n, respectively, and selected by the vertical scanning circuit 2. pixel signals of row is returned, the horizontal selection switches from time t ₃ 14-1,14
-2, ... 14-n through horizontal read line 16 in sequence
Output to -1, 16-2, 16-3. Here, the second horizontal read line 16-2 includes the first horizontal read line
A signal with a timing delayed by one pixel with respect to 16-1 and a signal with a timing delayed by two pixels with respect to the first horizontal readout line 16-1 are provided on the third horizontal readout line 16-3. Are read respectively. Subsequently, the pixel signals read to the horizontal read lines 16-1, 16-2 and 16-3 have horizontal scan switches 15-1, 15- from time t _5.
It is converted into a regular time series signal by 2 and 15-3.
That is, from the time t ₅ to t ₆ , the horizontal read line 16
The pixel signal of -1 is the horizontal scanning switch 15-1, the pixel signal is a horizontal scan switch 15-2 at time t ₇ from the time t ₆ the horizontal read line 16-2, from the time t ₇ t
_{In 8} , the pixel signals of the horizontal read line 16-3 are converted by the horizontal scanning switch 15-3 to become the 3-line to 1-line signal Sig.

According to such a reading configuration, the high-speed horizontal reading unit sequentially reads and switches the signals of the plurality of horizontal reading lines read by the low-speed horizontal reading unit. Since the start timing and the read start timing by the high-speed horizontal reading unit are the same in every horizontal reading line, that is, the time from turning on the horizontal selection switch to turning on the horizontal scanning switch is the same for all horizontal reading lines. Since the read lines are the same, the signal nonuniformity due to the read scanning does not occur, and the output is not modulated by the read, and a normal video signal corresponding to the output of the pixel can be obtained.

Further, the capacitance per horizontal read line is about 1/3 of that of the one-line type, and therefore the time constant is also about 1/3. Furthermore, the operating frequency of the horizontal shift register is 1 / the pixel readout frequency (sample rate).
At the same time as 3, the horizontal selection switches 14-1, 14-2,
Since the conduction time of 14-n is also tripled, a margin of about 9 times is produced as compared with the one-wire system. Furthermore, as in the first embodiment, it is possible to solve the problem that the horizontal read line is read before it is completely charged.

As described above, the signals after the high-speed horizontal reading are arranged in a time series equivalent to the signals read by the one-line type, even though the actual reading method is the multi-line reading, Do not need delay line etc.

Next, a third embodiment will be described with reference to FIG. This embodiment corresponds to each of the inventions described in claims 1, 3 and 4, and one shift register is provided in the low-speed horizontal reading unit, and a control circuit for controlling the horizontal selection switch is provided in addition to the shift register. It is the one.
That is, the solid-state imaging devices 1 arranged two-dimensionally, the vertical scanning circuit 2 for selecting pixels in the vertical direction, the horizontal shift register 31, the horizontal selection switches 32-1 and 32-2 that constitute the low-speed horizontal reading unit. , 32-n and a control circuit 33 for controlling the horizontal selection switch, and horizontal scanning switches 34-1, 34-2, 34-3 constituting a high-speed horizontal reading section. The solid-state imaging device 1 may be of any type as long as it is an XY address system. Horizontal selection switch 32-
1, 32-2, ... 32-n are composed of MOS transistors, and the outputs of the horizontal shift register 31 and the control circuit 33 are inputted to their gates. Also, the horizontal scan switch 34
-1, 34-2, 34-3 are also composed of MOS transistors. Here, the horizontal scan switches 34-1, 34-2,
34-3 is a horizontal selection switch as in the first embodiment.
On-resistance is 1 compared to 32-1, 32-2, ... 32-n
It can be less than / 10.

As the control circuit 33 of the horizontal selection switch,
A distributor composed of a C ² MOS shift register is used. An example of the structure of the control circuit 33 is shown in FIG. The distributor constituting the control circuit 33 is configured to generate the drive pulses V _OUT1 and V _OUT2 with a delay time of one pixel, respectively. Although the delay time for one pixel is set here, the pulse can be generated by arbitrarily setting the delay time for up to m pixels. The configuration of the low-speed horizontal reading unit is different from that of the first and second embodiments, but is functionally the same, and after performing 3-line reading in the low-speed horizontal reading unit, 1-line type in the high-speed horizontal reading unit. Are converted to video signals. The basic clock (Φ _H1 ) of the horizontal shift register 31 and the horizontal scan switches 34-1, 34−
2,34-3 control clock _{(Φ HH1, Φ HH2, Φ} HH3)
Have the same frequency but only differ in phase.

The operation of this embodiment will be described with reference to the timing chart of FIG. The start pulse Φ _HST is applied to the horizontal shift register 31 at time t ₀ . The output of the horizontal shift register 31 is input to the control circuit 33, and the horizontal selection switches 32-1, 32-2, ... Are used as pulses for controlling the horizontal selection switches 32-1, 32-2, ... 32-n.・
The pixel signal of the row applied to the gate of 32-n and selected by the vertical scanning circuit 2 is the horizontal selection switch from time t _3.
It is sequentially output to the horizontal read lines 35-1, 35-2, 35-3 via 32-1, 32-2, ... 32-n. Here, a signal at a timing delayed by one pixel from the first horizontal read line 35-1 is supplied to the second horizontal read line 35-2, and a signal whose timing is delayed by one pixel is supplied to the third horizontal read line 35-3. Signals at timings delayed by two pixels are read out from one horizontal read line 35-1. Subsequently, the pixel signals read to the horizontal read lines 35-1, 35-2, 35-3 have horizontal scanning switches 34- from time t _5.
1, 34-2 and 34-3 convert the signals into regular time series signals. That is, the time t by the pixel signal horizontal scanning switches 34-1 horizontal read line 35-1 in t ₆ from _5, the time t ₆ the t ₇ from the pixel signals of the horizontal read line 35-2 is horizontal scan switch 34-2 by, are respectively converted pixel signals of the horizontal read line 35-3 in t ₈ from the time t ₇ is a horizontal scanning switch 34-3, a three-wire and 1-wire signal Sig.

According to such a reading configuration, the high-speed horizontal reading unit sequentially reads and switches the signals of the plurality of horizontal reading lines read by the low-speed horizontal reading unit. Since the start timing and the read start timing by the high-speed horizontal reading unit are the same in every horizontal reading line, that is, the time from turning on the horizontal selection switch to turning on the horizontal scanning switch is the same for all horizontal reading lines. Since the read lines are the same, the signal nonuniformity due to the read scanning does not occur, and the output is not modulated by the read, and a normal video signal corresponding to the output of the pixel can be obtained.

Further, the capacitance per horizontal read line is about 1/3 that of the one-line type, and therefore the time constant is also about 1/3. Furthermore, the operating frequency of the horizontal shift register is 1 / the pixel readout frequency (sample rate).
At the same time as 3, the horizontal selection switches 32-1, 32-2,
Since the conduction time of 32-n is also tripled, a margin of about 9 times is produced as compared with the one-wire system. Furthermore, as in the first embodiment, it is possible to solve the problem that the horizontal read line is read before it is completely charged.

As described above, the signals after the high-speed horizontal reading are arranged in a time series similar to the signals read by the one-line method, even though the actual reading method is multi-line reading, Do not need delay line etc.

Further, since the control pulse of the horizontal selection switch is constituted by the distributor, the horizontal shift register is set to 1
The circuit configuration is simple. Furthermore, the delay time of the output pulse can be freely adjusted, and a pulse suitable for the driving frequency can be generated.

In the first, second and third embodiments described above, multi-line reading of two lines or three lines has been described as the structure and operation of the low speed horizontal reading unit, but it is limited to two lines or three lines reading. However, multi-line reading can be applied without any problem. Generally, in the case of multi-line reading of n lines (n: an integer of 2 or more) in the low-speed horizontal reading unit, the operating frequency of the horizontal shift register is 1 / n, the conduction time of the horizontal selection switch is n times, and the horizontal selection switch is The time from turning on to turning on the horizontal scanning switch is n times. Further, in the third embodiment, the one using the C ² MOS shift register as the control circuit is shown, but the present invention is not limited to this.
Any circuit having the same function can be used without any problem.

[0033]

As described above in detail, according to the present invention, the high-speed read operation of the solid-state image pickup device can be performed reliably and under uniform read conditions, and the output of the device is actually Despite multi-line reading, since it can be taken out as a normal time-series signal as if it were read by a one-line type, there is no need for an external delay line or output correction circuit.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of a solid-state imaging device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the first embodiment shown in FIG.

FIG. 3 is a circuit configuration diagram showing a second embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the second embodiment shown in FIG. 3;

FIG. 5 is a circuit configuration diagram showing a third embodiment of the present invention.

FIG. 6 is a diagram showing a configuration example of a control circuit in the third exemplary embodiment shown in FIG.

FIG. 7 is a timing chart for explaining the operation of the third exemplary embodiment shown in FIG.

FIG. 8 is a circuit configuration diagram showing a configuration example of a conventional solid-state imaging device.

9 is a timing chart for explaining the operation of the conventional example shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Solid-state image sensor 2 Vertical scanning circuit 3 1st horizontal shift register 4 2nd horizontal shift register 5-1, 5-2, ... 5-n Horizontal selection switch 6-1 and 6-2 Horizontal scanning switch 7 -1 First horizontal read line 7-2 Second horizontal read line 11 First horizontal shift register 12 Second horizontal shift register 13 Third horizontal shift register 14-1, 14-2, ... 14 -N horizontal select switch 15-1, 15-2, 15-3 horizontal scan switch 16-1 first horizontal read line 16-2 second horizontal read line 16-3 third horizontal read line 31 horizontal shift register 32-1, 32-2, ... 32-n horizontal selection switch 33 control circuit 34-1, 34-2, 34-3 horizontal scanning switch 35-1 first horizontal readout line 35-2 second horizontal Readout line 35-3 Third horizontal Read line

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shuichi Araki 2-43-2 Hatagaya, Shibuya-ku, Tokyo Inside Olympus Optical Co., Ltd.

Claims (4)

[Claims] 1. A low-speed horizontal reading section including a horizontal shift register and a horizontal selection switch for reading out pixel signals of pixel columns arranged in the horizontal direction to a plurality of horizontal reading lines, and a plurality of horizontal horizontal lines of the low-speed horizontal reading section. An XY having a high-speed horizontal reading section including a horizontal scanning switch for arranging pixel signals read on a reading line at a predetermined timing.
In the address-type solid-state image pickup device, the low-speed horizontal readout unit is configured to read out different pixel signals having a delay time of at least one pixel or more from each of the plurality of horizontal readout lines. Solid-state imaging device. 2. The low-speed horizontal read section includes at least n (n: an integer of 2 or more) horizontal shift registers, and horizontal selection switches are connected to a common horizontal shift register every (n-1). The solid-state imaging device according to claim 1, further comprising: 3. The low-speed horizontal read unit includes one horizontal shift register and m from the output of the horizontal shift register.
The control circuit for controlling the horizontal selection switch by generating an output pulse having an arbitrary delay time up to the number of pixels (m: integer of 1 or more). Imaging device. 4. A gm of a transistor forming a horizontal scanning switch of the high-speed horizontal reading unit is a gm of a transistor forming a horizontal selection switch of the low-speed horizontal reading unit.
It is set to a larger value.
The solid-state imaging device according to any one of 3 above.