JP2573029B2 - Solid-state imaging device - Google Patents

Description

The present invention relates to a solid-state imaging device having a CCD solid-state imaging device.

(B) Conventional technology In an imaging device such as a television camera using a CCD solid-state imaging device, various operation timings of the device are created based on a television synchronization signal, and the solid-state imaging device is pulse-driven in accordance with the timing. The Rukoto. That is, in the solid-state imaging device, image charges are accumulated over the vertical blanking period of the television synchronization signal, and the image charges are transferred and read during the flyback period of the vertical scanning lines. In an ordinary solid-state imaging device, the accumulation period (one field) of image charges is set to, for example, 1/60 second, and a continuous image signal is obtained in field units.

When the brightness of the subject decreases in the above-described imaging device,
The image charge stored in the solid-state imaging device decreases, and the image signal level decreases. For this reason, it has been considered to store image charges over a plurality of fields. For example, if image charge is accumulated over two fields, the image charge accumulation period is 1/30 second, and the imaging sensitivity is doubled. However, when image charges are accumulated over two fields, an image signal can be obtained only every other field, and a flicker occurs on the reproduction screen, so that it is necessary to interpolate the image signal for one field.

FIG. 6 is a configuration diagram for interpolating an image signal on a field basis. In this figure, (1) is a frame transfer type CCD solid-state imaging device including a light receiving section (P), an accumulation section (S), and a horizontal register (H).
S) (2H) is a drive circuit for supplying a drive pulse to each part of the solid-state imaging device (1), (3) is an image signal interpolation circuit,
(4) is a signal processing circuit that performs signal processing such as sample hold, amplification, and gamma correction, and (5) is a drive circuit (2P)
(2S) and (2H) are timing generation circuits that control each timing of the signal processing circuit (4).

The solid-state imaging device (1) is a drive circuit (2P) (2S) (2H)
In the present invention is pulsed, the light receiving unit (P) is the read transfer pulse phi _P supplied from the drive circuit (2P). Also, the storage unit (S) is accumulated transfer pulse phi _S is supplied from the drive circuit (2S), the output transfer pulse phi in the horizontal register (H)
_H is supplied from the drive circuit (2H). The image signal output from the horizontal register (H) is input to the signal processing circuit (4) through the interpolation circuit (3), and is output from the signal processing circuit (4) as a video signal.

The interpolation circuit (3) includes an A / D conversion circuit (31), a D / A conversion circuit (32), a field memory (33), and a coupling circuit (34), and converts the image signal X into an A / D conversion circuit (31). ) Is converted to digital data, and the field memory (3
Stored in 3). Then, read from the field memory (33) after the lapse of a predetermined period of time eg one vertical blanking period, is again converted into an image signal X _D in the D / A conversion circuit (32) in the image signal X and the coupling circuit (34) They are output as an interpolated image signal Y.

FIG. 7 is a timing chart when image charges are accumulated over two fields. Read transfer pulse phi _P is, in the blanking period of the vertical blanking pulse VD, 2 fields (2V period) driving pulses P _1, P ₂ each have a ..., the stored image charge 2V period From the light receiving part (P) to the storage part (S)
Transfer to Storage transfer pulse phi _S is, the drive pulse P _1, P _2,
, And drive pulses S ₁ , S ₂ ,..., And the image charges are stored in the storage section (S). Then, the image charges are transferred to each horizontal blanking period (1H period) to the horizontal register (H), it is sequentially outputted to the outside of the element depending on the output transfer pulse phi _H. The image charge accumulated over the 2V period is 1V
The image signal X output from the horizontal register (H) is output every 1 V period because it is read out during the period. Therefore,
The interpolation circuit (3), depending on the match image signal X, and an image signal X _D obtained which was 1V period delay, 1V
A continuous image signal Y is obtained for each period.

Further, even in the case where the image charge is accumulated for a period of 3 V or more, it is possible to interpolate the period during which the image signal is not output by using the image data for one field stored in the field memory (33). is there.

(C) Problems to be Solved by the Invention However, in the above-described image pickup apparatus, it is necessary to delay the image signal for one field by at least 1 V period in order to interpolate the non-signal portion of the image signal, so that a large scale A delay circuit was required. For example, the device shown in FIG. 6 requires an A / D conversion circuit (31), a D / A conversion circuit (32), a field memory (33), and the like, which increases the circuit scale and increases the cost of the device. Had become.

Therefore, an object of the present invention is to provide a solid-state imaging device capable of improving the sensitivity of an imaging device by interpolating a missing portion of an image signal using a relatively simple circuit.

(D) Means for Solving the Problems The present invention has been made to solve the above-mentioned problems, and a solid-state imaging device that photoelectrically converts a received image to obtain an image signal, and a photoelectric conversion of the solid-state imaging device A drive circuit that transfers and drives the charges and combines the photoelectric conversion charges of a plurality of pixels in the transfer process, an interpolation circuit that interpolates an image signal obtained from the solid-state imaging device in units of a horizontal blanking period,
And interpolating the image signal, in which a signal is present in one horizontal blanking period for each of a plurality of horizontal blanking periods, by combining photoelectric conversion charges of a plurality of pixels so that a signal is present in all horizontal blanking periods. It is characterized by the following.

(E) Operation According to the present invention, the sensitivity of the solid-state imaging device can be improved by synthesizing the photoelectric conversion charges of a plurality of pixels, and the interpolation of the image signal can be performed in units of the horizontal blanking period. In addition, the delay of the image signal can be configured by a 1H delay circuit, and the circuit can be simplified.

(F) Embodiment One embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of a solid-state imaging device according to the present invention. In this figure, (6) is an interpolation circuit provided with a 1H delay element (61), and the same parts as those in FIG. 6 are denoted by the same reference numerals. A feature of the present invention is to combine the image charges of a plurality of pixels in the process of transferring the image charges accumulated in the light receiving section (P).

FIG. 2 is a timing chart when image charges of two pixels are combined and transferred. Read transfer pulse phi _P is, in the blanking period of the vertical blanking pulse VD, the driving pulse P ₁ for each field, P _2, P _3, has a ..., receives the stored image charge to 1V period The data is transferred from the unit (P) to the storage unit (S). Image charges stored in the storage unit (S) is transferred to the horizontal register (H) for each horizontal blanking period (1H period) depending on the storage transfer pulse phi _S. The output transfer pulse φ _H supplied to the horizontal register (H) has driving pulses H ₁ , H ₂ ,... Every 2H period, and is used for the transfer of the transfer from the storage section (S) to the horizontal register (H). The image charge is transferred from the horizontal register (H) to the outside each time. That is, the sensitivity of the solid-state imaging device (1) is doubled by combining image charges of two pixels and outputting an image signal.

At this time, the image signal X obtained from the solid-state imaging device (1) has only a signal of 1H period every 2H period, and it is necessary to interpolate the remaining 1H period. Therefore, this image signal X
Is delayed by a 1H delay element (61) for a 1H period, and the delayed image signal _XD and the image signal X are combined to obtain an image signal Y having a signal every 1H period.

FIG. 3 shows an interpolation circuit used when image charges of two pixels are combined. The interpolation circuit (6) includes a first transistor in which the image signal X is connected to the base (T _1), a second transistor base to the delayed image signal X _D is connected (T ₂₎ and the common It is grounded via a resistor (R), the other collectors are connected to a power supply, and the emitter potential is the output of the image signal Y. Therefore, in the image signal X and the delayed video signal X _D, amplified signal corresponding to the signal towards the high potential for the image signal Y, the noise-free signal period is largely ignored.

In the above description, the case where the image charges of two pixels are combined is exemplified, but it is also possible to combine the image charges of three pixels or four or more pixels. For example 3 the case of synthesizing the pixels of the image charge, the output transfer pulse phi _H is configured to have a drive pulse for each 3H period, Hodokose the interpolation process on the image signal a signal of 1H period are present for each 3H period I just need. The interpolating circuit (6) in this case is obtained by expanding the interpolating circuit of FIG. 3 as shown in FIG. 4, and the 2H delay obtained through two 1H delay elements (61A) and (61B). Image signal
The third transistor (T ₃ ) whose gate is connected to X _2D is arranged in parallel with the first and second transistors (T ₁ ) and (T ₂ ).

Also, as shown in FIG. 5, the image signal X and the delayed image signal
And X _D may be configured to output an interpolated image signal Y are switched at every 1H period depending on the analog switch (SW).
However, in this case, a new switching pulse P for controlling the switching is required, and the number of parts is expected to increase as compared with the configuration shown in FIG.

In this embodiment, a frame transfer type CCD solid-state image sensor is used, and a horizontal register (H) is transferred from the storage section (S).
Although the case where image charges of a plurality of pixels are combined when transferring to the above is exemplified, the CCD solid-state imaging device of the interline transfer method is used, and when transferring from the light receiving element constituting each pixel to the vertical register, or from the vertical register. It is also possible to combine the image charges of a plurality of pixels when transferring to the horizontal register.

(G) Effects of the Invention According to the present invention, the photoelectric conversion charges of a plurality of pixels are combined in the transfer process, and the obtained image signal is interpolated in units of a horizontal blanking period, so that the solid-state imaging device The sensitivity can be easily improved with a relatively simple circuit, and the cost of a high-sensitivity solid-state imaging device can be reduced.

[Brief description of the drawings]

1 to 5 relate to the present invention, FIG. 1 is a configuration diagram, FIG. 2 is an operation timing diagram of FIG. 1, FIG. 3 is a circuit diagram of an interpolation circuit for synthesizing two pixels, FIG. FIG. 4 is a circuit diagram of an interpolation circuit for synthesizing three pixels, and FIG. 5 is a circuit diagram of an interpolation circuit having another configuration. FIG. 6 is a configuration diagram of a conventional solid-state imaging device, and FIG. 7 is an operation timing diagram of FIG. (1) solid-state imaging device, (2P) (2S) (2H) drive circuit, (3) (6) interpolation circuit, (4) signal processing circuit, (5) tamping generation circuit.

Claims (2)

(57) [Claims] 1. A solid-state imaging device for obtaining an image signal by photoelectrically converting a received image, and a driving device for transferring and driving photoelectric conversion charges of the solid-state imaging device and combining photoelectric conversion charges of a plurality of pixels in the transfer process. And a interpolation circuit for interpolating an image signal obtained from the solid-state imaging device in units of a horizontal blanking period. One horizontal blanking period is provided for each of a plurality of horizontal blanking periods by combining photoelectric conversion charges of a plurality of pixels. A solid-state imaging device comprising: interpolating an image signal having a signal during a ranking period so that a signal exists during all horizontal blanking periods. 2. An image signal whose signal is present in one horizontal blanking period every n (n is an integer) horizontal blanking periods is delayed by 1 to n horizontal blanking periods. 2. The solid-state imaging device according to claim 1, further comprising an interpolation circuit that combines the image signal and the image signal to output an interpolation image signal in which the image signal exists during all horizontal blanking periods.