JP3049917B2 - Linear sensor drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a linear sensor drive circuit, and more particularly to a drive circuit for sequentially reading out serially the output signals of a plurality of linear sensors arranged in parallel on the same chip.

[0002]

2. Description of the Related Art A typical one-dimensional linear sensor in which a plurality of one-dimensional linear sensors are arranged in parallel on the same chip typically includes:
3-line color (R, G, B rows) used in digital color copiers and color image scanner reading units
There are linear sensors and the like. Conventionally, a memory is used to serially read the output signals of the plurality of linear sensors. Incorporate line switching means. Each method was adopted.

[0003]

However, in the case of the prior art described above, the memory must be provided inside or outside the device, which is disadvantageous in terms of cost. In the case of (1), a readout pulse input for each line and a line select pulse input for switching the output signal of each line are required. Therefore, when the number of lines (the number of linear sensors) increases, the terminal of the device itself is increased. There is a drawback that the number increases in proportion to that and the external circuit becomes complicated.

Accordingly, an object of the present invention is to provide a linear sensor driving circuit which does not require a memory, can reduce the number of terminals of the device itself, and can simplify an external circuit.

[0005]

In a linear sensor driving circuit according to the present invention, a sensor array arranged one-dimensionally, a gate section for reading signal charges of each sensor in the sensor array, and a gate section for reading signal charges. A transfer section for transferring the output signal charges; and an output section for converting the signal charges transferred by the transfer section into an electric signal. N (n is an integer of 2 or more) arranged in parallel on the same chip ) Linear sensors, a switching circuit for sequentially selecting the output signals of the n linear sensors and serially outputting the signals, and sequentially applying the signals to the gates and the switching circuits of the n linear sensors. a timing circuit for generating n readout pulses and n line select pulses, wherein the timing circuit comprises: Determined by the number ^{n m (2 m-1 <} n ≦ 2
^m ) a first logic circuit for generating the n line select pulses by a logic combination of the timing control pulses, and a logic combination of the n line select pulses and a single basic readout pulse. And a second logic circuit for generating the n readout pulses.

[0006]

In a drive circuit for serially reading output signals of n lines of linear sensors, ^m driving circuits satisfying the condition of 2 ^m-1 <n ≦ 2 ^m are required for n lines of linear sensors. A timing control pulse and a single basic readout pulse are input, and n readout pulses and n line select pulses are internally generated by using a logic circuit. The output signals of the minute linear sensor can be output serially, and the number of terminals can be reduced.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 2 is a block diagram showing one embodiment of the linear sensor drive circuit according to the present invention. In the figure, a sensor array 1 arranged one-dimensionally, a shift gate 2 for reading signal charges of each sensor of the sensor array 1, and a CCD analog shift register for transferring the signal charges read by the shift gate 2 3, the output unit 4 comprising, for example, a floating diffusion amplifier is converted into an electric signal the signal charges transferred by the CCD analog shift register 3, the linear sensor 5 ₁ for one line is formed. Then, the linear sensor 5 _1, on the same chip, n (n is an integer of 2 or more) and has a deployed configuration in the parallel.

[0008] In n lines of linear sensor 5 ₁ to 5 _n, and each shift gate 2 readout pulse Φrog1~Φrogn output from the timing circuit 6 is applied. The CCD analog shift register 3 is driven in two phases by externally supplied transfer clocks ΦH1 and ΦH2. Each output signal of the linear sensor 5 ₁ to 5 _n is supplied to the switching circuit 8 through the buffer 7 ₁ to _7-n. The switching circuit 8 sequentially outputs selected by serially each output signal of the linear sensor 5 ₁ to 5 _n of n lines according to the line select pulse Φs1~Φsn output from the timing circuit 6.

[0009] The timing circuit 6, linear sensor 5 ₁ -
5 _n determined from the number n of ^{m (2 m-1 <n} ≦ 2 m) and number of the timing control pulses V1 ~Vm, readout pulse Φ based on a single base lead-out pulse ΦROG
rog1 to Φrogn and line select pulses Φs1 to Φsn are generated. FIG. 1 shows an example of the circuit configuration. In this example, a case where there are four linear sensors will be described as an example.

When n = 4, two timing control pulses V1 and V2 are sufficient from the condition of 2 ^m-1 <n ≦ 2 ^m . Then, the timing circuit 6 generates four line select pulses .PHI.s1 to .PHI.s4 according to a logical combination of the two timing control pulses V1 to V2.
Logic circuit 11 and four line select pulses Φs1 to
Four readout pulses Φrog1 to 4 readout pulses Φrog1 to Φs4 and a single basic readout pulse ΦROG
And a second logic circuit 12 for generating Φrog4.

Next, the operation in the case of four lines (n = 4) will be described with reference to the timing waveform chart of FIG.
Externally, a basic readout pulse ΦROG and two timing control pulses V1 and V2 synchronized with the basic readout pulse ΦROG are input to the timing circuit 6. The cycle of the timing control pulse V1 is twice as long as the cycle of the timing control pulse V2. These timing control pulses V1, V
2, the line select pulse Φ
s1 to Φs4 are generated and their line select pulses Φs1 to
The second logic circuit 12 generates readout pulses Φrog1 to Φrog4 from Φs4 and the basic readout pulse ΦROG.

At time t ₁ , a readout pulse Φrog1 is generated and applied to the shift gate 2 on the first line, whereby the signal charges accumulated in the sensor array 1 on the first line are converted by the shift gate 2 into a CCD analog signal. The data is read by the shift register 3, converted into an electric signal by the output unit 4, and supplied to the switching circuit 8. In the period from the time t ₁ to the next time t _2, the by-line select pulse Φs1 to the switching circuit 8 is applied, the first line of the signal is output.

Next, the readout pulse Φrog2 generated at time t ₂ is applied to the shift gate 2 on the second line, so that the signal charges accumulated in the sensor array 1 on the second line are changed by the shift gate 2. The signal is read by the CCD analog shift register 3, converted into an electric signal by the output unit 4, and supplied to the switching circuit 8. Time t
Period from ₂ time t _3, by the line select pulse Φs2 to the switching circuit 8 is applied, the second line of the signal is output. Thereafter, at times t ₃ , t ₄ ,.
By repeating the reading operation in the same manner as described above, each signal of the first to fourth lines is serially derived as the output Vout.

[0014] As described above, 4 to line linear sensor 5 ₁ to 5 _4, two of the timing control pulses V1
, V2 and a single basic readout pulse ΦROG
Is input, and the first and second logic circuits 11 and 12 are used to internally generate four readout pulses Φrog1 to Φrog4 and line select pulses Φs1 to Φs4. Four readout pulses Φrog1 to Φrog4 and line select pulses Φs1 to Φ
Where eight input terminals corresponding to s4 are required, three input terminals corresponding to two timing control pulses V1 and V2 and a single basic readout pulse ΦROG can be used, thus reducing the number of terminals. You can do it.

In this example, the case of four lines has been described. However, the present invention is not limited to four lines. However, the relationship between n and m generally needs to satisfy the conditional expression of 2 ^m-1 <n ≦ 2 ^m .

[0016]

As described above, according to the present invention,
In a drive circuit for serially reading each output signal of an n-line linear sensor, ^m timing control pulses satisfying a conditional expression of 2 ^m-1 <n ≦ 2 ^m for an n-line linear sensor Also, a single basic readout pulse is input, and n readout pulses and n line select pulses are internally generated by using a logic circuit. The output signals of the linear sensor can be serially output, and the number of terminals can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a circuit configuration of a timing circuit according to the present invention.

FIG. 2 is a block diagram showing one embodiment of a linear sensor drive circuit according to the present invention.

FIG. 3 is a timing waveform chart for explaining an operation in the case of four lines.

[Explanation of symbols]

1 sensor array 2 shift gate 3 CCD analog shift register 4 output section 5 ₁ to 5 _n linear sensor 6 timing circuit 8 the switching circuit 11 first logic circuit 12 and the second logic circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 1/028

Claims (1)

(57) [Claims] 1. A sensor array arranged one-dimensionally, a gate unit for reading signal charges of each sensor of the sensor array, a transfer unit for transferring signal charges read by the gate unit, and the transfer unit And n (where n is an integer of 2 or more) linear sensors arranged in parallel on the same chip, and an output unit for converting the signal charges transferred by the unit into an electric signal. A switching circuit for sequentially selecting each output signal and serially outputting the output signals; and n readout pulses and n line select pulses sequentially applied to each gate unit and the switching circuit of the n linear sensors. generated and a timing circuit for the timing circuit, said determined from number n of the linear sensor ^{m (2 m-1 <n} ≦ 2 m) pieces of timing control path A first logic circuit that generates the n line select pulses according to a combination of logics of the input and output, and the n readouts by a logic combination of the n line select pulses and a single basic readout pulse. A linear sensor driving circuit, comprising: a second logic circuit that generates a pulse.