JP3172359B2 - Imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an imaging apparatus for converting a video signal taken out of a solid-state imaging device into digital data and outputting the digital data.

[0002]

2. Description of the Related Art In a facsimile or an image scanner, signal processing such as shading correction and gamma correction is performed on a video signal obtained by an image pickup device that reads a document of a subject. In a signal processing circuit that performs such signal processing, there is a tendency to shift from analog signal processing to digital signal processing because the condition setting of each signal processing is easy and signal deterioration is reduced. For this reason, the imaging apparatus is configured to output the video signal as digital data (video data) by performing A / D conversion processing at the output stage in order to support digital signal processing of the video signal.

FIG. 8 is a block diagram of an image pickup apparatus for converting a video signal into digital data and outputting the digital data, and FIG. 9 is a timing chart for explaining the operation. The CCD solid-state imaging device 1 includes a plurality of light-receiving pixels arranged in one row, a shift register that receives and transfers information charges accumulated in each light-receiving pixel, and converts information charges output from the shift registers into voltages and extracts the voltages. It comprises an output section and outputs a video signal Y (t) in response to a drive clock DRV given from the drive circuit 2. The drive circuit 2 generates a drive clock DRV based on a reference clock CLK having a fixed cycle, and supplies the drive clock DRV to the image sensor 1. The drive clock DRV is generally obtained by dividing the reference clock CLK by a predetermined ratio, and includes a read clock φS for transferring information charges from the light receiving pixels to the shift register side, and an information charge of the shift register on the output side. Clock φH for sequentially transferring data to the reset clock φ for discharging information charges accumulated in the output unit
Including R. The A / D conversion circuit 3 samples and holds the video signal Y (t) at a timing set based on the reference clock CLK, and converts the held level into digital data to generate video data YD (n). . Then, the video data YD (n) is supplied to a signal processing circuit that performs signal processing for shading correction and gamma correction.

In the image pickup device 1, information charges taken into the shift register from the light receiving pixels are transferred to the transfer clock φ _H.
Is transferred to the output unit side in response to, and is converted into a voltage value for each bit at the output unit. Thus the video signal is taken out from the image pickup element 1 Y (t) is synchronized with the transfer clock phi _H, to repeat alternately the reset level and the signal level. Actually, a delay occurs from the reset level to the signal level due to the influence of the capacitance of the output unit and the moving speed of the electric charge. For this reason, the sampling and holding timing of the A / D conversion circuit 3 is set to a period during which the signal level of the video signal Y (t) is stable, that is, a period immediately before the information charges are discharged from the output unit of the image sensor 1. Is done.

However, even when the timing of the sample and hold of the A / D conversion circuit 3 is made to coincide with the drive timing of the drive circuit 2, the output of the image pickup device 1 may be delayed, and the video signal Y (t) is not always required. Cannot be sampled and held at a desired timing. Therefore, a delay circuit 4 is provided between the image sensor 1 and the A / D conversion circuit 3 to shift the input timing of the video signal Y (t) to the A / D conversion circuit 3 so that the video signal Y (t) is shifted. t) can be sampled and held at the right timing. That is, A
A delay circuit 4 in which the amount of delay is set so that the video signal Y (t) has a desired timing with respect to the monitor signal SMP at the sample hold point taken out from the / D conversion circuit 3
Is connected between the image sensor 1 and the A / D conversion circuit 3 to optimize the sample-hold timing of the A / D conversion circuit 3.

[0006]

A delay circuit 4 for delaying a video signal Y (t) is for delaying analog information, and has a more accurate delay amount setting than a delay circuit for delaying digital information. Is difficult. In particular, when the frequency of the video signal Y (t) increases, the reliability of the delay circuit 4 cannot be obtained, and the timing of the delay circuit 4 becomes less accurate. When the delay circuit 4 is configured, an amplifier for an analog signal with less distortion is required. Therefore, an increase in the circuit scale is predicted, and the circuit operation becomes more susceptible to a temperature change, and a stable circuit operation is performed. Can not be obtained.

Therefore, the present invention provides an A / D converter for a video signal.
It is an object of the present invention to facilitate timing control of a sample and hold of a conversion circuit and to ensure stable circuit operation.

[0008]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is characterized in that a plurality of light receiving pixels are arranged one-dimensionally or two-dimensionally. And a drive circuit for generating a drive clock based on a reference clock having a fixed period and supplying the drive clock to the solid-state image sensor An analog / digital conversion circuit that samples and holds the output of the solid-state imaging device at a timing synchronized with the drive timing of the drive circuit and generates digital data corresponding to the held level; Control means for controlling a phase difference between the sample and hold timing of the analog / digital conversion circuit and
And that the video signal is sampled and held by the analog / digital conversion circuit at a desired timing.

[0009]

According to the present invention, the timing at which the solid-state imaging device is driven, that is, the timing at which a video signal is output from the solid-state imaging device, and the timing at which the sample / hold of the analog / digital conversion circuit is set to the reference clock. It is set variably in units of one clock period. For this reason, it is possible to accurately control the difference between the timings, and to be less susceptible to noise and temperature changes.

[0010]

FIG. 1 is a block diagram of an imaging apparatus according to the present invention.
FIG. 2 is a timing chart for explaining the operation. CC
In the D solid-state imaging device 11, a plurality of light-receiving pixels are associated with each bit of a shift register in one column, and information charges for each bit of the shift register are output at an output unit provided on the output side of the shift register. Video signal Y
Output as (t). This image sensor 11 is the same as the image sensor 1 shown in FIG. The drive circuit 12 is activated by a start trigger TRG given from the frequency divider circuit 13, generates a drive clock DRV including a read clock φ _S , a transfer clock φ _H and a reset clock φ _R based on the reference clock CLK and performs imaging. Supply to element 11. Here, the read clock φ _S transfers the information charges accumulated in the light receiving pixels to the shift register, and the transfer clock φ _H
Sequentially transfers the information charges transferred to the shift register to the output side, and the reset clock φ _R periodically discharges the information charges stored in the output section. The frequency dividing circuit 13 frequency-divides the reference clock CLK at a predetermined ratio to generate a program signal PR.
A start trigger TRG having a phase designated by G is supplied to the drive circuit 13. In the frequency dividing circuit 13, it is possible to select a type of phase according to the frequency dividing ratio. For example, when dividing the reference clock CLK by four, four types of phases can be selected, and when dividing the frequency by eight, the phase can be selected. Can select eight kinds of phases.
Similarly, the drive clock DRV supplied from the drive circuit 12 to the image sensor 11 also has a phase specified by the program signal PRG corresponding to the start trigger TRG. The A / D conversion circuit 14 samples and holds the video signal Y (t) for each pixel at a timing set based on the reference clock CLK, converts the held level into digital data, and converts the video data YD (n). Is output.

Next, a case where the drive circuit 12 and the A / D conversion circuit 14 are operated at a cycle four times as long as the reference clock CLK will be described. The frequency dividing circuit 13 divides the frequency of the reference clock CLK by 4, and outputs a start trigger TRG having a cycle four times as long as the reference clock CLK. For the activation trigger TRG, four types of phases that are shifted from each other by one clock period of the reference clock CLK can be set, and a phase specified by the program signal PRG is selected from the four types of phases. The drive circuit 12 activated by the activation trigger TRG generates a transfer clock φ _H having a phase corresponding to the activation trigger TRG, that is, a phase specified by the program signal PRG. Video signal Y (t) is made to show alternate between the reset level and the signal level at a timing according to the transfer clock phi _H. On the other hand, the A / D conversion circuit 14 outputs the video signal Y
The timing at which (t) is sampled and held is set to a period four times as long as the reference clock CLK. In addition, the A / D conversion circuit 14 generates various timing pulses required for conversion from an analog value to digital data from the reference clock CLK in addition to the sample and hold pulse of the video signal Y (t). You. Therefore, the monitor signal SMP at the sample hold point indicating the timing at which the A / D conversion circuit 14 actually samples and holds the video signal Y (t).
Is compared with the video signal Y (t). As a result, if the sample-hold timing is shifted, the program signal PR
The phase of the transfer clock φ _H is changed by changing G, and the video signal Y (t) is converted to the A / D converter circuit 14 at the optimum timing.
Sample-hold. For example, assuming that the sample and hold timing of the video signal Y (t) is advanced by about 1/2 cycle with respect to the monitor signal SMP, as shown by a broken line in FIG. By shifting by two clocks, the phase of the transfer clock φ _H is delayed by 180 ° to delay the video signal Y (t) by 周期 cycle. Thus, the program signal PRG
Is changed, it is possible to easily change the sample / hold timing of the A / D conversion circuit 14. Here, since the frequency division ratio of the frequency dividing circuit 13 is set to 1/4, the output timing of the video signal Y (t) is four types. However, if the frequency dividing ratio of the frequency dividing circuit 13 is set further finely, Accurate timing control becomes possible.

FIG. 3 is a block diagram showing the configuration of the frequency dividing circuit 13, and FIG. 4 is a timing chart for explaining the operation thereof. The counter 15 counts the reference clock CLK and supplies the count value to the decoder 16. The decoder 16 supplies a reset signal to the counter 15 every time the count value of the counter 15 reaches a predetermined value,
5 is operated at a predetermined cycle. For example, the reference clock C
When the frequency of LK is divided by 4, the reset signal is supplied to the counter 15 when the count value of the counter 15 has advanced by "4", and the counter 15 is operated in a 4-clock cycle. By the way, the reference clock CLK is 2 ⁿ
In the case of frequency division, the counter 15 can be easily operated at 2 ⁿ clock cycles by making the counter 15 perform a loop operation with an n-bit configuration.
Further, the decoder 16 generates a plurality of timing pulses whose phases are shifted by one clock period while the counter 15 operates at a predetermined cycle, and supplies the timing pulses to the selector 17.
When the counter 15 operates in four clock cycles, it generates four types of timing pulses D1 to D4 as shown in FIG. Then, the selector 17 outputs the program signal P
One of a plurality of timing pulses supplied from the decoder 16 is selected according to the instruction of RG, and the activation trigger TR
Output as G. Therefore, the phase of the activation trigger TRG can be changed in units of one clock period of the reference clock CLK by changing the instruction of the program signal PRG. For example, by changing the program signal PRG so that the timing pulse D4 is selected from the state where the timing pulse D2 is selected, the phase of the activation trigger TRG can be delayed by two clock periods.

In this frequency dividing circuit 13, the selector 17 can be omitted by rewriting the decoding information of the decoder 16 by the program signal PRG. FIG. 5 is a block diagram showing the configuration of the drive circuit 12, and FIG. 6 is a timing chart for explaining the operation.

The counter 18 counts the reference clock CLK after being reset by the start trigger TRG, operates at a cycle corresponding to the start trigger TRG, and supplies the count value to the decoder 19. The decoder 19 generates a timing pulse at a specific timing while the counter 18 operates at a cycle corresponding to the activation trigger TRG, and supplies the timing pulse to the pulse generation unit 20. Also, the decoder 19
Supplies a reset signal to the counter 18 every time the count value of the counter 18 reaches a predetermined value, thereby causing the counter 18 to operate periodically. The reset cycle by the reset signal from the decoder 19 is set to match the reset cycle by the activation trigger TRG. For this reason, even if the activation trigger TRG is not supplied from the frequency dividing circuit 13, the counter 18 operates at a predetermined cycle according to the activation trigger TRG. Then, the pulse generator 20 generates two-phase transfer clocks φH1 and φH2 based on the timing pulse supplied from the decoder 19, and supplies the transfer clocks φH1 and φH2 to the image sensor 11. At the same time, a reset clock φR having the same cycle as the transfer clocks φH1 and φH2 is generated and supplied to the image sensor 11. Therefore, the phase of the drive clock DRV is set corresponding to the start trigger TRG.

FIG. 7 is a block diagram showing another embodiment of the present invention. The CCD solid-state imaging device 21 has a plurality of light-receiving pixels associated with each bit of the shift register, similarly to the imaging device 11 of FIG. 1, and an output unit provided on the output side of the shift register has one bit of the shift register. Each information charge is converted into a voltage value to output a video signal Y (t).
The drive circuit 22 outputs a read clock φ _S , a transfer clock φ _H and a reset clock φ based on the reference clock CLK.
A drive clock DRV including _R is generated and supplied to the image sensor 21. The A / D conversion circuit 23 samples and holds the video signal Y (t) for each pixel at a timing set based on the system clock SYS supplied from the frequency dividing circuit 24, and converts the held level into digital data. To output video data YD (n). The frequency dividing circuit 24 frequency-divides the reference clock CLK at a predetermined ratio and generates a system clock S having a phase designated by the program signal PRG.
YS is generated and supplied to the A / D conversion circuit 23. In this frequency dividing circuit 24, it is possible to select a type of phase according to the frequency dividing ratio. Therefore, the timing of the sample and hold of the A / D conversion circuit 14 is also controlled by the system clock S
As with YS, the phase is set to the phase specified by the program signal PRG.

According to such a configuration, the sample / hold timing of the A / D conversion circuit 23 is controlled by the video signal Y (t).
1, the video signal Y (t) can be taken into the A / D conversion circuit 14 at a desired timing as in the case of FIG.

[0017]

According to the present invention, it is easy to control the phase difference between the video signal output from the image sensor and the timing at which the video signal is sampled and held, and the video signal is sampled and held at an appropriate timing. Can be. Since the analog circuit is not used for controlling the timing of the sample and hold, accurate timing control is possible, and the circuit is less affected by temperature change and noise, so that stable circuit operation can be expected.

Further, the driving circuit and the video signal processing circuit are
In the case of a chip configuration, an external circuit for delaying an analog signal is not required, and the number of components constituting the imaging device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of an imaging apparatus according to the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG. 1;

FIG. 3 is a block diagram showing a configuration of a frequency dividing circuit.

FIG. 4 is a timing chart for explaining the operation of FIG. 3;

FIG. 5 is a block diagram illustrating a configuration of a driving circuit.

FIG. 6 is a timing chart for explaining the operation of FIG. 5;

FIG. 7 is a block diagram showing another embodiment of the imaging apparatus of the present invention.

FIG. 8 is a block diagram illustrating a configuration of a conventional imaging device.

FIG. 9 is a timing chart for explaining the operation of FIG. 8;

[Explanation of symbols]

 1, 11, 21 CCD solid-state imaging device 2, 12, 22 Drive circuit 3, 14, 23 A / D conversion circuit 13, 24 frequency divider 15, 18 Counter 16, 19 Decoder 17 Selector 20 Pulse generator

Claims (2)

(57) [Claims] 1. A solid-state imaging device in which a plurality of light receiving pixels are arranged one-dimensionally or two-dimensionally, information charges generated in each light receiving pixel are transferred and output in response to a driving clock, and a first solid-state imaging device having a fixed period. A frequency dividing circuit that divides the reference clock by a predetermined ratio to generate a second reference clock having a period that is an integral multiple of the first reference clock, and generates a drive clock based on the second reference clock And a drive circuit for supplying the solid-state image sensor with an output and sampling and holding the output of the solid-state image sensor at a timing synchronized with an integral multiple of the first reference clock to generate digital data corresponding to the held level. to an analog / digital converter, by changing the second reference clock phase output from the frequency dividing circuit in one cycle unit of the first reference clock, the upper Imaging apparatus for and control means for controlling the analog / digital converter of the sample hold timing for the driving clock phases, further comprising a said. 2. A solid-state imaging device in which a plurality of light receiving pixels are arranged one-dimensionally or two-dimensionally, information charges generated in each light-receiving pixel are transferred and output in response to a drive clock, and a first image pickup device having a fixed period. A frequency dividing circuit that divides the reference clock by a predetermined ratio to generate a second reference clock having a period that is an integral multiple of the first reference clock; A drive circuit that generates a drive clock having a period that is an integral multiple of the reference clock and supplies the drive clock to the solid-state imaging device; and samples and holds the output of the solid-state imaging device at a timing synchronized with the second reference clock. the analog / digital converter for generating digital data corresponding to the level, the second reference clock phase said first reference clock output from the frequency dividing circuit 1 by changing in cycle units, imaging, characterized in that and a control means for controlling the sample-and-hold timing of the analog / digital converter circuit for the drive clock device.