JP3877349B2 - Solid-state imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
In the present invention, photoelectric conversion elements are arranged in a matrix form as pixels, and vertical and horizontal scanning circuits for reading out signals from the photoelectric conversion elements are provided around the photoelectric conversion element unit to perform two-line mixed read interlace scanning. The present invention relates to an XY address type solid-state imaging device.
[0002]
[Prior art]
In a solid-state imaging device having photoelectric conversion elements arranged in a matrix as pixels and having vertical and horizontal scanning circuits for sequentially reading out signals from the arranged photoelectric conversion elements, two-line mixed readout in interlaced scanning is performed in the A field. In addition, it is necessary to select and read out signals of two horizontal selection lines adjacent to each other in the B field and the B field. As a selective reading circuit configuration, a configuration as shown in FIG. 8 has been proposed. This circuit has a configuration in which selection of a pair of two adjacent horizontal selection lines is simultaneously determined by a field index pulse φFDX input in synchronization with a start pulse φVST input to the shift register in each of the A field and the B field. It has become. In FIG. 8, the vertical scanning circuit is composed of a vertical shift register 100 and an interlace circuit 101, 102 is a photoelectric conversion element which is a pixel, and 101-1 to 101-8 are interlaces composed of MOS transistors constituting the interlace circuit 101. Switch. Reference numeral 103 denotes a horizontal scanning circuit, and 104-1, 104-2,... 104-9 are horizontal selection lines.
[0003]
Next, the operation of the thus configured vertical scanning circuit will be described based on the timing chart shown in FIG. At time t ₁ , φFDX changes from “L” to “H” in synchronization with the start pulse φVST being input to the first stage of the vertical shift register 100. A pair of two horizontal selection lines selected when φFDX is “H” is only the first row, the second and third rows, the fourth and fifth rows, and so on. One vertical scanning period [hereinafter abbreviated as 1 V period. 1V period corresponds to one field (1/60 second)] After elapse, φFDX changes from “H” to “H” in synchronization with the start pulse φVST being input to the first stage of the vertical shift register 100 at t ₂ . L "changes. The pairs of two horizontal selection lines selected when φFDX is “L” are as shown in the first and second rows, the third and fourth rows, the fifth and sixth rows, and so on.
[0004]
[Problems to be solved by the invention]
In the interlace circuit having such a configuration, in the scanning method such as super latitude for reading out signals of two different fields within 1V period previously proposed by the present applicant in Japanese Patent Laid-Open No. 7-38815, the following will be described. Such a problem occurs. In the super latitude scanning method, it is necessary to read out the B field signal after the nH period (nH period is within 1 V period) after the A field signal is read out. That is, in the super latitude scanning method, it is necessary to read out signals corresponding to two different fields of the A field and the B field within a 1V period.
[0005]
In the interlace circuit as shown in FIG. 8, a pair of two horizontal selection lines selected by the field index pulse φFDX inputted in synchronization with the start pulse φVST (once every 1V) inputted to the vertical shift register is simultaneously generated. Therefore, when the B field signal is read after the nH period (nH period is within 1V period) after the A field signal is read, the signal in the same pair as the A field is read. . Therefore, when a signal of the B field (A field) is read after nH period after reading out the signal of the A field (or B field) as in super latitude scanning, the field index pulse φFDX is used simultaneously. In a circuit configured to determine a pair of two adjacent horizontal selection lines, interlaced scanning corresponding to super latitude scanning is impossible.
[0006]
The present invention has been made to solve the above-mentioned problems in the conventional solid-state imaging device. When performing interlaced scanning with two-line mixed readout, two different fields exist simultaneously within a 1V period ( For example, even in super latitude scanning, an object is to provide a solid-state imaging device including a vertical scanning circuit in which a pair of two horizontal selection lines selected in each field is reliably selected.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides a plurality of photoelectric conversion elements arranged in a two-dimensional array, and a horizontal selection line group provided corresponding to the photoelectric conversion elements arranged in a horizontal direction. A vertical scanning circuit that scans the photoelectric conversion elements arranged in the horizontal direction via the horizontal selection line group, and a vertical selection line group provided corresponding to the photoelectric conversion elements arranged in the vertical direction, A horizontal scanning circuit provided corresponding to the vertical selection line group, and performing two-row mixed readout interlace scanning for reading out signals corresponding to two different fields of the A field and the B field within one vertical scanning period. In the solid-state imaging device thus configured, the vertical scanning circuit includes a first shift register for sequentially shifting the readout pulse and a second shift register for sequentially shifting the field index pulse. The output of the first shift register and the output of the second shift register are controlled by the output of the second shift register, and a pair of two adjacent horizontal selection lines selected in the A field and the B field when performing interlaced scanning. It is composed of an interlace circuit for determination.
[0008]
As described above, the vertical scanning circuit includes the second shift register for sequentially shifting the field index pulse in addition to the first shift register for the readout pulse, and is input twice to the vertical scanning circuit within a 1V period. The field index pulse is input to the second shift register in response to the read start pulse to be read, and the field index pulse is sequentially shifted in response to the read pulse being sequentially shifted. Even in the case of interlaced readout in super latitude scanning, for example, which are simultaneously mixed within a period, it is possible to reliably select two adjacent horizontal selection line pairs in correspondence with two different fields.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments will be described. FIG. 1 is a block diagram showing a first embodiment of a solid-state imaging device according to the present invention. In FIG. 1, 1 is a first shift register for shifting a read pulse, 2 is a second shift register for shifting a field index pulse, 3 is an interlace circuit, 4 is a photoelectric conversion element, and 5 is a horizontal scanning circuit. is there. In the present invention, in addition to the read pulse shift register constituting the vertical scanning circuit, a second shift register 2 for newly shifting the field index pulse is provided, and the interlace circuit 3 is controlled to control the interlace circuit 3 within 1 V period. Two different field signals are read out. In FIG. 1, reference numerals 3-1 to 3-8 denote interlace switches constituting the interlace circuit 3.
[0010]
Next, a detailed configuration of the first shift register 1, the second shift register 2 and the interlace circuit 3 constituting the vertical scanning circuit will be described with reference to FIG. The unit unit 10 of the first shift register 1 is composed of, for example, two stages of clocked inverters composed of a PMOS transistor 11 and an NMOS transistor 12 as shown in FIG. The first shift register 1 receives the two-phase clocks φ1, φ2 and the inverted clocks / φ1, / φ2 and the start pulse φVST, and applies the start pulse φVST to the first stage unit as shown in the timing chart of FIG. Then, signals SR1, SR2, SR3,... Synchronized with the falling of the clock φ1 are output to the output terminal of each unit unit 10. In this embodiment, a shift register in which a unit unit is configured by two stages of CMOS type clocked inverters is used. However, any configuration and format may be used as long as the shift register operates as described above.
[0011]
The second shift register 2 has the same configuration as the first shift register 1 and is composed of unit units 2-1, 2-2, 2-3,. Further, the driving clock is also a clock common to the first shift register 1 and φ1, φ2, and / φ1, / φ2. However, the difference is that the field index pulse φFDX is input instead of the start pulse φVST and that the output is taken out from each stage of the inverter of each unit unit in addition to the output of each unit unit. Yes.
[0012]
The outputs of the first and second shift registers 1 and 2 are input to the interlace circuit 3, and each unit circuit of the interlace circuit 3 has two CMOS transfer gate circuits 3A, 3B; 3C, 3D; It consists of The configuration of the first unit circuit will be described. The first transfer gate circuit 3A is composed of an NMOS transistor 3A-1 and a PMOS transistor 3A-2, and the input is a unit output SR1- of the corresponding first shift register 1. 1 is input, and outputs SR2-1 and SR2-2 for each stage of the inverter of the corresponding unit unit 2-1 of the second shift register 2 are input to the gates of the NMOS transistor 3A-1 and the PMOS transistor 3A-2. Each is entered. The unit output SR1-2 after one unit from the unit unit of the corresponding first shift register 1 is input to the input of the second transfer gate circuit 3B, and the gates of the NMOS transistor 3B-1 and the PMOS transistor 3B-2 are input. Are applied with outputs SR2-2 and SR2-1 for each stage of the inverter of the corresponding unit unit 2-2 of the second shift register 2, respectively. The outputs of the first and second transfer gate circuits 3A and 3B are connected in common and connected to the second horizontal selection line G2. On the other hand, the output SR1-1 of the first unit unit of the first shift register 1 is connected to the first horizontal selection line G1. Each unit of the first and second shift registers 1 and 2 and the interlace circuit 3 constituting the vertical scanning circuit is configured as described above, and each subsequent unit has this repeated configuration.
[0013]
Next, the operation of the first embodiment configured as described above will be described with reference to the timing chart shown in FIG. First, the reading of the A field signal will be described. At time t ₁ , the start pulse φVST is input to the first stage unit of the first shift register 1. At this time, the field index pulse φFDX is assumed to be “H”. Between times t _{2 and} t ₃ , the output SR1-1 of the first shift register 1 is “H”, SR1-2 is “L”, and the output SR2-1 of the second shift register 2 is “L”, SR2. -2 is “H”. Therefore, although the transfer gate circuit 3A of the interlace circuit 3 is “OFF” and 3B is “ON”, the output SR1-2 of the first shift register 1 that is the input is “L”. The second horizontal selection line G2 to which the output of the first unit is connected is “L”. Therefore, only the horizontal selection line G1 corresponding to the output SR1-1 of the first shift register 1 becomes “H” during the period of time t _{2 to} t ₃ .
[0014]
Subsequently, between times t _{3 and} t ₄ , the output SR1-2 of the first shift register 1 is “H”, the SR1-3 is “L”, and the output SR2-1 of the second shift register 2 is “L”. SR2-2 is “H”, SR2-3 is “L”, and SR2-4 is “H”. Therefore, the transfer gate circuit 3A is “OFF”, but 3B is “ON”, and the output SR1-2 of the first shift register 1 as the input is “H”, so that the first unit of the interlace circuit 3 is turned on. The second horizontal selection line G2 to which the outputs are connected is “H”. On the other hand, although the transfer gate circuit 3C is “OFF” and 3D is “ON”, the output SR1-3 of the first shift register 1 that is the input is “L”, so the second unit of the interlace circuit 3 The fourth horizontal selection line G4 to which the outputs are connected is “L”. Therefore, in the period from time t _{3 to} time t ₄ , the horizontal line corresponding to the second horizontal selection line G2 to which the output of the first unit of the interlace circuit 3 is connected and the output SR1-2 of the first shift register 1 is connected. The selection line G3 becomes “H” and is selected. Similarly, in the A field, only G1 is selected first, then two horizontal selection lines are simultaneously selected, such as G2, G3, G4, G5, G6, G7,. Are sequentially read out.
[0015]
Next, a signal corresponding to the B field is read. At time t ₅ , a start pulse φVST is input to the first shift register 1. Before that, it is assumed that the field index pulse φFDX is changed from “H” to “L”. In other words, field switching is performed within a 1V period, which is the A field readout period. In between times t ₆ ~t _7, first shift register 1 outputs SR1-1 is "H", SR1-2 is "L", the second shift register 2 outputs SR2-1 is "H", SR2- 2 is “L”. As a result, the transfer gate circuit 3A is “ON” and 3B is “OFF”, so that the second horizontal selection line G2 to which the output of the first unit of the interlace circuit 3 is connected is “H”. Therefore, during the period from time t _{6 to} t ₇ , the second horizontal line in which the horizontal selection line G1 corresponding to the output SR1-1 of the first shift register 1 and the output of the first unit of the interlace circuit 3 are connected. The selection line G2 becomes “H” and is selected.
[0016]
Subsequently, between times t ₇ and t ₈ , the output SR1-2 of the first shift register 1 is “H”, the SR1-3 is “L”, and the output SR2-1 of the second shift register 2 is “H”. SR2-2 is “L”, SR2-3 is “H”, and SR2-4 is “L”. Therefore, the transfer gate circuit 3C is turned “ON”, but 3D is turned “OFF”, and the output SR1-2 of the first shift register 1 as the input is “H”, so that the second unit of the interlace circuit 3 is turned on. The fourth horizontal selection line G4 to which the outputs are connected is “H”. Therefore, in the period from time t _{7 to} time t ₈ , the fourth horizontal line in which the horizontal selection line G3 corresponding to the output SR1-2 of the first shift register 1 and the output of the second unit of the interlace circuit 3 are connected. The selection line G4 becomes “H” and is selected. In the same manner, in the B field, G1 and G2, G3 and G4, G5 and G6, and so on are selected in pairs, each in a different pair from the A field. More read scanning of the B field, and ends at time t ₉ is in the normal 1V period, followed by readout scanning of the signal corresponding to the A field in the new next 1V period begins.
[0017]
As described above, in the first embodiment, even when two fields are mixed within a 1V period as in super latitude scanning, interlace scanning corresponding to each field of the A field and the B field is performed. Therefore, it is possible to reliably select a pair of two horizontal selection lines adjacent to each other, and it is possible to perform interlaced scanning for two-line mixed readout.
[0018]
In the first embodiment, the case of super latitude scanning has been described. However, even in normal interlace scanning (when one field is read in 1V period), n times (n is 3 or more) in 1V period. It is clear that the present embodiment can be applied even when interlace scanning is performed.
[0019]
Next, a second embodiment will be described. FIG. 6 is a circuit configuration diagram showing a vertical scanning circuit portion in the second embodiment. Components identical or corresponding to those in the first embodiment shown in FIG. ing. The first shift register 1 and the interlace circuit 3 in this embodiment have the same configuration as that of the first embodiment shown in FIG. 2, and the second shift register 2 for shifting the field index pulse φFDX is The transfer gate circuit configuration is different from the first embodiment. That is, the second shift register 2 has a transfer gate circuit configuration, and its unit units 2-1, 2-2,... Have a CMOS transfer gate circuit composed of an NMOS transistor 21 and a PMOS transistor 22 and two inverter circuits. It is made up of. The first unit 2-1 will be described. The output SR1-0 one stage before the corresponding unit unit of the first shift register 1 is input to the gate of the NMOS transistor 21 constituting the CMOS transfer gate circuit, and the PMOS Similarly, the output SR1-0 of the first shift register 1 is inverted and input to the gate of the transistor 22 via the inverter circuit 23. The output of the CMOS transfer gate circuit is connected to the next unit unit 2-2 via two inverter circuits. As in the first embodiment, the output is extracted from each stage of each inverter circuit.
[0020]
Next, the operation of the second embodiment configured as described above will be described with reference to the timing chart shown in FIG. First, a case where the A field signal is read first will be described. At time t ₁ , a start pulse φVST is input to the first stage unit of the first shift register 1, and the field index pulse φFDX changes from “L” to “H” in synchronization with the start pulse φVST. Between times t _{2 and} t ₃ , the output SR1-1 of the first shift register 1 is “H”, SR1-2 is “L”, the output SR2-1 of the second shift register 2 is “L”, SR2- 2 is “H”. Therefore, although the transfer gate circuit 3A of the interlace circuit 3 is “OFF” and 3B is “ON”, the output SR1-2 of the first shift register 1 that is the input is “L”. The second horizontal selection line G2 to which the output of the first unit is connected is “L”. Therefore, during the period from time t _{2 to} time t ₃ , only the horizontal selection line G 1 corresponding to the output SR 1-1 of the first shift register 1 becomes “H” and is selected.
[0021]
Subsequently, between times t _{3 and} t ₄ , the output SR1-2 of the first shift register 1 is “H”, the SR1-3 is “L”, and the output SR2-1 of the second shift register 2 is “L”. SR2-2 is “H”, SR2-3 is “L”, and SR2-4 is “H”. Therefore, the transfer gate circuit 3A is “OFF”, but 3B is “ON”, and the output SR1-2 of the first shift register 1 as the input is “H”, so that the first unit of the interlace circuit 3 is turned on. The second horizontal selection line G2 to which the outputs are connected is “H”. On the other hand, although the transfer gate circuit 3C is “OFF” and 3D is “ON”, the output SR1-3 of the first shift register 1 that is the input is “L”, so the second unit of the interlace circuit 3 The fourth horizontal selection line G4 to which the outputs are connected is “L”. Therefore, in the period from time t _{3 to} time t ₄ , the horizontal line corresponding to the second horizontal selection line G2 to which the output of the first unit of the interlace circuit 3 is connected and the output SR1-2 of the first shift register 1 is connected. The selection line G3 becomes “H” and is selected. Similarly, in the A field, only G1 is first selected, and then two horizontal selection lines are simultaneously selected, such as G2, G3, G4, G5, G6, G7,.
[0022]
Next, the B field signal is read out. At time t ₅ , the field index pulse φFDX is changed from “H” to “L” in synchronization with the input of the start pulse φVST to the first shift register 1. That is, the field is switched within the 1V period, which is the normal A field readout period. In between times t ₆ ~t _7, first shift register 1 outputs SR1-1 is "H", SR1-2 is "L", the second shift register 2 outputs SR2-1 is "H", SR2- 2 is “L”. As a result, the transfer gate circuit 3A is “ON” and 3B is “OFF”, so that the second horizontal selection line G2 to which the output of the first unit of the interlace circuit 3 is connected is “H”. Therefore, during the period from time t _{6 to} t ₇ , the second horizontal line in which the horizontal selection line G1 corresponding to the output SR1-1 of the first shift register 1 and the output of the first unit of the interlace circuit 3 are connected. The selection line G2 becomes “H” and is selected.
[0023]
Subsequently, between times t ₇ and t ₈ , the output SR1-2 of the first shift register 1 is “H”, the SR1-3 is “L”, and the output SR2-1 of the second shift register 2 is “H”. SR2-2 is “L”, SR2-3 is “H”, and SR2-4 is “L”. Therefore, the transfer gate circuit 3C is “ON”, 3D is “OFF”, and the output SR1-2 of the first shift register 1 that is the input is “H”, so that the output of the second unit of the interlace circuit 3 is The connected fourth horizontal selection line G4 is “H”. Therefore, in the period from time t _{7 to} time t ₈ , the fourth horizontal line in which the horizontal selection line G3 corresponding to the output SR1-2 of the first shift register 1 and the output of the second unit of the interlace circuit 3 are connected. The selection line G4 simultaneously becomes “H” and is selected. Similarly, in the B field, G1 and G2, G3 and G4, G5 and G6,... More read scanning of the B field, and ends at time t ₉ is in the normal 1V period, followed by readout scanning of the signal corresponding to the A field in the new next 1V period begins.
[0024]
In the second embodiment, since the configuration of the second shift register 2 is a transfer gate type shift register, the clocked inverter of the second shift register 2 used in the first embodiment is driven. This eliminates the need for a driving clock. In the second embodiment, the output of one stage before the corresponding unit stage of the first shift register is input to the gates of the NMOS transistor and the PMOS transistor constituting the transfer gate circuit used for the second shift register. However, it is clear that the output of the unit stage of the first shift register n stages before can be used as an input.
[0025]
Further, in the second embodiment, the case of super latitude scanning has been described. However, in normal interlace scanning (in the case of reading one field in 1V period), n times (n is 3 in the 1V period). It is clear that the present embodiment can be applied to the case where the above-described interlaced scanning is performed.
[0026]
【The invention's effect】
As described above based on the embodiments, according to the present invention, the vertical scanning circuit includes a shift register for shifting the field index pulse in addition to the shift register for shifting the readout pulse. Therefore, even in the case of reading out signals of two different fields within a 1V period as in super latitude scanning, interlaced scanning with two-line mixed readout is possible.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of a solid-state imaging device according to the present invention.
FIG. 2 is a circuit configuration diagram showing a configuration of a vertical scanning circuit portion in the first embodiment shown in FIG. 1;
3 is a circuit configuration diagram showing a configuration of a first shift register of the vertical scanning circuit shown in FIG. 2; FIG.
4 is a timing chart for explaining the operation of the first shift register shown in FIG. 3;
FIG. 5 is a timing chart for explaining the operation of the vertical scanning circuit shown in FIG. 2;
FIG. 6 is a circuit configuration diagram showing a vertical scanning circuit portion in a second embodiment.
7 is a timing chart for explaining the operation of the second exemplary embodiment shown in FIG. 6;
FIG. 8 is a block diagram illustrating a configuration example of a conventional solid-state imaging device of a two-row mixed readout interlace scanning method.
9 is a timing chart for explaining the operation of the conventional example shown in FIG. 8;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 1st shift register 2 2nd shift register 3 Interlace circuit 4 Photoelectric conversion element 5 Horizontal scanning circuit 2-1, 2-2, ... Unit unit 3-1, 3-2, ... of 2nd shift register Interlace switches 3A, 3B, ... Transfer gate circuits 3A-1, 3B-1, ... NMOS transistors 3A-2, 3B-2, ... PMOS transistors
10 Unit unit of the first shift register
11 PMOS transistor
12 NMOS transistor
21 NMOS transistor
22 PMOS transistor
23 Inverter circuit

Claims (3)

A plurality of photoelectric conversion elements arranged in a two-dimensional array, a horizontal selection line group provided corresponding to the photoelectric conversion elements arranged in the horizontal direction, and horizontally through the horizontal selection line group A vertical scanning circuit for scanning the arranged photoelectric conversion elements; a vertical selection line group provided corresponding to the photoelectric conversion elements arranged in a vertical direction; and a vertical selection line group provided corresponding to the vertical selection line group In the solid-state imaging device, wherein the vertical scanning circuit includes a horizontal scanning circuit, and performs two-row mixed readout interlace scanning for reading out signals corresponding to two different fields of the A field and the B field within one vertical scanning period. Includes a first shift register for sequentially shifting read pulses, a second shift register for sequentially shifting field index pulses, and the first shift register. And an interlace circuit for determining a pair of two adjacent horizontal selection lines selected in the A field and B field when interlace scanning is performed by controlling the output of the second shift register. A solid-state imaging device characterized by being configured. The solid-state imaging device according to claim 1, wherein the second shift register has a clocked inverter configuration. The solid-state imaging device according to claim 1, wherein the second shift register has a transfer gate type shift register configuration.

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