JPH05308575A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To operate the internal circuit of a solid-state image pickup element such as an output gate and a reset gate, etc., and the external circuit of a sample-and-hold circuit, etc., at slow speed. CONSTITUTION:A horizontal shift register 22 is equipped with main transfer areas phiH1, phiH2 and auxiliary transfer areas phiH1', phiH2' which transfer the electric charge of a picture element on a horizontal line, independently, and plural output gates 26, 28, floating diffusions 34, 36, and reset gates 38, 40, etc., are formed on the terminal parts of the areas successively in parallel. The horizontal shift register 22 is driven by a transfer pulse with frequency doubling that of a conventional element, and the frequencies of the output gates 26, 28 are 1/2 of the transfer pulse of the horizontal shift register 22, and they are controlled by reset pulses OG1, OG2 with phase difference of 180 deg.. Operating speed requested for the internal circuit such as the output gates 26, 28, etc., and the external circuit of the sample-and-hold circuit, etc., is decreased corresponding to the parallel number of output gates 26, 28.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device for outputting pixel outputs of a plurality of horizontal lines in parallel.

[0002]

2. Description of the Related Art A solid-state image pickup device previously filed by the applicant of the present application as Japanese Patent Application No. 7406 will be described with reference to FIGS. 2 and 4 to 6 attached for explaining the present invention. .. The solid-state image sensor shown in FIG. 2 has pixels (10) to (16) arranged in a matrix (only four units of pixels are shown) and pixels of each column.
(10) (14) ~ Multiple vertical shift registers arranged for
(20) (only two columns of vertical shift registers are shown), a plurality of vertical shift registers (20) are input in parallel and a horizontal shift register (22) is provided for serial output.

The vertical shift register (20) is a vertical transfer area V driven by three-phase vertical transfer pulses VCK1 to VCK3.
One stage register is formed by φ1 to Vφ3. The horizontal shift register (22) is a main transfer area H driven by two-phase horizontal transfer pulses HCK1 and HCK2.
φ1 and Hφ2, or auxiliary transfer areas Hφ1 ′ and Hφ
2'constitutes a one-stage register, and the main transfer areas Hφ1 and Hφ2 and the auxiliary transfer area Hφ1 ′,
Hφ2 ′ forms a unit transfer area for the pixels (10) to (16) of two horizontal lines.

Next, the charge transfer operation shown in FIGS. 5 and 6 is performed at the timing T shown in the timing chart of FIG.
1 to T14 will be described. At timing T1, the electric charge CO output from the pixels (10) and (12) on the odd line and the electric charge CE output from the pixels (14) and (16) on the even line are under the gate where the vertical transfer pulse VCK2 = H is output. Are transferred and accumulated in the respective transfer areas Vφ2 (see FIG. 5A ′). At this timing, since VCK3 = L, charges are not transferred to the horizontal shift register (22) (FIG. 5A).
reference).

At timing T2, the vertical transfer pulse VC
Since K2 and VCK3 are at the H level, the electric charges CO transferred and accumulated in the transfer area Vφ2 at the previous timing are transferred and accumulated in the transfer area Hφ1 of the horizontal shift register (22) via the transfer area Vφ3 (FIG. 5B). reference). Further, the output charges CE of the even-numbered pixels (10) and (12) transferred and accumulated in the transfer area Vφ2 of the vertical shift register (20) are transferred and accumulated across the transfer areas Vφ2 and Vφ3 (FIG. 5B ′).
reference).

At timing T3, the vertical transfer pulse VC
Since only K2 is inverted to the L level, the transfer area Vφ
The charges CE transferred and accumulated over 2 and Vφ3 are transferred and accumulated in the transfer region Vφ3. There is no change in the potential wells of the other transfer regions (see FIGS. 5C and 5 ').
At timing T4, since the vertical transfer pulse VCK1 is inverted to the H level, the electric charge CE transferred and accumulated in the transfer area Vφ3 at the previous timing is transferred and accumulated across the transfer area Vφ3 and the transfer area Vφ1. There is no change in the potential wells of other transfer regions (see FIGS. 5D and 5 ').

At timing T5, the vertical transfer pulse VC
Since K3 is inverted to the L level, the charge CE is transferred to the transfer region V
Transferred and stored in φ1 (see FIG. 5E ′). As a result, the electric charge CE is transferred by one step. At timings T6 and T7, charge transfer processing is performed in the vertical shift register (20), and there is no charge transfer in the horizontal shift register (22) (see FIGS. 6A, A ′, B, and B ′).

At timing T8, the horizontal shift clocks SCK1 and SCK2 are output, and the potential profiles of the transfer regions Hφ1 and Hφ2 of the horizontal shift register (22) are inverted. This allows the horizontal shift register
The charges CO transferred and accumulated in the transfer area Hφ1 of (22) are transferred and accumulated in the transfer area Hφ2 ′ (see FIG. 6C). At timing T9, vertical transfer pulses VCK1 to VC
The potential relationship between K3 and the horizontal transfer pulses HCK1 and HCK2 returns to the state of timing T1, and from timing T10 to T13.
In the above, the transfer operation described above is performed on the electric charge CE output from the pixels (14) and (16) of the even line (FIG. 6D,
See D ', E, E').

Then, at timing T14, the charges CO for two horizontal lines of the vertical shift register (20) and the transfer accumulation operation of CE to the main transfer area Hφ1 and the auxiliary transfer area Hφ1 ′ of the horizontal shift register (22) are completed. To do. By the charge transfer operation described above, the output charges of the pixels (10) on the odd line and the output charges of the pixels (14) on the even line accumulated in the horizontal shift register (22) are transferred to the horizontal transfer pulses HCK1 and HC.
By the high speed transfer pulses HC1 and HC2 of K2, horizontal transfer is performed at a speed twice as fast as that of the conventional device, and the output charges of the pixels (10) of odd lines and the output charges of the pixels (14) of even lines are alternately output. Therefore, in the case of interlaced driving, the output of the pixel (10) of the odd line and the output of the pixel (14) of the even line are mixed at an appropriate ratio to form the image signal of the unit field.

[0010]

DISCLOSURE OF THE INVENTION The solid-state image pickup device of a single horizontal shift register proposed above has a problem of inconsistency in transfer efficiency of respective horizontal shift registers when using two horizontal shift registers and a vertical shift register. To solve the problem of fixed pattern noise caused by transferring the output charge through one horizontal shift register to the other horizontal shift register.

However, in this solid-state image pickup device, internal circuits such as an output gate, an on-chip amplifier, and a reset gate must be operated at a frequency twice as high as that of the conventional device. There is a problem that the high frequency loss increases. Further, since the charges of the floating diffusion must be periodically reset at twice the speed of the conventional device, there is a problem that a high performance reset gate is required.

Further, there is a problem that a high speed operation is required for an external signal processing circuit such as a sample hold circuit, an automatic gain control, an A / D converter and the like.

[0013]

In the solid-state image pickup device of the present invention, a charge allocating section is continuously formed at an end of a horizontal shift register in which a main transfer area and one or more auxiliary transfer areas are formed. The main feature is that the charges are transferred through the main transfer area and one or more auxiliary transfer areas of the horizontal shift register, separated, and processed in parallel.

[0014]

In order to process charges transferred in the main transfer area and the auxiliary transfer area of the horizontal shift register in parallel, internal circuits such as an output gate, an on-chip amplifier, a reset gate and a sample hold circuit, an automatic gain control, A / It is possible to read all pixels without increasing the operating speed of an external signal processing circuit such as a D converter.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a schematic configuration diagram of the present embodiment, and FIGS. 2 and 3 are plan views of a main part of the embodiment shown divided into the end portions of the horizontal shift register.
6 and 6 are potential profiles of the aa line cross section and the bb line cross section of FIG. 2, respectively.

FIG. 1 shows an example of a solid-state image pickup device for reading out the charges of pixels on two horizontal lines of an odd line and an even line in parallel. Referring to the figure, the solid-state imaging device of this embodiment is arranged for pixels (10) and (14) arranged in a matrix (only two vertically adjacent pixels are shown) and pixels (10) and (14) in each column. A plurality of vertical shift registers (20) (only a single vertical shift register is shown), a horizontal shift register (22) that inputs the outputs of multiple vertical shift registers (20) in parallel and outputs serially, this horizontal shift register ( The charge distribution part (24) is continuously formed at the end of (22), and the output parts (30) and (32) are provided for each of a plurality of outputs of the charge distribution part (24).

In the vertical shift register (20), as shown in FIG. 2, a one-stage register is formed by vertical transfer regions Vφ1 to Vφ3 driven by three-phase vertical transfer pulses VCK1 to VCK3. Also horizontal shift register (22)
Is a one-stage register composed of main transfer areas Hφ1 and Hφ2 driven by two-phase horizontal transfer pulses HCK1 and HCK2, or auxiliary transfer areas Hφ1 ′ and Hφ2 ′. A unit transfer area is formed by Hφ1 ′ and Hφ2 ′.

The vertical transfer areas Vφ1 to Vφ3, the horizontal main transfer areas Hφ1 and Hφ2, and the auxiliary transfer area Hφ1 ',
Since Hφ2 ′ specifies the charge transfer direction, it has a built-in structure in which the potential well in the charge transfer direction becomes deep. The charges accumulated in the pixels (10) to (16) are transferred to the transfer area Vφ2 of the vertical shift register (20) through the read-out gate (18). Channel stops are formed in the boundary regions between the pixels (10) to (16) and the vertical shift register (20) and other boundary regions.

Referring to FIG. 3, the charge distribution unit 28 is shown as an output gate 26, 28 formed continuously at the end of the horizontal shift register 22, and an output unit 30, 28. 32) is a plurality of floating diffusions (34) (36), reset gates (38) (40) and drain diffusions (42) (44) that are formed after the output gates (26) (28).
Indicated by. The output gates (26) and (28) have a built-in structure by changing the oxide film thickness under the gate or changing the impurity concentration.

In the present embodiment, the pixels (10) to (16) are designed to have a size that extends over approximately three vertical transfer regions Vφ1 to Vφ3, but the present invention is not limited to this size. Not done. In addition, the lead-out gate (18) is connected to the vertical transfer area V
Although it is provided in association with φ2, it may be provided corresponding to another vertical transfer region Vφ1 or Vφ3. FIG. 4 shows vertical transfer pulses VCK1 to VC in the horizontal blanking period HBLK.
The waveforms of K3 and horizontal transfer pulses HCK1 and HCK2 are shown.

The vertical transfer pulses VCK1 to VCK3 are three-phase pulses having a phase difference of 120 degrees with each other. The horizontal transfer pulse HCK1 is at the H level at the start of HBLK and is at the L level at the middle of HBLK.
CK1 is output. The horizontal transfer pulse HCK2 is at the L level at the start of HBLK, and the H-level shift clock SCK2 is output at the intermediate point of HBLK.

Next, referring to FIGS. 5 and 6 showing potential profiles of the vertical shift register (20) and the horizontal shift register (22), according to the timing T1 to T14 described in the timing chart of FIG. The charge transfer operation will be described. Referring to FIG. 5A ′, at the timing T1, the vertical transfer pulse VCK1 = L, VCK2 =
Since H and VCK3 = L, the pixels (10) (1
Charge CO output from 2) and pixels on even lines (14)
The electric charge CE output from (16) is the vertical transfer pulse VCK2.
= H output from each transfer area Vφ2 under the gate
Transferred to and accumulated.

At this timing, the vertical shift register
Since the potential well of the transfer area Vφ at the boundary between (20) and the horizontal shift register (22) is shallow, the horizontal shift register (22)
Charges are not transferred to the cell (see FIG. 5A). Timing T
2, the vertical transfer pulses VCK2 and VCK3 are at the H level, so a potential well is formed in the transfer region Vφ3 at the boundary between the vertical shift register (20) and the horizontal shift register (22) (see FIG. 5B ′). The charges CO transferred and accumulated in the transfer area Vφ2 at the timing are transferred to the transfer area Vφ2.
3 is transferred to and accumulated in the transfer area Hφ1 of the horizontal shift register (22) (see FIG. 5B). Further, the electric charge CE output from the pixels (10) (12) on the even lines, which has been transferred and accumulated in the transfer area Vφ2 of the vertical shift register (20), is transferred and accumulated across the transfer areas Vφ2 and Vφ3 (FIG. 5B). '
reference).

At timing T3, the vertical transfer pulse VC
Since only K2 is inverted to the L level, the potential well of the transfer region Vφ2 of the vertical shift register (20) becomes shallow, and the electric charge CE previously transferred and accumulated over the transfer regions Vφ2 and Vφ3 is transferred to the transfer region Vφ3. Accumulated. There is no change in the potential wells of the other transfer regions (see FIGS. 5C and 5 ').

At timing T4, the vertical transfer pulse VC
Since K1 is inverted to H level, the vertical shift register (2
6) A potential well is formed in the transfer region Vφ1 of
The charges CE transferred and accumulated in the transfer area Vφ3 at the previous timing are transferred and accumulated across the transfer area Vφ3 and the transfer area Vφ1. There is no change in the potential wells of other transfer regions (see FIGS. 5D and 5 ').

At timing T5, the vertical transfer pulse VC
Since K3 is inverted to L level, the vertical shift register (2
The potential well of the transfer region Vφ3 of (0) becomes shallow,
The electric charge CE is transferred and accumulated in the transfer region Vφ1 (FIG. 5E ′).
reference). As a result, the electric charge CE is transferred by one step. At timings T6 and T7, charge transfer processing is performed in the vertical shift register (20), and there is no movement of charge in the horizontal shift register (28) (FIG. 6A, A ′,
See B and B ').

At timing T8, since the horizontal shift clocks SCK1 and SCK2 are output, the potential profiles of the transfer regions Hφ1 and Hφ2 of the horizontal shift register (22) are inverted. As a result, the charges CO transferred and accumulated in the transfer area Hφ1 of the horizontal shift register (22) are transferred and accumulated in the transfer area Hφ2 ′ (see FIG. 6C).

At timing T9, vertical transfer pulses VCK1 to VCK3, horizontal transfer pulses HCK1 and HC
The potential relationship of K2 returns to the state of timing T1, and the above-described transfer operation is performed on the electric charge CE output from the pixels (14) and (16) on the even lines (see FIGS. 6D and 6 '). Then, as shown in FIG. 6E, after timing T10, the electric charge C is applied to the main transfer area Hφ1 or Hφ2 and the auxiliary transfer area Hφ1 ′ or Hφ2 ′ of the horizontal shift register (28).
O and CE are alternately accumulated and transferred.

By the above charge transfer operation, the output charges of the pixels (10) to (14) of two horizontal lines accumulated in the horizontal shift register (22) are transferred to the horizontal transfer pulses HCK1 and HCK.
2 of the conventional element by the high-speed transfer pulses HC1 and HC2 of 2
It is transferred to the charge distribution unit (24) at double speed. Next, the operation of the embodiment after the charge distribution unit (24) will be described with reference to FIGS. 3, 7, and 8. Note that FIG. 8 is a potential profile of the cc line cross section and the dd line cross section of FIG. 3.

In FIG. 3, the charge distribution unit (24) is an output gate formed at the output end of the horizontal shift register (22).
(26) (28), the output section (30) (32) is a plurality of floating diffusions (34) (36), reset gate (38) formed after the output gate (26) (28) (Four
0) and drain diffusions (42) (44).

FIG. 7 shows the high speed transfer pulses HC1 and HC2 of the horizontal shift register (22) and the output gates (26) (2).
8 shows a timing chart of the gate pulses OG1 and OG2 of 8). As shown in the figure, the output gates (26) (2
The gate pulses OG1 and OG2 of 8) have a phase difference of 180 degrees with each other and have a cycle twice that of the high speed transfer pulses HC1 and HC2 of the horizontal shift register (22).

High speed transfer pulse HC1 = H, HC2 = L,
At timing T11 in FIG. 7 in which the gate pulses OG1 = H and OG2 = L, the output charges CO of the pixels on the odd lines are transferred and accumulated in the horizontal main transfer area Hφ1, and the auxiliary transfer area Hφ is obtained.
The output charges CE of the pixels on the even lines are transferred and accumulated in 1 '. Further, the output gate (26) is turned on and the output gate (28) is turned off (see FIGS. 8A and 8 ').

At timing T12, the high speed transfer pulse HC
The levels of 1 and HC2 are inverted, and the electric charge CE accumulated in the transfer region Hφ1 at the previous timing is transferred to the first floating diffusion (34) via the output gate (26). In addition, a transfer area Hφ not shown
The charge CE of 1 ′ is transferred and accumulated in the transfer region Hφ2 (see FIGS. 8B and 8 ′).

At timing T13, the high speed transfer pulse HC
1, HC2 and the levels of the gate pulses OG1 and OG2 are inverted, the output gate (26) is turned off, and the output gate (28) is turned on. In addition, the charge C of the transfer region Hφ2
O is transferred and accumulated in the transfer area Hφ1 (see FIGS. 8C and 8 '). At timing T14, the levels of the high-speed transfer pulses HC1 and HC2 are inverted, and the charge CO accumulated in the transfer area Hφ1 at the previous timing is output to the output gate.
The second floating diffusion (3
Transferred to 6). Further, new charges CE in the transfer region Hφ1 ′ (not shown) are transferred and accumulated in the transfer region Hφ2 (see FIGS. 8D and D ′).

By the above transfer operation, the signal charges CO and CE over two horizontal lines are transferred to the horizontal shift register (22) using the time within the horizontal briking period HBLK without being mixed with each other, and during the horizontal scanning period. , Horizontal transfer clock HC of a predetermined frequency (twice the frequency of the conventional)
1, is horizontally transferred by HC2, and image pickup signals are obtained in parallel from the first and second floating diffusions (34) and (36).

When interlace driving the solid-state image pickup device of this embodiment, the outputs of the pixels (10) -in the odd lines and the outputs of the pixels (14) -in the even lines are mixed at an appropriate ratio to form a unit field. The image pickup signal of is formed. In the case of non-interlaced drive, one of the output of the pixel (10) on the odd line or the output of the pixel (14) on the even line is stored in the line memory and the pixel output of the other line and the line are stored. A non-interlaced image pickup signal is formed by continuously outputting the memory output.

A second embodiment of the present invention will be described with reference to FIG. Since the present embodiment uses the horizontal shift register (22) used in the previous embodiment, only a schematic configuration will be described. This embodiment is an application example to a color solid-state imaging device, and pixels (10) to (16) (only four pixels are shown) arranged in a matrix, and pixels (10) (12) or (14) (16) in each column. ) Arrayed to the vertical shift registers (20) (20), the vertical shift registers (20) (20) output in parallel,
A horizontal shift register (22) for serial output, and a charge distribution unit (4) formed continuously at the end of this horizontal shift register (22).
6) is composed of three output units (48) (50) (52) formed for each of the plurality of outputs of the charge distribution unit (46).

The sensitivity colors of the pixels (17) to (19) arranged in a matrix are changed in a predetermined cycle, and the charge distribution section (46) outputs the output charge of the horizontal shift register (22) in the output section (48). ) (50)
Sort to (52). This charge distribution unit (26) can be realized by forming three independent output gates in parallel at the end of the horizontal shift register (22). Configured above,
According to this working example, the image pickup signals corresponding to the same color are always output from the output units (48), (50) and (52).

FIG. 10 shows a modification of the second embodiment. Since FIG. 10 corresponds to FIG. 2 provided for the description of the first embodiment, corresponding regions (elements) will be assigned the same reference numerals and detailed description thereof will be omitted. The horizontal shift register (2
3) is the main transfer areas Hφ1 and Hφ2 and two auxiliary transfer areas H
It comprises φ1 ′, Hφ2 ′ and Hφ1 ″, Hφ2 ″, which form a unit transfer area. Then, at the output end of the horizontal shift register (23), a charge distribution unit capable of separating the output charge into three is continuously formed.

In this modification, the horizontal blanking period HBL
In K, the charges of the pixels (10) on the first line are sequentially transferred and accumulated in the horizontal shift register (23). Therefore, at the end of accumulation, the charge of the pixel (10) of the first line is accumulated in Hφ1 ″ of the auxiliary transfer area, and the charge of the pixel (12) of the second line is accumulated in Hφ1 ′ of the auxiliary transfer area. , And the charges of the pixel (14) on the third line are accumulated in Hφ1 of the main transfer region.

Thereafter, the charges of three lines transferred to the horizontal shift register (23) are horizontally transferred within the horizontal scanning period,
Image processing signals for three lines are independently output by signal processing. Further, it is also possible to mix and output the image pickup signals of appropriate lines as needed.

[0042]

As described above, in the solid-state image pickup device of the present invention, the charge allocating portion is continuously formed at the output end of the horizontal shift register, and the charge allocating portion allows the main transfer area and the auxiliary transfer area of the horizontal shift register to be formed. Internal circuits such as output gates, on-chip amplifiers, reset gates, etc., and sample hold circuits, automatic gain control, A / D to separate the charges transferred in each area and process them in parallel
It is possible to read all pixels without increasing the operating speed of an external signal processing circuit such as a converter.

Further, since a single horizontal shift register is used, the transfer efficiency mismatch problem of a plurality of horizontal shift registers and the vertical shift register output charge are transferred to the other horizontal shift register via one horizontal shift register. By doing so, the problem of the generation of fixed pattern noise is solved.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a first embodiment of the present invention.

FIG. 2 is a plan view of the essential parts of the first embodiment showing up to the output end of the horizontal shift register.

FIG. 3 is a plan view of the essential parts of the first embodiment showing the horizontal shift register output end and thereafter.

FIG. 4 is a timing chart of the vertical shift register and the horizontal shift register according to the embodiment.

5 is a potential profile of a cross section taken along the line aa and the line bb in FIG. 2. FIG.

6 is a potential profile of a cross section taken along the line aa and the line bb in FIG. 2. FIG.

FIG. 7 is a timing chart of the charge distribution unit and the output unit according to the embodiment.

FIG. 8 is a potential profile of a c-c line section and a d-d line section of FIG.

FIG. 9 is a schematic configuration diagram of a second embodiment of the present invention.

FIG. 10 is a plan view of a main part of a modified example of the second embodiment.

[Explanation of symbols]

 10-16 pixels 18 read-out gate 20 vertical shift register 22 horizontal shift register 24 charge distribution unit 26, 28 output gate 30, 32 output unit 34, 36 floating diffusion 38, 40 reset gate 42, 44 drain diffusion

Claims (2)

[Claims] 1. A plurality of pixels arranged in a matrix, a plurality of vertical shift registers formed for pixels in each column arranged in a vertical direction, and a main transfer area and one or more main shift areas for each vertical shift register output. An auxiliary transfer area is formed, and a horizontal shift register that horizontally transfers the outputs of a plurality of vertical shift registers, a charge distribution unit that is continuously formed at the end of this horizontal shift register, and each output of this charge distribution unit A solid-state image sensor including a plurality of formed output parts. 2. The charge distributing section and the output section are formed in correspondence with three outputs of RGB.
Solid-state image sensor.