JP2578683B2 - Solid-state imaging device and driving method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device in which the number of bits of a horizontal transfer register is halved with respect to the number of horizontal pixels of an imaging unit, and a driving method thereof.

(B) Conventional technology FIG. 3 shows the structure of a horizontal transfer register of a conventional CCD solid-state imaging device.

(1) is a horizontal transfer unit, (2) is a vertical transfer unit,
(3), (5), and (6) are second-layer gate electrodes, (4),
(7) and (8) are first layer gate electrodes, and (9) is a channel stop portion. The first layer gate electrode (8) and the second layer gate electrode (6) are connected to the input terminal (a) of the horizontal transfer clock φH1, and the first layer gate electrode (7) and the second
The layer gate electrode (5) is connected to the input terminal (b) of the horizontal transfer clock φH2. As shown in this figure, one bit of the normal horizontal transfer register is composed of the second layer gate (5),
(6) The first layer gates (7) and (8) are composed of a total of four gates, and charges are transferred in the left direction in the drawing by alternately inverting φH1 and φH2.

(C) Problems to be Solved by the Invention In the above-described structure, it is necessary to configure four gates within one pitch of the horizontal transfer channel. This is a major obstacle to high integration.

(D) Means for Solving the Problems The present invention has been made to solve the above-mentioned problems, and has a first feature in that a plurality of bits of an appropriate number of bits for receiving signal charges from a light receiving element are provided. Vertical transfer registers are arranged in parallel with each other, and the output of the vertical transfer register is a solid-state imaging device associated with each bit of the horizontal transfer register. An additional bit is provided on the output side, and the additional bit is driven independently of the other bits of the vertical transfer register, so that each bit of the horizontal transfer register has an odd column and an even column. Are alternately transferred.

The second feature is that a plurality of vertical transfer registers of a suitable number of bits for receiving signal charges from the light receiving element are arranged in parallel with each other, and the output of the vertical transfer register is associated with each bit of the horizontal transfer register. Along with
In a method for driving a solid-state image pickup device in which 1-bit additional bit that can be independently driven is provided on an output side in an even-numbered vertical transfer register, the 1-bit signal charge is transferred from the vertical transfer register to the horizontal transfer register. After the transfer, the driving of the vertical transfer register is stopped, and the additional bit is driven to transfer the signal charges of the vertical transfer register to each bit of the horizontal transfer register alternately in odd columns and even columns. It is in.

(E) Operation According to the present invention, by providing an additional bit for temporarily holding signal charges on the output side of the vertical transfer register, the signal charges of the vertical transfer register are alternately transferred to the horizontal transfer register in odd columns and even columns. And the number of bits in the horizontal transfer register is reduced to at least half.

(F) Example An example of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a structure of a solid-state imaging device. The vertical transfer registers (23) and (24) are defined by the channel stop region (22), and are formed by the first-layer gate electrodes (10) and (1).
2), (14), (15) and the second layer gate electrode (11), (1
3), (16) and (17) are formed in an array, and four transfer gates (10), (11), (12) and (13) are defined as 1 bit.
There are as many as the number of vertical pixels, and every other channel
Four transfer gate electrodes (14), (15), (16), (17)
, One bit is added. The four transfer gate electrodes (10), (11), (12), and (13) are input terminals (c), (d), (e), and (f) of a transfer clock, respectively.
And the vertical transfer clocks VT1, VT2, VT3, VT4 are inputted. On the other hand, four transfer gate electrodes (14), (15),
(16) and (17) are input terminals (g) and (h), respectively.
(I) connected to (j), the vertical shift clock, VS1, VS
2, VS3, VS4 are input.

The horizontal transfer register (25) includes first layer gate electrodes (18) and (19) and second layer gate electrodes (20) and (21). The gate electrodes (18) and (21) are connected to the input terminal (a). ), The gate electrodes (19) and (20) are connected to the input terminal (b), and HT1 and HT2 are input, respectively.

Next, the operation of the first solid-state imaging device will be described with reference to FIG. In this figure, (k) indicates a horizontal blanking signal, and a High period is an effective video period.

The signal in the vertical transfer register (23) is the vertical transfer pulse
The signals are transferred to the horizontal transfer register (25) by VT1, VT2, VT3, and VT4, and output by the horizontal transfer pulses HT1 and HT2 in the period (26). The signals in the vertical transfer register (24) are transferred by the vertical transfer pulses VT1, VT2, VT3, and VT4 in the same manner as the signals in the vertical transfer register (23), and at timing T1, the gate electrodes (14) and (16) Exists under

Next, at timing T2 when the signal of the vertical transfer register (23) is output from the horizontal transfer register (25), the signal is transferred to the horizontal transfer channel (25) by the vertical shift pulses VS1, VS2, VS3, and VS4, and the period ( 27) Horizontal transfer pulse HT
Output by 1, HT2. By repeating these operations sequentially, all pixel signals can be output on a horizontal transfer channel having half the number of horizontal pixels.

Note that the number of bits of the horizontal transfer channel is reduced by 1 /
It can be reduced to 3,1 / 4.

(G) Effects of the Invention According to the present invention, the structure of the horizontal transfer channel, which has been one obstacle to the increase in the density of the solid-state imaging device, can be configured more easily and with twice the size of the conventional one. This is advantageous for reducing the size of the element or increasing the number of pixels.

In the signal processing of a normal video camera, it is necessary to convert the CCD output signal to the time axis of a normal signal.This can be easily realized by a 1H delay line or a line memory. Can be converted more easily.

Further, in the single-chip color camera, sampling for color separation is not necessary, and aliasing of high frequency noise due to the sampling can be prevented, which leads to improvement in image quality.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a solid-state imaging device of the present invention, and FIG.
FIG. 3 is a timing chart showing the operation, and FIG. 3 is a configuration diagram of a conventional solid-state imaging device. (10) (11) (12) (13): Vertical transfer gate electrode
(14) (15) (16) (17) ... vertical 1-bit shift gate electrode, (18) (19) (20) (21) ... horizontal transfer gate electrode, (22) ... channel stop area ,(twenty three)
(24) Vertical transfer channel area (25) Horizontal transfer channel area VT1, VT2, VT3, VT4 Vertical transfer pulse, VS1, VS2, VS3, VS4 Vertical shift pulse, HT1, HT2
... horizontal transfer pulse.

Claims (3)

(57) [Claims] A plurality of vertical transfer registers of a suitable number of bits for receiving signal charges from a light receiving element are arranged in parallel with each other;
An output of the vertical transfer register is a solid-state imaging device corresponding to each bit of the horizontal transfer register. In the even-numbered vertical registers, one additional bit that can be driven independently is provided on the output side. By driving the additional bit independently of the other bits of the vertical transfer register, the signal charges of the odd-numbered column and the even-numbered vertical transfer register are alternately transferred to each bit of the horizontal transfer register. Solid-state imaging device. 2. An additional bit for temporarily holding the signal charge between the vertical transfer register and the horizontal transfer register is provided at an output side of the vertical transfer register at a predetermined interval. Item 2. The solid-state imaging device according to Item 1. 3. A plurality of vertical transfer registers of a suitable number of bits receiving a signal charge from a light receiving element are arranged in parallel with each other,
The output of the vertical transfer register is associated with each bit of the horizontal transfer register, and the additional bits of one bit that can be independently driven are provided on the output side in the even-numbered vertical transfer registers. After the 1-bit signal charge is transferred from the vertical transfer register to the horizontal transfer register, the driving of the vertical transfer register is stopped, and the additional bit is driven to change the signal charge of the vertical transfer register into an odd number. A method for driving a solid-state imaging device, wherein columns and even columns are alternately transferred to each bit of the horizontal transfer register.