JPH01238156A - Solid-state image sensing device - Google Patents

Abstract

PURPOSE:To equalize a transferring order and to reduce size and weight, and cost with a common clock signal by providing a dummy register between an image sensor and a storage unit. CONSTITUTION:When a pixel signal of W is input to a second storage vertical shift register 27 of first row from an image sensing vertical shift register 23 of second row of an image sensor 21, pixel signals F, L are input from an image sensing vertical shift register 22 of first row of the sensor 21 to a first storage vertical shift register 24 of a first row. That is, the transfer is delayed by one cycle in a conventional one. However, the fact that a dummy register 6 is provided to originally directly input it from an image sensor 1 to a first storage vertical shift register 7 is equalized at a timing of transferring to the first and second storage vertical shift registers by once transferring it to the dummy register, and a common clock can be used.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a solid-state imaging device for taking images.

(b) Conventional Technology In general, solid-state image pickup devices (CCD) are currently fully utilized in video cameras and the like, and research and development are being carried out by various companies.

For example, there is a technique in which the transfer directions of vertical shift registers in odd-numbered columns and even-numbered columns of an imaging unit are made different, and an image signal is divided into two and transferred.

This configuration allows approximately 172 drive pulses. However, although the image signals generated from one horizontal shift register can be taken out in the normal order, the image signals from the other horizontal shift register are taken out in the reverse order, posing a problem that requires a new external circuit.

In order to solve this problem, there is, for example, Japanese Patent Application No. 58-8219.

As shown in Fig. 2, there is an imaging section (22) in which a photoelectric conversion element is coupled to each bit, and an imaging vertical shift register (22) with alternating transfer directions.
, (23), (22), (23)... are arranged in parallel. Each pixel signal obtained from each imaging vertical shift register (22) in the odd-numbered columns is temporarily accumulated in a first storage vertical shift register group (24), and then transferred to a first horizontal shift register. (25) is outputted to the outside as an image signal V. Here this first
Accumulation vertical shift register group (24)... is FIFO
For example, the imaging vertical shift register (22) in the first column of the imaging unit (c) functions as the first buffer memory group of the configuration.
The image signals are input from the storage vertical shift register (24) to the storage vertical shift register (24) in the order of F, L, R, and X, and the image signals are input from the storage vertical shift register (24) to the first horizontal shift register (25) As in the input case, pixel signal sequences are output in the order of F, L, R, and X.

On the other hand, the second accumulation vertical shift register group ( 27) Connect each input and output terminal of... and connect this second
It is temporarily stored in the accumulation vertical shift register group (27), and then outputted to the outside as an image signal (2) from the second horizontal shift register (27).

Here, this second accumulation vertical shift register group (27)
... constitutes the second buffer memory group with LIFO configuration, and serves as the imaging vertical shift register (2) in the second column of the imaging unit (fu).
3) to the second storage vertical shift register (2) in the first column.
7), a pixel signal string is inputted in the order of W, Q, and E, and the second accumulation vertical shift register (27)
The pixel signal string is output to the horizontal shift register (26) in the order of E, Q, and W, contrary to the input case.

The above configuration eliminates reversal of image signals.

(c) Problems to be Solved by the Invention In a configuration that eliminates the reversal of image signals as described above, the transfer order up to the output of the first horizontal shift register (25) and the output of the second horizontal shift register (26) are Since the transfer order is different, there is a problem that a common clock signal cannot be used.

Therefore, a new external circuit is required, which hinders the reduction in size, weight, and cost of equipment that uses this type of solid-state imaging device, such as television cameras.

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems. Between the imaging section (1) and the first accumulation vertical shift register group (4)...
This problem is solved by providing a dummy register (6).

(E) Effect For example, in FIG. 2, a pixel signal of W is transferred from the imaging vertical shift register (23) in the second column of the imaging section (silver) to the second accumulation vertical shift register (27) in the first column. When input, the imaging vertical shift register (2) in the first column of the imaging unit (c)
2) to the first accumulation vertical shift register (2) in the first column.
4), F and L pixel signals are input. In other words, conventionally, transfer is delayed by one cycle.

To solve this problem, a dummy register (6) is provided, and originally the first storage vertical shift register (7) is connected to the imaging section (1).
) can be transferred to this dummy register at the same time so that the timing of transfer to the first and second storage vertical shift registers can be made the same.

Embodiment FIG. 1 schematically shows an embodiment of the solid-state imaging device of the present invention.

First, the imaging unit (1) stores a plurality of imaging vertical shift I registers (2), (3), (2), (3)...
are arranged in parallel, a photoelectric conversion element is coupled to each bit, and the transfer directions are alternately different.

These imaging vertical shift registers (2), (3),
(2).

(3) Two-phase clock pulse φt + dr
By applying , the image signals obtained by each photoelectric conversion element are alternately transferred in the opposite direction. In Figure 1, (F,
L, R, X), (D, J, P, V), (B.

H, N, T) and (W, Q, E), (U, O.

I, C), (S, M, G, A) are transferred downward and upward, respectively.

Next, the first and second storage vertical shift register groups (4
)..., (5)... are arranged in parallel, and each pixel signal string obtained from each imaging vertical shift register (2)... in an odd column is passed through a dummy register (6). The signal is temporarily stored in the first storage vertical shift register group (4), and then outputted from the first horizontal shift register (7) to the outside as an image signal vl.

This first accumulation vertical shift register group (4)...
It acts as a first buffer memory group consisting of FIFOtM,
For example, from the imaging vertical shift register (2) in the first column of the imaging unit (↓) to the accumulation vertical shift register (4) in the first column.
A pixel signal sequence is input in the order of (F, L, R, X),
From this accumulation vertical shift register (4) to the first horizontal shift register (7), the same <(F, L,
Pixel signal strings are output in the order of R, X).

In addition, the second storage vertical shift register group (5)...
It functions as a second buffer memory group with a LIFO configuration, and for example, a second horizontal shift register (
The respective input terminals of the second storage vertical shift register group (5)... are connected through each bit of the second storage vertical shift register group (5). From the imaging vertical shift register (3) in the second column of the imaging unit (↓) to the second accumulation vertical shift register (5) in the first column, (
A pixel signal string is inputted to W, Q, and E) in the order of (E) from this accumulation vertical shift register (5) to the second horizontal shift register (8). ,Q,W
) The pixel signal strings are output in this order.

The characteristics of the present invention reside in the dummy register (6), and the FIFO-configured first storage vertical shift register group (4)... and the imaging section (1) (or the first horizontal shift register ( 7)) to delay by one cycle. The first and second horizontal shift registers (7) are delayed by this dummy register (6).
, the output timing of (8) becomes the same, and a common lock can be used.

FIG. 3 shows an example of this configuration. solid line,
- The dash-dot and dotted lines indicate the upper layer electrode, the lower layer electrode and the channel region, respectively.

First, the imaging vertical shift register (2) of the imaging unit (↓).

(3) A driving pulse φ1. By applying I, the odd column imaging vertical shift register (2)
At the same time, the pixel signals (F, L, R,
3) The pixel signals (W, Q, E)... are transferred upward.

At this time, imaging vertical shift registers (2), (3)
Gate electrode (9) of the gate part provided at the output end of ,...
A pulse of "Hn level is applied to turn it on, and drive pulses φ,, φ, are applied to the second accumulation vertical shift register group (5)... to generate the pixel signal string (W).

Q, E)... are transferred to the second storage vertical shift register group (5) via the gate section (second horizontal shift register).
)... will be temporarily transferred and stored.

Similarly, the first storage vertical shift register (4)
Since the driving pulses φ,, -1 are applied to the pixel signal arrays (F, L, R, X), the gate section (
dummy registers) to the first accumulation vertical shift register group (4) . . . at the same time.

Therefore, by providing the dummy register (6), the clocks after the first and second accumulation vertical shift register groups can be made the same.

Next, the second storage vertical shift register group (5)...
Using a switch etc., recombine the upper and lower layer electrode pairs,
By applying φ and 2φ, respectively, it is accumulated (
W, Q, ni, E) is (E, ni, Q.

W) and transferred to the second horizontal shift register (8) (at this time, the gate electrode (9) of the gate part is set to "L +
It is in the OFF state as t. ), and the accumulated (F, L, R, X) are transferred as they are to the first horizontal shift register (7), and are output as V, , V, respectively.

(g) Effects of the invention As is clear from the above explanation, the imaging section and the storage section (FI
By providing a dummy register between the two (having an FO configuration), the transfer order becomes the same and a common clock signal can be used.

Therefore, no new external circuit is required, and the device can be made smaller, lighter, and lower in cost.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing an embodiment of the solid-state imaging device of the present invention, FIG. 2 is a schematic diagram of a conventional solid-state imaging device, and FIG. 3 is a schematic plan view of the main parts of the solid-state imaging device of the present invention. It is a diagram. (1)...imaging section, (2), (3)...imaging vertical shift register, (4), (5)...accumulation vertical shift register group, (6)...dummy register, ( 7), (8)...Horizontal shift register. Figure 1 (ph ph Figure 2 ψhψh

Claims (2)

[Claims] (1) An imaging unit in which a plurality of vertical shift registers in which photoelectric conversion elements are combined for each bit are arranged in parallel, and the transfer method between each vertical shift register in odd-numbered columns and each vertical shift register in even-numbered columns is different. , a FIFO that is connected to the output end of each vertical shift register in odd columns of this imaging section and temporarily stores one-dimensional image signals for each vertical shift register.
a first accumulation vertical shift register group of the configuration; and a first storage vertical shift register group of the LIFO configuration that is connected to the output terminal of each vertical shift register in even columns of the imaging section and temporarily stores one-dimensional image signals for each vertical shift register. a first horizontal shift register whose respective bits are connected to each output terminal of the first accumulation vertical shift register group, and which transfers and outputs the image signal from the first accumulation vertical shift register group; a register; a second horizontal shift register, each bit of which is connected to each output end of the second storage vertical shift register group, and which transfers and outputs an image signal from the second storage vertical shift register group; and the imaging section. and a dummy register between the first storage vertical shift register group and the first storage vertical shift register group. (2) The solid-state imaging device according to claim (1), wherein the dummy register is provided between the first accumulation vertical shift register group and the first horizontal shift register.