JPS6135750B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interline shift type solid-state imaging device using a charge-coupled device (CCD). The aim is to improve the afterimage characteristics by reducing the light reception and accumulation time for each element to half of the conventional one.

A conventional CCD solid-state imaging device employing an interline shift method uses a plurality of light-receiving elements, each serving as a picture element, arranged in a matrix on a common semiconductor substrate, as shown in Figure 1 with a typical principle diagram. 1, a vertical shift register 2 with a CCD configuration extending in the vertical direction provided corresponding to each column of the light receiving section 1, and a vertical shift register 2 on the output side of the vertical shift register 2.
Transfer horizontal line signal charge horizontally
It consists of a horizontal shift register 3 with a CCD configuration,
The minority carriers based on the optical information accumulated in each light receiving section 1 are once transferred to the vertical shift register 2 for each vertical line.
, and then sequentially transferred in the vertical direction by each vertical shift register, and the signal charges for each horizontal line are read out from the output terminal t of the horizontal shift register 3 through the horizontal shift register 3.

In addition, as another example of an interline shift type CCD solid-state imaging device, as shown in FIG. Arranged in
Overall, the vertical shift register 2 compared to FIG.
A configuration in which the number of pixels is reduced and the number of picture elements in the horizontal direction is increased has also been proposed.

Incidentally, in such conventional interline shift type CCD solid-state imaging devices, as is clear from FIGS. 1 and 2, the light receiving section 1 is connected to the 1-bit transfer section L of the vertical shift register 2. (In a vertical shift register driven by two-phase clock pulses φV ₁ and φV ₂ , a 1-bit transfer section is configured by a transfer section to which φV ₁ is applied and a transfer section to which φV ₂ is applied.) In the case of an interlaced scanning method, the accumulated carriers of the light receiving section 1 corresponding to the solid line arrows are transferred in the odd field, and the accumulated carriers of the light receiving section 1 corresponding to the dotted line arrows are transferred in the odd field. For example, the data may be transferred using even fields.
In order to adopt such a pixel arrangement and readout method, when interlacing is performed, the reception and accumulation time of optical information in each light receiving section 1 becomes 2 field hours, and the frame in which the light reception and accumulation time is 1 field time. Its afterimage characteristics are inferior to those of transfer type imaging devices. In other words, since the light reception and accumulation time is two fields, the image is such that the image of the first field and the image of the second field overlap.

In view of the above points, the present invention improves the afterimage characteristics and increases the number of picture elements compared to the conventional one without deteriorating the image quality.
The present invention provides an interline shift type solid-state imaging device that can be reduced to 1/2.

The present invention arranges a plurality of picture elements at predetermined pitches in the horizontal direction and the vertical direction, respectively, and arranges a vertical shift register corresponding to each column of picture elements. In a CCD solid-state imaging device that has a common horizontal shift register on the output side, one of each shift register
One or two picture elements correspond to a bit, and each picture element or a set of two vertically adjacent picture elements corresponds to a bit, and each picture element or a set of two picture elements adjacent to each other in the vertical direction The overall arrangement is in a so-called checkerboard pattern so that the carriers of all pixels are read out to the vertical shift register for each field, and the carriers of two adjacent rows are read out from the horizontal shift register within one horizontal time. The picture elements are simultaneously read out as picture elements of one horizontal line. According to such a configuration, the light reception and accumulation time of each picture element is one field time, so that the afterimage characteristics are improved, and the number of picture elements is also one for each 1-bit transfer section of the vertical shift register. This reduces the cost by half compared to the conventional method.

Next, each embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a fundamental configuration diagram showing an embodiment of a solid-state imaging device according to the present invention, in which 1 indicates a plurality of light receiving sections serving as picture elements, and 2 indicates a plurality of CCD configurations corresponding to each column of the light receiving section 1. The vertical shift register 3 is a horizontal shift register having a similar CCD configuration and placed close to the output end of each vertical shift register 2. Each vertical shift register 2 is configured to be driven by, for example, two-phase clock pulses φV ₁ and φV ₂ , and has a first transfer section φ 1 G to which clock pulse φV ₁ is applied, and a first transfer section φ ₁ G to which clock pulse φV ₂ is applied. The second transfer portions φ ₂ G are formed alternately in the vertical direction, and the transfer portions φ ₁ G and φ ₂ G of each vertical shift register 2 are formed so as to be common to each horizontal line. Also, although not shown, the electrodes of each transfer section φ ₁ G and each transfer section φ
The _2G electrodes are commonly connected to each other and each terminal T ₁
and _T2 , clock pulses φV ₁ and φV ₂ are applied. On the other hand, a plurality of light receiving sections 1
are the transfer parts φ 1 G and _{φ 2 G} so that one bit corresponds to 1 bit L of the transfer part of the vertical shift register 2, respectively.
They are arranged in a checkerboard pattern such that adjacent rows are shifted by half a bit in the vertical direction. (This is called a one-row checkerboard arrangement.) That is, for example, each light receiving section 1 corresponding to an odd column is connected to a vertical shift register 2 via a gate region (not shown).
is connected to the first transfer section φ ₁ G of the
Storage carriers based on optical information in X ₁ , X ₃ ,
X _{5 , .}
Further, each light receiving section 1 (shown with diagonal lines) corresponding to an even numbered column is connected to the second transfer section φ ₂ G of the vertical shift register 2 via a gate region (not shown), The stored carriers Y ₂ , Y ₄ , Y ₆ , . . . based on the optical information in each light receiving section 1 are transferred to each corresponding second transfer section φ ₂ G through the gate region by applying a clock pulse φV ₂ . done to. Further, the sensor electrodes of the light receiving sections 1 in the odd rows are commonly connected to the common first electrode.
A sensor voltage φS ₁ is applied, and the sensor electrodes of the light receiving sections 1 in even-numbered columns are commonly connected so that a common second sensor voltage φS ₂ is applied thereto.

In such a configuration, the present invention simultaneously reads out the signal charges of all the picture elements, that is, the accumulated carriers based on the optical information of all the light receiving sections 1, into the vertical shift register 2 during the vertical blanking period, and reads out the signal charges of all the picture elements, that is, the accumulated carriers based on the optical information of all the light receiving sections 1, at the same time, and reads out the signal charges of the two adjacent rows. The charges of the light receiving section 1 are set as signal charges of one horizontal line, and one bit is transferred in the vertical direction in each horizontal blanking period, and one horizontal line is transferred from the output terminal t of the horizontal shift register 3 every horizontal time. It is designed to read out the signal charge of
Especially when interlacing, in odd fields, lines 2 and 3, lines 4 and 5, lines 6 and 7, etc.
The charges of the set of picture elements (A) of ... are read out as signal charges of one horizontal line, and in the even field, the sets of picture elements of the 1st and 2nd rows, the 3rd and 4th rows, the 5th and 6th rows, etc.
The charges in (B) are each read out as signal charges for one horizontal line.

Next, this specific operation will be explained using FIGS. 3 to 7. First, in FIG. 3, in all the light receiving sections 1, a predetermined sensor voltage is applied to the sensor electrode of the light receiving section 1 corresponding to the odd numbered column and the sensor electrode of the light receiving section 1 corresponding to the even numbered column during the light receiving period of one field. φS ₁ =“1” and φS ₂ =“1” are given, and minority carriers based on each optical information are accumulated.
In the case of signal readout of an odd numbered field, as shown in the signal waveform diagram _{of FIG} . A nearby small potential φS ₁ = “0” is applied to each transfer section φ of the vertical shift register 2 at the time t ₁ .
Two-phase clock pulse φV ₁ applied to ₁ G and φ ₂ G
and φV ₂ are respectively set to φV ₁ = “1” and φV ₂ = “0”, and as shown in FIG. 6A, the accumulated carriers X ₁ , X ₃ , . . . It is transferred to the first transfer section φ ₁ G of the corresponding vertical shift register 2. Next, at time t ₂ in FIG. 4, the potential of the sensor electrode of the light receiving section 1 in the even row is set to φS ₂ = "0",
At the same time, by setting the clock pulses given to the vertical shift register 2 to φV ₁ = “0” and φV ₂ = “1”, the accumulated carriers Y ₂ and Y ₄ of the light receiving sections 1 in the even columns are set as shown in FIG. 6B. , ... are transferred to the second transfer section φ ₂ G of the vertical shift register 2, and at the same time, _the accumulated carriers X ₃ , Half a bit is transferred to part _φ2G . By this, lines 2 and 3,
Accumulation carrier Y ₂ of light receiving section 1 in 4th and 5th rows...
and X ₃ , Y ₄ and X ₅ , ... are each arranged in one horizontal line,
By the subsequent clock pulses φV ₁ and φV ₂ , each carrier is transferred one bit at a time within the vertical shift register 2 toward the horizontal shift register 3 during the horizontal blanking period, and from the output terminal t of the horizontal shift register 3 one horizontal time The signal charges of one horizontal line are read out every time. That is, a set of two rows of picture elements indicated by the symbol (A) in FIG. 3 is read out as a signal of one horizontal line in an odd field.

On the other hand, in the case of signal readout of an even field, as shown in the signal waveform diagram _{of FIG} . Apply 0V or a small potential φS ₂ = “0” to the electrode, and at that time t' ₁ , the clock pulse applied to the vertical shift register 2 is set to φV ₁ = “0”.
and φV ₂ = “1”, and as shown in FIG.
Y ₂ , Y ₄ , . . . are transferred to the corresponding second transfer section φ ₂ G of the vertical shift register 2. Next, the fifth
At time t' ₂ in the figure, the potential of the sensor electrode of the light receiving section 1 in the odd row is set to φS ₁ = "0", and the clock pulse is set to φV ₁ = "1" and φV ₂ = "0". As shown in FIG. 7B, the accumulated carriers X ₁ , _{X 3} , . The even-numbered stored carriers Y ₂ , Y ₄ , Y ₆ , ... that were being transferred are transferred to the first transfer unit φ
Transfer half a bit to _1G . This results in 1 line and 2
Accumulated carrier of light receiving section 1 in rows, 3rd and 4th rows...
X ₁ and Y ₂ , X ₃ and Y ₄ , X ₅ and Y ₆ , . . . are arranged in one horizontal line, and the subsequent clock pulses φV ₁ and φ
By V ₂ each carrier has horizontal shift register 3
The signal charges of one horizontal line are read out from the output terminal t of the horizontal shift register 3 every horizontal time. That is, a set of two rows of picture elements indicated by the symbol (B) in FIG. 3 is read out as one horizontal line signal in an even field.

Note that FIGS. 8 to 10 show an example of a specific structure of the solid-state imaging device shown in FIG. 3, particularly the structure of a light receiving section, a vertical shift register, and a gate region. FIG. 9 is a sectional view taken along line AA, and FIG. 10 is a sectional view taken along line BB. In FIG. 8, the hatched area is the channel stopper area 10, and the dashed diagonal area is the light-receiving part 1, which becomes a picture element, and is arranged in a one-line checkered pattern as explained in FIG. , etc., one vertical shift register 2 is arranged corresponding to each column of light receiving sections. The channel stopper region 10, the light receiving section 1, and the vertical shift register 2 are formed on a common semiconductor substrate, for example, a P-type silicon semiconductor substrate 11, as shown in FIGS. 9 and 10. The light receiving section 1 is constructed by depositing a transparent electrode, that is, a sensor electrode 13, on a substrate 11 through an insulating layer of a predetermined thickness, for example, a SiO ₂ layer 12a. The sensor electrodes corresponding to the columns are connected in common, and the sensor electrodes corresponding to the even columns are connected in common to lead out mutually independent terminals T _S1 and T _S2 , respectively. On the other hand, the vertical shift register 2 has transfer sections whose number of bits corresponds to the number of light receiving sections 1, and for example, carriers are transferred in the direction of arrow a by two-phase clock pulses φV ₁ and φV ₂ . Each transfer section has a first transfer section φ 1 G to which a clock pulse φV ₁ is applied, a second transfer section φ ₂ G to which a clock pulse φV ₂ is applied, and a respective first transfer section φ ₂ G to which a clock pulse φV 2 is applied. The first and second transfer sections φ ₁ G and φ ₂ G are each configured to have a transfer gate region and a storage gate region. That is, the first transfer unit φ
_1G has a transfer gate region φ ₁ T and a storage gate region φ ₁ S, and also has a second transfer region φ 1
_2G has a transfer gate region φ ₂ T and a storage gate region φ ₂ S. Here, the storage gate regions φ ₁ S and φ ₂ S are each formed with a thin insulating layer such as the SiO ₂ layer 12b under the electrode, and the transfer gate regions φ ₁ T and φ ₂ T are each formed with an insulating layer under the electrode. For example, SiO ₂ layer 1
2c is formed thicker than storage gate regions φ ₁ S and φ ₂ S, and a common clock pulse φV ₁ or φ
Storage gate area φ ₁ S when V ₂ is applied
Alternatively, the potential well 14s under φ ₂ S is configured to be deeper than the potential well 14t under the transfer gate region φ ₁ T or φ ₂ T (see FIG. 10). Also, for example, each light receiving section 1 corresponding to an odd numbered column and the first transfer section φ of the vertical shift register 2
A gate region ST ₁ is provided between each storage gate region φ ₁ S of 1 G for transferring accumulated carriers from the light receiving section ₁ to the first transfer section φ ₁ G by a clock pulse φV ₁ . Furthermore, between each light receiving section 1 corresponding to an even-numbered column and the storage gate region φ ₂ S of the second transfer section φ ₂ G of the vertical shift register 2, accumulated carriers from the respective light receiving sections 1 are transferred by a clock pulse φV ₂ . A gate region ST ₂ for transferring to the second transfer section φ ₂ G is provided. Note that the electrodes of the storage gate region φ ₁ S, transfer gate region φ ₁ T, and gate region ST ₁ are the common electrode 1, respectively.
5A, the storage gate region φ
₂ S and transfer gate region φ ₂ T and gate region
The electrodes of ST ₂ are each formed by a common electrode 15B. Furthermore, the region 16 is an overflow drain region made of a semiconductor region of the opposite conductivity type to that of the substrate 11, and the region OG is a gate region provided between each light receiving section and the overflow drain region 16. Flowed through area OG to the overflow drain area.
Further, 17 is a light-shielding layer deposited on the surface of other parts except for the light-receiving part 1 through an insulating layer 18 of SiO ₂ or the like. In addition,
The overflow drain region 16 and its gate region OG may be formed in an empty area between the light receiving sections arranged every other bit. In this case, the light receiving area of the light receiving section 1 is increased and the integration is increased. can be expected. Therefore, in such a configuration, a predetermined positive voltage φS ₁ = is applied to the sensor electrode 13 of each light receiving section through the terminals T _S1 and T _S2 during the light receiving period.
When "1" and φS ₂ = "1" are given, a deep potential well 19 is formed under the sensor electrode 13 and minority carriers 20 are accumulated in accordance with the amount of received light. Next, φS ₁ =“0” or φS ₂ =“0” is applied to the sensor electrode 13 corresponding to the odd or even column, and the clock pulses φV ₁ =“1” and φV ₂ =“0” are applied to the vertical shift register 2. ”, or φV ₁ = “0”
and φV ₂ =“1”, a potential well indicated by 19′ is formed, and the storage carriers in the odd-numbered columns or the storage carriers in the even-numbered columns are transferred to the vertical shift register 2 through the gate region ST ₁ or ST ₂ , respectively. The data is transferred to the first transfer unit φ ₁ G or the second transfer unit φ ₂ G. Therefore, in this configuration, φS ₁ , φ
If S ₂ , φV ₁ and φV ₂ are applied at the timings shown in FIGS. 4 and 5, the operations described in FIGS. 6 and 7 will be performed.

According to the above-mentioned configuration, since the accumulated carriers of all the light receiving sections 1 are read out for each field, the light receiving accumulation time in each light receiving section 1 becomes one field time, which is shorter than the light receiving accumulation time in the conventional interline shift method. Because it is 1/2, the afterimage characteristics are improved. In addition, although the light receiving section 1 is arranged every other bit of the transfer section in the vertical shift register 2, and the so-called number of picture elements is halved compared to the conventional one, the vertical correlation of the image is used to Since a video signal for one horizontal line is created and read out, the same level of image quality as the conventional method can be obtained in both the vertical and horizontal directions. Furthermore, since the storage carriers are transferred from the light receiving section 1 to the vertical shift register 2 at different timings for each adjacent column, the structure of the vertical shift register 2 and the horizontal shift register 3 is different from that of the conventional interline shift method. Two rows of picture elements can be read out simultaneously without any changes compared to the structure. Furthermore, interlacing can be easily implemented by alternating the carrier transfer timing for the odd-numbered columns and even-numbered columns of the light receiving section 1 for each field.

FIG. 11 shows another embodiment of the invention. It is constructed by arranging light receiving sections 1, which serve as picture elements, in a checkered pattern in one line as in the case of FIG. 3, and the same sensor voltage φ _S is applied to all the light receiving sections 1 at the same time. Each vertical shift register 2 has a first transfer section φ to which a clock pulse _φV1 is applied.
₁ G and a second transfer section φ ₂ G to which a clock pulse φV ₂ is applied.
The first and second transfer units φ ₁ G and φ ₂ G are arranged with a half bit shift between the odd and even columns.
Therefore, each light receiving section 1 is arranged in a checkered pattern as a whole.
are all connected to, for example, the first transfer section φ ₁ G of the vertical shift register 2. On the other hand, between each vertical shift register 2 and horizontal shift register 3, there is a 1-bit buffer register with a CCD configuration in order to synchronize the signals as will be explained later.
Ba and Bb are provided. In this case, independent two-phase clock pulses are applied to buffer registers Ba corresponding to odd columns and buffer registers Bb corresponding to even columns.

Signal reading in such a configuration is performed as follows. First, during the light receiving period of one field, the same sensor voltage φ _S = “1” is applied to all light receiving sections 1.
is given, and minority carriers based on each optical information are accumulated. For example, in the case of an even field, the potential of the sensor electrode is set to φ _S =“0” within the vertical blanking period, and the first and second transfer portions φ ₁ of the vertical shift register are switched at the time t=t ₁ . G
and φ ₂ G as φV ₁ = “1” and φ
V ₂ =“0” and the accumulated carriers X ₁ , Y ₂ , X ₃ , Y ₄ , . . . of the light receiving section 1 of each row are transferred to the first transfer section φ ₁ G of the vertical shift register 2. In this state, the carriers in the odd and even columns are at positions shifted by half a bit from each other (FIG. 12A). In the following, φV ₁ =
12th at the time t=t ₂ when “0” and φV ₂ = “1”
As shown in Figure B, each carrier X ₁ , Y ₂ , X ₃ , Y ₄ ,...
For example, the carrier X ₁ in the first row corresponding to the odd column is transferred to the buffer register Ba (Fig. 12B), and the next φV ₁ =
With half-bit transfer of “1” and φV ₂ = “0”, carrier X ₁ is waited in buffer register Ba, and carrier Y ₂ of the second row corresponding to the even column
is transferred to the buffer register Bb, and the carrier _X1 on the first line and the carrier _Y2 on the second line are synchronized (FIG. 12C). As for driving the buffer registers Ba and Bb for this synchronization, for example, in the buffer register Ba corresponding to the odd numbered column, the carrier is transferred by one bit in the transfer period of one bit of the vertical shift register at the time t= t ₂ and t
At = t ₃ , two-phase clock pulses φa ₁ and φa 2 synchronized with the two-phase clock pulses φV ₁ and φV ₂ applied to the vertical shift register ₂ are applied.On the other hand, in the buffer register Bb corresponding to the even column, the carrier is transferred to the vertical shift register 2. The buffer register is set at time t= _t3 so that one bit is transferred in a half-bit transfer period.
It is sufficient to provide two-phase clock pulses φb ₁ and φb ₂ with twice the period of the clock pulses φa ₁ and φa ₂ applied to Ba. After that, if the carriers X ₁ and Y ₂ are simultaneously transferred from the buffer registers Ba and Bb to the horizontal shift register 3 within the horizontal blanking period, the carriers of the light receiving sections of the first and second rows are
X ₁ and Y ₂ are read out from the output terminal t of the horizontal shift register 3 as signal charges of one horizontal line (Fig. 12C), and thereafter, 3 signal charges are read out from the output terminal t every horizontal time in the same way. Rows and 4 lines, 5 lines and 6 lines, etc.
The signal charges of the set of picture elements are read out. For odd fields, buffer registers Ba and Bb
The clock pulses φa ₁ , φa ₂ and φb ₁ , φ
b ₂ is reversed from the case of an even field, the carriers Y ₂ , Y 4 , ... corresponding to the odd columns are made to wait in the buffer register Bb, and the carriers X 1 , Y ₄ , ... corresponding to the even columns are made to wait in the buffer register _Bb .
The _13th
As shown in the charge transfer state diagrams in Figures A to C, the final lines are 2nd and 3rd (hereinafter 4th and 5th lines, 6th and 7th lines, etc.)
…) of the picture element set Y ₂ and X ₃ (Y ₄ and X ₅ , Y ₆
and X ₇ , . . . ) are each read out as signal charges of one horizontal line.

In such a configuration, as in the case of FIG.
Since the light reception and accumulation time in each light receiving section 1 is one field time, the afterimage characteristics are improved, and the number of picture elements can be reduced to half of the conventional one without deteriorating the image quality.

FIG. 14 shows another embodiment of the present invention in which the picture elements are arranged in a one-row checkered pattern. In this example, the first transfer unit φ in the vertical shift register 2 of each column
₁ G and the second transfer section φ ₂ G are arranged in common for each horizontal line as in FIG. ₁ G, and the same sensor voltage φ is applied to all light receiving parts 1 at the same time.
Try to give _S. A horizontal shift register 3 is disposed on the output side of each vertical shift register 2. The operation of this configuration is such that during the light reception period of one field, the same sensor voltage φ _S = "1" is applied to all the light receiving parts and carriers based on optical information are accumulated, and then all the light reception parts are applied during the vertical blanking period. φ _S =“0”, and clock pulses φV ₁ =“1” and φ are applied to the first and second transfer portions φ ₁ G and φ ₂ G of the vertical shift register, respectively.
By giving V ₂ = "0", the carriers X ₁ , Y ₂ , X ₃ , Y ₄ , ... accumulated in the light receiving section 1 of each row are transferred to the first transfer section φ ₁ G of the corresponding vertical shift register 2. Forward. Therefore, at this point, as shown in Fig. 15, the carriers Y ₂ and X ₃ , Y 4 and X 5 , etc. of the light receiving sections of the 2nd and 3rd rows, _4th and _5th rows, etc. are one horizontal line. The pictures in the two rows are sequentially transferred in the vertical direction within the vertical shift register 2 by the two-phase clock pulses φV ₁ and φV ₂ applied to the vertical shift register 2, and from the output end t of the horizontal shift register 3. The signal charges of one horizontal line of elements are read out every horizontal time. Note that when interlacing is performed, the first
In Fig. 4, the signal of an odd field is set as a signal of one horizontal line using the sets of picture elements of the 2nd and 3rd rows, the 4th and 5th rows, and the 1st and 2nd rows, the 3rd and 4th rows, and so on.
The signal of an even field is read out as a signal of one horizontal line with a set of picture elements.

In the solid-state imaging device having such a configuration, as in FIG. 3, the light reception and accumulation time in the light receiving section 1 becomes one field hour, improving the afterimage characteristics, and reducing the number of picture elements by half without deteriorating the image quality. be able to.

FIG. 16 shows still another embodiment of the present invention. As mentioned above, there are a plurality of light-receiving sections 1 that serve as picture elements, and a plurality of light-receiving sections 1 corresponding to each row of the light-receiving sections 1.
It has a vertical shift register 2 with a CCD configuration and a horizontal shift register 3, and each vertical shift register 2
are the first transfer section φ ₁ G to which, for example, a two-phase clock pulse φV ₁ is applied, and the clock pulse φV ₂
The second transfer portions φ ₂ G in each column are formed alternately, and the first and second transfer portions φ ₁ G in each column are
and φ ₂ G are configured to be common for each horizontal line. The electrodes of each first transfer section φ ₁ G and the electrodes of each second transfer section φ ₂ G are connected in common, respectively, so that clock pulses φV ₁ and φV ₂ are applied. On the other hand, the plurality of light receiving sections 1 are
The vertical shift register is arranged such that the two light receiving sections 1A and 1B, one set of each, are connected to the vertically adjacent first transfer section φ ₁ G and second transfer section φ ₂ G of the vertical shift register 2. Two bits of the transfer section are arranged every 2L, and adjacent rows are arranged in a checkerboard pattern with a 1 bit shift in the vertical direction.
(This is called a two-row checkerboard arrangement.) That is, the accumulated carriers of the light receiving sections 1A corresponding to the odd rows are transferred to each corresponding first transfer section φ ₁ G through the gate region by the application of the clock pulse φV ₁ , and Accumulated carriers in the light receiving sections 1B corresponding to even-numbered rows are transferred to each corresponding second transfer section φ ₂ G through the gate region by applying a clock pulse φV ₂ . Further, the sensor electrodes of the light receiving sections 1A on the odd rows are commonly connected and a common first sensor voltage φS ₁ is applied thereto, and the sensor electrodes of the light receiving sections 1A on the even rows are connected in common.
The sensor electrodes of B are commonly connected so that a common second sensor voltage φS ₂ is applied thereto.

Next, the operation of such a configuration will be explained using FIGS. 16 to 18. First, in FIG. 16, in all the light receiving sections 1A and 1B, a predetermined sensor voltage φS _{1 = is applied to the sensor electrode of the light receiving section 1A in the odd row and the sensor electrode of the light receiving section 1B in the even row during the light receiving period of one} field. “1” and φS ₂ =“1” are given, and minority carriers based on each optical information are accumulated.
As shown in the signal waveform diagram of FIG. 17, within the vertical blanking period T _V of the vertical blanking pulse φ _B , the light receiving section 1 corresponding to the odd row first
The potential of the sensor electrode of A is set to φS ₁ = “0”,
At the time t=t ₁ , φV ₁ = “1” and φV 2 = φ _{1 G} and φ ₂ G of the vertical shift register 2, respectively.
"0" is given, and as shown in FIG. 18A, each storage carrier X ₁ , Y ₃ , X ₅ ,
Y ₇ , . . . are transferred to the first transfer section φ ₁ G of the corresponding vertical shift register. Next, at time t=t ₂ in FIG. 17, the potential of the sensor electrode of the light receiving section 1 in the even row is set to φS ₂ =“0”, and at the same time, the clock pulse given to the vertical shift register 2 is set to φV ₁ =“0” and φV By setting ₂ = "1", the accumulated carriers of the light receiving sections 1B in even-numbered rows are set as shown in FIG. 18B.
X ₂ , Y ₄ , X ₆ , Y ₈ , ... are transferred to the second transfer section φ ₂ G of the vertical shift register 2, and at the same time, the accumulated carriers X ₁ , Y _{3 , 7} , . . . are transferred by half a bit to the second transfer section φ ₂ G. As a result, as shown in FIG. 18B, the accumulated carriers X ₂ and Y ₃ , X ₅ and Y ₄ ,
. . . are lined up in one horizontal line, and thereafter, this state is maintained by clock pulses φV ₁ and φV ₂ , and one bit at a time is transferred from the vertical shift register 2 toward the horizontal shift register 3. The signal charges of one horizontal line are read out from the output terminal t every horizontal time. That is, the third
A set of picture elements in two rows indicated by the symbol A in the figure is read out as a signal of one horizontal line, which corresponds to a signal in an odd field. When interlacing is performed in such a configuration, it is performed through an external interlacing device. Fig. 19 shows the basic configuration of an interlacing device when picture elements are arranged in a checkered pattern in two lines, and S is connected to the output side of the horizontal shift register 3 of the solid-state imaging device shown in Fig. 16. The switching circuit D is a delay circuit for delaying one horizontal time. Now, if only the picture element arrangement (two-line checkered arrangement) is schematically shown in FIG. 20, the signals of each horizontal line in an odd field are X ₂ and Y ₃ , Y ₄ and X ₅ ,..., and the signals of each horizontal line in the even field are X ₁ and X ₂ , Y ₃ and Y ₄ ,... as shown by symbol B.
This is a combination of Therefore, in the case of an odd number field, the driving described in FIGS. 17 and 18 above produces output signals M ₁ and M in the combination shown in FIG. 21 for each horizontal line at the terminal C. ₂ ,... are obtained, and therefore one switch S ₁ of the switch circuit S
By turning on the signals M ₁ , M ₂ , . . . and outputting them as they are to terminal A, an odd field signal can be obtained. Next, in the case of an even field, the terminal C
_The contents of the signals M ₁ , M _{2 ,} . . . obtained in The other signal corresponding to the even row is taken out to terminal A as it is. That is, in this case, the 22nd
Signals n ₁ , n ₂ , . . . as shown in FIG. 22B are obtained at terminal B, and signals n′ ₁ , n′ ₂ , . Therefore, by combining the signals n ₁ and n' ₁ , n ₂ and n' ₂ , etc. obtained simultaneously at terminals A and B, respectively, a signal as shown in FIG. 22C is obtained.
N ₁ , N ₂ , . . . are obtained, and this becomes a signal for each horizontal line of an even field.

Even in this configuration, since all picture elements in each field are read out, the light reception and accumulation time is one field time, and the afterimage characteristics are improved. Furthermore, even though the total number of picture elements is reduced to 1/2 of that of the conventional method, image quality equivalent to that of the conventional method can be obtained in the case of an odd numbered field, as in the case of a single line checkered pattern, and in the case of an even numbered field, by utilizing the vertical correlation.

FIG. 23 shows yet another embodiment of the invention.
As in the case of FIG. 16, two light-receiving sections 1 are arranged in a checkerboard pattern with respect to the vertical shift register 2 so that every two bits are arranged in pairs, but the light-receiving sections 1A and 1B of each set are It is connected to the first transfer section φ ₁ G of the vertical shift register 2. 24th
The figure is a plan view of the main parts showing the specific structure of the first transfer section φ ₁ G consisting of a storage gate region φ ₁ S and a transfer gate region φ ₁ T, a storage gate region φ ₂ S and a transfer gate region φ.
A pair of light receiving sections 1A and 1B are disposed on one side of a vertical shift register having a second transfer section φ ₂ G consisting of ₂ T, and each light receiving section 1A and 1B is connected to a gate region, respectively.
Each first transfer unit φ separated by 1 bit from each other via ST ₁
Connected to a _1G storage gate region φ _1S .
The sensor electrodes of all the light receiving sections 1A and 1B are commonly connected and the same sensor voltage φ _S is applied thereto. 1
5A is a common electrode on the first transfer section φ ₁ G to which the clock pulse φV ₁ is applied and the gate region ST ₁ ;
B is a common electrode on the second transfer section φ ₁ G to which the clock pulse φV ₂ is applied;
By applying the clock pulse _φV1 , the storage carriers of B are transferred to the storage gate region φ of each first transfer section _φ1G through _the respective gate region ST1.
₁ made to be forwarded to S.

The operation of such a configuration is that after applying a sensor potential φ _S = "1" to the light receiving section 1 during the light receiving period of one field and accumulating a carrier based on optical information, all the light receiving sections are applied within the vertical blanking period. A common potential φ _S =“0” is applied to 1A and 1B, and clock pulses φV ₁ =“1” and φV 2 are applied to the first and second transfer sections φ ₁ G and φ ₂ G of the vertical shift register, _respectively .
= "0" and transfer the accumulated carriers X ₁ , X ₂ , Y ₃ , Y ₄ , ... of the light receiving sections 1A, 1B of each row to the first transfer section φ ₁ G of the corresponding vertical shift register 2, respectively. . At this point, as shown in FIG. 25, carriers X ₂ , Y ₃ , Y ₄ , X ₅ , ₆ , _Y7 ,…
... are arranged on one horizontal line, and are sequentially transferred by two-phase clock pulses φV ₁ and φV ₂ applied to the vertical shift register 2, and from the output terminal t of the horizontal shift register 2 rows of picture elements are set as a set. Signal charges for each horizontal line are read out. In this case, interlacing is performed through the external interlacing device described in FIG. 19. In this configuration as well, the total number of picture elements is reduced to half that of the conventional one, and all the picture elements in each field are read out, so that the light reception and accumulation time becomes one field time, and the afterimage characteristics are improved.

[Brief explanation of the drawing]

1 and 2 are fundamental block diagrams showing an example of a conventional CCD solid-state imaging device, FIG. 3 is a fundamental block diagram showing an embodiment of a solid-state imaging device according to the present invention, and FIGS. 5 is a drive signal waveform diagram, FIGS. 6A and 7A and 7A and 7A and 7A and 7A and 7A and 7A and 7B are respectively diagrams of the charge movement state, and FIG. 8 is a plan view of the main part showing the specific structure of FIG. 3. Figure 9 is a cross-sectional view along line A-A.
FIG. 10 is a sectional view taken along the line B--B, FIG. 11 is a basic configuration diagram showing another embodiment of the present invention, and FIG.
FIGS. A to D and FIGS. 13A to D are diagrams of charge movement states during operation, and FIGS. 14 and 15 are principle configuration diagrams showing still other embodiments of the present invention and charges during operation. FIG. 16 is a principle block diagram showing still another embodiment of the present invention, FIG. 17 is a drive signal waveform diagram, FIG. 18 A and B are charge movement state diagrams, and FIG. The figure is a basic configuration diagram of an external interlacing device, Figure 20 is a schematic diagram showing the arrangement of light receiving sections, Figures 21 and 22 are explanatory diagrams of signal extraction, and Figure 23 is the invention of the present invention. FIG. 24 is a plan view of a main part showing its specific structure, and FIG. 25 is a charge movement state diagram during its operation. 1 is a light receiving section, 2 is a vertical shift register, 3 is a horizontal shift register, φ ₁ G is a first transfer section, and φ ₂ G is a second transfer section.

Claims (1)

[Claims] 1 It has a plurality of picture elements arranged along the horizontal and vertical directions, and a plurality of shift registers extending in the vertical direction, and one or two picture elements are arranged for each bit of each shift register. correspond to each other, each picture element or each pair of vertically adjacent picture elements is located at a position corresponding to between picture elements or between sets of picture elements in adjacent columns, and the shift register is A solid-state imaging device arranged in a one-to-one relationship with the columns of picture elements and configured to simultaneously read out picture elements in adjacent rows within one horizontal time.