JPS59154882A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To improve the area ratio of picture element in one cell and to improve the degree of integration in horizontal direction by performing plural number of times of transfer of signal charge from a photosensing section to a storage register so as to reduce the number of trnsfer electrodes at a vertical CCD shift register. CONSTITUTION:A signal charge from picture element groups 211-244 arranged two-dimensionally on a semiconductor substrate 1 is read by a vertical shift register 31 and fed to a horizontal transfer register via the storage register 51. A signal charge from the picture element group of an odd number order is transferred to the 1st group of the transfer electrode group of the storage register 51 from the vertical CCD shift register, and the 2nd signal charge from the picture element group of an even number order is transferred under the transfer electrode of the 2nd group of the storage register 51. When the transfer of the signal charge to the storage register 51 is finished, the signal charge from the transfer electrode at the lowermost part of the storage register 51 is transferred to a horizontal CCD shift register 6 and one line of picture element signal is read externally.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a charge-coupled solid-state imaging device, and particularly to an improvement of an interline transfer type area sensor (two-dimensional image sensor).

[Technical background of the invention and its problems]

An example of a conventional interline transfer type area sensor will be explained with reference to FIG. This area sensor includes pixel groups 2, 1 to 2, which are two-dimensionally arranged on a conductive type semiconductor substrate 1.
No. 24: Vertical charge transfer type (COD) shift register for reading signal charges of each pixel column 3. 4. Overflow drain to absorb excess charge from each pixel. It consists of an accumulation register 5 that temporarily accumulates the signal charge of each pixel column before transferring it to the horizontal COD shift register 6. In the figure φ
1. φ2. φ'1 vφ/2 simultaneously refer to the transfer electrodes of the vertical CCD shift register 3 and storage register 5 and the clock pulses applied thereto. An interline transfer type area sensor provided with this storage register is known from Japanese Patent Laid-Open No. 55-52675. Note that the area sensor shown in FIG. 1 is an example of a case where interlace ground motion is not performed. When interlaced driving is performed, the number of transfer electrodes in the KFi, vertical 78 CCD shift register, and storage register may be half of that shown in the figure.

However, in the configuration shown in Figure 1, in the photosensitive section where the structure is lost due to the pixel, rough CCD shift register, and overflow drain, there is a pixel section that generates and accumulates signal charges in the -19th cell, and the signal charge is accumulated in the pixel section. φ1 for transferring the charge within the cell. Since there is a vertical CCD shift register and an overflow drain section consisting of two independent transfer electrodes φ, the area ratio occupied within one pixel cell is small, so-called aperture ratio is reduced, and sensitivity cannot be increased. There was a drawback that the degree of integration in the horizontal direction was not high.

[Purpose of the invention]

The present invention addresses the above situation! By transferring the Shinagata charge from the photosensitive section to the storage register multiple times, the transfer i! in the vertical COD shift register is performed. The objective is to provide a solid-state @weisowa r that can reduce the number of electrodes, increase the area ratio of pixels within one cell, and improve the degree of integration in the horizontal force direction to increase the N image resolution. .

[Outline of the invention]

The present invention reduces the number of transfer stages of the narrow CCD shift register to, for example, half the number of pixels in each pixel column of the WiII pixel group that is continuously read out and forms one screen f4F'j, and It is characterized in that the charges are transferred, for example, twice to the product register, and the (%) charge 4J of the pixel group is sequentially read out from the horizontal COD shift register for each row from the accumulation register. By this, the area occupied by the vertical COD shift register in the photosensitive area is halved compared to the conventional one, increasing the degree of horizontal integration and the relative proportion of the pixel area,
This is intended to improve sensitivity.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Happy 2
The figure is a conceptual diagram of the undercurrent side 1, but since this is an example of the case where it corresponds to the one in Figure 1, corresponding parts are given the same reference numerals and explanations are omitted. I will explain the points. The characteristics of this embodiment are that the number of transfer electrodes of the vertical CCD shift register is half the IC of FIG. 1, and the number of transfer electrodes of the storage shift register 51 is the same as that of FIG. 1. However, they form two columns, each forming a sub-storage register, and each transfer! As shown in the figure, there are independent clock pulses (φz%, φ/, k), (φ
〃8. φ〃,) is applied in its entirety.

The operation of the configuration shown in FIG. 2 will be explained using FIGS. 3 and 4. Figure 3 shows each transfer' polarization φ.

φ1. φl1. φ't t φ〃0. FIG. 4 shows the clock pulses applied to the vertical shift register 30 and the storage register 5 at the timings t1 to j and oK of each clock pulse, and the signal charges a to a4 of one pixel column are applied to the vertical shift register 30 and the storage register 5.
Indicates which electrode of 1 it is under. Clock pulse φ1. φ2 has three levels, in addition to the normal transfer mode (two-phase drive in the figure), tlf
This is because a high level is required to carry out the so-called field shift mode in which charge is transferred from odd-numbered pixel groups and even-numbered pixel groups to the vertical COD shift register at timing t4.

As can be seen from FIG. 4, the first signal charge al? from the odd-numbered pixel group? a3 is vertical COD shift I/
After being transferred (field shifted) to the register (timing t1), the data is transferred from the vertical COD shift register to the storage register 5. The first group of transfer electrodes (sub-storage register) φ'
1 eφI.

(timing t, to t,) and is transferred from the vertical COD shift register to the storage register 5. signal charge to al s
After the transfer of a3 is completed (evening timing t4), the second signal charges a2*a4 from even-numbered image areas are transferred to vertical shift registers θ3. More accumulated registration i+
5. 2nd group of transfer electrodes (sub storage 8f1/distor φ3
．． φ〃2 is transferred downward (timing t, ~ta). The first signal charges an t a3 of this transfer are stopped at the bottom of the first group of transfer 'd' and are not transferred to the horizontal CCD shift register 6. Next F Senkei Yoiga a, ~
After the transfer of a4 to the storage register is completed (timing t8), the cram school frame is transferred to θ5. The bottom of! The signal charge a is transferred from the transfer electrode of ++ to the water-strike CCD shift register 6, and the water-strike XP-CCD shift register is transferred to the output side, and the pixel number of one line is read to the outside, and the power is read at l+1. Below, the signal charges are transferred alternately to the horizontal CCD shift register from below i, and pixel signals are read out row by row from the horizontal CCD shift register 76. When the camera is pressed, the imaging and hiding of one side is completed.

As explained above, according to this embodiment, the vertical CO of the photosensitive area
Since the number of transfer stages of the D shift register 31 can be halved compared to the conventional one, the area occupied by the vertical COD shift register can be halved compared to the conventional one. Therefore, by narrowing the channel width of the vertical CCD shift register, the degree of integration in the horizontal direction is improved, and a larger number of pixels can be arranged in the horizontal direction Vζ, so that the resolution in the horizontal direction is improved. A portion of the reduced area of the vertical CCD shift register ii! ii Expand the base size,
Sensitivity can also be increased by increasing the area of the aperture for light transmission. Naturally, like the conventional figure 1, it is a normal interline type CCD that does not have a storage register.
Approximately 1/20 to 3 times less smear (dirt) than area sensors
Can be set to 0.

Note that the present invention is not limited to the above-mentioned embodiments, and can be applied in various ways. For example, if interlaced driving is used, the number of pixels to be read out at once is half of the total number of pixels, so the number of transfer electrodes Fi in the CCD shift 1/register and storage shift register (FI) can be half of that in FIG. That is, the relationship between the number of transfer electrodes M is as shown in Table 1 below between the conventional example and the present invention.

Although the vertical CCD shift register and storage register in Table 1 and the embodiments are both driven in two phases, they may be driven in three phases, four phases, or a combination thereof. In the above explanation, the number of transfer stages of the vertical COD shift register is set to half the number of pixels read out at once in a pixel column, and the transfer of signal charges from the vertical COD shift register to the storage 1/2 register is set to 2.
However, the number of transfer stages of the vertical COD shift register is generally set to 1/N of the number of pixels to be calculated at one time in a pixel column (N is an integer, N≧ 2)
Then, the accumulated signal charge is transferred from the vertical CCD shift register fN times, and after all the signal charges of the pixels to be read out at one time are transferred to the accumulation register, the signal charge is transferred from the accumulation register to the horizontal COD shift register 1 time corresponding to the pixel arrangement. The signal charges may be transferred line by line and read out from the horizontal COD shift register.

〔Effect of the invention〕

As explained above, according to the present invention, since the number of transfer electrodes of a vertical CCD shift register can be reduced by IK for a plurality of conventional ones,
By increasing the degree of integration in the horizontal direction, it is possible to provide a solid-state imaging device with improved horizontal resolution and sensitivity.

[Brief explanation of drawings]

Figure 1 is a configuration diagram of a conventional solid-state imaging device, Figure 2 is a configuration diagram of an embodiment of the present invention, Figure 3 is a waveform diagram of a clock pulse used in the same configuration, and Figure 4 is the operation of the same configuration. It is an explanatory diagram. 2.1 to 244...Pixel, 3m...Vertical CCD shift register, 5m...Storage register, 6...Horizontal C
CD shift register. Figure 1: 4 Dingshizhuang Portrait Songs - Unexamined Publication Date U39-154882 (4)

Claims (1)

[Claims] An integer N (N≧2 )
1/100% transfer! a photosensitive section consisting of a vertical charge transfer type shift register existing between pixel columns of the two-dimensionally arranged pixel group consisting of a number of poles; KN sub-storage registers are provided at each end of each vertical charge transfer type shift register to temporarily accumulate signal charges of 1/H pixels of the pixel column of the continuous pixel group constituting one screen in 8 series. Charge transfer y ; a horizontal charge transfer type shift register provided adjacent to the end f of the storage register and for continuously and sequentially reading out signal charge groups from the pixel groups accumulated in the storage register in accordance with the pixel arrangement; A solid-state imaging device featuring: