JPH06268923A - Drive method for solid-state image pickup device - Google Patents

Abstract

PURPOSE:To provide a solid-state image pickup device with a high dynamic range by devising a clock pulse so as to realize the increase in the maximum transfer signal charge of a vertical CCD transfer electrode. CONSTITUTION:In the drive method for the solid-state image pickup device provided with photosensing picture elements arranged on a semiconductor substrate in 2-dimension and plural vertical transfer sections provided along a vertical arrangement direction of the photosensing picture elements and a horizontal transfer section at the end of the vertical transfer sections to provide a signal charge, it is characterized in that a field shift gate reading a signal charge from the photosensing picture element and a vertical transfer electrode impress bipolar clock pulses to the vertical transfer electrode used not in common and a negative clock pulse and a 0 are impressed to the common vertical transfer electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method for a CCD (solid-state image pickup device), and more particularly to a driving method for expanding a dynamic range.

[0002]

2. Description of the Related Art CCD solid-state image pickup devices are used in a wide variety of fields by taking advantage of their features. In particular, it has a great application to miniaturized and high-resolution cameras. FIG. 11 shows a block diagram of an interline transfer type CCD. This CCD is a photosensitive pixel (PD), vertical CCD (VCCD), horizontal CCD
(HCCD) and output amplifier (AMP). The signal charges photoelectrically converted by the photosensitive pixels are transferred in the horizontal CCD direction by four-phase pulses φV ₁ , φV ₂ , φV ₃ , and φV ₄ applied to the VCCD, and in the horizontal CCD, two-phase pulses φH ₁ and φH _{2 are transferred.} The signal charges are transferred in the AMP direction. Then, the signal charges are read out to the output OS.

As a method of improving the sensitivity and dynamic range of this CCD, there is a structure in which the photosensitive pixel portion has a two-story structure. The conventional problems will be described below with reference to the structure of the two-story solid-state imaging device shown in FIG. 11 is a p-type Si substrate, for example, n ⁺ -type layer 12 ₂ of the first n ⁺ -type layer 12 ₁ and the signal charge storage portion is a signal charge readout channels on the surface thereof, the storage unit and, for example, aluminum (A
There is an n ^{+ +} type layer 14 for making ohmic contact with the metal electrode 17a formed in 1) and ap ⁺ type layer 13 serving as a channel stopper. On the CCD channel, there are CCD transfer electrodes 15a and 15b formed of, for example, a two-layer polycrystalline silicon film via a gate oxide film. This 2
A first insulating film 16a is deposited on the layer transfer electrodes 15a and 15b, and a second metal electrode 17b is connected to the n ^{+ +} type layer 14 through a contact hole formed in the first insulating film 16a.
Are provided in each pixel region. On top of this, for example, a photoconductive film 18 made of amorphous Si and a transparent conductive film 1 such as ITO.
9 is formed.

Here, the signal charge storage section n ⁺ type layers 12 ₂ and n
^{+ +} -Type layer 14, a first metal electrode 17a and the second metal electrode 17b are arranged two-dimensionally formed independently for each pixel. That is, the second metal electrode 17b defines the image pickup pixel region, and the potential change obtained by the second metal electrode 17b as a result of the image pickup by the photoconductive film 18 is the first metal electrode 1.
It is transmitted to the n ⁺ type layer 12 ₂ of the signal charge storage portion via 7a and is stored therein as signal charge. Although the figure shows a cross section in which the p ⁺ -type layer 13 that is the channel stopper is visible, a transfer unit that transfers the signal charges of the n ⁺ -type layer 12 _{2 to} the n ⁺ -type layer 12 ₁ that is the CCD channel for each pixel. Have
An interline transfer type CCD image pickup device is configured.

Since the interline transfer type (IT) CCD having the two-story structure as described above improves the light utilization rate,
Higher sensitivity can be realized. However, this two-story IT structure
-CCD has a high sensitivity, and therefore the amount of signal charges photoelectrically converted increases. Vertical C to carry this large amount of signal charge
It is necessary to increase the transfer charge amount of the CD, but increasing the size of the vertical CCD results in increasing the pixel size, which is disadvantageous in reducing the size and increasing the number of pixels.

When the number of pixels is increased, the vertical CCD
There is also a problem that the channel width becomes smaller and the amount of transfer charge handled decreases. Furthermore, in the high-definition CCD, the horizontal blanking time is 3.
This is 77 μs less, which causes a problem that a large amount of signal charge cannot be carried in a short time and the dynamic range is reduced.

[0007]

As described above, when the conventional solid-state image pickup device has a two-story structure, has a large number of pixels, or is manufactured for high-definition, the maximum transfer charge of the vertical CCD is required. However, there is a problem that the reproduced image is deteriorated due to a decrease in the amount, a decrease in dynamic range, a decrease in saturated charge amount, and the like.

The present invention has been made in view of the above circumstances, and provides a solid-state image pickup device having a high dynamic range capable of increasing the maximum transfer charge amount while keeping the channel width of the vertical CCD as it is. It is in.

[0009]

The essence of the present invention is to transfer a plurality of vertical CCD transfer electrodes, which are not commonly connected to a gate for reading out a signal charge from a photosensitive pixel, with plus / minus pulses to transfer the light. The electrode commonly connected to the gate for reading out the signal charge from the pixel is to transfer by 0 and a negative clock pulse.

[0010]

According to the present invention, the vertical CC of the conventional structure is maintained.
The maximum signal charge can be increased with D. That is,
According to the present invention, it becomes possible to transfer a highly sensitive signal charge amount in an IT-CCD having a two-story structure without loss. Further, even when the horizontal blanking period becomes short as in a high-definition solid-state imaging device, it is possible to transfer without handling the signal charge amount.

[0011]

The details of the present invention will be described below with reference to the illustrated embodiments. FIG. 1 shows an enlarged view and an operation diagram of a part of a solid-state image pickup device according to the first embodiment of the present invention. 2 is an overall view of the clock pulse applied to FIG. 1, FIG. 3 is an enlarged view of the clock pulse applied to FIG. 1, and FIG. 4 is a channel potential operation diagram of the vertical CCD when the clock pulse of FIG. 3 is applied. It is a figure. This device is a photodiode PD,
Vertical CCD VCCD, channel stopper CS, field shift gate FSG, vertical CCD transfer electrode φV
It is composed of four-phase electrodes of ₁ , φV ₂ , φV ₃ , and φV ₄ . In addition, the IT-CC of the two-story structure described in the conventional example
In D, the PD portion in this figure is the n ⁺ type layer 12 of the signal charge storage portion
_{The same} applies to the vertical CCD section when viewed from the structure in which the ₂ , n ^{+ +} type layer 14 is replaced.

The channel width of the VCCD becomes narrower as the number of pixels increases, and the channel width A having the FSG and the channel width B sandwiched by the channel stoppers CS on both sides are two.
Can have one channel width. At this time, a step is formed in the channel B due to the narrow channel effect as shown in the potential diagram of FIG. 1C, and just below the electrodes of φV ₂ and φV ₄ , the signal charges Q _2a , Q _4a and the channel width A are located. Q ₁ , ₃
Will be smaller than. This lowers the maximum transfer charge amount.

In this embodiment, the decrease in the signal charge amount of the electrodes sandwiched by the channel stoppers CS of the vertical CCD is
The driving method is not limited to the same method as other electrodes, but rather can be increased more. The state of the position is shown in FIG. That is, only the electrodes sandwiched by the channel stoppers CS of the vertical CCD are applied with the plus and minus clock pulses from the normal 0 and minus clock pulses to become Q _2b and Q _4b, and as shown in FIG. _The maximum transfer charge amount can be increased by the increase of _max . According to the experimental results of the inventor, this increased charge amount is more than twice as much as that in the case of applying 0 and a negative clock pulse in the conventional method to all four electrodes.

FIG. 2 shows a concrete clock pulse waveform applied to φV _{1 to} φV ₄ . Since the interlace operation is performed, the signal read timing from the pixel differs between the ODD field and the EVEN field. FS is a field shift pulse period, AD is a period for adding the signal charges of two pixels, LS is a line shift period for transferring the signal charges of the vertical CCD, and the operation of this line shift period is the same as that of the first embodiment of the present invention. It is a driving method. In this period, the voltage of the clock pulse is set to 0V and negative V _{LV for} φV ₁ and φV ₃ , and the positive V _HV and negative V _LV for φV ₂ and φV ₄ to drive the vertical CCD.

A more specific pulse timing is shown in FIG. HBL is a horizontal blanking period. From the viewpoint of noise prevention, it is necessary to perform the line shift operation within this period. Therefore, a transfer method having a high speed and a wide dynamic range is required. The potential operation diagram of the pulse shown here is shown in FIG. Pulse timing t
₁ to t ₉ correspond to t ₁ to t ₉ in the potential operation diagram. Vertical CCD transfer electrodes φV ₁ , φV ₂ , φV ₃ , φ
Potential levels generated on the high level side when V ₄ is applied are indicated by P ₁ , P ₂ , P ₃ , and P ₄ . It is apparent that the signal charge Q is transferred from t ₁ to t _{9 in} sequence with the amount of signal charge being accurately increased.

Next, a second embodiment of the present invention will be described. The feature of this embodiment is that the clock pulses for applying plus and minus are in two stages. FIG. 5 shows a clock pulse waveform. .phi.V _2, the rise time of the clock pulses of .phi.V _4, the falling edge of .phi.V ₂ as shown and fall time t _4, t _5, the rise of _{φV 4 t 2, t 3,} φ
There are two stages, t ₈ and t ₉ at the rising edge of V ₂ and t ₁₀ and t _{11 at the} falling edge of φV ₄ . This makes it possible to more reliably bring out the effects of the present invention. The reason for this will be described with reference to FIG. As shown in FIG. 6B, when the amplitude of the clock pulse increases, the pulse ringing shown by the waveform 63 occurs. As a result, the channel potential of the vertical CCD may be faint, and the signal charge amounts separated in each pixel may be mixed to reduce the signal charge amount to be handled. With the circuit configuration shown in FIG.
And its output by the driver 62 and applied to φV ₁ . The multiplexer input is P shown in FIGS. 6 (d) and 6 (e).
Input the _A and P _B pulses. And V _H , V _M , V
If the voltages of _L and V _C are selected by the multiplexer,
The two-stage clock pulse shown in (c) can be created. Figure 6
Compared to (b), the rise and fall times of the pulse are halved, and ringing disappears.

Next, a third embodiment will be described. Here, a method of increasing the signal charge amount during the field shift operation will be described. 7 shows a clock pulse waveform, and FIG. 8 shows a potential operation diagram during the field shift period and the signal charge addition period when the clock pulse waveform shown in FIG. 7 is applied. Immediately after the field shift, the electrodes of φV ₁ and φV ₃ are set to V
_F → V _B → V _M and lower it in two steps. Then, this period φV ₂ or φV ₄ is set to a voltage intermediate between plus and minus. _A potential operation diagram in this series of operations t _{A to} t _E is shown as t _A to t _E in FIG. Potential P _A voltage V _F, the potential P _B voltage V _L, the potential P _C voltage V _B, the potential P _D voltage V _D, the potential P _E is the voltage V _M, the potential P _F corresponds to the voltage V _H . If this two-stage field shift operation is not performed, it corresponds to the period of t _B. At this time, the maximum transfer charge amount is determined by the difference between the potentials P _E and P _B. As is apparent from the figure, the amount of charge is less than half that of the operation at t _B and overflows at each pixel. The maximum signal charge transfer amount can be obtained by intertwining the third embodiment with the first or second embodiment.

Next, a fourth embodiment will be described. This embodiment is particularly effective as a driving method for a high-definition solid-state imaging device when the horizontal blanking period is narrow. Φ of the present invention
By driving V ₂ and φV ₄ with positive and negative voltages, the shape of the clock pulse can be simplified and transfer in a short time becomes possible. In the four-phase drive pulse in the first embodiment, there are eight pulse rising / falling change time differences, whereas in the fourth embodiment, only five points are required. This means that high speed transfer is possible. Alternatively, the signal charge can be transferred in a short period. In this operation, as shown in FIG. 9, among the four-phase drive pulses, the high level is 3 electrodes, 1 electrode, 3 electrodes.
The electrodes are repeated so that φV ₂ and φV ₄ are set to plus and minus voltages, and φV ₁ and φV ₃ are set to 0 and minus voltages. FIG. 10 shows a potential operation diagram when this pulse is applied. Wherein t ₁ ~t ₆ corresponds to t ₁ ~t ₆ timing of FIG. The hatched portion indicates the signal charge, and the arrow indicates the flow of the signal charge. Especially t
During the periods indicated by ₂ to t ₃ and t ₄ to t ₅ , the potential changes as indicated by the dotted line, indicating that the signal charges can be transferred in the direction of the arrow. When this operation is performed, the size of the electrodes of the vertical CCD is increased by φV ₁ and φV ₃ , and φV ₂ and φV ₄ are increased.
The effect can be increased by decreasing.

[0019]

As described above in detail, according to the present invention, a field shift gate is formed by sharing a field shift gate among a plurality of vertical CCD transfer electrodes and applying positive and negative pulses to the vertical CCD transfer electrodes. The maximum vertical signal transfer amount can be increased by performing a driving method in which the shared vertical CCD transfer electrode is applied with 0 or a negative pulse. As a result, it is possible to significantly improve the blinding phenomenon on the reproduced image, which has been conventionally seen.
Further, the present invention has an effect that the maximum transfer signal charge amount does not decrease even if the vertical CCD transfer electrode is made smaller than the conventional one.
It is an effective means for future miniaturization elements and multi-pixel elements.

[Brief description of drawings]

FIG. 1 is a partially enlarged view and an operation diagram of a solid-state imaging device according to a first embodiment of the present invention.

FIG. 2 is a clock pulse waveform diagram in the first embodiment.

FIG. 3 is an enlarged view of a clock pulse waveform according to the first embodiment.

FIG. 4 is a channel potential operation diagram in the first embodiment.

FIG. 5 is an enlarged view of a clock pulse waveform according to the second embodiment.

FIG. 6 is a diagram for explaining clock pulse waveform generation in the second embodiment.

FIG. 7 is a clock pulse waveform diagram in the third embodiment.

FIG. 8 is a channel potential operation diagram in the third embodiment.

FIG. 9 is an enlarged view of a clock pulse waveform according to the fourth embodiment.

FIG. 10 is a channel potential operation diagram in the fourth embodiment.

FIG. 11 is a block diagram of an interline transfer CCD.

FIG. 12 is a structural diagram of a two-story solid-state imaging device.

[Explanation of symbols]

PD ... photosensitive pixels FSG ... field shift gate VCCD ... vertical CCD transfer channel _{φV 1, φV 2, φV 3} , φV 4 ... vertical CCD transfer electrode CS ... channel stopper FS ... field shift pulse LS ... line shift pulse V _H ... positive voltage _VL ... Negative voltage

Claims (4)

[Claims] 1. A photosensitive pixel arranged two-dimensionally on a semiconductor substrate, a plurality of vertical transfer sections provided along the vertical arrangement direction of these photosensitive pixels, and transfer ends of these vertical transfer sections. And a horizontal transfer unit provided adjacent to the unit, and outputting the signal charges photoelectrically converted by the photosensitive pixel through the vertical transfer unit and the horizontal transfer unit. A unit in which a field shift gate electrode for reading out signal charges to a portion and a part of the plurality of vertical transfer electrodes are configured in common, and the remaining electrodes in the plurality of vertical transfer electrodes are configured in common with the field shift gate electrode. And a means for applying a plus / minus clock pulse to an electrode that is not common to the field shift gate electrode, and a driving method for a solid-state imaging device. 2. The method for driving a solid-state image pickup device according to claim 1, wherein the rising and falling waveforms of the plus and minus clock pulses are performed in two or more stages. 3. The field shift operation of the field shift gate electrode is such that at least one applied pulse which is not common to the field shift gate electrode is set to the plus / minus voltage intermediate point, and the field shift pulse falls. The method for driving a solid-state image pickup device according to claim 1, wherein the step is performed by a staircase pulse having two or more steps. 4. The vertical transfer electrode is a four-phase drive, and the clock pulse to be applied is performed by means of repeating high-level application of three electrodes, application of one electrode, and application of three electrodes. Driving method of solid-state imaging device.