JPS63234677A - Drive method of charge coupling element - Google Patents

Abstract

PURPOSE:To prevent improper operation by applying an intermediate voltage to vertical shift registers at both sides adjacent to a vertical shift electrode being impressed a high voltage so as to receive a signal charge at readout of the signal charge. CONSTITUTION:When a clock pulse phiv1 is added to a read pulse phiTGON during the vertical blanking period to obtain a high voltage VH, the signal charge is moved beneath the transfer electrode of a vertical shift register area 2 via a transfer gate area 3 from a photoelectric converting region 1. During this period, the clock pulse phiv2 changes from a low voltage VL to keep an intermediate voltage VM and since the clock pulse phiv4 is in the intermediate voltage VM during this time, the transfer electrode at both adjacent transfer electrodes of the read pulse phiTGON goes to the intermediate voltage VM. Thus, the read signal charge is stored under the transfer electrode given by clock pulses phiv4, phiv1, phiv2 are stored under the transfer electrode. The only the voltage for the clock pulse phiv3 is lowered ad the low voltage VL and since the potential beneath the transfer electrode given with the clock pulse phiv3 is low, the separation between the signal charges is kept.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state image sensor used in a VTR camera or an industrial measurement camera, and particularly relates to a method for driving a charge-coupled device.

[Conventional technology]

Fig. 2 is a plan view of two cells of the photoelectric conversion section of a two-dimensional interline transfer type charge-coupled image sensor, Fig. 3 is a timing chart of a conventional drive method, and Fig. 4 is an A-A' shown in Fig. 2.
A cross-sectional view of each is shown.

The two-dimensional interline transfer type charge-coupled device is classified into a surface channel type and a buried channel type depending on the charge transfer format, and the one shown is a buried channel type. This buried channel type two-dimensional interline transfer type charge-coupled image pickup device is described in detail in Japanese Patent Application Laid-Open No. 114922/1983. The devices shown in FIGS. 2 to 4 differ from the device disclosed in Japanese Unexamined Patent Publication No. 114922/1983 in that the charge transfer lock is four-phase, but they are basically the same.

An N-type photoelectric conversion region 1, a P-type channel stop region 3, and an N-type well region 13 serving as a vertical shift register region are formed in a surface region of a P-type semiconductor substrate 11. Channel stop region 8 surrounds photoelectric conversion region 1 except for a portion of transfer gate region 3 that transfers charge from photoelectric conversion region 1 to vertical shift register region 2 .

In the transfer gate region 3, a P-type semiconductor substrate is formed on the surface. The photoelectric conversion region l is covered with a transparent insulating film, and light incident through this insulating film generates charges, which are transferred to the P between the semiconductor substrate 11 and the photoelectric conversion region l.
Accumulates in the N junction capacitance.

N-type well region 13 in vertical shift register region 2
A transfer electrode having a two-layer structure consisting of a 'g electrode made of first polysilicon 9 and an electrode made of second polysilicon 10 is formed thereon with a thin insulating film 12 interposed therebetween.

Clock signals φ7□, φ7□, and φVS+φv4 are sequentially applied to these transfer electrodes via electrodes 4.5.6.7. The photoelectric conversion regions 1 are formed in multiple columns along the vertical shift register region 2, and a large number of pairs of vertical shift register regions 2 and columns of photoelectric conversion regions 1 are arranged in parallel. A horizontal shift register is provided at the end of each vertical shift register area 2, and an output detection section that performs charge-voltage conversion is formed at the end of the horizontal shift register.

Charges are accumulated by light incident on the photoelectric conversion region 1 during the accumulation period, and these become signal charges corresponding to the incident light. The signal charge is generated by clock pulse φ7 during the vertical blanking period.
．． Read pulse φTGON of high voltage level VH generated at
is transferred from the photoelectric conversion area 1 to the vertical shift register area 2 via the transfer gate area 3. This signal charge transfer is performed by turning on the transfer gate region 3 by the high voltage Vu of the clock pulse φl. The signal charges transferred to the vertical shift register area 2 have an intermediate level VM and a low level Vt.

A four-phase clock pulse with a binary level of φv1+φV2°φv3. At φv4, the signal is transferred through the vertical shift register area 2, reaches a horizontal shift register (not shown), is transferred through the horizontal shift register, and is converted into a voltage by the output detection section. During this period of charge transfer, the photoelectric conversion region 1/'i order signal charge is accumulated.

The accumulated signal charges are transferred from the photoelectric conversion region 1 to the vertical shift register region 2 via the turned-on transfer gate region 3 to perform the next signal charge transfer.

[Problems to be solved by the invention]

In this conventional driving method, the electrode of the vertical shift register that receives the signal charge read out when the signal charge is read out has a high potential VH, and the adjacent vertical shift register electrodes have an intermediate voltage VM and a low voltage VL by the clock pulse φV4 + φY2, respectively. ing. For this reason, the second layer polysilicon 10 to which the clock pulse φv4 is applied
Mu-VL as the voltage difference between the electrode and the electrode of the fourth layer polysilicon 9 to which the clock pulse φv2
voltage will be applied. In concrete numbers, it is 19v.
Large voltages were to be applied both front and rear.

Because of this large potential difference, the first layer polysilicon 9 and the second layer
Dielectric breakdown may occur in the insulating film 12 between the polysilicon layer 10 and the polysilicon layer 10. This dielectric breakdown may cause a short circuit between the first polysilicon layer 9 and the second polysilicon layer 10, resulting in malfunction.

[Means for solving problems]

The method for driving a charge-coupled device of the present invention is such that when reading signal charges from a photoelectric conversion region, a high voltage is not applied between a transfer electrode to which a readout pulse is applied and a transfer electrode adjacent thereto. The transfer electrode adjacent to the electrode has a
An intermediate voltage is applied between the two levels of the intermediate voltage and low voltage of the clock pulse.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a timing chart of one embodiment of the present invention. The following will explain using the timing chart of FIG. 1 with reference to FIGS. 2 and 4. φ78.
φV21φvS+φv4 is a four-phase clock pulse applied to the vertical shift register, and indicates its timing and peak value (voltage value). clock pulse φv
1, when transferring signal charges from the photoelectric conversion region 1 to the vertical shift register, a read pulse φTGO of high voltage VH is applied.
N is added. In synchronization with this read pulse φTGON, the potential of the clock pulse φv2 is raised from the low voltage VL to the intermediate voltage VM.

Next, to explain the operation, during the vertical plugging period, the read pulse φTGON is added to the clock pulse φv1, and the high voltage V
When the signal becomes H, the signal charge is transferred from the photoelectric conversion region 1 to the vertical shift register region 2 via the transfer gate region 3.
Move directly under the transfer electrode.

During this period, the clock pulse φv2 changes from the low voltage VL to maintain the intermediate voltage VM. At this time, since the clock pulse φv4 is at the intermediate voltage VM, the read pulse φTG
The transfer electrodes on both sides of the transfer electrode to which ON is applied both have an intermediate voltage VM. The signal charge read out by this is the clock pulse φV4+φv1. φv2 is accumulated under a given transfer electrode.

Only the voltage value of the clock pulse φv3 is the low voltage VL, and the potential immediately below the transfer electrode to which the clock pulse φv3 is applied is low, so that separation between signal charges is maintained. After the read pulse φTGON, the voltage value of the clock pulse φv2 changes again from the high voltage VM to the low voltage VL. Therefore, the read signal charges are accumulated directly under the electrodes to which the clock pulses φv4 and φv1 are applied.

After the blanking period ends, the signal is sequentially transferred to the vertical shift register by the same operation as the conventional one, and then transferred to the output detection section via the horizontal shift register t, where it becomes a signal output.

In the next read period, the read pulse φTGON appears as the clock pulse φv3, and the potential of the clock pulse φv4 is raised from the low voltage VL to the intermediate voltage VM only during this period. Thereafter, by transferring the signal charges read out by the above-described operation, the signal charges in all the photoelectric conversion regions 1 are read out.

〔Effect of the invention〕

As explained above, the present invention applies intermediate voltage VM f to the vertical shift registers on both sides adjacent to the vertical shift register electrodes to which the high voltage VH, which can receive and receive signal charges, is applied when reading signal charges. During vertical blanking, the voltage applied between adjacent electrodes is kept low, which prevents electrostatic damage between adjacent electrodes and prevents malfunctions.

Further, although the present invention has been described with respect to an interline method, it goes without saying that it can also be applied to an interline frame transfer method.

[Brief explanation of drawings]

Fig. 1 is a timing chart of a charge transfer lock according to an embodiment of the present invention, Fig. 2 is a schematic plan view of a cell of a two-dimensional interline transfer type charge-coupled image sensor, and Fig. 3 is a conventional charge transfer lock. FIG. 4 is a sectional view taken along line AA' in FIG. 2. DESCRIPTION OF SYMBOLS 1...Photoelectric conversion area, 2...Vertical shift register area, 3...Transfer gate area, 4.5°6.7...Electrode, 8・・・・・・
Channel stop, 9...first layer polysilicon, 10...second layer polysilicon. Figure 3

Claims (1)

[Claims] One of the binary-level charge transfer clock pulses applied to the charge-coupled shift register of a charge-coupled device having a photoelectric conversion region on a semiconductor substrate and a charge-coupled shift register for transferring signal charges generated in the photoelectric conversion region. During the period in which charges are read from the photoelectric conversion region to the charge-coupled shift register by setting the voltage higher than the binary level, the transfer on both sides adjacent to the transfer electrodes to which the high-voltage charge transfer clock pulse is applied is performed. A method for driving a charge-coupled device, characterized in that the voltage of a charge transfer clock pulse applied to an electrode is set to a higher voltage level among the two levels.