JP2630492B2 - Solid-state imaging device - Google Patents

Description

The present invention relates to a charge-coupled solid-state imaging device (CCD),
In particular, the present invention relates to a charge-coupled solid-state imaging device having an electronic shutter function, improving the resolution in the vertical scanning direction, and further including a shift register for performing a novel scanning readout for realizing the improvement in the resolution.

[Conventional technology]

2. Description of the Related Art As a charge-coupled solid-state imaging device, a frame transfer type solid-state imaging device (FT-CCD) to which scanning readout by an accordion transfer method is applied is conventionally known (PHILIPS TEC).
HNICAL REVIEW VOL.43, No.1 / 2,1986, The accordion ima
ger, a new solid-state image sensor, AJPTheuwiss
en and CHLWeijtens).

The outline of this solid-state imaging device will be described with reference to FIGS. 16 to 21. First, as shown in FIG. 16, the overall configuration is m vertical transfer paths L ₁ having a photoelectric conversion function and a charge transfer function.
A light receiving portion A consisting ~L _m, a storage unit B to the light-shielding film in these vertical transfer path L ₁ is continuously to ~L _m and the surface is made of a laminated charge transfer paths, each charge accumulation unit B transfers A horizontal charge transfer path C connected to the end of the path and covered with a light-shielding film is provided.

On the upper surface of the vertical charge transfer paths L ₁ ~L _m, the transfer gate electrode, so as to correspond one by one for each pixel, are arranged along the charge transfer direction Y, accordion transferred to these gate electrodes by applying a gate signal of a predetermined timing in accordance to method, the time of exposure to generate potential wells and potential barriers corresponding to the pixels in the vertical transfer path L ₁ ~L _m, at a predetermined timing potential wells and potential barriers during transfer By changing it, charge transfer is performed in the Y direction.

The shift register indicated by reference symbol D in the figure performs the transfer operation of the start pulse IM in synchronization with the two-phase clock signals φ ₁ and φ ₂ , thereby generating the gate signal.

The charge transfer path of the storage section B is also provided with a similar gate electrode, and the shift register E is provided with two-phase clock signals φ ₁ , φ ₂
The charge is transferred in the Y direction by the gate signal formed by performing the transfer operation of the start pulse ST in synchronization with the operation.

Then, the pixel signal generated by the light receiving portion A, was temporarily held charge transfer path of the vertical charge transfer paths L ₁ ~L _m and the storage section B is transferred to the storage unit B synchronously, the storage unit B The pixel signals are transferred one row at a time to the horizontal charge transfer path C, and each time one row is transferred, the horizontal charge transfer path C performs horizontal charge transfer in synchronization with a gate signal at a predetermined timing, so that all pixel signals are chronologically transferred. read out.

FIG. 17 shows the timing of each signal for scanning and reading. As shown in FIG. 3A, the start pulses IM and ST are supplied to the shift registers D and E at predetermined timing.
And transfer them in synchronization with the two-phase clock signals φ ₁ and φ ₂ , as shown in FIG. 1B, the gate electrodes of the vertical charge transfer paths L _{1 to} L _m of the light receiving section A. The gate signals A _I , B _I , C _I , D _I , ... from each bit output contact of the shift register D
Are supplied in order, and similarly, as shown in FIG. 3C, the gate signals A _S , B _S , C from the respective bit output contacts of the shift register E are applied to the gate electrode of the charge transfer path of the storage section B. _S , D _S ,
Are supplied in order. For convenience of explanation, only gate signals corresponding to eight gate electrodes are shown.

These gate signals A _I , B _I , C _I , D _I ,…, A _S , B _S , C _S , D _S ,
According to the voltage change of…, as shown in FIG. 18, each gate electrode (even-numbered gate electrode
Ev, the odd-numbered gate electrode is indicated by Od)
Potential wells and potential barriers to transfer in order from the pixel signal q _a horizontal charge transfer path C side changes.

Therefore, the charge transfer of a certain vertical charge transfer path and the charge transfer path of the storage section B connected to the certain vertical charge transfer path can be represented as follows.
It looks like Figure 19. That is, when it is assumed to be exposed at a certain point in time t _0, the light receiving portion A in accordance with the arrangement of the gate electrodes in the vertical charge transfer path potential well (in the drawing ■ mark portion) and a potential barrier (in FIG □ mark ) Occur alternately, and the pixel signals q _a , q _b ,
q _c , q _d ... occur. And these pixel signals are
Most storage unit storage unit B from the side of the pixel signal q _a sequentially near to B
Will be transferred to Since the appearance of the potential well and the potential barrier at the time of this transfer is similar to that when the accordion of the musical instrument is gradually expanded and then closed again, it is called an accordion transfer method.

Then, after temporarily storing all the pixel signals in the storage section B, the storage section B similarly stores the gate signals A _S , B from the shift register E.
_S, C _S, D _S, while performing accordion transferred in synchronization with ...... reading the pixel signals via the horizontal charge transfer path C in time series.

This charge-coupled solid-state imaging device using the scanning readout method has an effect that the number of transfer gate electrodes can be reduced, and is excellent in high density.

[Problems to be solved by the invention]

However, such a conventional accordion transfer type solid-state imaging device has a so-called frame transfer (FT) type structure in which a vertical charge transfer path in a light receiving unit has a photoelectric conversion function as a pixel. Therefore, there is a lot of smear, and the vertical charge transfer path is formed in the P-type substrate, so that the function of the vertical overflow drain and the so-called electronic shutter without substrate cannot be exhibited. Integrated video tape recorder (VTR),
This has made application to electronic still cameras and other imaging devices difficult.

Therefore, in the case of a P-well structure having such a function, as a shift register for forming a gate signal for realizing accordion transfer type charge transfer, a twenty-fourth shift register is used.
It is common to apply a circuit configuration as shown in the figure, but there are the following problems.

That is, first, the circuit configuration will be described with reference to FIG.
Each bit of the shift register has a cell structure as shown by each circuit within a dotted line, and an appropriate number of circuits of this cell structure are cascaded to realize the shift register. As a representative example of the circuit of the first-stage cell, three NMOS transistors u ₁₁ , u ₁₂ , and u ₁₃ are connected between the signal line of the second clock signal φ ₂ and the ground contact with the source / drain path in series. as well as connecting to a capacitor C ₁₁ with a capacitance of the gate oxide film layer is connected between the gate contact and the source contact of the transistor u _11, a gate contact and a drain contact of the transistor u ₁₂ is short-circuited, the other NMOS Transistor u
₁₄ drain paths as well as connections between the source contact and the ground contact point of the transistors u _11, its gate contacts are connected to the first clock signal phi ₁ signal line. Further, NMOS transistors u ₁₅ , u ₁₆ , u ₁₇ , u ₁₈ and a capacitor C
It has a similar circuit consisting of _12, the drain contact of the transistor u ₁₃ of the first circuit is connected to the gate contact of the transistor u ₁₅ of the second circuit.

The gate contact of the transistor u ₁₁ is input contact,
Drain contact output contact of the transistor u _17, the gate contacts of the transistors u ₁₃ and u ₁₇ is reset contacts, a circuit having such a cell structure, input contacts and output contacts of each is to be connected to the subordinate In addition to the wiring, the start pulse signal IM (or ST) is supplied to the first clock signal φ.
NMOS transistor u _{00 that} operates on and off in synchronization with ₁
It is wired so as to supply to the gate contact of the transistor u ₁₁ of the first stage of the cell through the.

Furthermore, in a combination of cells connected in a subordinate relationship to each other, for example, as shown in cells SE ₁ and SE ₂ , the previous cell
While connected to the source contact of the first circuit of the transistor u ₁₁ cells SE ₂ after a gate contact of the first circuit of the transistor u ₁₃ of SE _1, front of the second circuit cell SE ₁ transistor second cell SE ₂ after a gate contact of u ₁₇
Th is connected to the source contact of the transistor u ₁₅ of the circuit.

The last cell is provided with a termination circuit as shown.

Each transistor u ₁₅ respective bit outputs a signal generated in the source contact A _I of in each _{cell, B I, C I, D} I ...... or A _S,
Are applied to the transfer gate electrodes of the light receiving section A and the storage section B as B _S , C _S , D _S.

The timings of these bit output signals, the clock signals φ ₁ , φ ₂ and the start pulse signal are as shown in FIG.

In such a conventional shift register, the time t ₀ of FIG. 21, t _1, as t _2, the clock signal phi ₁ or phi ₂ of 2 each bit output for each period A _I, B _I, C _I , D _I …… or A _S , B _S , C _S ,
Since D _S ...... outputs, obtained only half the transfer rate with respect to the frequency of the clock signal phi ₁ or phi _2. This means that clock signals φ ₁ and φ ₂ having twice the frequency of the charge transfer frequency in the vertical direction are required. Circuits are required, leading to technical difficulties.

In addition, since the entire shift register is not reset unless the first start pulse signal reaches the cells of the final group, it is not possible to perform control such as resetting the shift register at an appropriate timing by some external control. For this reason, there were problems such as poor controllability. The present invention has been made in view of such conventional problems, and has an electronic shutter function and realizes a high vertical resolution. It is an object of the present invention to provide a solid-state imaging device including a shift register that generates a gate signal for performing a new scan readout.

[Means for solving the problem]

In order to achieve such an object, the present invention forms a plurality of photoelectric conversion elements corresponding to pixels in a matrix in a row direction and a column direction, and adjoins each photoelectric conversion element group arranged in a column direction. Forming a vertical charge transfer path, transferring a pixel signal generated in a pixel to the vertical charge transfer path, and then supplying a gate signal at a predetermined timing output from the shift register to a transfer gate electrode of the vertical charge transfer path. , And vertically transfers pixel signals for each row, and scans and reads out pixel signals for each row through a horizontal charge transfer path.

In such a charge-coupled solid-state imaging device, the shift register is connected in series with each other between the first timing signal and the predetermined voltage line via each source / drain path. Transistor, a bootstrap capacitor connected between the gate and source of the first transistor, a second timing signal is applied to the gate contact, and the drain contact is connected to both the gate and drain of the second transistor. And a fourth transistor having a source contact connected to the voltage line and a second transistor connected to the voltage line.
Fifth, sixth, and seventh transistors connected in series with each other between the timing signal and a predetermined voltage line via respective source / drain paths, and a boot connected between the gate and source of the fifth transistor A strap capacitor, and an eighth transistor to which a first timing signal is applied to a gate contact and whose drain contact is connected to both the gate and drain contacts of the sixth transistor and whose source contact is connected to the voltage line. Wherein the connection contact of the second and third transistors and the gate contact of the fifth transistor are connected, the gate contact of the first transistor is an input contact, and the connection contact of the sixth and seventh transistors is an output contact A plurality of bit circuits having a cell structure are wired so that the input contact and the output contact are subordinately connected to each other, and the input contact of the lowest bit circuit is connected. A start pulse signal is applied via a switching element which is turned on / off in synchronization with the second timing signal, and a reset signal is applied to the gate contacts of the third and seventh transistors of each bit circuit;
A bit signal generated at the output contact of each bit circuit is supplied to each of the transfer gate electrodes.

[Action]

According to the solid-state imaging device of the present invention having the shift register having such a circuit configuration, only the first bit output signal is at “H” level, and all other upper bit outputs are at “L” in synchronization with the timing signal. Level, and in the next cycle, the lower 2 bit output signal becomes “H” level and all other upper bit outputs become “L” level, and in the next cycle, the lower 3 bit output signal becomes “H” level. Therefore, the output level of the bit output signal changes so that the "H" output level of the bit output signal gradually increases from the lower bit to the upper bit, such that all the other upper bit outputs become "L" levels.

The output of each bit changes in synchronization with the frequency of the timing signal, and can be reset at an appropriate time by a reset signal.

〔Example〕

Hereinafter, an embodiment of a charge-coupled solid-state imaging device according to the present invention will be described with reference to the drawings. A case where the present invention is applied to an electronic still camera for capturing a still image will be described.

First, the overall structure of an electronic still camera will be described with reference to FIG. 1. In FIG. 1, 1 is an imaging optical system including an imaging lens and the like, 2 is a mechanical diaphragm mechanism, and 3 is a charge-coupled type to which the present invention is applied. These are solid-state imaging devices, each of which is arranged in order along the optical axis of the imaging optical system 1 and in which an optical image of a subject is incident on a light receiving region of the charge-coupled solid-state imaging device 3.

Further, reference numeral 4 denotes a signal processing circuit, and 5 denotes a recording mechanism. The signal processing circuit 4 performs color separation, γ correction, white balance adjustment, and the like on a pixel signal output from the charge-coupled solid-state imaging device 3 and outputs a luminance signal. A color difference signal is formed, and the recording mechanism 5 performs a recordable modulation process on the luminance signal and the color difference signal, and then records the signal on a magnetic recording medium or the like.

The synchronization control circuit 6 controls a series of operations from imaging to recording by synchronously controlling the readout timing of the aperture mechanism 2, the charge-coupled solid-state imaging device 3, and the operations of the signal processing circuit 4 and the recording mechanism 5. I do.

The charge-coupled solid-state imaging device 3 has a configuration shown in FIG. 2, and is integrally formed in the same semiconductor chip.

That is, the light receiving area 7 for receiving the subject optical image is:
A plurality of photodiodes corresponding to pixels arranged in a matrix along the column direction Y and the row direction X (in the figure,
A portion) indicated by P, the vertical charge transfer paths L ₁ ~L _m formed adjacent to each photodiode group arranged in the column direction Y are provided.

Horizontal charge transfer path 8 is formed at the end of each of these vertical charge transfer paths L ₁ ~L _m, an output amplifier 9 at the end of the horizontal charge transfer path 8 is formed.

Further, the vertical charge transfer paths L ₁ ~L _m, the gate electrode of the predetermined arrangement is provided as will be described later, it is further laminated shielding layer for preventing incidence of light on their upper surface.

These gate electrodes, a signal for causing the charge transfer operation in synchronism with a predetermined timing in the vertical charge transfer paths L ₁ ~L _m first, second, third driver circuits 10, 11, 12 Supplied. The timing signals φ _H , φ _L , φ _G , φ _FS , V _S , φ ₁ , φ ₂ , φ ₃ , φ ₄ , φ _A , φ _B supplied to the respective drive circuits 10, 11, 12
A start pulse signal phi _S is the synchronization control circuit 6 is generated.

Moreover, the horizontal charge transfer path 8 receives the forwarded come signal charges from the vertical charge transfer paths L ₁ ~L _m, and further a gate electrode for horizontal transfer is provided to the output amplifier 9 side, these Gate signals α ₁ , α ₂ , α ₃ , α ₄ to be applied to the gate electrodes for performing the operation are supplied from the synchronization control circuit 6.

Next, the structure of the light receiving area 7 and the driving circuit connected thereto
The circuit configurations of 10, 11, and 12 are shown in FIG. 3, FIG. 4, FIG.
This will be described in detail with reference to the drawings. FIG. 3 shows the structure of the main part of the light receiving region 7 when viewed from the light receiving surface side, and FIG. 4 shows xx in FIG.
FIG. 5 is a vertical sectional view taken along the line yy of FIG. 3, and FIG. 6 is a shift register circuit corresponding to the drive circuit 12.

First, in FIGS. 3 to 5, a p-well layer 14 for forming the light receiving region 7 is formed on the surface side of the n-type semiconductor substrate 13.
A p-well layer 15 for forming the first drive circuit 10,
A p-well layer 16 for forming the second and third drive circuits 11 and 12 is buried, and predetermined circuits to be described later are formed in the p-well layers 14, 15, and 16, respectively.

First, the light receiving region 7 is formed by arranging a plurality of impurity layers 17 made of n ^{+ -type} impurities in a p-well layer 14 in a matrix along the column direction Y and the row direction X, thereby forming a P-type region shown in FIG. Are formed. Further, by forming an n-type impurity layer (portion shown by a dotted line in FIG. 5) 18 adjacent to each impurity layer 17 arranged in the column direction Y, the vertical charge transfer path L _{1 in} FIG. ~L _m is formed. Then, ap _{+ -type} impurity layer 19 is formed around the portion excluding the portion serving as the transfer gate indicated by Tg (only one portion is shown), the photodiode portion, and the vertical charge transfer path portion. Thus, a channel stopper region (a hatched portion surrounded by a dotted line in FIG. 3) is formed.

In the third drawing shows in _{P 1, P 2, P 3} , P 4 ...... photodiodes P in FIG. 2 for each row. Further, in FIG. 3, on the upper surfaces of the vertical charge transfer paths L _{1 to} L _m , the regions adjacent to the photodiodes P ₁ , P ₂ , P ₃ , P ₄ ... to manner, the gate electrode G ₁₁ ~G ₄₁ consisting of separate polysilicon layer by _{two, G 12 ~G 42, G 13} ~G
₄₃ ,... G _{1n to} G _4n are stacked. Further, the gate electrode G
_Assuming that ₁₁ is the first gate electrode, as shown in FIGS. 3 and 4, the odd-numbered gate electrodes G ₁₁ , G ₃₁ , G ₁₂ , G ₃₂ ,
The width W1 of G ₁₃ , G ₃₃ ,...
_{21, G 41, G 22,} G 42, G 23, G 43, are wider form width W2 of ....

Then, a gate signal φ ₁₁ , φ ₂₁ , φ ₃₁ , φ ₄₁ , φ ₁₂ , φ ₂₂ , φ ₃₂ , at a later-described predetermined timing is applied to each gate electrode.
By applying φ ₄₂ ,..., a potential well (hereinafter referred to as a transfer pixel) and a potential barrier for charge transfer are generated in a vertical charge transfer path below each gate electrode. Also, even-numbered gate electrodes _{G 21, G 41, G 22} , G 42, G 23,
When a predetermined high-voltage signal is applied to G ₄₃ ,..., The transfer gate Tg becomes conductive, and each photodiode
Transfer pixels generated under even-numbered gate electrodes G ₂₁ , G ₄₁ , G ₂₂ , G ₄₂ , G ₂₃ , G ₄₃ ,... Adjacent to P ₁ , P ₂ , P ₃ , P _4. Are in a conductive state, and a signal charge can be transferred from the photodiode to the transfer pixel.

Furthermore, as shown in Figure 3, the horizontal charge transfer path 8 is formed at the end portion of the vertical charge transfer paths L ₁ ~L _m, horizontal timing signal charge according to the four-phase drive method or the two-phase driving mode A gate electrode for transfer to the gate electrode.

Next, the circuit configuration of the first drive circuit 10 is shown in FIGS.
It will be described with reference to the drawings. When the gate electrode G ₁₁ closest to the horizontal charge transfer path 8 and the first gate electrode, the odd-numbered gate electrodes _{G 11, G 31, G 12} , G 32, G 13, G 33, the tip of the ...... Department
Connected to the signal line of the signal _VL via NMOS transistors M ₁₁ , M ₃₁ , M ₁₂ , M ₃₂ , M ₁₃ , M ₃₃ ,..., And the even-numbered gate electrode G
_{21, G 41, G 22,} G 42, G 23, G 43, the tip NMOS transistor M ₂₁ of _{......, M 41, M 22,} M 42, M 23, M 43, through ..., It is connected to the signal line of the driving signal phi _H. Further, the gate contact of these transistors, the driving signal phi _G is supplied.

Furthermore, the even-numbered gate electrodes _{G 21, G 41, G 22} , G 42, G 23, G
₄₃ , ... npn transistors Q ₂₁ , Q ₄₁ , Q ₂₂ ,
_{Q 42, Q 23, Q 43} , and connect the respective emitter contact of ..., the timing signal phi _FS the base contacts of each npn transistor, the collector contact voltage V _S is applied.

These NMOS transistors have a pair of n ^{+ -type} impurity layers 2 as shown in the structure in the P-well layer 15 in FIG.
0, 21 and a structure in which a gate electrode is laminated on a surface portion, and a drive signal φ _H is applied to an n ^{+ -type} impurity layer 20 serving as a drain contact.
Is applied, and the n ^{+ -type} impurity layer 21 serving as the source contact is connected to the gate electrode on the vertical charge transfer path. The signal _VL is applied to the p ^{+ -type} impurity layer 22 embedded in the p-well layer 15. Further, npn transistors, a p-well layer p ⁺ -type impurity layer 23 buried in the 15 and n ⁺ type impurity layer 24 and the n-type semiconductor substrate 13, n ⁺ -type impurity layer 24 serving as the emitter contact each gate connected to the electrode, the timing signal phi _FS to the p-well layer 15 and the p ⁺ -type impurity layer 23 serving as a base contact is applied, the bias voltage V _S for the substrate is applied to the n-type semiconductor substrate 13 as a collector contact You.

Next, the second drive circuit 11 converts the timing signals φ _{1 to} φ ₄ supplied from the synchronization control circuit 6 to the drive signals S ₁ , S ₂ , S ₃ , S ₄ ,. ... consists NMOS transistors _{m 11, m 21, m 31} , m 41 ...... which switching operation in synchronization with the S _n,
A set of four NMOS transistors is provided, and the drive signals S ₁ , S ₂ ,
S _3, S ₄ ...... is applied, the first NMOS transistor m ₁₁ of each _{set, m 12, m 13, m} 14 timing signal to the drain contact of the ...... φ _1, the second NMOS transistor m ₂₁ , m ₂₂ , m ₂₃ , m
₂₄ timing signal phi ₂ to the drain contacts of _..., the third NMOS transistor _{m 31, m 32, m 33} , m 34 ...... timing signal phi ₃ to the drain contacts _of the fourth NMOS transistor
_{m 41, m 42, m 43} , the timing signal phi ₄ to the drain contacts of m ₄₄ ...... is supplied. In FIG. 3, the signals φ ₁₁ , φ on the source contact side of the NMOS transistors m ₁₁ , m ₂₁ , m ₃₁ , m ₄₁ ...
_21, phi _31, the timing signal phi ₁ is _{φ 41 ......, φ 2, φ} 3, a signal corresponding to phi _4.

As shown, the source contact of each NOMS transistor in order from the gate electrode G ₁₁ closest to the horizontal charge transfer path 8 is connected.

Next, the third drive circuit 12 will be described with reference to FIGS. Drive circuit 12, by transferring in synchronization with the start pulse signal phi _S and a timing signal phi _A-shifted two-phase phi _B, sequentially logic values from the lower bit output to the upper bit output "H" of This is a shift register that generates a drive signal. That is, as shown in FIG.
Only S ₁ is "H" level, all other upper bits output becomes "L" level, the drive signals S ₁ of the lower 2 bits in the next cycle
Other upper bits output S ₂ is "H" level, becomes all "L" level, further the drive signals S ₁ of the lower 3 bits in the next cycle
S ₂ and S ₃ is "H" every other upper bits output at the level "L"
The output level changes so that the “H” output level of the drive signal gradually increases from the lower bits to the upper bits.

In FIG. 6, since each bit has a cell structure, a circuit will be described as a representative of the circuit of the first bit.
Three MOS transistors u _11, u _12, u ₁₃ is connected between the signal line of the signal line and the timing signal phi _B of the voltage V _L as a serial source-drain path, the gate contact of the transistor u ₁₃ is reset signal Connect the φ _RS signal line. Transistor u
Bootstrap capacitor epsilon ₁₁ is between the gate contact and source contact ₁₁ is connected, together with the gate and drain contacts of the transistor u ₁₂ is commonly connected, and connected to the drain contact of the other MOS transistor u _14, transistor u
₁₄ source contact signal line voltage V _L, the gate contact is respectively connected to a signal line of the timing signal phi _A.

Further, a circuit having the same configuration as the circuit configured by the MOS transistors u ₁₁ , u ₁₂ , u ₁₃ , and u ₁₄ is formed by MOS transistors u ₂₁ , u ₂₂ , u ₂₃ , and u ₁₄ .
₂₄ and a capacitor ε ₂₁ for bootstrap,
Transistor source contact (output point) of u ₁₂ and gate contact of the transistor u ₂₁ (input point) are connected. However,
The connection of the timing signals φ _A and φ _B is reversed.

Then, the input corresponds to the gate contact of the transistor u _11, the output corresponds to the source contact of the transistor u _22. Then, a shift register of n bits output by cascading the inputs and outputs of these bit cells, the input of the start pulse signal phi _S to the lowest bit cell includes a conducting state in synchronism with the timing signal phi _A It is adapted to perform via the analog switch u ₀₀ made.

As described above, the shift register having such a configuration, for example, as shown in FIG. 7, when a certain period of time t ₀ ~t a start pulse signal phi _S in _n "H" level, in synchronism with the timing signal phi _A And the lower bit output S ₁
The "H" level to turn toward the output S _n of most significant bits from. Also, reset signal φ _{RS is set} to “H” at appropriate timing.
Level, all bit outputs S ₁ to
The S _n can be reset to "L" level.

Each contact i _{1 of} the internal circuit forming each bit in FIG.
Signal generated through i _9, etc., a waveform as shown in FIG. 8, in particular bootstrap capacitor epsilon _11, epsilon _21, transistor u ₁₁ by ......, u _21, ...... gate contact i _1, i ₃ ,
i _7, i _9, the voltage of the ...... becomes higher as shown, it is possible to obtain a rectangular-bit output signal S ₁ to S _n which is shaped by sufficient amplitude.

Next, a case where the operation of the charge-coupled solid-state imaging device having such a structure is applied to an electronic still camera that captures a still image will be described.

First, a schematic operation for photographing a still image will be described with reference to FIG. _Assuming that a period _TVB in the figure corresponds to a vertical blanking period of a standard television system such as NTSC, a so-called field shift operation of moving from a pixel to a vertical charge transfer path at a predetermined time during the period _TVB is performed. If the time point of the field shift operation corresponds to the time point of closing the shutter (ie, the time point of completion of exposure), an electronic shutter function can be obtained. Therefore, control is performed such that the exposure operation is started at this point in time and before the start of the field shift operation is the exposure period.

Furthermore, to become such unwanted charge the vertical charge transfer paths L ₁ ~L _m and smear components and dark current components in the horizontal charge transfer path 8 is swept out by the charge transfer operation before the start of the field shift operation. Further, just before the start of exposure, unnecessary charges in the photodiode are completed by being discarded to the substrate side by the vertical overflow drain structure.

In a period T _VB corresponding to the vertical blanking interval of the standard television system such as NTSC, and transferred to the transfer pixels simultaneously the vertical charge transfer paths L ₁ ~L _m pixel signals of all the photodiodes, the next horizontal In a period _THB corresponding to a blanking period, a pixel signal of a transfer pixel closest to the horizontal charge transfer path 8 is transferred to the horizontal charge transfer path 8, and then corresponds to a horizontal scanning period (a so-called 1H period). Period T _1H
, The horizontal charge transfer path 8 horizontally transfers the pixel signals of one row to read out the pixel signals of the first row.

Then, a period T corresponding to the next horizontal blanking period
In _HB, the vertical charge transfer paths L ₁ ~L _m forwards the pixel signal of the next line to the horizontal charge transfer path 8, further horizontal charge transfer path 8 horizontal in the period T _IH corresponding to the next horizontal scanning period By the transfer, the pixel signals in the second row are read.

Further, it reads the pixel signal of the third row in each period T _HB and T _IH corresponding to the next horizontal blanking period and the horizontal scanning period. Then, the pixel signals in the remaining rows are sequentially read out by repeating the same processing, and finally all the pixel signals corresponding to one frame image are read out.

Next, the scanning read operation will be described in detail with reference to the timing chart of each drive signal and timing signal shown in FIG. Note that the period _{TVB in} FIG. 10 corresponds to the vertical blanking period, the period _{THB corresponds} to the horizontal blanking period, and the period _T1H corresponds to the horizontal scanning period. In the drawing, "H" indicates 12 volts, "M" indicates 0 volts, "L" indicates -8 volts, and "HH" indicates a voltage level of about 15 to 25 volts, which is equal to the voltage of the substrate.

First, in the period T _VB corresponding to the vertical blanking period, the timing signal phi _H and phi _G at a predetermined time t ₂ "H"
The level becomes "M" level outside the
_FS is at the “L” level except when the timing signal φ _H is at the “H” level in synchronization with the “H” level, and all drive signals output from the third drive circuit (shift register) 12 S ₁ ~S _n is always "L" level.

Therefore, in the period T _VB, the "H" and "M" level of the timing signal phi _G, all the NMOS transistors of the first drive circuit 10 is turned, while all of the third driving circuit 12 Since the drive signals S ₁ , S ₂ , S ₃ ... _Sn are at “L” level, all the NMOS transistors in the second drive circuit 11 are turned off, and all the gate electrodes G ₁₁ , G ₂₁ , G
₃₁ , G _{41 to} G _1n , G _2n , G _3n , G _4n are controlled by the first drive circuit 10.

That is, when the timing signals φ _H and φ _FS do not become “H” level, the odd-numbered gate electrodes G ₁₁ , G ₃₁ , G ₁₂ , G _{32 to} G
_1n , gate signals applied to G _3n φ ₁₁ , φ ₃₁ , φ ₁₂ , φ ₃₂ ~
φ _1n and φ _3n are “L” level signals V _L (this signal is always −
8 volts is set to) the equal potential barrier is generated in these vertical charge transfer paths L ₁ ~L _m beneath the gate electrode.

On the other hand, the even-numbered gate electrodes _{G 21, G 41, G 22} , G 42 ~G 2n, G
Gate signals φ ₂₁ , φ ₄₁ , φ ₂₂ , φ _{42 to} φ _2n , applied to _4n
phi _4n is equal to the "M" level signal phi _H, transfers pixel is generated in these vertical charge transfer paths L ₁ ~L _m beneath the gate electrode.

Therefore, all portions (see FIG. 3) adjacent to the transistor gate Tg become transfer pixels, and these transfer pixels are separated by a potential barrier.

In this state, when the timing signals φ _H and φ _{FS attain the} “H” level at a predetermined time t ₂ , all the npn transistors Q ₂₁ , Q ₄₁ , Q _61, ... Since only the electrodes G ₂₁ , G ₄₁ , G ₂₂ , G _{42 to} G _2n , G _4n are applied with a voltage of about 12 volts “H” level, all the transfer gates Tg become conductive and all the photodiode pixels The signal is transferred to each adjacent transfer pixel.

As described in the timing of FIG. 9, exposed with just before the time point t ₂ is completed, also has been completed also disposal of unnecessary charges.

Thus, in the period T _VB, so-called field shift operation is performed, as shown at time t ₁ in Figure 14, each pixel signal (indicating a pixel signal is part of the closed symbols) of the vertical transfer path Moved. FIG. 14 shows a charge transfer operation of one certain vertical charge transfer path.

Next, a period T corresponding to the first horizontal blanking period
In _HB, the timing signal phi _G becomes the constant "L" level, all the NMOS transistors of the first drive circuit 10 becomes nonconductive, is separated from all of the gate electrode.

On the other hand, the drive signal of the first output terminal of the third drive circuit 12
Only S ₁ is "M" level, the other of the drive signals S ₂ to S _n is by the "L" level, the first pair in the NMOS transistors m involved in driving signals S ₁ in the second driving circuit 11 Only ₁₁ , m ₂₁ , m ₃₁ , and m ₄₁ are conducting.

Then, during the period of the driving signal by S ₁ is "M" level, the timing signal of 4 phases for performing vertical charge transfer φ
₁ , φ ₂ , φ ₃ , φ ₄ are input to the second drive circuit 11, so that the first to fourth first sets of gate signals φ ₁₁ , φ ₂₁ , φ ₃₁ ,
Only φ ₄₁ becomes equal to the timing signals φ ₁ , φ ₂ , φ ₃ , φ ₄ and the first to fourth gate electrodes G ₁₁ , G ₂₁ , G of the first set.
_31, and thus performing the charge transfer operation in G _41. This period
The signal waveforms of T _HB (the period up to the time t ₃ ~t ₄₎ shown enlarged in FIG. 11.

As a result, the signal charges are changed to the gate signals φ ₁₁ and φ of FIG.
_21, phi _31, the first horizontal charge transfer path 8 side as the transfer of that shown in FIG. 14 in accordance with the timing of phi ₄₁ (indicated by 4, 5, 6, 7 code) The pixel signal q _1j of the first row closest to the horizontal charge transfer path 8 is transferred to the horizontal charge transfer path 8 and the pixel signal q _2j of the second row moves to the position of the first row. I do.

Next, in the first horizontal scanning period T _1H (time period from t _{4 to} t ₅ ), the change of the signal to the gate electrode is stopped.
The horizontal charge transfer path 8 performs horizontal transfer in synchronization with gate signals α _{1 to} α ₄ at predetermined timings according to the four-phase driving method or the two-phase driving method, thereby reading out the pixel signals of the first row.

Next, in a period of time t ₅ ~t _7, by repeating the same operation as the time t ₃ ~t _5, reading out pixel signals of the next line. However, the horizontal blanking period from time t ₃ ~t ₄ T
In _HB, the third drive signals S ₁ and S ₂ are simultaneously "M" level of the drive circuit 12, the remaining drive signals S ₃ to S _n becomes "L" level. The waveform of each gate signal during this period _THB is shown in an enlarged manner in FIG.

As a result, the first to fourth first set of gate electrodes G ₁₁
And ~G _41, fifth to eighth second set of gate electrode G ₁₂ ~G
₄₂ is a gate signal φ equal to the timing signals φ _{1 to} φ _4
11 will be driven by to [phi] ₄₁ and phi ₁₂ to [phi] _42,
Pixel signals under these gate electrodes are vertically transferred.

That is, according to the timing shown in FIG. 12, as shown by the second vertical scanning in FIG.
_2j is transferred to the horizontal charge transfer path 8, and q _3j in the third row is transferred to the horizontal charge transfer path 8 side, and q _{4j in} the fourth row is transferred to the horizontal charge transfer path 8 side.

Then, in the horizontal scanning period T _IH time t ₆ ~t _7, the horizontal charge transfer path 8 reads the pixel signals q _2j of the second row.

Then, from the time t ₇ when starting the third time scan reading, third drive signals S ₁ of the drive circuit 12, S ₂ and S ₃ is a "M" level, the remaining drive signal S ₄ to S _n Becomes the "L" level, so that the first to twelfth gate electrodes G of the first to third sets are set.
_{11 ~G 41, G 12 ~G 42} , G 13 ~G 43 vertical charge by the transfer is performed. Accordingly, the pixel signals q _3j in the third row are transferred to the horizontal charge transfer path 8 as in the third transfer in FIG. 14, and the pixel signals q _4j , q _{5j in the} fourth to seventh rows are transferred. , q _6j , q
_7j are transferred to the horizontal charge transfer path 8 side by row.

Then, the pixel signal q _{3j in} the third row is read out by the horizontal charge transfer path 8.

Thereafter, each read out each row of pixel signals, the third by a drive signal S ₄ to S _n of the drive circuit 12 is gradually inverted "M" level in sequence, the drive is transferred pixels below the gate electrodes There will sequentially expand the four by four as a set, the last horizontal blanking period T _HB (time t ₉ ~t _10), as shown in FIG. 13, all the gate signal phi ₁₁ to [phi] _4n The waveform becomes equal to the timing signals φ _{1 to} φ ₄ , and the pixel signal of the last row can be read by the last scan reading.

FIG. 15 shows an arbitrary order, that is, the k-th and (k + 1) -th vertical charge transfer operations by a potential profile. As shown in FIG. 15, the transfer pixels on the horizontal charge transfer path 8 side are sequentially enlarged or enlarged. As the interval between the transfer pixels in the empty state increases, the pixel signals closer to the horizontal charge transfer path 8 are sequentially read out.

As described above, according to this embodiment, a pixel signal corresponding to one frame image can be read by one frame scanning read.

Further, in this embodiment, since the even-numbered gate electrode width is wider than the odd-numbered gate electrode width, the charge holding capacity of the transfer pixel adjacent to the transfer gate can be increased. Since charge transfer is always performed in the transfer pixels below the even-numbered gate electrodes, transfer efficiency is improved.

Further, since the shift register corresponding to the third driving circuit generates each bit output signal at the same frequency as the frequency of the timing signal, it is not necessary to increase the timing frequency as in the prior art. Can be performed at an appropriate timing.

In this embodiment, the period T _HB corresponding to each horizontal blanking period, but to perform the charge transfer in synchronism with the timing signal phi ₁ to [phi] ₄ of 4 phase, appropriate number of four or more phases The timing signal described above may be used to drive the gate electrode according to the number of phases.

〔The invention's effect〕

As described above, according to the charge-coupled solid-state imaging device of the present invention, the shift register generates each bit output signal at the same frequency as the frequency of the timing signal.
There is no need to increase the timing frequency as before,
In addition, reset control can be performed at an appropriate timing, and controllability is improved.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an electronic still camera to which a charge-coupled solid-state imaging device according to an embodiment of the present invention is applied, FIG. 2 is a schematic configuration diagram of a charge-coupled solid-state imaging device of the embodiment, and FIG. FIG. 4 is an explanatory view showing a main part structure and a peripheral circuit configuration of a light receiving region in the embodiment, FIG. 4 is a vertical sectional view taken along line xx in FIG. 3, and FIG. 5 is a line yy in FIG. FIG. 6 is a diagram showing the circuit configuration of the shift register, FIGS. 7 and 8 are timing charts showing the operation of the shift register, and FIG. 9 is a schematic diagram showing the scanning read operation of the embodiment. FIG. 10 is a timing chart showing the scanning readout operation of the embodiment in detail, and FIGS. 11, 12, and 13 are timing charts showing enlarged main part timings in FIG. FIG. 14 is a diagram conceptually showing a charge transfer operation at the time of scanning reading, and FIG. FIG. 16 is a diagram showing a charge transfer operation at the time of discharge with a potential profile, FIG. 16 is a structural explanatory view showing a main part structure of a conventional charge-coupled solid-state imaging device, and FIG. FIG. 18 is an explanatory diagram for explaining the operation timing, FIG. 18 is an explanatory diagram for explaining the operation of the conventional charge-coupled solid-state imaging device with a potential profile, and FIG. 19 is an explanation for the operation of the conventional charge-coupled solid-state imaging device. FIG. 20 is a circuit diagram of a conventional shift register, and FIG. 21 is a timing chart for explaining operation timing of the conventional shift register. 1; imaging optical system 2; mechanical diaphragm mechanism 3; charge-coupled solid-state imaging device 4; signal processing circuit 5; recording mechanism 6; synchronization control circuit 7; light receiving area 8; horizontal charge transfer path 9 ; output amplifier 10; the first driving circuit 11: second driving circuit 12; a third driving circuit (shift register) L ₁ ~L _m; vertical charge transfer path _{M 11, M 21, M 31} , M 41 ~ NMOS transistors m ₁₁ , m ₂₁ , m ₃₁ , m ₄₁ N; NMOS transistors G ₁₁ , G ₂₁ , G ₃₁ , G ₄₁ ；; gate electrodes u _{00 to} u ₂₃ ; NMOS transistors

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kazuhiro Kawajiri 798 Miyadai, Kaisei-cho, Ashigara-gun, Kanagawa Prefecture Fuji Photo Film Co., Ltd. (56) References JP-A-61-214871 (JP, A)

Claims (1)

(57) [Claims] A plurality of photoelectric conversion elements corresponding to pixels are arranged in a matrix in a row direction and a column direction, and a vertical charge transfer path is formed adjacent to each photoelectric conversion element group arranged in a column direction. After the pixel signal generated in the pixel is transferred to the vertical charge transfer path, the gate signal at a predetermined timing output from the shift register is supplied to the transfer gate electrode of the vertical charge transfer path so that the pixel signal is In a charge-coupled solid-state imaging device that transfers and scans and reads out pixel signals for each row by a horizontal charge transfer path, the shift register includes a source connected between a first timing signal (φ _B ) and a predetermined voltage line. .First and serially connected to each other via a drain path
A second and third transistor (u ₁₁ , u ₁₂ , u ₁₃ ), a bootstrap capacitor (ε ₁₁ ) connected between the gate and source of the first transistor (u ₁₁ ), and a second gate connected to the gate contact. fourth transistor whose source contact with the timing signal (phi _a) is and its drain contact is applied is connected to the gate and drain both contacts of said second transistor (u ₁₂₎ is connected to the voltage line (u ₁₄ ), and a fifth, serially connected between the second timing signal (φ _A ) and the predetermined voltage line via each source / drain path.
A sixth and seventh transistor (u ₂₁ , u ₂₂ , u ₂₃ ), a bootstrap capacitor (ε ₂₁ ) connected between the gate and source of the fifth transistor (u ₂₁ ), eighth transistor whose source contact with the timing signal (phi _B) is and its drain contact is applied is connected to the gate and drain the contacts of the sixth transistor (u ₂₂₎ of the is connected to the voltage line (u ₂₄ ), wherein the connection contact of the second and third transistors (u ₁₂ , u ₁₃ ) and the gate contact of the fifth transistor (u ₂₁ ) are connected,
A gate contact of the first transistor (u ₁₁ ) as an input contact,
A plurality of bit circuits having a cell structure in which the connection contacts of the sixth and seventh transistors (u ₂₂ , u ₂₃ ) are output contacts are wired such that the input contacts and the output contacts are connected in a subordinate manner, and are located at the lowest position. _A start pulse signal is applied to the input contact of the bit circuit via a switching element which is turned on / off in synchronization with the second timing signal (φ _A ), and the third and seventh transistors ( A charge-coupled solid-state imaging device comprising a circuit configuration in which a reset signal is applied to a gate contact of u ₁₃ , u ₂₃ ) and a bit signal generated at an output contact of each bit circuit is supplied to each of the transfer gate electrodes. apparatus.