JPH05176234A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To provide a solid-state image pickup device operated at a high speed with respect to a charge coupled solid-state image pickup device having lots of picture elements. CONSTITUTION:The device includes lots of photoelectric conversion elements P arranged in a matrix, charge transfer lines L formed along each array of the photoelectric conversion elements and including plural gate electrodes and two sets of control circuits arranged to both sides of the array in the row direction and having an equal circuit function and two sets of drive circuits 10a, 11a, 12a and 10b, 11b, 12b applying an equal control signal to each gate electrode of the charge transfer path in two directions.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge-coupled solid-state image pickup device (CCD), and more particularly to a charge-coupled solid-state image pickup device having a large number of pixels.

[0002]

2. Description of the Related Art Conventionally, as a charge-coupled solid-state image pickup device,
A frame transfer type solid-state imaging device (FT-CCD) to which investigation readout by the accordion transfer method is applied is known (PHILIPS TECHNICAL REVIEW VOL.43, No.1 /
2, 1986, The accordion imager, a new solid-state
image sensor, AJPTheuwissen and CHLWeijten
s).

The outline of this solid-state image pickup device is shown in FIGS.
Will be explained together. First, as shown in FIG. 16, the overall structure includes a light receiving portion A including _m vertical transfer paths L _{1 to} L _m having a photoelectric conversion function and a charge transfer function, and these vertical transfer paths L _{1 to} L. _A storage part B formed of a charge transfer path continuous to _m and having a light-shielding film laminated on the surface, and a horizontal charge transfer path connected to the end of each charge transfer path of the storage part B and having a surface covered with a light-shielding film. It has C.

On the upper surfaces of the vertical charge transfer paths L _{1 to} L _m , several transfer gate electrodes are provided along the charge transfer direction Y so that one transfer gate electrode corresponds to each pixel. By applying a gate signal at a predetermined timing according to the accordion transfer method to these gate electrodes arranged in parallel, potential wells and potential barriers corresponding to pixels are generated in the vertical transfer paths L _{1 to} L _m during exposure,
During transfer, charges are transferred in the Y direction by changing the potential well and the potential barrier at a predetermined timing.

A shift register indicated by reference symbol D in the figure transfers the start pulse IM in synchronization with the two-phase clock signals φ ₁ and φ ₂ to generate the gate signal.

The charge transfer path of the storage section B is also provided with the same gate electrode, and is formed by the shift register E transferring the start pulse ST in synchronization with the two-phase clock signals φ ₁ and φ ₂ . The charge is transferred in the Y direction by the gate signal.

Then, the pixel signal generated in the light receiving portion A is
The vertical charge transfer paths L _{1 to} L _m and the charge transfer paths of the storage section B are synchronously transferred to the storage section B and once held, and then the pixel signals of the storage section B are transferred row by row to the horizontal charge transfer path C. Then, every time the charges are transferred, the horizontal charge transfer path C transfers the horizontal charges in synchronization with the gate signal from the shift register F, thereby reading all pixel signals.

Further, the timing of each signal for this scanning and reading is shown in FIG. As shown in FIG. 3A, the start pulses IM and ST are supplied to the shift registers D and E at a predetermined timing to generate a two-phase clock signal φ.
These are transferred in synchronization with ₁ and φ ₂ .

As shown in FIG. 1B, the gate signals A _I , B _I from the bit output contacts of the shift register D are connected to the gate electrodes of the vertical charge transfer paths L _{1 to} L _m of the light receiving area A, respectively.
C _I , D _I ... Are supplied in order.

Similarly, as shown in FIG. 1C, the storage unit B
Of the gate signals A _S , B _S , C _S , D _S from the bit output contacts of the shift register E to the gate electrode of the charge transfer path.
... are supplied in order. For convenience of explanation, only gate signals corresponding to eight gate electrodes are shown.

These gate signals A _I , B _I , C _I , D
_{I ......, A S, B S} , C S, D S according to the change in voltage ..., as shown in FIG. 18, Ev each gate electrode (the even-numbered gate electrodes of the storage unit B and the light-receiving unit A, The horizontal charge transfer path C is formed on the lower transfer path of the odd-numbered gate electrode indicated by Od.
The potential well and the potential barrier change so that the pixel signals q _a on the side are sequentially transferred.

Therefore, the charge transfer of a certain vertical charge transfer path and the charge transfer path of the storage portion B connected to it is represented as shown in FIG. That is, at a certain time point t ₀
If the exposure is carried out by, the potential well (hatched part in the figure) and the potential barrier (white part in the figure) are alternately generated in the vertical charge transfer path of the light receiving region A according to the arrangement of the gate electrodes. Then, pixel signals q _a , q _b , q _c , q _d ... Are generated with the potential well as each pixel.

These pixel signals are stored in the most storage section B.
The pixel signals q _a on the side closer to are sequentially transferred to the storage unit B. The generation of potential wells and potential barriers during this transfer is called the accordion transfer method because it resembles that of gradually expanding the bellows of the accordion of the musical instrument and then closing it again.

Then, after all the pixel signals are temporarily stored in the storage section B, the pixel signals can be read out in time series through the horizontal charge transfer path C while performing the accordion transfer similarly.

This scanning readout type charge coupled type solid-state image pickup device has an effect that the number of transfer gate electrodes is small and is excellent in high density. In this charge-coupled solid-state imaging device, circuits such as a shift register are formed by transistors having a CMOS structure, and these circuits, a light receiving portion A, a storage portion B, and a horizontal charge transfer path C are integrally formed in a semiconductor substrate. ing.

That is, the shift register comprises the circuit shown in FIG. 20, and the vertical sectional structure in the semiconductor substrate is as shown in FIG. First, in FIG. 20, the shift register has a circuit configuration between the power supply voltage V _CC and V _DD (in the relationship of V _CC > V _DD ) and each bit is a p-channel MOS transistor connected to the voltage V _CC side. , An n-channel MOS transistor connected to the voltage V _DD side is composed of an inverting circuit connected in a complementary relationship.

A MOS transistor, which is switched between conductive and non-conductive by clock signals φ ₁ and φ _2, is connected between these input / output contacts. Note that the capacitive element ε in the figure
Are formed by applying line capacitance or the like. When inputting a start pulse signal IM (or ST) to the first stage bits, the clock signal phi _1, phi ₂ to perform the transfer operation in synchronization, the clock signal phi ₁ and phi gate signal synchronized with ₂ each bit output It occurs at the contact.

FIG. 21 shows a structure in which the shift register and the charge transfer path are integrally formed on the same semiconductor chip. That is, in FIG. 21, vertical charge transfers L _{1 to} L _m are formed by forming a plurality of n-type impurity layers in a region serving as a light receiving portion of a p-type semiconductor substrate, and further vertical charge transfers L _{1 to} L _m.
A gate electrode is stacked on the upper surface of the gate electrode via a gate oxide film (not shown).

On the other hand, an n-well layer is buried in a drive region where a circuit such as a shift register is formed, a pair of p ⁺ -type impurity layers are formed in the n-well layer, and a gate oxide film layer (see FIG. A p-channel MOS transistor is formed by stacking gate electrodes η _p via (not shown).

In addition, n ⁺ in the semiconductor substrate (p-Sub)
-Type impurity layer is buried and the gate electrode η _n
To form an n-channel MOS transistor, and by connecting these gate electrodes η _p and η _n and predetermined nodes, a CMOS inversion circuit (see FIG. 20) is formed.

In such a charge-coupled solid-state image pickup device, the power supply voltage V _{CC is set} to about 10 V, the power supply voltage V _DD is set to 0 V, and the gate signal voltage of the gate electrode is also set to 0.
It varies in the range of -10 volts.

[0022]

However, in this charge coupled type solid-state image pickup device, as described above, the peripheral circuit such as the shift register for controlling the charge transfer is CMOS.
Since it is composed of elements such as transistors having a structure, a more excellent function, for example, a so-called vertical overflow drain for discarding unnecessary charges to the semiconductor substrate side or an electronic shutter function for the charge-coupled solid-state imaging device itself It was not possible to realize the above structure in terms of structure and withstand voltage.

First, from a structural point of view, the above-mentioned conventional example is a frame transfer type image pickup device in which a vertical charge transfer path has a function as a pixel. Therefore, when an electronic shutter function is to be provided, a smear component is generated. It is not feasible because it causes an increase in

On the other hand, in terms of withstand voltage, if the function of the vertical overflow drain is to be provided, a high voltage of, for example, 15 to 25 V is applied to the semiconductor substrate, and C
The impurity region corresponding to the node of the MOS transistor may be destroyed, or the gate oxide film layer may be broken down.

In order to realize the function of the electronic shutter, a higher voltage needs to be applied to the semiconductor substrate than in the case of the vertical overflow drain, which is naturally impossible in terms of withstand voltage.

Further, these problems will be described in comparison with the actual structure shown in FIG. First, it is necessary to adopt an interline transfer system configuration including a photodiode and a CCD transfer path in order to have an electronic shutter function.

That is, the light receiving section forms a plurality of photodiodes corresponding to pixels in a matrix and forms a vertical charge transfer path adjacent to these photodiodes, and pixel signals generated in these photodiodes are formed. Is transferred to the vertical charge transfer path via the transfer gate and then the pixel signal is read out by the charge transfer through the vertical charge transfer path.

Therefore, the vertical sectional structure of the shift register for driving the light receiving region and the gate electrode of the vertical charge transfer path is as shown in FIG. First, in the light receiving area,
A photodiode is formed by arranging a plurality of n ⁺ -type impurity layers in a matrix in a p-well layer embedded in an n-type semiconductor substrate (n-Sub).

Adjacent to these n ⁺ -type impurity layers, n-type impurity layers serving as vertical charge transfer paths L _{1 to} L _m are formed, and a high-concentration p-type impurity is buried around them to form a channel. Use as a stopper. Further, a gate electrode is laminated.

On the other hand, a p-well layer is buried in the drive region, a pair of n ⁺ -type impurity layers are formed in the p-well layer, and a gate electrode η _n is formed through a gate oxide film (not shown). To form an n-channel MOS transistor.

In the semiconductor substrate (n-Sub), p ⁺
-Type impurity layer is buried and the gate electrode η _p
To form a p-channel MOS transistor.
By connecting these gate electrodes η _p and η _n and predetermined nodes, a CMOS inversion circuit for a shift register as shown in FIG. 20 is formed.

In order to obtain a so-called vertical overflow drain structure, a voltage of 15 to 25 V is applied to the semiconductor substrate to lower the height of the potential barrier formed by the p-well to a predetermined level, which has a charge extraction function. Let

In order to have an electronic shutter function at the same time, when an electrode is formed in the p-well layer of the light receiving region where the charges generated in the photodiode are positively discarded to the semiconductor substrate side and the shutter voltage SS is applied. First, an npn transistor structure is generated between the photodiode and the substrate so that the charges flow to the substrate side.

Further, in order to transfer the pixel signal generated in the photodiode by exposure to the vertical charge transfer path, a high voltage of about 12 V is applied to the transfer gate.

Further, a normal charge transfer operation is performed on the vertical charge transfer path.
In order to carry out the work, generate a potential well
0 volt gate signal and potential barrier
The gate signal of about -8V to generate is CMO
Each is supplied to the gate electrode from the S shift register.
You will be setting the voltage of the signal. That is, in FIG.
The substrate voltage V_SIs 15 to 25 volts, power supply voltage V
_CCIs 0V, voltage V _LIs set to -8 volts.

If such a CMOS structure is provided and the above voltage relationship is set, the gate signal voltage of the gate electrode changes in the range of -8 to 12 volts, and the p channel of the CMOS structure in the drive region is formed. A high voltage of 23 to 33 volts may be applied to the junction between the n-type substrate and the gate oxide film layer or the p ⁺ -type impurity layer under the gate electrode η _p of the MOS transistor, which may greatly exceed the allowable withstand voltage, resulting in damage. Invite.

The present inventors have previously proposed a solid-state image pickup device capable of non-interlaced full-frame reading as in the accordion transfer system and having an overflow drain structure to enable excess charge sweep and electronic shutter.

This solid-state image pickup device has a withstand voltage improved by using a single structure MOS (for example, n-channel MOS) as a drive circuit. However, as a result of prototyping this structure, it was found that the high speed operation is difficult due to the limited operation speed.

An object of the present invention is to provide a solid-state image pickup device capable of high speed operation.

[0040]

A solid-state image pickup device according to the present invention includes a plurality of photoelectric conversion elements arranged in a matrix and a charge including a plurality of gate electrodes formed along each column of the photoelectric conversion elements. Two sets of control circuits, which are arranged on both sides of the matrix with respect to the transfer path and the row direction and have the same circuit function, and to apply the same control signal from two directions to each gate electrode of the charge transfer path. And two sets of control circuits capable of operating.

[0041]

Since the control signals are applied to the respective gate electrodes of the charge transfer path from two directions, the effective resistance and the effective capacitance of the control signal transmission line are about 1/2.

Therefore, the RC time constant becomes about 1/4,
High-speed operation becomes possible.

[0043]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to the description of the embodiments of the present invention, the inventors' previous proposal will be described. Even in the embodiment of the present invention, the details of the above proposal can be used almost as they are.
The case of application to an electronic still camera for capturing a still image will be described.

First, the overall structure of the electronic still camera is shown in FIG.
Will be described. In FIG. 3, 1 is an image pickup optical system including an image pickup lens and the like, 2 is a mechanical diaphragm mechanism, 3 is a charge-coupled solid-state image pickup device, which are arranged in order in accordance with the optical axis of the image pickup optical system 1. The subject optical image is configured to enter the light receiving region of the charge coupled solid-state imaging device 3.

Further, 4 is a signal processing circuit, 5 is a storage mechanism, and the pixel signals output from the charge coupled solid-state image pickup device 3 are subjected to color separation, γ correction, white balance adjustment, etc. in the signal processing circuit 4. A luminance signal and a color difference signal are formed, and the storage mechanism 5 performs a recordable modulation process on the luminance signal and the color difference signal and then stores them in a magnetic recording medium or the like.

Then, the synchronization control circuit 6 causes the diaphragm mechanism 2,
By synchronously controlling the read timing of the charge-coupled solid-state imaging device 3 and the operations of the signal processing circuit 4 and the storage mechanism 5, a series of operations from imaging to storage is processed.

The charge-coupled solid-state image pickup device 3 has the structure shown in FIG. That is, the light receiving region 7 for receiving the subject optical image includes a plurality of photodiodes (portions indicated by P in the figure) corresponding to pixels arranged in a matrix along the row direction X and the column direction Y. , Vertical charge transfer paths L _{1 to} L _m formed adjacent to each photodiode group arranged in the row direction X are provided.

A horizontal charge transfer path 8 is formed at the end of each of the vertical charge transfer paths L _{1 to} L _m , and an output amplifier 9 is formed at the end of the horizontal charge transfer path 8. Further, the vertical charge transfer paths L _{1 to} L _m are provided with predetermined-arranged gate electrodes as will be described later, and light-shielding layers for blocking the incidence of light are further laminated on the upper surfaces thereof.

Signals for causing the charge transfer operation to be performed on these gate electrodes in synchronization with the vertical charge transfer paths L _{1 to} L _m at a predetermined timing are provided in the first, second and third drive circuits 1.
It is supplied from 0, 11, 12. The timing signals φ _H , V _L , φ _G , φ _FS , V _S , φ ₁ , φ ₂ , φ ₃ , and φ supplied to the drive circuits 10, 11, and 12, respectively.
_The synchronous control circuit 6 generates ₄ and the start pulse signal.

Further, the horizontal charge transfer path 8 is provided with a gate electrode for receiving the signal charges transferred from the vertical charge transfer paths L _{1 to} L _m and further horizontally transferring them to the output amplifier 8 side. The gate signals α ₁ , α ₂ , α ₃ , α ₄ and the start pulse signal applied to the gate electrodes for performing these operations are supplied from the synchronization control circuit 6.

Next, the structure of the light receiving region 7 and the circuit configurations of the drive circuits 10, 11 and 12 connected thereto are shown in FIGS.
Will be described in detail. Note that FIG. 5 shows the third drive circuit 12
6 is a circuit diagram of FIG. 6, when the structure of the main part of the light receiving region 7 is viewed from the light receiving surface side, FIG. 7 is a vertical sectional view taken along the line xx in FIG. 6, and FIG. It is a vertical cross-sectional view taken along the line -y.

First, based on FIG. 5, the third drive circuit 1
The circuit configuration of No. 2 will be described. The drive circuit 12 transfers the start pulse signal φ _S in synchronism with the two-phase clock signals φ _A and φ _B which are out of phase, so that the logical value “H” is sequentially output from the lower bit output to the upper bit output. It is a shift register that generates a drive signal.

That is, first, only the drive signal S ₁ is at the “H” level, and the outputs of the other upper bits are all at the “L” level, and in the next cycle, the drive signals S ₁ , S of the lower 2 bits are set.
₂ becomes the "H" every other upper bits output at the level "L" level, yet other upper bit output by the lower three drive signals S ₁ and S ₂ and S ₃ bits "H" level in the next cycle Are all at the "L" level, and the "H" output level of the drive signal changes so as to sequentially expand from the lower bit to the upper bit.

Since each bit has the same cell structure as shown in FIG. 5, the circuit of the first bit will be representatively described. Three MOS transistors u ₁₁ , u ₁₂ , u ₁₃
Is connected between the signal line of the voltage V _{L and} the signal line of the clock signal φ _B with the source / drain path connected in series, and the signal line of the reset signal RS is connected to the gate contact of the transistor u ₁₃ .

Transistor u₁₁Gate contact and drain
Bootstrap capacitor ε between contacts₁₁Connected
And transistor u₁₂Common gate and source contacts
While connecting, other MOS transistor u₁₄Source of
Connect to contact, transistor u ₁₄The drain contact of the
V_LSignal line and gate contact are clock signals φ_ASignal line
Are connected to each.

Further, the MOS transistors u ₁₁ , u ₁₂ ,
A circuit having the same structure as the circuit composed of u ₁₃ and u ₁₄ is a MOS.
The transistor u ₁₂ , u ₂₂ , u ₂₃ , u ₂₄ and the bootstrap capacitor ε ₂₁ form a transistor u _12.
The drain contact (output point) of is connected to the gate contact (input point) of the transistor u ₂₁ . However, the signals φ _A and φ
_B connections are reversed.

The bit input is the transistor u
Corresponding to the gate contact of ₁₁ , the bit output is transistor u
Equivalent to ₂₂ drain contacts. Then, the input and output of these bit cells are cascaded to form an n-bit output shift register, and the input of the start pulse signal φ _S to the least significant bit cell is turned on in synchronization with the clock signal φ _A. The analog switch u ₀₀ is used.

Next, in FIGS. 6 to 8, on the surface side of the n-type semiconductor substrate 13, a p-well layer 14 for forming the light receiving region 7 and a p-well for forming the first drive circuit 10 are formed. A layer 15 and a p-well layer 16 for forming the second and third drive circuits 11 and 12 are buried, and these p
Predetermined circuits are formed in the well layers 14, 15 and 16, respectively.

First, as shown in FIG.
By forming a plurality of impurity layers 17 made of n ⁺ -type impurities in the well layer 14 in a matrix along the row direction X and the column direction Y, a photodiode shown by P in FIG. 4 is formed, and By forming an n-type impurity layer (a portion indicated by a dotted line in FIG. 8) 18 adjacent to each impurity layer 17 arranged in the row direction Y, the vertical charge transfer paths L _{1 to} L _{m in} FIG. Has been formed.

Then, it is shown by Tg in FIG. 6 (only one place is
(Shown as an example) Transfer gate and photo
Periphery excluding the ion part and the vertical charge transfer path part
To p ⁺By forming the type impurity layer 19,
Forming the topper area (the shaded area surrounded by the dotted line in FIG. 6)
It

In FIG. 6, the photodiodes P in FIG. 4 are indicated by P ₁ , P ₂ , P ₃ , P _4, ... For each row. Further, in FIG. 6, the vertical charge transfer paths L _{1 to} L _m
On the upper surface of the gate, in regions adjacent to the photodiodes P ₁ , P ₂ , P ₃ , P ₄ ... Electrodes G _{11 to} G ₄₁ , G _{12 to} G ₄₂ , G _{13 to} G ₄₃ ,
.. G _{1n to} G _4n are stacked, and when the gate electrode G ₁₁ is the first gate electrode, as shown in FIGS. 6 and 7, odd-numbered gate electrodes G ₁₁ , G ₃₁ , G ₁₂ ,
The width W2 of G ₃₂ , G ₁₃ , G ₃₃ , ... Is wide.

Then, gate signals φ ₁₁ , φ ₂₁ , φ ₃₁ , at predetermined timings, which will be described later, are applied to the respective gate electrodes.
By applying φ ₄₁ , φ ₁₂ , φ ₂₂ , φ ₃₂ , φ ₄₂ , potential wells (hereinafter referred to as transfer pixels) and potential barriers for charge transfer are generated in the vertical charge transfer paths under each gate electrode. Let

Further, the even-numbered gate electrodes G ₂₁ , G ₄₁ ,
_{G 22, G 42, G 23} , G 43, is applied a signal of a predetermined high voltage to ..., the transfer gate Tg is rendered conductive, the photodiodes _{P 1, P 2, P 3} , P 4 ... ... and even-numbered gate electrodes G ₂₁ , G ₄₁ , and
The transfer pixels generated under G ₂₂ , G ₄₂ , G ₂₃ , G ₄₃ , ... Are in a conductive state, and the signal charge can be field-shifted from the photodiode to the transfer pixel.

Further, as shown in FIG. 6, a horizontal charge transfer path 8 is formed at the end of the vertical charge transfer paths L _{1 to} L _m .
A gate electrode for transferring signal charges in the horizontal direction is provided at a timing conforming to the 4-phase driving method or the 2-phase driving method.

Next, the circuit configuration of the drive circuit 10 of FIG. 4 will be described with reference to FIGS. 6 and 8. If the gate electrode G ₁₁ closest to the horizontal charge transfer path 8 is the first gate electrode, odd-numbered gate electrodes G ₁₁ , G ₁₂ , G ₁₃ , G ₃₃ , ...
Each of the leading ends of ... Is an NMOS transistor M ₁₁ , M ₃₁ ,
The even-numbered gate electrodes G ₂₁ , G ₄₁ , connected to the signal line of the signal V _L via M ₁₂ , M ₃₂ , M ₁₃ , M ₃₃ , ....
The tips of G ₂₂ , G ₄₂ , G ₂₃ , G ₄₃ , ... Are NMOS transistors M ₂₁ , M ₄₁ , M ₂₂ , M ₄₂ , M ₂₃ , M ₄₃ ,.
Is connected to the signal line of the drive signal φ _H via. The drive signal φ _G is supplied to the gate contacts of these transistors.

Furthermore, the even-numbered gate electrodes G ₂₁ ,
G ₄₁ , G ₂₂ , G ₄₂ , G ₂₃ , G ₄₃ , ...
npn transistor Q ₂₁ , Q ₄₁ , Q ₂₂ , Q ₄₂ , Q ₂₃ , Q
₄₃ , ... Emitter contacts are connected, a drive signal φ _FS is applied to the base contact of each npn transistor, and a voltage V _S is applied to the collector contact.

As shown in the structure in the p well layer 15 of FIG. 8, each of these NMOS transistors has a structure in which a pair of n ⁺ type impurity layers 20 and 21 and a gate electrode are laminated on the surface portion, The drive signal φ _H is applied to the n ⁺ -type impurity layer 20 serving as the drain contact, and the n ⁺ -type impurity layer 21 serving as the source contact is connected to the gate electrode on the vertical charge transfer path. The signal V _L is applied to the p ⁺ type impurity layer 22 embedded in the p well layer 15.

The npn transistor is composed of the p ⁺ -type impurity layer 23 and the n ⁺ -type impurity layer 24 and the n-type semiconductor substrate 13 embedded in the p-well layer 15, and serves as an emitter contact of the n ⁺ -type impurity layer 24. Connects to each gate electrode,
A timing signal φ _FS is applied to the p-well layer 15 and the p ⁺ -type impurity layer 23 that are base contacts, and the bias voltage V _S of the substrate 13 is applied to the n-type semiconductor substrate 13 that is a collector contact.

Next, the second drive circuit 11 supplies the timing signals φ _{1 to} φ ₄ supplied from the synchronization control circuit 6 to the third drive signals S ₁ , S ₂ , S ₃ , S ₄ ... S _n. NMOS transistors m ₁₁ , m ₂₁ , m ₃₁ , m that perform switching operation in synchronization with
₄₁ consists of ...

One set of four NMOS transistors is provided, and the third drive circuit 12 is sequentially connected to their gate contacts.
Drive signals S ₁ , S ₂ , S ₃ , S ₄ , ...
The first NMOS transistors m ₁₁ , m ₁₂ , and m of each set
Timing signal φ ₁ , at the drain contact of ₁₃ , m ₁₄ , ...
The second NMOS transistors m ₂₁ , m ₂₂ , m ₂₃ , m
_The timing signal φ _{2 is applied} to the drain contacts of ₂₄ , ..., The third NMOS transistors m ₃₁ , m ₃₂ , m ₃₃ , m ₃₄ ,.
Timing signal φ ₃ , 4th N on drain contact
The timing signal φ ₄ is supplied to the drain contacts of the MOS transistors m ₄₁ , m ₄₂ , m ₄₃ , m ₄₄ , ....

In FIG. 6, the NMOS transistor
m₁₁, M_{twenty one}, M₃₁, M₄₁, ... Signals on the source contact side
φ₁₁, Φ_{twenty one}, Φ₃₁, Φ₄₁, …… is the timing signal φ₁,
φ₂, Φ ₃, Φ_FourIs a signal corresponding to.

Then, as shown in the figure, the source contact of each NMOS transistor is connected in order from the gate electrode G ₁₁ closest to the horizontal charge transfer path 8. The third drive circuit 12 is formed of a shift register that outputs the drive signals S ₁ , S ₂ , S ₃ , S ₄ , ... S _n at predetermined timings as described above.

Incidentally, these second and third drive circuits 1
1 and 12 are N formed in the p-well layer 16 shown in FIG.
It is formed of a MOS structure transistor and an electronic element. In the p-well layer 16 of FIG. 8, as an example, NMO
The n ⁺ -type impurity layers 25 and 26 and the gate contact forming the S transistor are shown.

Next, a charge-coupled solid having such a structure
Electronic still camera that captures still images
The case of application to will be described. First, take a still image
A general operation for doing so will be described with reference to FIG. In the figure
At some point t₁Start scanning and reading pixel signals from
If so, at that time t ₁Previously, all photodio
And vertical charge transfer path L₁~ L_mAnd horizontal charge transfer path 8
Unnecessary charges remaining in the
The exposure is performed between the photodiodes
A pixel signal corresponding to the subject optical image is generated at.

First, in a period T _VB corresponding to a vertical blanking period of a standard television system such as NTSC,
The pixel signals of all the photodiodes are simultaneously transferred to the transfer pixels in the vertical charge transfer paths L _{1 to} L _m , and in the period _THB corresponding to the next horizontal blanking period, the transfer pixel closest to the horizontal charge transfer path 8 is transferred. Of the pixel signals of 1 row are transferred to the horizontal charge transfer path 8, and then the horizontal charge transfer path 8 horizontally transfers the pixel signals of one row in a period T _1H corresponding to a horizontal scanning period (so-called 1H period). The pixel signals for the first row are read out by.

Then, in the period _THB corresponding to the next horizontal blanking period, the vertical charge transfer paths L _{1 to} L _m transfer the pixel signals of the next row to the horizontal charge transfer path 8, and further,
In the period T _1H corresponding to the next horizontal scanning period, the horizontal charge transfer path 8 horizontally transfers the pixel signals of the second row.

Further, the pixel signals of the third row are read in the periods T _HB and T _1H corresponding to the next blanking period and horizontal scanning. Then, the pixel signals of the remaining rows are sequentially read by repeating the same processing, and finally all pixel signals corresponding to one frame image are read.

Next, the scanning read operation will be described in detail based on each drive signal and timing chart shown in FIG. The period T _VB in FIG. 10 corresponds to the vertical blanking period, the period T _{HB corresponds} to the horizontal blanking period, and the period T _1H corresponds to the horizontal scanning period. Further, the symbol "H" in the figure is 1
2V, "M" is 0V, "L" is -8V,
"HH" indicates a voltage level of about 15-25 volts which is equal to the voltage on the substrate.

First, the period corresponding to the vertical blanking period
Interval T_VBThen the timing signal φ_HIs a predetermined time t₂so
The outside of the "H" level becomes the "M" level,
Signal φ _GIs always "M" level, and timing signal
φ_FSIs the timing signal φ_HBecomes the "H" level
In addition to "H" level, it becomes "L" level.
 All drive signals S output from the drive circuit 12 of 3₁~
S_nIs always at "L" level.

Therefore, during this period T _VB , the first drive circuit 1 is driven by the timing signal φ _G at the “M” level.
0 of all the NMOS transistors become conductive, while all driving signals S ₁ , S ₂ , of the third driving circuit 12
Since S ₃ , ..., S _n become “L” level, all the NMOS transistors in the second drive circuit 11 become non-conductive, and all the gate electrodes G ₁₁ , G ₂₁ , G ₃₁ , G ₄₁ to. G
_1n , G _2n , G _3n , and G _4n are controlled by the first drive circuit 10.

That is, when the timing signals φ _H and φ _FS are not at the “H” level, the gate signals applied to the odd-numbered gate electrodes G ₁₁ , G ₃₁ , G ₁₂ , G _{32 to} G _1n and G _3n. φ ₁₁ , φ ₃₁ , φ ₁₂ , φ _{32 to} φ _1n , φ _3n are “L”
It becomes equal to the level signal V _L (this signal is always set to −8 V), and potential barriers are generated in the vertical charge transfer paths L _{1 to} L _m below these gate electrodes.

On the other hand, the even-numbered gate electrodes G ₂₁ , G ₄₁ ,
A gate signal φ ₂₁ , applied to G ₂₂ , G _{42 to} G _2n and G _4n ,
φ ₄₁ , φ ₂₂ , φ _{42 to} φ _2n , φ _4n become equal to the “M” level signal φ _H, and transfer pixels are generated in the vertical charge transfer paths L _{1 to} L _m below these gate electrodes. ..

Therefore, all the portions (see FIG. 6) adjacent to the transfer gate Tg are transfer pixels, and these transfer pixels are in a state of being separated by the potential barrier.

In such a state, when the timing signals φ _H and φ _FS become “H” level at a predetermined time t ₂ , all the npn transistors Q ₂₁ , Q ₄₁ , Q _61, ... Th gate electrode G ₂₁ , G ₄₁ , G
_22, G ₄₂ ~G _2n, since G _4n only about 15-25 volts at the "H" level of the substrate voltage V _S is applied, all the transfer gate Tg is rendered conductive, the pixel signals of all the photodiodes, respectively It is transferred to the next transfer pixel.

As described above, in the period T _VB , a so-called field shift operation is performed, and each pixel signal (the hatched portion indicates each pixel signal) is transferred to the vertical transfer path as shown at time t ₂ in FIG. Is moved to. Note that FIG. 14 shows a charge transfer operation of a certain vertical charge transfer path.

Next, during the period T _HB corresponding to the first horizontal blanking period, the timing signal φ _G is constantly at the “L” level, so that all NMOs in the first drive circuit 10 are included.
The S transistor becomes non-conductive and is separated from all the gate electrodes.

On the other hand, the first output terminal of the third drive circuit 12
Child drive signal S₁Only "M" level, other drive signal S
₂~ S_nBecomes the "L" level, and the second drive
Drive signal S in circuit 11₁First set of NMOS related to
Transistor m₁₁, M_{twenty one}, M ₃₁, M₄₁Only with continuity
Become.

Then, the drive signal S₁Only "M" level
During the period of
Imming signal φ₁, Φ₂, Φ₃, Φ_FourIs the second drive circuit
Since it is input to 11, the first to fourth sets of games
Signal φ₁₁, Φ_{twenty one}, Φ₃₁, Φ ₄₁Only the timing signal φ
₁, Φ₂, Φ₃, Φ_FourEquals 1st to 1st in the first set
Fourth gate electrode G₁₁, G_{twenty one}, G₃₁, G₄₁Charge transfer
It will be sent. In addition, this period T_HB(Time t₃
~ T_FourThe signal waveforms for the
You

As a result, the signal charges are generated at the timings of the gate signals φ ₁₁ , φ ₂₁ , φ ₃₁ , and φ ₄₁ of FIG.
2, 3, 4, 5, 6, and 7), the first row is moved to the horizontal charge transfer path 8 side as in the first transfer shown in FIG. 14 and is closest to the horizontal charge transfer path 8. Eye pixel signal q
_1j is transferred to the horizontal charge transfer path 8, and the pixel signal q _2j on the second row moves to the position on the first row.

Next, in the first horizontal scanning period T _1H (the period from time t _{4 to} t ₅ ), the change of the signal to the gate electrode is stopped, while the horizontal charge transfer path 8 is in the four-phase driving system. Or a gate signal α _{1 at} a predetermined timing according to the two-phase drive method
By performing the horizontal transfer in synchronism with to? _4, it reads the first pixel signals for one row.

Next, in the period from time t _{5 to} t ₇ , the same operation as at time t _{3 to} t ₅ is repeated to read the pixel signal of the next row. However, the time t ₃ ~
In the horizontal blanking period T _{HB of} t ₄ , the drive signals S ₁ and S _{2 of} the third drive circuit 12 simultaneously become “M” level, and the remaining drive signals S _{3 to} S _n become “L” level. The waveforms of the respective gate signals in this period _THB are shown enlarged in FIG.

[0092] Consequently, the first to fourth first set of gate electrodes G ₁₁ ~G _41, fifth to eighth second set of gate electrode G ₁₂ ~G ₄₂ is a timing signal phi ₁ Driven by gate signals φ ₁₁ to φ ₄₁ and φ ₁₂ to φ ₄₂ , which are equal to φ ₄ , and pixel signals under these gate electrodes are vertically transferred.

That is, according to the timing shown in FIG. 12, as shown in the second vertical scanning of FIG. 14, the pixel signal q _2j of the second row is moved to the horizontal charge transfer path 8 and the third row The second row and the fourth row are transferred to the horizontal charge transfer path 8 side one by one.

Then, at time t₆~ T₇Horizontal scanning period T
_1H, The pixel signal of the second row from the horizontal charge transfer path 8
q_2jRead out. Then at time t₇From the 3rd scan reading
When the protrusion starts, the drive signal S of the third drive circuit 12
₁, S₂And S₃Becomes "M" level and the remaining drive signal
S_Four~ S _nBecomes the "L" level,
1st to 12th gate electrodes G₁₁~ G₄₁, G₁₂~
G₄₂, G₁₃~ G₄₃The vertical charge transfer is performed by.
Therefore, as shown in the third set of FIG.
Eye pixel signal q_3jIs transferred to the horizontal charge transfer path 8,
To the pixel signals q of the 4th to 6th rows._4j, Q_5jEach is 2
Pixel signal q for each row_6jFor one line, horizontal charge transfer path₈~ side
Transferred to.

Then, the pixel signal q _{3j on} the third row is read out by the horizontal charge transfer path 8. After that, every time the pixel signal of each row is read, the drive signal S of the third drive circuit 12 is read.
_{By 4} to S _n is gradually inverted "M" level in sequence, a gate electrode to be driven is continue to gradually expand the four addressed as a set, the last horizontal blanking period T _HB (time t ₉
At ~ t ₁₀ ), as shown in FIG. 13, all the gate signals φ _{11 to} φ _4n have the same waveforms as the timing signals φ _{1 to} φ ₄ , and the pixel signal of the last row can be read by the last scanning read. it can.

FIG. 15 shows an arbitrary order, that is, the k-th and k + 1-th vertical charge transfer operations by the potential profile. As shown in the figure, charges are sequentially transferred from the transfer pixels on the horizontal charge transfer path 8 side. By increasing the number of transfer pixels with the distance therebetween increased, the pixel signals on the side closer to the horizontal charge transfer path 8 are sequentially read.

According to the above-described structure, the drive circuit for supplying the gate signal to the gate electrode has the CMOS structure M
Since the MOS transistor having an NMOS structure and the transistor having a bipolar structure are used instead of the OS transistor, a high breakdown voltage drive circuit can be realized and a vertical overflow drain and an electronic shutter function can be provided. ..

Further, by providing the vertical overflow drain structure, excess charges of the photodiode are discarded to the substrate side to prevent the occurrence of blooming and the like, and the electronic shutter without the substrate is enabled to realize the non-interlaced full frame reading. It is possible to provide a charge-coupled solid-state imaging device suitable for still image capturing.

As a result of actually making a prototype of the charge-coupled solid-state image pickup device as described above, it was confirmed that full-frame reading can be performed as expected at the initial stage, and excess charges can be swept out and an electronic shutter can be performed. However, it has been found that there is a limitation when trying to operate such a charge-coupled solid-state imaging device at high speed.

As a result of studies by the present inventors, it has been found that the limitation on the high speed operation is mainly due to the resistance and capacitance of the gate electrode formed of polycrystalline silicon. Figure 1
FIG. 3 is a block diagram showing a configuration of a solid-state imaging device according to an embodiment of the present invention, which can improve the above-mentioned problems.
In addition, the same reference numerals are given to the same parts as those in the above-mentioned proposal.

The light receiving portion 7 has a structure in which a large number of photodiodes P are arranged in the row direction X and the column direction Y. Adjacent to each column of the photodiodes P, a charge transfer path L ₁ ,
L ₂ , ..., L _m are formed. A horizontal charge transfer path 8 is formed adjacent to the output ends of these charge transfer paths L ₁ , L ₂ , ..., L _m . The output of the horizontal charge transfer path 8 is
It is taken out through the output amplifier 9.

Two sets of drive circuits are provided on both sides of the light receiving section 7 in the X direction. That is, the drive circuits 10a, 11a, 12a are provided on the right side of the light receiving section 7, and the drive circuits 10b, 11b, 12b are provided on the left side of the light receiving section 7.

Each of the drive circuits 10a and 10b has the same structure as the drive circuit 10 according to the above-mentioned invention.
Similarly, each of the drive circuits 11a and 11b has the same configuration as that of the drive circuit 11 described above, and the drive circuits 12a and 12b.
Each has a configuration equivalent to that of the drive circuit 12 described above.
Equivalent control signals are applied to these two sets of drive circuits.

Each electrode of the charge transfer path has a drive circuit at both ends, and a control signal is applied from both sides. Therefore, the number of gate electrodes that each drive circuit should be responsible for is about half that of the above-mentioned proposal. As the number and the distance of the gate electrodes are reduced to about half, the resistance value of the signal line to be driven by each drive circuit is reduced to about half and the associated capacitance is also reduced to about half. Therefore, when the resistance of the drive line of each gate electrode is R and the associated capacitance is C, the RC time constant is about 1/4. Therefore, high-speed operation of the solid-state imaging device becomes possible.

The structure of the solid-state image pickup device having the drive circuits on both sides of the light-receiving portion is not limited to the above-described embodiment, but can be applied to various solid-state image pickup devices. Figure 2 shows FITC
An example of a solid-state imaging device of the CD system will be shown. Light receiving part 7
Has the same configuration as that of the embodiment shown in FIG. 1, and the storage unit 57 arranged therebelow is the photodiode P of the light receiving unit 7.
Is omitted and only the charge transfer path is included. In addition,
The storage unit 57 has a light-shielding film on it, and light does not enter.
The horizontal charge transfer path 8 is arranged at the output end of the charge transfer path of the storage section 57, and its output is taken out via the output amplifier 9.

Two sets of drive circuits 10c, 11c, 12c and 10d, 11 are provided on both sides of the light receiving section 7 and the storage section 57.
d and 12d are provided. These drive circuits are different from the drive circuit 10a shown in FIG. 1 except that the charge transfer path to be driven is formed over the light receiving portion 7 and the storage portion 57.
Equivalent to 11a, 12a and 10b, 11b, 12b.

By reducing the resistance and capacitance of the signal line from the drive circuit to the gate electrode of the charge transfer path to about 1/2, the RC time constant becomes about 1/4, and high speed operation can be promoted. Becomes

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example,
It will be apparent to those skilled in the art that various modifications, improvements, combinations and the like can be made.

[0109]

As described above, according to the present invention,
In the solid-state imaging device having a large number of photoelectric conversion elements arranged in a matrix, the effective resistance and effective capacitance of the signal line for applying the control signal to the charge transfer path are about 1/2, respectively, so that the RC time constant is It is about 1/4, which enables high-speed operation.

[Brief description of drawings]

FIG. 1 is a schematic plan view of a charge-coupled solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a schematic plan view of a charge-coupled solid-state imaging device according to another embodiment of the present invention.

FIG. 3 is a configuration diagram of an electronic still camera to which the charge-coupled solid-state imaging device proposed above is applied.

FIG. 4 is a schematic configuration diagram of a charge-coupled solid-state imaging device proposed above.

5 is a circuit diagram illustrating a configuration of a drive circuit 12 in the solid-state imaging device shown in FIG.

FIG. 6 is a schematic plan view showing the structure of a main part of a light receiving region having the configuration of FIG. 4 and a peripheral circuit configuration.

FIG. 7 is a vertical cross-sectional view taken along the line xx in FIG.

FIG. 8 is a vertical cross-sectional view taken along the line yy in FIG.

FIG. 9 is a signal waveform diagram schematically showing a scanning read operation.

FIG. 10 is a timing chart showing the scanning read operation in detail.

11 is a timing chart showing an enlarged main part timing in FIG.

12 is a timing chart showing an enlarged main part timing in FIG.

13 is a timing chart showing an enlarged main part timing in FIG.

FIG. 14 is a diagram conceptually showing a charge transfer operation at the time of scanning and reading.

FIG. 15 is a potential profile for performing a charge transfer operation during scanning reading.

FIG. 16 is a schematic plan view showing a main part structure of a conventional charge-coupled solid-state imaging device.

FIG. 17 is a signal waveform diagram for explaining the operation of the conventional example.

FIG. 18 is a potential profile for explaining the operation of the conventional example.

FIG. 19 is a schematic diagram illustrating an operation of a conventional example.

FIG. 20 is a circuit diagram of a shift register for explaining the problems of the conventional example.

FIG. 21 is a partial cross-sectional view of a solid-state imaging device for explaining the problems of the conventional example.

FIG. 22 is a partial cross-sectional view of a solid-state imaging device for explaining the problems of the conventional example.

[Explanation of symbols]

 1 Imaging Optical System 2 Mechanical Aperture Mechanism 3 Charge-Coupled Solid-State Imaging Device 4 Signal Processing Circuit 5 Storage Mechanism 6 Synchronization Control Circuit 7 Light-Receiving Area 8 Horizontal CCD 9 Output Amplifier 10, 11, 12 Drive Circuit

Claims (1)

[Claims] 1. A large number of photoelectric conversion elements arranged in a matrix, a charge transfer path formed along each column of the photoelectric conversion elements and including a plurality of gate electrodes, and both sides of the matrix in the row direction. Solid-state imaging including two sets of control circuits arranged in the same direction and having the same circuit function, and capable of applying the same control signal from two directions to each gate electrode of the charge transfer path. apparatus.