JPH0465874A - Solid-state image sensing device - Google Patents

Abstract

PURPOSE:To realize a vertical overflow drain and electronic shutter function, by forming driving circuits in well layers buried in a semiconductor substrate, so as to be independent of a well layer or in a unified body with well layers, and using a transistor having a single MOS structure. CONSTITUTION:In the surface side of an n-type semiconductor substrate 13, the following are buried; a p-well layer 14 for forming a photo detecting region 7, a p-well layer 15 for forming a first driving circuit 10, and a p-well layer 16 for forming a second and a third driving circuits 11, 12. Each tip part of odd number gate electrodes G11, G31, G12, G32, G13, G33,< is connected with the signal line of a signal VL, via NMOS transistors M11, M31, M12, M32, M13, M33,.... Each tip part of even number gate electrode G21, G41, G22, G42, G23, G43,... is connected with the signal line of a driving signal phiH via NMOS transistors M21, M41, M22, M42, M23, M43,.... A driving signal phiG is supplied to the gate contacts of these transistors.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a charge-coupled solid-state imaging device (COD).
In particular, the present invention relates to a charge-coupled solid-state imaging device having a vertical eberflow drain structure.

[Conventional technology]

Conventionally, as a charge-coupled solid-state imaging device, a frame transfer solid-state imaging device (FT-COD), which applies scanning readout using an accordion transfer method, is known (PHI).
LIPS TECHNICAL REVIEW VOL
, 43°No, 1/2.1986. The acc.
ordion imager, a new solid
-state image 5ensor, A, J,
P, Theuwissenand C, H, L, Wei
jtens).

The outline of this solid-state imaging device will be explained with reference to FIGS. 14 to 19. First, the overall configuration is as shown in FIG. 14.
A light-receiving section A consisting of m vertical transfer paths L1 to L, each having a photoelectric conversion function and a charge transfer function, and a light-shielding film that is connected to these vertical transfer paths L1 to L and is laminated on the surface thereof. The horizontal charge transfer path C is connected to the terminal end of each charge transfer path of the storage portion B and whose surface is covered with a light-shielding film.

On the upper surface of the vertical charge transfer paths L1 to L, transfer gate electrodes are arranged in parallel along the charge transfer direction Y, one for each pixel, and an accordion transfer method is applied to these gate electrodes. By applying a gate signal at a predetermined timing according to
, and by changing the potential well and potential barrier at predetermined timing during transfer, Y
Charge is transferred in the direction.

The shift register indicated by the reference numeral in the figure generates the above gate signal by transferring the start pulse IM in synchronization with the two-phase cross-over signal φ1 φ.

Further, the charge transfer path of the storage section B is also provided with a similar gate electrode, and the shift register E receives two-phase clock signals φ and φ.
Charges are transferred in the Y direction by a gate signal formed by transferring a start pulse ST in synchronization with .

Then, the pixel signal generated in the light receiving section A is transferred to the vertical charge transfer path, ~L. After the charge transfer path of the storage section B is synchronized and transferred to the storage section B and temporarily held, the pixel signals of the storage section B are transferred row by row to the horizontal charge transfer path C, and the horizontal charge is transferred each time it is transferred. The transfer path C performs horizontal charge transfer in synchronization with the gate signal from the shift register F, thereby reading out all pixel signals.

Furthermore, the timing of each signal for this scanning readout is shown in FIG. As shown in figure (a), each start pulse IM and ST is supplied to shift registers D and E at a predetermined timing, and these are transferred in synchronization with two-phase clock signals φ1 and φ2. ), gate signals A, B, C,, D, . - are sequentially supplied to the gate electrode of the charge transfer path of the storage section B as shown in FIG. DS is supplied in order.

For convenience of explanation, only gate signals corresponding to eight gate electrodes are shown.

These gate signals A,,B,,C,,DA,,B,,
According to the voltage changes of C, D, -, as shown in FIG. ) The potential wells and potential barriers change so that the pixel signal q on the horizontal charge transfer path C side is sequentially transferred to the lower transfer path.

Therefore, to represent the charge transfer of a certain vertical charge transfer path and the charge transfer path of the storage section B connected thereto, the first
It will look like Figure 7. That is, assuming that exposure is performed at a certain time t, the vertical charge transfer path in the light-receiving area A has a potential well (the part marked with ■ in the figure) and a potential barrier (the part marked with ■ in the figure) and a potential barrier (the part marked with portion) are generated alternately, and the potential well is used as each pixel to generate the pixel signal q.

qb, q-, Qa''- are generated.These pixel signals are the pixel signals q, q, and Qa'' on the side closest to the storage unit.
The data are sequentially transferred to the storage unit B. It is called the accordion transfer method because the way the potential wells and potential barriers are generated during this transfer is similar to the way the bellows of an accordion, a musical instrument, gradually expands and then closes again.

After all pixel signals are temporarily held in the storage section, the pixel signals can be read in time series via the horizontal charge transfer path C while similarly performing accordion transfer.

This scanning readout type charge-coupled solid-state imaging device has the advantage that the number of transfer gate poles is small, and is excellent in high density.

In addition, in this charge-coupled solid-state imaging device, circuits such as a shift register are formed using transistors of a CMOS structure, and these circuits, a light receiving section A, an accumulation section B, and a horizontal charge transfer path C are integrally formed in a semiconductor substrate. has been done.

That is, the shift register consists of the circuit shown in FIG.
The vertical cross-sectional structure of the semiconductor substrate is as shown in FIG. First, in FIG. 18, the shift register has power supply voltages Vcc and Vo. (Vcc > Vo.

Each bit has an n-channel MOS transistor connected to the voltage Vcc side and a voltage Vcc side. . It consists of an inverting circuit in which n-channel MOS transistors connected to the side are connected in a complementary relationship, and a MOS transistor that is switched between conduction and non-conduction by clock signals φ and φ2 is connected between these input contacts. ing. Note that the capacitive element ε in the figure is formed by applying line capacitance or the like. Then, when a start pulse signal IM (or ST) is input to the first stage bit, a transfer operation is performed in synchronization with clock signals φ1 and φ2,
Gating signals synchronized with clock signals φ1 and φ are generated at the respective bit output contacts.

Further, a structure in which a shift register and a charge transfer path are integrally formed on the same semiconductor chip is shown in FIG. That is,
In FIG. 19, a plurality of n-type impurity layers are formed in a region of a p-type semiconductor substrate that will become a light-receiving portion, and a vertical charge transfer path is formed.
.about.L, and further a gate electrode is laminated on the upper surface of the vertical charge transfer path and .about.L via a gate oxide film (not shown).

On the other hand, an n-well layer is buried in the driving region where a circuit such as a shift register is formed, and a pair of p° type impurity layers are formed in this n-well layer, and a gate oxide film layer (not shown) is formed in the n-well layer. A p-channel MOS transistor is formed by stacking a gate electrode η through the semiconductor substrate (p-Sub), and an n-type impurity layer is buried in the semiconductor substrate (p-Sub), and the gate electrode η is formed on the surface portion. An n-channel MOS transistor is formed by forming these gate electrodes η. and η. , a CMOS inverter circuit (see FIG. 18) is formed by connecting predetermined nodes.

In such a charge-coupled solid-state imaging device, the power supply voltage Vcc is set to approximately 10 volts, the power supply voltage v0° is set to O volts, and the gate signal voltage of the gate electrode is also set to 0 to 10 volts.
Varies within the range of bolts.

[Problem to be solved by the invention]

However, as mentioned above, in this charge-coupled solid-state imaging device, peripheral circuits such as shift registers for controlling charge transfer are configured with elements such as CMOS transistors, and therefore, superior functions such as It has not been possible to provide a so-called vertical overflow drain for discarding unnecessary charges to the semiconductor substrate side, or to provide an electronic shutter function to the charge-coupled solid-state imaging device itself due to structural and breakdown voltage issues.

First, in terms of structure, the above conventional example is a frame transfer type imaging device in which the vertical charge transfer path has a pixel mechanism, so if you try to add an electronic shutter function, it will cause an increase in smear components. It is not practical because it involves inviting people.

On the other hand, in terms of withstand voltage, when attempting to provide the function of a vertical overflow drain, it is necessary to
As a high voltage of volts is applied, the impurity region corresponding to the node of the CMOS transistor may be destroyed, or the gate oxide film layer may undergo dielectric breakdown.

Furthermore, if an attempt is made to realize the function of an electronic shutter, it is necessary to apply a higher voltage to the semiconductor substrate than in the case of a vertical overflow drain, which is naturally impossible in terms of withstand voltage.

Furthermore, these problems will be explained in comparison with the actual structure shown in FIG. First, in order to provide an electronic shutter function, it is necessary to configure an interline transfer method. That is, the light receiving section has a plurality of photodiodes corresponding to pixels arranged in a matrix, a vertical charge transfer path is formed adjacent to these photodiodes, and pixel signals generated in these photodiodes are transferred to a transfer gate. After the pixel signal is transferred to the vertical charge transfer path via the vertical charge transfer path, the pixel signal is read out by the charge transmission through the vertical charge transfer path.

Therefore, the vertical cross-sectional structure of the shift register for driving the gate electrodes of the light receiving region and the vertical charge transfer path is 20.
The result will be as shown in the figure.

First, in the light receiving area, an n-type semiconductor substrate (n-Sub) is used.
A photodiode is formed by arranging a plurality of n+ type impurity layers in a matrix in the p-well layer buried in the p-well layer, and vertical charge transfer paths L1 to L are formed adjacent to the n+ type impurity layers. An n-type impurity layer is formed, and a highly concentrated p-type impurity is buried around these layers to form a channel stopper. Furthermore, a gate electrode is laminated.

On the other hand, a p-well layer is buried in the drive region, a pair of n° type impurity layers are formed in the p-well layer, and a gate electrode η is formed through a gate oxide film layer (not shown). An n-channel MOS transistor is formed by stacking the MOS transistors, and a p+ type impurity layer is buried in the semiconductor substrate (n-Sub), and a gate electrode η is formed on the surface of the p+ type impurity layer.
These node electrodes η9 and η constitute a channel MOS transistor. , a CM for a shift register as shown in FIG. 18 by connecting predetermined nodes.
Form an OS inversion circuit.

Since it is necessary to create a so-called vertical overflow drain structure, a voltage of 15 to 25 volts is applied to the semiconductor substrate, and in order to have an electronic shutter function, the charge generated in the photodiode must be transferred to the semiconductor substrate. When a shunter voltage SS is applied to the p-well layer of the light-receiving region to be discarded to the side, an npn transistor structure is generated between the photodiode and the substrate, so that charges flow to the substrate side.

Furthermore, in order to transfer the pixel signal generated in the photodiode by exposure to the vertical charge transfer path, a high voltage of about 12 volts must be applied to the transfer gate. In addition, in order to cause the vertical charge transfer path to perform normal charge transfer operation, a gate signal of O volts to generate a potential well and a gate signal of about -8 volts to generate a potential barrier are required. The voltage of each signal is set so as to be supplied from the CMOS shift register to the gate electrode. That is, in FIG. 20, the substrate voltage V is a power supply voltage of 15 to 25 volts. C is set to 0 volts, and voltage VL is set to 18 volts.

If a CMOS structure like this is used and the voltage relationship described above is set, the gate signal voltage at the gate pole will be 18 to 12
The CM in the drive area will vary in the range of volts.
Gate electrode η of the n-channel MOS transistor of the OS,
A high voltage of 23 to 33 volts may be applied between the junction between the lower gate oxide film layer or p+ impurity layer and n-3ub,
This greatly exceeds the allowable withstand pressure, leading to damage.

The present invention has been made in view of such problems,
Equipped with a vertical overflow drain structure, the excess charge of the photodiode is discarded to the substrate side, eliminating the occurrence of blooming, etc. Also, by discarding the charge to the substrate side, it is possible to provide a substrate-excluding electronic shutter. To provide a charge-coupled solid-state imaging device of a full-frame scanning readout type suitable for still image imaging by being an interline charge-coupled solid-state imaging device and capable of performing non-interlaced full-frame scanning readout. The purpose is to

[Means to solve the problem]

In order to achieve such an object, the present invention provides a charge-coupled solid-state imaging device having a vertical Eberflow drain structure that discards unnecessary charges in a light-receiving region to the semiconductor substrate side. A charge transfer path is formed in the layer, and a drive circuit for generating a signal for driving the charge transfer path is formed in a well layer buried separately or integrally with the well layer in the semiconductor substrate; 1M
It was decided to use a transistor having an O8 structure.

[For use]

According to the solid-state imaging device of the present invention having such a structure, the semiconductor substrate and the well layer have a relatively low impurity concentration, so that a high breakdown voltage can be achieved. This breakdown voltage can withstand the high voltage required to realize the function of a vertical overflow drain, and the structure also withstands the high voltage applied when operating the electronic shutter.

〔Example〕

Hereinafter, one embodiment of a charge-coupled solid-state imaging device according to the present invention will be described with reference to the drawings. A case will be described in which the present invention is applied to an electronic still camera for capturing still images.

First, the overall structure of an electronic still camera will be explained with reference to Fig. 1. In Fig. 1, 1 is an imaging optical system consisting of an imaging lens, 2 is a mechanical diaphragm mechanism, and 3 is a charge-coupled type to which the present invention is applied. Each solid-state imaging device has an imaging optical system 1.
They are arranged in order along the optical axis of the image pickup device 3, and are configured to make an optical image of the object incident on the light receiving area of the charge-coupled solid-state imaging device 3.

Further, 4 is a signal processing circuit, and 5 is a recording mechanism. The signal processing circuit 4 performs color separation, T correction, white balance adjustment, etc. on the pixel signal output from the charge-coupled solid-state imaging device 3, and also converts it into a luminance signal. Color difference signals are formed, and the recording mechanism 5 performs recordable modulation processing on these luminance signals and color difference signals, and then records them on a magnetic recording medium or the like.

The synchronous control circuit 6 processes a series of operations from imaging to recording by synchronously controlling the aperture mechanism 2, the readout timing of the charge-coupled solid-state imaging device 3, and the operation of the signal processing circuit 4 and recording mechanism 5. do.

The charge-coupled solid-state imaging device 3 has a configuration shown in FIG.

That is, the light receiving area 7 for receiving the optical image of the subject includes a plurality of photodiodes (in the figure, P
), vertical charge transfer paths L1 to L formed adjacent to each photodiode group arranged in the column direction X,
,, are provided.

A horizontal charge transfer path 8 is formed at the end of each of these vertical charge transfer paths L1 to L, and an output amplifier 9 is formed at the end of the horizontal charge transfer path 8.

Furthermore, the vertical charge transfer paths L1 to L, . .

These gate electrodes are connected to the first . Second. It is supplied from the third drive circuit 10, 11.12. Incidentally, the timing signals φH, VL φ6 φps supplied to the respective drive circuits 10, 11, and 12
, Vs φφ2 φ, φ4 and the start pulse signal are generated by the synchronous control circuit 6.

Further, the horizontal charge transfer path 8 is provided with a gate electrode for receiving the signal charge transferred from the vertical charge transfer path L and then horizontally transferring it to the output amplifier 8 side. Gate signals α1 α2 α, applied to the gate electrodes to perform the following.

α4 is supplied from the synchronous control circuit 6.

Next, we will discuss the structure of the light receiving area 7 and the drive circuit 1 connected thereto.
0, 11.12 will be described in detail with reference to FIGS. 3 to 6. 3 is a circuit diagram of the third drive circuit 12, FIG. 4 is a circuit diagram of the main part of the light-receiving area 7 when viewed from the light-receiving surface side, and FIG. X-ray longitudinal cross-sectional view, No. 6
The figure is a longitudinal sectional view taken along the line y--y in FIG. 4.

First, the circuit configuration of the third drive circuit 12 will be explained based on FIG. The drive circuit 12 receives a start pulse signal φ
, in synchronization with two-phase clock signals φ and φ8 whose phases are shifted from each other, thereby sequentially generating drive signals of logic value “H” from the lower bit output to the upper bit output. That is, at first, only the drive signal s1 is at "H" level, all other upper bit outputs are at "L" level, and in the next cycle, the lower two bits of drive signals S1 and S
, is at "H" level, all other upper bit outputs are at "L" level, and in the next cycle, the lower 3 bits of drive signals S1, S, and S are at "H" level, and the other upper bits' outputs are at "H" level. The drive signal “
The H'' output level changes from the lower bits to the upper bits in order.

As shown in FIG. 3, each bit has a cell structure, so when explaining the circuit on behalf of the first bit, three Mos transistors Uu++ and LI++ connect the source-drain path. It is connected in series between the signal line of the voltage VL and the signal line of the clock signal φ, and the signal line of the reset signal RS is connected to the gate contact of the transistor UZ. A bootstrap capacitor ε,1 is connected between the gate contact and the drain contact of the transistor U11, the gate contact and the source contact of the transistor U++ are commonly connected, and the transistor U11 is connected to the source contact of another MOS transistor u14. The drain contact of u14 is at voltage VL
The gate contact is connected to the signal line of the OFF signal φ, respectively.

Furthermore, a circuit having the same configuration as the circuit consisting of the MOS transistors uz, u+, uU+4 is formed by the MOS transistors u++, urt, u2+, u, a and the footstrap capacitor ε21, and the transistor U
+2 drain contact (pressure point) and transistor Llzr
The gate contact (input point) of is connected.

However, the connections between the signals φ and φ8 are reversed.

This bit input corresponds to the gate contact of the transistor ul+, and the bit specific power corresponds to the drain contact of the transistor LJzr. By cascading the inputs and outputs of these bit cells, a shift register with n-bit output is constructed, and the input of the start pulse signal φ to the least significant bit cell becomes conductive in synchronization with the clock signal φ. This is done via an analog switch u0°.

Next, in FIGS. 4 to 6, a p-well layer 14 for forming a light-receiving region 7 is formed on the surface side of the n-type semiconductor substrate 13.
and a p-well layer 1 for forming the first drive circuit 10.
5, and 2nd. P well layers 16 for forming third drive circuits 11 and 12 are buried, and these p well layers 1
Predetermined circuits are formed within the 4 and 15 degrees 16, respectively.

First, the light-receiving region 7 is formed by arranging a plurality of impurity layers 17 made of n+ type impurities in a matrix along the row direction X and the column direction Y in the p-well layer 14. The photodiode shown in FIG. A vertical charge transfer path, ~L, is formed. Then, there is a p
By forming the impurity layer 19 in the shape of 2, a channel stopper region (the shaded area surrounded by the dotted line in FIG. 4) is formed.

In FIG. 4, the photodiodes P in FIG. 2 are indicated by P, P, , P, , P, etc. in each row.

Furthermore, in FIG. 4, on the upper surface of the vertical charge transfer paths L1 to L, there are photodiodes P, , P arranged in each row.
, ,P, ,P, -, as shown in the figure, are gate electrodes Gll~04G11~G41+ Gll made of two separate polysilicon layers, respectively.
~G 41. ”” ””””' G l~G,.

are stacked, and if the gate electrode G l 1 is the first gate electrode, as shown in FIGS. 4 and 5,
Odd numbered gate electrode G I 11 G S l+ G
l+! Gl! + 011 HG I! +
""' narrows the convergence W1, and the even-numbered gate electrode G
! l! G 41 g G 2 t + G 4
! +G! 31 G 41+-"'-"-width W
2 is formed widely.

Then, gate signals φ11, φ21, φ87, . φ4゜φ,
2 φ2. φ8. By applying φ42, potential wells (hereinafter referred to as transfer pixels) and potential barriers for charge transfer are generated in the vertical charge transfer path under each gate electrode. Moreover, the even numbered gate electrode G 1
1 g G 41 g G r! ＋GJ!
＋G! S*G4! When a predetermined high voltage signal is applied to the transfer gate T
9 becomes conductive, and each photodiode P, , Pf
, P, , P, − and adjacent even-numbered gate electrodes G f 11 G 4 InG2□+ G 4
The structure is such that the transfer pixels generated under I + G r I HG 4 S + -.- become conductive, and the signal charge can be field-shifted from the photodiode to the transfer pixel.

Furthermore, as shown in FIG. 4, vertical charge transfer paths L1-L.

A horizontal charge transfer path 8 is formed at the terminal end of the blade, and a gate electrode is provided for horizontally transferring signal charges at a timing similar to the four-phase drive blade type or the two-phase drive blade type.

Next, the circuit configuration of the first drive circuit 10 is shown in FIGS. 4 and 6.
This will be explained with figures. If the gate electrode G In closest to the horizontal charge transfer path 8 is the first gate electrode, then the odd-numbered gate electrode G I 11 G 311G1□T G
, l+ G l )g G I! Each tip of + is an NMOS transistor M 11 TM ! +
, M I I HM I I + M I I iM
s + + −・−, connected to the signal line of the signal vL, and even-numbered gate electrodes G + l, G 1
1.G! □、G 11 +G 21! G4
Each tip of IT − is an NMOS transistor M 2+
, Mal, Mtt, Mtt+ Mll, Mts
It is connected to the signal line of the drive signal φ via +.

Further, a drive signal φ6 is supplied to the gate contacts of these transistors.

Furthermore, even-numbered gate electrodes G11. G 4t,
G+++G4! , G l! +G 41+
- At each tip of the npn transistor Q II
, Q 4, + Q If + Q 41 + Q
Is +043. - The emitter and terminal contacts of each npn transistor are connected, and the drive signal φ23,
A voltage V is applied to the collector contact.

These NMOS transistors are
As shown in the structure in the well layer 15, it consists of a pair of n+ type impurity layers 20, 21 and a gate electrode laminated on the surface portion, and a drive signal φ is applied to the n1 type impurity layer 20, which serves as a drain contact. The n'' type impurity layer 21, which becomes the source contact, is connected to the gate electrode on the vertical charge transfer path.
Ru. Further, the signal V is applied to the p' type impurity layer 22 buried in the p well layer 15. The npn transistor is composed of a p+ type impurity layer 23 buried in a p well layer 15, an n type impurity layer 24, and an n type semiconductor substrate 13, and an n type impurity layer 24 serving as an emitter contact is connected to each gate. A timing signal φ, 5 is applied to the p-well layer 15 and the p-type impurity layer 23, which are connected to the electrode and serve as the base contact, and the n-type semiconductor substrate 13 serves as the collector contact. is applied.

Next, the second drive circuit 11 transfers the timing signals φ1 to φ4 supplied from the synchronous control circuit 6 to the third drive circuit 12.
The driving signals from,s,,s,,s,,s,.

・- NMOS transistors mz mrl , m, + , mat ・- which switch and operate in synchronization with So, and a third drive circuit 12 is connected to the gate contacts of each set of four NMOS transistors in turn. The drive signals s,,s',,s,,s.

is applied to the first NMOS transistor m of each set.
+1. The timing signal φ7 is applied to the drain contacts of m1r, ml,, mat """"-, and the second NMOS transistor m++, mrr', mrl, mrl -
The timing signal φ1 is applied to the drain contact of the third NM.
OSl-transistor ms+, ml,, m, 1. rn,
The timing signal φ3 is applied to the drain contact of a, and the fourth N
MOS transistor ma+, mat, m55m
A timing signal φ4 is supplied to the drain contacts of 4a--1--. In FIG. 4, the signals φ1. φ2. φ3. φ4 is a signal corresponding to the timing signals φ1φ, φ, and φ4.

As shown in the figure, the source contacts of the N0M5 transistors are connected in order from the gate electrode G I + closest to the horizontal charge transfer path 8.

The third drive circuit 12 is formed of a shift register that outputs drive signals s, s, s, s, .So at predetermined timings, as described above.

In addition, these second. The third drive circuit 11.12 is the sixth drive circuit 11.12.
It is formed of an NMOS transistor and an electronic element formed in the p-well layer 16 shown in the figure. In the p-well layer 16 of FIG. 6, for example, n-type impurity layers 25 and 26 constituting an NMOS transistor and a gate contact are shown.

Next, a case will be described in which the operation of the charge-coupled solid-state imaging device having such a structure is applied to an electronic still camera that takes still images.

First, the general operation for photographing a still image will be explained with reference to FIG. Assuming that scanning readout of pixel signals is started from time t1 in the figure, at that time t, all the photodiodes and charge transfer paths 1 to 1 remain on the horizontal charge transfer path 8, and the remaining charge transfer path 8 remains at the time t. The unnecessary charges that were present are discarded, and exposure is performed for an appropriate period of time, so that a pixel signal corresponding to the optical image of the object is generated in the photodiode.

First, in a period TVll corresponding to the vertical blanking period of a standard television system such as NTSC, the pixel signals of all photodiodes are simultaneously transferred from the vertical charge transfer path L1 to the wrinkle transfer pixel, and then in the next horizontal blanking period. During the corresponding period THB, the pixel signal of the transfer pixel closest to the horizontal charge transfer path 8 is transferred to the horizontal charge transfer path 8, and then during the period TIN corresponding to the horizontal scanning period (so-called 1H period). , the horizontal charge transfer path 8 is 1
The pixel signals of the first row are read and compared by horizontally transferring the pixel signals of the rows.

Then, a period T corresponding to the next horizontal blanking period
In He, the vertical charge transfer paths L1 to L transfer the pixel signals of the next row to the horizontal charge transfer path 8, and furthermore, in the period TIN corresponding to the next horizontal scanning period, the horizontal charge transfer path 8 performs horizontal transfer. By doing this, the pixel signals of the second row are read out.

Furthermore, pixel signals on the third row are read out during each period T Ha and T IH corresponding to the next horizontal blanking period and horizontal scanning period. Then, the pixel signals of the remaining rows are read and compared in order by repeating the same process, and finally all the pixel signals corresponding to one picture of one frame are read and compared.

Next, the scanning readout operation will be described in detail based on the timing chart for each drive signal and timing signal shown in FIG. Note that the period T ve in FIG. 8 corresponds to the vertical blanking period, the periods T 1 and 1B correspond to the horizontal blanking period, and the period T I H corresponds to the horizontal scanning period. Also, the symbol "H" in the figure is 12 volts, "M" is 0 volts, and 'L'
is 18 volts, and "HH" is about 15 to 15 volts, which is equal to the board voltage.
Indicates a voltage level of 25 volts.

First, in the period TVB corresponding to the vertical blanking period, the timing signal φ□ reaches a predetermined time t.

The timing signal φ6 is always at the “M” level, and the timing signal φ2 is at the “H” level in synchronization with the timing signal φ becoming the “H” level. Narugai is at “L” level,
All drive signals 81 output from the third drive circuit 12
~So is always at "L" level.

Therefore, in this period TvB, the "M" level timing signal φ. As a result, all the NMOS transistors of the first drive circuit 10 become conductive, while all the drive signals s, , s2 . s, -
91, s. is “L” level, so the second drive circuit 1
All NMOS transistors in 1 are non-conductive, and all gate electrodes G II , Gll , G, l
, G41~GIn, Gin, Gl,.

G4° is controlled by the first drive circuit 1o.

That is, the timing signals φ and φ2. When the “H” level does not rise, the odd-numbered gate electrode GG! l, G
ll, G++~G,. G. The gate signal φ1. applied to the gate signal φ1. φ1 φ11. φ! 2~φ1 φ,. teeth,
It becomes equal to the "L" level signal VL (this signal is always set at 18 volts), and a potential barrier is generated in the vertical charge transfer path L□ below these gate electrodes.

On the other hand, even-numbered gate electrodes G t + , G 4+
, G t rG 4 t ” G I n , G
Gate signal φ2φ4.4n applied to gate signal φ2φ4. φ7.
φ4. ~φ, 0 φ4o is equal to the “M” level signal φ, and the vertical charge transfer path L1 under these gate electrodes
A transfer pixel occurs in .

Therefore, the portion adjacent to transfer gate T9 (
(see FIG. 4) all become transfer pixels, and these transfer pixels are separated by a potential barrier.

In this state, at a predetermined time point 1. When the timing signals φ and φ1 become “H” level, all npn
The transistor Q 21 041 , os+ ” becomes conductive, and the even-numbered gate electrode G.

G41, G27, G47~G,. G
Since the "H" level substrate voltage V of about 15 to 25 volts is applied only to 4e, all the transfer gates T9 become conductive, and the pixel signals of all the photodiodes can be transferred to the respective adjacent transfer pixels.

In this way, during the period Tva, a so-called field shift operation is performed, and as shown at time t in FIG. 12, each pixel signal (the black mark indicates each pixel signal) is transferred to the vertical transfer path. be transferred. Incidentally, FIG. 12 shows the charge transfer operation of one vertical charge transfer path.

Next, a period T corresponding to the first horizontal blanking period
In Ha, since the timing signal φ6 is always at the "L" level, all NMOS transistors in the first drive circuit 10 are rendered non-conductive and are isolated from all gate electrodes.

On the other hand, only the drive signal Sl of the first output terminal of the third drive circuit 12 is at "M" level, and the other drive signals S, ~S, are at "L" level, so that the second drive circuit 11 is Only the first coarse NMo5 transistors m++, ff+++, m++m a r related to the drive signal S1 become conductive.

Then, during the period when only the drive signal S1 is at "M" level, a four-phase timing signal φ for performing vertical charge transfer is generated.
1 φ, φ, φ4 are input to the second drive circuit 11, the first to fourth gate signals φ1,
φ2. φ, 1 φ4. Only the timing signal φ,
are equal to φ, φ, φ4, and the first to fourth of the first set
th gate electrode G Il, Gl'1. G1+
, Gll performs charge transfer operation. Incidentally, each signal waveform during this period T, . . . (period from time t to time t4) is shown enlarged in FIG.

As a result, the signal charge is increased to the gate signal φ1. φ
2. Timing of φ,1 φ4 (sign 12.3,
4, 5, 6.7) shown in Figure 12.
As in the second transfer, the pixel signal q + of the first row, which is moved to the horizontal charge transfer path 8 side and is closest to the horizontal charge transfer path 8,
is transferred to the horizontal charge transfer path 8, and the pixel signal Q r + of the second row moves to the position of the first row.

Next, the first horizontal scanning period T, (time 14 to t,
(period), the signal to the gate electrode stops changing, and on the other hand, the horizontal charge transfer path 8 synchronizes with the gate signals α1 to α4 at predetermined timing according to the four-phase drive blade type or the two-phase drive blade type. By performing horizontal transfer, pixel signals for the first row are read out.

Next, in the period of time t, ~t, time t, ~t,
By repeating the same operation as above, pixel signals of the next row are read out. However, during the horizontal blanking period THa from time t to t4, the drive signals S1 and S of the third drive circuit 12 are simultaneously at "M" level, and the remaining drive signals S,
~So becomes “L” level. In addition, during this period T. FIG. 10 shows an enlarged waveform of each gate signal.

As a result, the first to fourth gate electrodes G l
The timing signals φ1 to φ
Gate signal φ1.4 equal to 4. ~φ4. and φ1. ~φ4.
The pixel signals under these gate electrodes are vertically transferred.

That is, according to the timing shown in FIG. 10, as shown in the second vertical scan in FIG. minutes,
The fourth row is transferred one row at a time to the horizontal charge transfer path 8 side.

and - horizontal scanning period T I )l at time t, ~t7
, the horizontal charge transfer path 8 transfers the pixel signal Qz of the second row.
Read +.

Next, when the third scanning readout is started from time t, the drive signals SS and S of the third drive circuit 12 become "M".
level, and the remaining drive signals 84 to So become L'' level, so that the first to twelfth gate electrodes G to G41, G11 to G41, G I I of the first to third sets
Vertical charge transfer is performed by ~G41. Therefore, as in the third transfer in FIG. Pixel signals q,1 are transferred to the horizontal charge transfer path 8 side for one row at a time.

Then, the pixel signal ql+ of the third row is read and compared by the horizontal charge transfer path 8.

Thereafter, each time the pixel signals of each row are read, the drive signals 84 to so of the third drive circuit 12 are sequentially inverted to the "M" level, so that four gate electrodes are driven. The group is expanded sequentially, and in the final horizontal blanking period T, (time t, to t1°), as shown in FIG. 11, all the gate signals φ1. .about..phi.4 has a waveform equal to the timing signal .phi..about..phi.4, and the pixel signals of the last row can be read out in the last scanning readout.

FIG. 13 shows potential profiles of vertical charge transfer operations in arbitrary order, that is, the 1st and +1st vertical charge transfer operations. Alternatively, as the interval between empty transfer pixels increases, pixel signals closer to the horizontal charge transfer path 8 are read out in order.

According to the embodiment described above, the drive circuit that supplies the gate signal to the gate electrode is not formed using a CMOS transistor, but is formed using an NMOS structure MOS transistor and a bipolar structure transistor. It is possible to realize a high-voltage driving circuit, and it is also possible to provide a vertical overflow drain and an electronic shutter function.

By providing a vertical overflow drain structure, the excess charge of the photodiode is discarded to the substrate side, eliminating occurrences of blooming, etc., and also enables an electronic shutter without the substrate, allowing non-interlaced full frame readout. A charge-coupled solid-state imaging device suitable for capturing still images can be provided.

[Effects of the Invention] As described above, according to the present invention, a well layer is formed in a semiconductor substrate, and a circuit using a single-structure MOSI (transistor) is formed in this well layer, so that the withstand voltage is improved. It can also be equipped with a vertical overflow train and an electronic shutter function.

By providing a vertical overflow train structure, the excess charge of the photodiode is disposed of to the substrate side, eliminating the occurrence of blooming, etc. Also, by realizing interline transfer and frame transfer simultaneously, it has an electronic shutter function. A full-frame scanning readout type charge-coupled solid-state imaging device suitable for still image imaging can be provided.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of an electronic still camera to which a charge-coupled solid-state imaging device according to an embodiment of the present invention is applied, FIG. 2 is a schematic configuration diagram of a charge-coupled solid-state imaging device according to an embodiment, and FIG. FIG. 4 is an explanatory diagram showing the main part structure of the light receiving area and peripheral circuit configuration in the embodiment; FIG. 5 is a vertical cross-sectional view taken along the line x-X in FIG. The figure is a vertical cross-sectional view taken along line V-Y in FIG. 4, FIG. 7 is an explanatory diagram schematically showing the scanning readout operation of the embodiment, and FIG. 8 is a detailed illustration of the scanning readout operation of the embodiment. Timing chart: Figures 9, 10, and 11 are timing charts showing the main timing in Figure 8 in an enlarged manner; Figure 12 is a diagram conceptually showing the charge transfer operation during scan readout. , Fig. 13 is a diagram showing the charge transfer operation during scanning readout using a potential profile, Fig. 14 is a structural explanatory diagram showing the main structure of a conventional charge-coupled solid-state imaging device, Figs. 15 and 16 17 are explanatory diagrams for explaining the operation of the conventional example, and FIGS. 18, 19, and 20 are circuit diagrams and structural diagrams for explaining the problems of the conventional example. Symbols in the figure: 1. Imaging optical system 2. Mechanical aperture mechanism 3. Charge-coupled solid-state imaging device 4. Signal processing circuit 5. (Self-recording mechanism 6. Synchronization control circuit 7. Light receiving area Figure 5 122-m
- and time procedure amendment specification August 9, 1990

Claims (1)

[Scope of Claims] In a charge-coupled solid-state imaging device having a vertical Eberflow drain structure that discards unnecessary charges in a light-receiving region toward a semiconductor substrate, a charge transfer path is formed in a well layer buried in the semiconductor substrate. A drive circuit that generates a signal for driving the charge transfer path is formed in a well layer buried separately or integrally with the well layer in the semiconductor substrate, and a transistor having a single MOS structure is formed. What is claimed is: 1. A charge-coupled solid-state imaging device configured using a charge-coupled solid-state imaging device.