JP2880011B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge-coupled solid-state imaging device (CCD), and more particularly to a charge-coupled solid-state imaging device having an electronic shutter function.

[0002]

2. Description of the Related Art In recent years, there has been a demand for a solid-state imaging device having a high resolution and capable of imaging all pixels simultaneously. To achieve high resolution, it is necessary to increase the number of pixels,
When the number of pixels is increased, it is necessary to increase the number of electrodes for charge transfer. For example, if three-phase driving is to be performed, three times as many transfer electrodes as pixels are required.

Conventionally, as a charge-coupled solid-state imaging device, a frame transfer type solid-state imaging device (FT-CCD) to which scanning readout by an accordion transfer method is applied is known (PHILIPS TECHNICAL REVIEW VOL. 43, No. 1). / 2,
1986, The accordion imager, a new solid-state ima
ge sensor, AJPTheuwissen and CHLWeijtens).

FIGS. 14 to 19 schematically show this solid-state imaging device.
This will be described with reference to FIG. First, the entire structure, as shown in FIG. 14, a light receiving portion A consisting of vertical transfer path L ₁ ~L _m of the m having a photoelectric conversion function and a charge transfer function, these vertical transfer path L ₁ ~L a storage unit B to the light-shielding film provided continuously to and the surface is made of a charge transfer path laminated to _m, the horizontal charge transfer path whose surface is covered with a light shielding film with connecting the end of each charge transfer path of the storage section B C is provided.

On the upper surfaces of the vertical charge transfer paths L _{1 to} L _m, a plurality of transfer gate electrodes are provided along the charge transfer direction Y such that one transfer gate electrode corresponds to each pixel. By applying gate signals at predetermined timings according to the accordion transfer method to these gate electrodes, potential wells and potential barriers corresponding to pixels are generated in the vertical transfer paths L _{1 to} L _m during exposure,
At the time of transfer, charge is transferred in the Y direction by changing the potential well and the potential barrier at a predetermined timing.

The shift register indicated by reference symbol D in the figure performs the transfer operation of the start pulse IM in synchronization with the two-phase clock signals φ ₁ and φ ₂ to generate the above gate signal.

The charge transfer path of the storage section B is also provided with a similar gate electrode, and is formed by the shift register E performing a transfer operation of the start pulse ST in synchronization with the two-phase clock signals φ ₁ and φ ₂ . The charge is transferred in the Y direction by the gate signal.

Then, the pixel signal generated in the light receiving section A is
After charge transfer path of the vertical charge transfer paths L ₁ ~L _m and the storage section B is held temporarily transferred to the accumulation unit B while synchronizing, transferring pixel signal accumulation unit B to the horizontal charge transfer path C line by line Then, every time the transfer is performed, the horizontal charge transfer path C transfers the horizontal charge in synchronization with the gate signal from the shift register F, thereby reading out all the pixel signals.

FIG. 15 shows the timing of each signal for scanning and reading. As shown in FIG. 3A, the start pulses IM and ST are supplied to the shift registers D and E at a predetermined timing, and the two-phase clock signal φ is supplied.
_1, and transfers them in synchronism with phi _2.

As shown in FIG. 1B, the gate signals A _I , B _I , from the bit output contacts of the shift register D are applied to the gate electrodes of the vertical charge transfer paths L _{1 to} L _m in the light receiving area A, respectively.
C _I , D _I ... Are supplied in order.

[0011] Similarly, as shown in FIG.
The gate signals A _S , B _S , C _S , D _S.
Are supplied in order. For convenience of explanation, only gate signals corresponding to eight gate electrodes are shown.

These gate signals A _I , B _I , C _I , D
_{I ......, A S, B S} , C S, D S according to the change in voltage ..., as shown in FIG. 16, Ev each gate electrode (the even-numbered gate electrodes of the storage unit B and the light-receiving unit A, Odd gate electrodes are indicated by Od).
Potential wells and potential barriers to transfer in order from the pixel signal q _a side changes.

FIG. 17 shows a typical vertical charge transfer path and charge transfer of the charge transfer path of the storage section B connected thereto. That is, at a certain time t ₀
In this case, potential wells (hatched portions in the drawing) and potential barriers (white portions in the drawing) are generated alternately in the vertical charge transfer path of the light receiving region A in accordance with the arrangement of the gate electrodes. Then, pixel signals q _a , q _b , q _c , q _d ... Are generated using the potential well as each pixel.

These pixel signals are most accumulated in the storage section B.
It will be transferred in order to the storage section B from the side of the pixel signal q _a near. Since the appearance of the potential well and the potential barrier at the time of this transfer is similar to that when the accordion of the musical instrument is gradually expanded and then closed again, it is called an accordion transfer method.

Then, after all the pixel signals are once stored in the storage section B, the pixel signals can be read out in time series via the horizontal charge transfer path C while performing accordion transfer in the same manner.

The charge-coupled solid-state imaging device of the scanning readout type has an effect that the number of transfer gate electrodes can be reduced, and is excellent in high density. In this charge-coupled solid-state imaging device, circuits such as shift registers are formed by transistors having a CMOS structure, and these circuits, a light receiving unit A, a storage unit B, and a horizontal charge transfer path C are integrally formed in a semiconductor substrate. ing.

That is, the shift register comprises the circuit shown in FIG. 18, and the vertical sectional structure in the semiconductor substrate is as shown in FIG. First, in FIG. 18, the shift register is configured as a circuit between a power supply voltage V _CC and V _DD (V _CC > V _DD ), and each bit includes a p-channel MOS transistor connected to the voltage V _CC side. , An n-channel MOS transistor connected to the voltage V _DD side comprises an inverting circuit connected in a complementary relationship.

A MOS transistor which is turned on / off by the clock signals φ ₁ and φ ₂ is connected between these input / output contacts. Note that the capacitive element ε in the figure
Are formed by applying line capacitance or the like. When inputting a start pulse signal IM (or ST) to the first stage bits, the clock signal phi _1, phi ₂ to perform the transfer operation in synchronization, the clock signal phi ₁ and phi gate signal synchronized with ₂ each bit output Occurs at the point of contact.

FIG. 19 shows a structure in which the shift register and the charge transfer path are integrally formed on the same semiconductor chip. That is, in FIG. 19, a plurality of n-type impurity layers are formed in a region serving as a light-receiving portion of a p-type semiconductor substrate to obtain vertical charge transfer L _{1 to} L _m, and further, vertical charge transfer L _{1 to} L _m
A gate electrode is stacked on the upper surface of the device via a gate oxide film (not shown).

On the other hand, an n-well layer is buried in a drive region where a circuit such as a shift register is formed. A pair of p ⁺ -type impurity layers are formed in the n-well layer, and a gate oxide film layer (see FIG. By stacking the gate electrode η _p via a not-shown), a p-channel MOS transistor is formed.

Further, n ^{+ is formed} in a semiconductor substrate (p-Sub).
Buried type impurity layer and a gate electrode η _n
Are formed to form an n-channel MOS transistor, and a CMOS inversion circuit (see FIG. 18) is formed by connecting these gate electrodes η _p and η _n and predetermined nodes.

In such a charge-coupled solid-state imaging device, the power supply voltage V _{CC is set} to about 10 volts, the power supply voltage V _DD is set to 0 volts, and the gate signal voltage of the gate electrode is also set to 0.
It varies in the range of 10 to 10 volts.

[0023]

However, in this charge-coupled solid-state imaging device, as described above, a peripheral circuit such as a shift register for controlling charge transfer is formed by CMOS.
Since it is composed of elements such as transistors with a structure, it has better functions such as a so-called vertical overflow drain for discarding unnecessary charges to the semiconductor substrate side and an electronic shutter function for the charge-coupled solid-state imaging device itself. Has not been realized in terms of structure and pressure resistance.

First, in terms of structure, the above-described conventional example is a frame transfer type image pickup device in which a vertical charge transfer path has a function as a pixel. Is not feasible because of the increase in

On the other hand, in terms of withstand voltage, if a function of a vertical overflow drain is to be provided, a high voltage of, for example, 15 to 25 volts is applied to the semiconductor substrate, and C
The impurity region corresponding to the node of the MOS transistor is destroyed, or the gate oxide film layer is broken down.

Further, in order to realize the function of the electronic shutter, it is necessary to apply a higher voltage to the semiconductor substrate than in the case of the vertical overflow drain.

Further, these problems will be described in comparison with the actual structure shown in FIG. First, in order to have an electronic shutter function, it is necessary to adopt a configuration of an interline transfer system including a photodiode and a CCD transfer path.

That is, in the light receiving section, a plurality of photodiodes corresponding to pixels are arranged in a matrix, a vertical charge transfer path is formed adjacent to these photodiodes, and pixel signals generated in these photodiodes are formed. Is transferred to the vertical charge transfer path via the transfer gate, and then the pixel signal is read out by charge transfer through the vertical charge transfer path.

Accordingly, the vertical sectional structure of the shift register for driving the light receiving region and the gate electrode of the vertical charge transfer path is as shown in FIG. First, in the light receiving area,
A photodiode is formed by arranging a plurality of n ⁺ -type impurity layers in a matrix in a p-well layer embedded in an n-type semiconductor substrate (n-Sub).

[0030] These n ⁺ -type impurity layer adjacent to form an n-type impurity layer serving as a vertical charge transfer path L ₁ ~L _m, further channels embedded these high-concentration p-type impurity around Stopper. Further, a gate electrode is stacked.

On the other hand, a p-well layer is buried in the drive region, a pair of n ⁺ -type impurity layers are formed in the p-well layer, and a gate electrode η _n is formed via a gate oxide film (not shown). Are stacked to form an n-channel MOS transistor.

Further, p ^{+ is formed} in the semiconductor substrate (n-Sub).
Type impurity layer is buried and the gate electrode η _p
To form a p-channel MOS transistor.
By connecting these gate electrodes η _p and η _n to predetermined nodes, a CMOS inversion circuit for a shift register as shown in FIG. 18 is formed.

In order to form a so-called vertical overflow drain structure, a voltage of 15 to 25 volts is applied to the semiconductor substrate to lower the height of the potential barrier formed by the p-well to a predetermined level and have a charge extracting function. Let

In order to simultaneously provide an electronic shutter function, an electrode is formed on a p-well layer in a light receiving region where charges generated in a photodiode are positively discarded toward the semiconductor substrate, and a shutter voltage SS is applied. Then, an npn transistor structure is generated between the photodiode and the substrate so that the charge flows to the substrate side.

Further, in order to transfer the pixel signal generated in the photodiode by the exposure to the vertical charge transfer path, a high voltage of about 12 volts is applied to the transfer gate.

The normal charge transfer operation is performed in the vertical charge transfer path.
In order to do the work, create a potential well
0 volt gate signal and potential barrier
The gate signal of about -8 volts to generate
S so that it is supplied from the S shift register to the gate electrode.
You have to set the signal voltage. That is, in FIG.
And the substrate voltage V_SIs 15-25 volts, power supply voltage V
_CCIs 0 volt, voltage V _LIs set to -8 volts.

With such a CMOS structure, if the above-mentioned voltage relationship is set, the gate signal voltage of the gate electrode changes in the range of -8 to 12 volts, and the p-channel of the CMOS structure in the drive region A high voltage of 23 to 33 volts may be applied to the junction between the gate oxide film layer or the p ⁺ -type impurity layer under the gate electrode η _p of the MOS transistor and the n-type substrate, which greatly exceeds the allowable breakdown voltage. Invite.

The present inventors have previously proposed a solid-state imaging device capable of non-interlaced full-frame reading similarly to the accordion transfer system, and having an overflow drain structure and capable of discharging excess charges and an electronic shutter.

This solid-state imaging device has an improved withstand voltage by using a single-structure MOS (eg, n-channel MOS) as a drive circuit. However, as a result of trial production of this structure, it has been found that it is difficult to provide a logic circuit with a sufficient logic margin when the electronic shutter operates.

An object of the present invention is to provide a solid-state imaging device in which the operation of a control circuit is stable and an electronic shutter operation is possible.

[0041]

A solid-state imaging device according to the present invention comprises a semiconductor substrate of a first conductivity type and a second conductivity type formed on a surface portion of the semiconductor substrate and opposite to the first conductivity type. A first well having a first impurity concentration, a second well formed on a surface portion of the semiconductor substrate and having a second impurity concentration of a second conductivity type and higher than the first impurity concentration, A photoelectric conversion element including a plurality of first conductivity type regions formed in the first well; a bias voltage application terminal connected to the semiconductor substrate; and a plurality of the plurality of first conductivity type regions formed in the second well. A control circuit including the first conductivity type region.

[0042]

The photoelectric conversion element is formed in the first well, and the first well is designed to be operable with an electronic shutter by applying a bias voltage to the semiconductor substrate. The control circuit is formed in a second well having a higher impurity concentration than the first well. Therefore, even when the electronic shutter is activated, the second
Elements in a given well can have a sufficient operation margin.

[0043]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to an example in which the present invention is applied to an electronic still camera for capturing a still image.

First, the overall structure of the electronic still camera is shown in FIG.
This will be described with reference to FIG. In FIG. 1, 1 is an imaging optical system including an imaging lens and the like, 2 is a mechanical stop mechanism, 3 is a charge-coupled solid-state imaging device, and each is arranged in order along the optical axis of the imaging optical system 1, It has a configuration in which a subject optical image is incident on a light receiving area of the charge-coupled solid-state imaging device 3.

Reference numeral 4 denotes a signal processing circuit, and 5 denotes a storage mechanism. The pixel signal output from the charge-coupled solid-state imaging device 3 is subjected to color separation, γ correction, white balance adjustment, and the like by the signal processing circuit 4. A luminance signal and a chrominance signal are formed, and a recording process is performed on the luminance signal and the chrominance signal in the storage mechanism 5 and then stored in a magnetic recording medium or the like.

Then, the synchronization control circuit 6 controls the aperture mechanism 2,
A series of operations from imaging to storage are processed by synchronously controlling the read timing of the charge-coupled solid-state imaging device 3 and the operations of the signal processing circuit 4 and the storage mechanism 5.

The charge-coupled solid-state imaging device 3 has a configuration shown in FIG. That is, the light receiving region 7 for receiving the subject optical image is formed in the p ⁻ -type well having a relatively low impurity concentration, and corresponds to pixels arranged in a matrix along the row direction X and the column direction Y. (in the figure, the portion shown by P) to a plurality of photodiodes and the vertical charge transfer paths L ₁ ~L _m formed adjacent to each photodiode group arranged in the row direction X are provided.

A horizontal charge transfer path 8 is formed at the end of each of the vertical charge transfer paths L _{1 to} L _m , and an output amplifier 9 is formed at the end of the horizontal charge transfer path 8. Further, gate electrodes of a predetermined arrangement are provided in the vertical charge transfer paths L _{1 to} L _m as described later, and a light-shielding layer for preventing light from being incident thereon is laminated on the upper surfaces thereof.

In these gate electrodes, signals for causing the vertical charge transfer paths L _{1 to} L _m to perform a charge transfer operation in synchronization with a predetermined timing are formed in a p-type well having a relatively high impurity concentration. First, second, and third drive circuits 10,
Supplied from 11 and 12.

The driving circuits 10, 11, 1
2, the timing signals φ _H , V _L , φ _G ,
The synchronization control circuit 6 generates φ _FS , V _S , φ ₁ , φ ₂ , φ ₃ , φ ₄ and a start pulse signal.

[0051] The horizontal charge transfer path 8 receives the forwarded come signal charges from the vertical charge transfer paths L ₁ ~L _m, and a gate electrode for horizontal transfer is provided further to the output amplifier 8 side The gate signals α ₁ , α ₂ , α ₃ , α ₄ to be applied to the gate electrodes for performing these operations and the start pulse signal are supplied from the synchronization control circuit 6.

Next, the structure of the light receiving area 7 and the circuit configuration of the driving circuits 10, 11, and 12 connected thereto will be described with reference to FIGS.
It will be described in detail with reference to FIG. FIG. 3 shows the third driving circuit 12.
FIG. 4 is a vertical sectional view taken along line xx in FIG. 6, and FIG. 6 is a sectional view taken along line y-x in FIG. 6, when the structure of the main part of the light receiving region 7 is viewed from the light receiving surface side. FIG. 4 is a vertical sectional view taken along line -y.

First, based on FIG. 3, the third driving circuit 1
Circuit configuration 2 will be described. Drive circuit 12, by transferring in synchronization with the start pulse signal phi _S phase-shifted two-phase clock signals phi _A and phi _B, sequentially logic values from the lower bit output to the upper bit output "H" of This is a shift register that generates a drive signal.

That is, first, only the drive signal S ₁ is at the “H” level, all the other upper bit outputs are at the “L” level, and in the next cycle, the lower two bits of the drive signals S ₁ , S _1
2 becomes the "H" every other upper bits output at the level "L" level, yet other upper bit output by the lower three drive signals S ₁ and S ₂ and S ₃ bits "H" level in the next cycle Are all "L" levels, so that the "H" output level of the drive signal is gradually expanded from the lower bits to the upper bits.

As shown in FIG. 3, since each bit has the same cell structure, the circuit of the first bit will be representatively described. Three MOS transistors u ₁₁ , u ₁₂ , u ₁₃
There is connected between the signal line of the signal line and the clock signal phi _B of the voltage V _L as a serial source-drain path, the gate contact of the transistor u ₁₃ is a signal line of the reset signal RS is connected.

Transistor u₁₁Gate contacts and drains
Bootstrap capacitor ε between contacts₁₁Is connected
And the transistor u₁₂Gate and source contacts are common
Connected, and another MOS transistor u₁₄Source of
Connected to the contact, transistor u ₁₄Drain contact is voltage
V_LSignal line, gate contact is clock signal φ_ASignal line
Connected to each other.

Further, MOS transistors u ₁₁ , u ₁₂ ,
A circuit having the same configuration as the circuit configured by u ₁₃ and u ₁₄ is a MOS
The transistor u ₁₂ is formed by the transistors u ₂₁ , u ₂₂ , u ₂₃ , u ₂₄ and the bootstrap capacitor ε _21.
The drain contact (output point) and gate contact (input point) of the transistor u ₂₁ is connected. However, signals φ _A and φ
_B 's connection is reversed.

This bit input is applied to the transistor u
_The bit output corresponds to transistor u
_This corresponds to ₂₂ drain contacts. Then, a shift register of n bits output by cascading inputs and outputs of these bit cells, the input of the start pulse signal phi _S to the lowest bit cell includes a conducting state in synchronism with the clock signal phi _A It has to do via the analog switch u ₀₀ made.

4 to 6, a p ^- well layer 14 having a relatively low impurity concentration for forming the light receiving region 7 and a first driving circuit 10 are formed on the surface side of the n-type semiconductor substrate 13. Are embedded, and a p-well layer 16 having a relatively high impurity concentration for forming the second and third drive circuits 11 and 12 is buried. ^- the well layer 14, p-well layer 15,
A predetermined circuit is formed in each of the reference numerals 16.

First, as shown in FIG.
^- by arranging in a matrix along a plurality of impurity layers 17 made of n ⁺ -type impurity in the well layer 14 in the row direction X and the column direction Y, the photo diode shown by P in FIG. 2 is formed, Further, by forming an n-type impurity layer (a portion shown by a dotted line in FIG. 6) 18 adjacent to each impurity layer 17 arranged in the row direction Y, the vertical charge transfer paths L _{1 to} L _{m in} FIG. Are formed.

Then, it is indicated by Tg in FIG.
Transfer gate and photoda)
Peripheral except for the ion and vertical charge transfer paths
To p ⁺By forming the impurity layer 19, the channel
A topper region (shaded portion surrounded by a dotted line in FIG. 4) is formed.
You.

In FIG. 4, the photodiodes P in FIG. 2 are indicated by P ₁ , P ₂ , P ₃ , P ₄ ... For each row. Further, in FIG. 4, the vertical charge transfer paths L _{1 to} L _m
Are arranged in regions adjacent to the photodiodes P ₁ , P ₂ , P ₃ , P ₄ ... Arranged in each row, as shown in FIG. electrode _{G 11 ~G 41, G 12 ~G} 42, G 13 ~G 43,
... G _{1n to} G _4n are stacked.

[0063] Further, when the gate electrode G ₁₁ and the first gate electrode, as shown in FIGS. 4 and 5, the odd-numbered gate electrodes _{G 11, G 31, G 12} , G 32, G 13, G ₃₃ ,
The width W2 of... Is formed wide.

Then, gate signals φ ₁₁ , φ ₂₁ , φ ₃₁ ,...
By applying φ ₄₁ , φ ₁₂ , φ ₂₂ , φ ₃₂ , φ ₄₂ , a potential well (hereinafter referred to as a transfer pixel) and a potential barrier for charge transfer are generated in the vertical charge transfer path under each gate electrode. Let it.

The even-numbered gate electrodes G ₂₁ , G ₄₁ ,
When a predetermined high-voltage signal is applied to G ₂₂ , G ₄₂ , G ₂₃ , G ₄₃ ,..., The transfer gate Tg becomes conductive, and the photodiodes P ₁ , P ₂ , P ₃ , P ₄ ,. , And the even-numbered gate electrodes G ₂₁ , G ₄₁ ,
The transfer pixels generated below G ₂₂ , G ₄₂ , G ₂₃ , G ₄₃ ,... Become conductive, and have a structure in which signal charges can be field-shifted from the photodiodes to the transfer pixels.

[0066] Further, as shown in FIG. 4, the end portions of the vertical charge transfer paths L ₁ ~L _m horizontal charge transfer path 8 is formed,
A gate electrode for transferring signal charges in the horizontal direction at a timing according to the four-phase driving method or the two-phase driving method is provided.

Next, the circuit configuration of the drive circuit 10 of FIG. 2 will be described with reference to FIGS. When the gate electrode G ₁₁ closest to the horizontal charge transfer path 8 and the first gate electrode, the odd-numbered gate electrodes _{G 11, G 12, G 13} , G 33, ...
, Each of which has an NMOS transistor M ₁₁ , M ₃₁ ,
Are connected to the signal line of the signal _VL via M ₁₂ , M ₃₂ , M ₁₃ , M ₃₃ ,..., And the even-numbered gate electrodes G ₂₁ , G ₄₁ ,
_{G 22, G 42, G 23} , G 43, the tip NMOS transistor M ₂₁ of _{......, M 41, M 22,} M 42, M 23, M 43, ......
Through, and is connected to the signal line of the driving signal phi _H.

Also, the gate contacts of these transistors
Has a drive signal φ_GIs supplied. In addition, even-numbered
Gate electrode G_{twenty one}, G₄₁, G_{twenty two}, G₄₂, G_{twenty three}, G₄₃, ……
 Each end has an npn transistor Q_{twenty one}, Q₄₁, Q
_{twenty two}, Q₄₂, Q_{twenty three}, Q₄₃, …… Emitter contacts are connected
The drive signal φ is applied to the base contact of each npn transistor.
_FS, The collector contact has the voltage V_SIs applied.

As shown in the structure in the p-well layer 15 in FIG. 6, these NMOS transistors have a structure in which a pair of n ⁺ -type impurity layers 20 and 21 and a gate electrode are laminated on the surface. The drive signal φ _H is applied to the n ⁺ -type impurity layer 20 serving as the drain contact, and the n ⁺ -type impurity layer 21 serving as the source contact is connected to the gate electrode on the vertical charge transfer path. The signal _VL is applied to the p ⁺ -type impurity layer 22 embedded in the p-well layer 15.

The npn transistor comprises ap ⁺ -type impurity layer 23, an n ⁺ -type impurity layer 24 buried in a p-well layer 15, and an n-type semiconductor substrate 13, and has an n ⁺ -type impurity layer 24 serving as an emitter contact. Connects to each gate electrode,
Is p-well layer 15 and the p ⁺ -type timing signal to the impurity layer 23 phi _FS is applied as a base contact, the bias voltage V _S of the substrate 13 is applied to the n-type semiconductor substrate 13 as a collector contact.

Next, the second driving circuit 11, a timing signal phi ₁ to [phi] ₄ are supplied from the synchronization control circuit 6 a third driving signals _{S 1, S 2, S 3} , S 4 ...... S n NMOS transistors m ₁₁ , m ₂₁ , m ₃₁ , m
₄₁ ......

A set of four NMOS transistors is provided, and the third drive circuit 12 is sequentially connected to their gate contacts.
Drive signals S ₁ , S ₂ , S ₃ , S ₄ ,.
First NMOS transistors m ₁₁ , m ₁₂ , m of each set
₁₃ , m ₁₄ ,... Timing signal φ ₁ ,
Second NMOS transistors m ₂₁ , m ₂₂ , m ₂₃ , m
_The timing signal φ ₂ , the third NMOS transistors m ₃₁ , m ₃₂ , m ₃₃ , m ₃₄ ,.
, The timing signal φ ₃ , the fourth N
MOS transistors _{m 41, m 42, m 43} , m 44, the timing signal phi ₄ to the drain contact of the ...... is supplied.

In FIG. 4, the NMOS transistor
m₁₁, M_{twenty one}, M₃₁, M₄₁, …… Signal of each source contact side
φ₁₁, Φ_{twenty one}, Φ₃₁, Φ₄₁,... Are the timing signals φ₁,
φ_Two, Φ _Three, Φ_FourIs a signal corresponding to.

[0074] Then, as illustrated, the source contact of each NMOS transistor in order from the gate electrode G ₁₁ closest to the horizontal charge transfer path 8 is connected. Third driving circuit 12, the driving signals S ₁ of a predetermined timing as described above, S _2, S _3, S _4, and is formed with a shift register for outputting ...... S _n.

The second and third drive circuits 1
Numerals 1 and 12 indicate N formed in the p-well layer 16 shown in FIG.
It is formed of MOS-structure transistors and electronic elements. In the p-well layer 16 of FIG.
The n ⁺ -type impurity layers 25 and 26 constituting the S transistor and the gate contact are shown. The p-well layer 15,
The impurity concentration of 16 is, for example, 1.3 times or more the impurity concentration of p ⁻ well layer 14.

N-type regions 17 and 18 in p ^- well layer 14
Is the emitter, p ^- well layer 14 is the base, n-type substrate 13
Is a collector, a bipolar transistor is formed. When a positive forward bias voltage is applied to the shutter switch SS, the base is forward-biased, and charges flow from the n-type regions 17 and 18 serving as emitters to the n-type substrate 13 serving as a collector. The reset is performed by this operation.

Note that the substrate withdrawing electronic shutter operation can be performed by increasing the substrate potential V _S. To approximate the spectral sensitivity of each photodiode in luminosity, p ^-
The thickness of the well layer 14 is generally limited. When the effective thickness of the photodiode is reduced, the sensitivity on the short wavelength side where the absorption coefficient is high increases relatively with respect to the long wavelength side where the absorption coefficient is low.

Under such conditions, the substrate potential V _S
, The potential barrier formed by p ⁻ well layer 14 can be reduced. When the potential barrier becomes low, the electric charges accumulated in the n-type regions 17 and 18 are extracted to the substrate 13.

[0079] If the p-well layer 15, 16 p ^- to form a p-type region of the same characteristics as the well layer 14, there is a current from the n-type region in the substrate to form a transistor may flow when an electronic shutter operation . Then, an unexpected current flows through the transistor, and the control circuit malfunctions.

In the present embodiment, the p-well layers 15 and 16 for forming the control circuit are set to have a higher impurity concentration than the p ^- well layer 14 for forming the light receiving portion, and the malfunction of the control circuit is prevented. To prevent.

Next, a charge-coupled solid having such a structure
An electronic still camera that captures still images of the operation of the imaging device
A description will be given of a case where the present invention is applied. First, take a still image
The general operation for performing this will be described with reference to FIG. In the figure
At some point t₁Start scanning of pixel signals from
At that time t ₁Previously, all Photodaio
And vertical charge transfer path L₁~ L_mAnd horizontal charge transfer path 8
Unnecessary charge remaining in the
Exposure is performed between the photodiodes
Generates a pixel signal corresponding to the subject optical image.

First, in a period _TVB corresponding to a vertical blanking period of a standard television system such as NTSC,
The pixel signals of all the photodiodes are simultaneously transferred to the transfer pixels on the vertical charge transfer paths L _{1 to} L _m , and during a period _THB corresponding to the next horizontal blanking period, the transfer pixel closest to the horizontal charge transfer path 8 Is transferred to the horizontal charge transfer path 8, and then the horizontal charge transfer path 8 horizontally transfers the pixel signals for one row in a period _T1H corresponding to a horizontal scanning period (a so-called 1H period). To read the pixel signals of the first row.

[0083] Then, in the period T _HB corresponding to the next horizontal blanking period, the vertical charge transfer paths L ₁ ~L _m forwards the pixel signal of the next line to the horizontal charge transfer path 8, further
In the period T _1H corresponding to the next horizontal scanning period, the horizontal charge transfer path 8 performs horizontal transfer, so that pixel signals in the second row are read.

[0084] Further, reads the third row of the pixel signal in each period T _HB and T _IH equivalent during the next blanking period and horizontal scanning. Then, the pixel signals in the remaining rows are sequentially read out by repeating the same processing, and finally all the pixel signals corresponding to one frame image are read out.

Next, the scanning read operation will be described in detail with reference to each drive signal and timing chart shown in FIG.
In FIG. 8, a period _{TVB corresponds} to a vertical blanking period, a period _THB corresponds to a horizontal blanking period, and a period _T1H corresponds to a horizontal scanning period. Also, reference symbols "H" in the figure are 12 volts, "M" is 0 volt, "L" is -8 volts, "HH"
Indicates a voltage level of about 15 to 25 volts equal to the voltage of the substrate.

First, a period corresponding to the vertical blanking period
Interval T_VBThen the timing signal φ_HIs a predetermined time t_Twoso
Outside the “H” level, the “M” level is reached.
Signal φ _GIs always at the “M” level and the timing signal
φ_FSIs the timing signal φ_HBecomes “H” level.
In the meantime, except for the “H” level, the “L” level
 All drive signals S output from the third drive circuit 12₁~
S_nIs always at the “L” level.

Therefore, during this period T _VB , the first drive circuit 1 is driven by the “M” level timing signal φ _G.
0, all the NMOS transistors become conductive, while all the drive signals S ₁ , S ₂ ,
S _3, since ...... S _n becomes "L" level, all the NMOS transistors in the second driving circuit 11 is turned off, and all the gate electrodes _{G 11, G 21, G 31} , G 41 ~ G
_1n , G _2n , G _3n , G _4n are controlled by the first drive circuit 10.

That is, when the timing signals φ _H and φ _FS do not become “H” level, the gate signals applied to the odd-numbered gate electrodes G ₁₁ , G ₃₁ , G ₁₂ , G _{32 to} G _1n , G _3n φ ₁₁ , φ ₃₁ , φ ₁₂ , φ _{32 to} φ _1n , φ _3n are “L”
Level signal V _L (this signal is always set to −8 volts), and a potential barrier is generated in the vertical charge transfer paths L _{1 to} L _m below these gate electrodes.

On the other hand, even-numbered gate electrodes G ₂₁ , G ₄₁ ,
G _22, G ₄₂ ~G _2n, the gate signal phi ₂₁ to be applied to the G _4n,
φ ₄₁ , φ ₂₂ , φ _{42 to} φ _2n , φ _4n are equal to the “M” level signal φ _H, and transfer pixels are generated in the vertical charge transfer paths L _{1 to} L _m below these gate electrodes. .

Therefore, all the portions adjacent to the transfer gate Tg (see FIG. 4) become transfer pixels, and these transfer pixels are separated by a potential barrier.

In this state, when the timing signals φ _H and φ _FS go to the “H” level at the predetermined time t ₂ , all the npn transistors Q ₂₁ , Q ₄₁ , Q ₆₁ ... Th gate electrodes G ₂₁ , G ₄₁ , G
_22, G ₄₂ ~G _2n, since G _4n only about 15-25 volts at the "H" level of the substrate voltage V _S is applied, all the transfer gate Tg is rendered conductive, the pixel signals of all the photodiodes, respectively Transfer to the next transfer pixel.

[0092] Thus, in the period T _VB, so-called field shift operation is performed, as shown at time t ₂ in FIG. 12, the pixel signal (hatched portion indicates a pixel signal) is vertical transfer path Moved to FIG. 12 shows a charge transfer operation of a certain vertical charge transfer path.

Next, in the period _THB corresponding to the first horizontal blanking period, since the timing signal φ _G is always at the “L” level, all the NMOs in the first drive circuit 10
The S transistor becomes non-conductive and is separated from all gate electrodes.

On the other hand, the first output terminal of the third drive circuit 12
Child drive signal S₁Only the "M" level, other drive signals S
_Two~ S_nBecomes “L” level so that the second drive
Drive signal S in circuit 11₁First set of NMOS related to
Transistor m₁₁, M_{twenty one}, M ₃₁, M₄₁Only the conduction state
Become.

Then, the driving signal S₁Only "M" level
During the period when the four-phase
Imming signal φ₁, Φ_Two, Φ_Three, Φ_FourIs the second drive circuit
11 so that the first to fourth first set of games
Signal φ₁₁, Φ_{twenty one}, Φ₃₁, Φ ₄₁Only the timing signal φ
₁, Φ_Two, Φ_Three, Φ_FourAnd the first pair of the first to
Fourth gate electrode G₁₁, G_{twenty one}, G₃₁, G₄₁Charge transfer
Will be sent. Note that this period T_HB(Time t_Three
~ T_FourFigure 9 shows the signal waveforms of
You.

As a result, the signal charges are generated at the timings of the gate signals φ ₁₁ , φ ₂₁ , φ ₃₁ , φ ₄₁ shown in FIG.
3, 4, 5, 6, and 7), the transfer is made to the horizontal charge transfer path 8 side as in the first transfer shown in FIG. The pixel signal q _1j is transferred to the horizontal charge transfer path 8 and the pixel signal q _2j on the second row moves to the position on the first row.

Next, in the first horizontal scanning period T _1H (time period from t _{4 to} t ₅ ), the change of the signal to the gate electrode stops, while the horizontal charge transfer path 8 is driven by the four-phase driving method. Alternatively, the gate signal α _{1 at} a predetermined timing according to the two-phase driving method
By performing the horizontal transfer in synchronism with to? _4, it reads the first pixel signals for one row.

[0098] Next, in a period of time t ₅ ~t _7, by repeating the same operation as the time t ₃ ~t _5, reads the pixel signal of the next line. However, the time t ₃ ~
In the horizontal blanking period T _HB of t _4, the third drive signals S ₁ and S ₂ are simultaneously "M" level of the drive circuit 12, the remaining drive signals S ₃ to S _n becomes "L" level. The waveform of each gate signal during this period _THB is shown in an enlarged manner in FIG.

As a result, the first to fourth first set of gate electrodes G _{11 to} G ₄₁ and the fifth to eighth second set of gate electrodes G _{12 to} G ₄₂ generate the timing signal φ _1. will be driven to the gate signal phi ₁₁ to [phi] ₄₁ equals to [phi] ₄ by phi ₁₂ to [phi] _42, the pixel signals under these gate electrodes are vertically transferred.

That is, according to the timing shown in FIG. 10, as shown by the second vertical scanning in FIG. 12, the pixel signal q _{2j in} the second row is transferred to the horizontal charge transfer path 8, and the third row is The second and fourth rows are transferred to the horizontal charge transfer path 8 side by row.

Then, at time t₆~ T₇Horizontal scanning period T
_1H, The pixel signals in the second row from the horizontal charge transfer path 8
q_2jIs read. Next, at time t₇3rd scan reading from
When the reading is started, the drive signal S of the third drive circuit 12 is output.
₁, S_TwoAnd S_ThreeBecomes "M" level, and the remaining drive signals
S_Four~ S _nBecomes the “L” level.
First to twelfth gate electrodes G₁₁~ G₄₁, G₁₂~
G₄₂, G₁₃~ G₄₃Causes vertical charge transfer.
Therefore, as shown in the third set of FIG.
Eye pixel signal q_3jIs transferred to the horizontal charge transfer path 8,
Are the pixel signals q of the fourth to sixth rows._4j, Q_5jIs 2
For each row, the pixel signal q_6jIs for one row, horizontal charge transfer path₈~ side
Transferred to

Then, the pixel signal q _{3j in} the third row is read out by the horizontal charge transfer path 8. Thereafter, every time the pixel signal of each row is read, the drive signal S of the third drive circuit 12 is
_{By 4} to S _n is gradually inverted "M" level in sequence, a gate electrode to be driven is continue to gradually expand the four addressed as a set, the last horizontal blanking period T _HB (time t ₉
~ T ₁₀ ), as shown in FIG. 11, all the gate signals φ _{11 to} φ _4n have waveforms equal to the timing signals φ _{1 to} φ ₄ , and the pixel signals of the last row can be read by the last scan reading. it can.

FIG. 13 shows an arbitrary order, that is, the k-th and (k + 1) -th vertical charge transfer operations by a potential profile. As shown in FIG. As the number of transfer pixels with the distance between them increases, the pixel signals closer to the horizontal charge transfer path 8 are read out sequentially.

According to the configuration described above, the driving circuit for supplying a gate signal to the gate electrode of the light receiving section is formed by a CMOS circuit.
An NMOS transistor M formed not in a MOS transistor having a structure but in a p-well having a higher impurity concentration than a light receiving portion.
Since the transistor is formed using an OS transistor and a transistor having a bipolar structure, a driving circuit with high withstand voltage can be realized, and a vertical overflow drain and an electronic shutter function can be provided.

By providing a vertical overflow drain structure, excess charge of the photodiode is discarded to the substrate side to eliminate blooming and the like, and an electronic shutter without a substrate is enabled, so that non-interlaced full frame reading can be performed. It is possible to provide a charge-coupled solid-state imaging device suitable for imaging a still image.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example,
It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0107]

As described above, according to the present invention,
In a solid-state imaging device having a large number of photoelectric conversion elements arranged in a matrix, an electronic shutter can be enabled and malfunction of an integrated control circuit can be prevented.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an electronic still camera to which a charge-coupled solid-state imaging device is applied.

FIG. 2 is a schematic configuration diagram of a charge-coupled solid-state imaging device.

FIG. 3 is a circuit diagram illustrating a configuration of a drive circuit 12 in the solid-state imaging device illustrated in FIG.

FIG. 4 is a schematic plan view showing a main part structure and a peripheral circuit structure of a light receiving region in the structure of FIG.

FIG. 5 is a vertical sectional view taken along the line xx in FIG. 4;

FIG. 6 is a vertical sectional view taken along line yy in FIG. 4;

FIG. 7 is a signal waveform diagram schematically showing a scanning read operation.

FIG. 8 is a timing chart showing a scanning read operation in detail.

FIG. 9 is an enlarged timing chart showing the main part timing in FIG. 8;

FIG. 10 is an enlarged timing chart showing the main part timing in FIG. 8;

FIG. 11 is a timing chart showing an enlarged main part timing in FIG. 8;

FIG. 12 is a diagram conceptually showing a charge transfer operation at the time of scanning readout.

FIG. 13 is a potential profile for performing a charge transfer operation during scanning readout.

FIG. 14 is a schematic plan view showing a main structure of a conventional charge-coupled solid-state imaging device.

FIG. 15 is a signal waveform diagram for explaining the operation of the conventional example.

FIG. 16 is a potential profile illustrating the operation of the conventional example.

FIG. 17 is a schematic diagram illustrating the operation of a conventional example.

FIG. 18 is a circuit diagram of a shift register for explaining a problem of a conventional example.

FIG. 19 is a partial cross-sectional view of a solid-state imaging device for describing a problem of a conventional example.

FIG. 20 is a partial cross-sectional view of a solid-state imaging device for describing a problem of a conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 imaging optical system 2 mechanical diaphragm mechanism 3 charge-coupled solid-state imaging device 4 signal processing circuit 5 storage mechanism 6 synchronization control circuit 7 light receiving area 8 horizontal CCD 9 output amplifier 10, 11, 12 drive circuit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 5/335 H01L 27/148

Claims (2)

(57) [Claims] 1. A semiconductor substrate of a first conductivity type, and a first well formed on a surface portion of the semiconductor substrate and having a first impurity concentration of a second conductivity type opposite to the first conductivity type. A second well formed on a surface portion of the semiconductor substrate and having a second conductivity type and a second impurity concentration higher than the first impurity concentration; and a plurality of second wells formed in the first well. A photoelectric conversion element including a first conductivity type region, a bias voltage application terminal connected to the semiconductor substrate, and a control circuit including a plurality of first conductivity type regions formed in a second well. Solid-state imaging device. 2. The solid-state imaging device according to claim 1, further comprising another bias voltage application terminal connected to said first well portion.