TWI416948B - Stack-type semiconductor device with integrated sensors - Google Patents

Abstract

Provided is a sensor circuit and an address specification type image sensor capable of accumulating signal charges of all the pixels substantially simultaneously and realizing a high pixel numerical aperture. A plurality of pixels (11) arranged in a matrix are divided into groups of n pixels, which are connected in parallel to a common node (13) so as to constitute a plurality of pixel blocks (12). Each of the pixel blocks (12) includes: n photoelectric conversion elements (PD<SUB>1</SUB> to PD<SUB>n</SUB>) connected in parallel to the common node (13); and n transfer gates (TG<SUB>1</SUB> to TG<SUB>n</SUB>) for opening and closing channels connecting the photoelectric conversion elements (PD<SUB>1</SUB> to PD<SUB>n</SUB>) and the common node (13). Outside of each of the pixel blocks (12), a common reset transistor (Tr<SUB>RST</SUB>) for resetting all the pixels (11) and a common amplification transistor (Tr<SUB>AMP</SUB>) for amplifying the signal read from the n pixels (11).

Description

Multilayer semiconductor device loaded with integrated sensor

The present invention relates to a stacked type semiconductor device mounted with an integrated body sensor, and more particularly to a sensor circuit including a photoelectric conversion element, a transfer gate, a reset transistor, and an amplifying transistor, and By using the sensor circuit, it is possible to easily design an address-receiving type image sensor in which all pixels can be simultaneously exposed.

In the past, a solid-state imaging device uses a CCD (Charge-Coupled Device) to transmit a CCD image sensor (charge-transfer type image sensor) of signal charges of all pixels arranged in an array. It is often profitable. However, in recent years, CMOS image sensors (X-Y address-specified image sensors) that select pixels from all pixels arranged in an array by scanning in the horizontal direction and the vertical direction have gradually increased. From advanced monocular digital cameras to mobile phones, they are already in use. The reason why it is valued is that compared with CCD image sensors, CMOS image sensors have the following advantages: only one power supply is needed to save power, and standard CMOS (Complementary Metal-Oxide-Semiconductor: complementary) Metal oxide semiconductor processes are manufactured to make and easy to implement system on chips.

However, in the conventional general CMOS (address-specific) image sensor, there are the following two problems.

The first problem is that the signal charges of all the pixels cannot be simultaneously stored (in other words, simultaneously exposed).

That is, in the CCD image sensor, the storage of the signal charge is started at the same time for all the pixel systems, and the stored signal charge is read and transmitted from each pixel together, and therefore, the signal charge storage of all the pixels is performed. The period (this is equivalent to the exposure period) is the same. In contrast, in the conventional CMOS image sensor, the storage of the signal charge is started for each column or each pixel of the pixel array, and the signal charge stored in each pixel is determined by the address specification. The timing is read sequentially, with a time error (time-point error) during the storage of the signal charge for each pixel. Therefore, the signal charge cannot be stored at the same time as the CCD image sensor. The reason will be described below using FIG. 33 and FIG.

Fig. 33(a) is a conceptual diagram of a general circuit configuration of a CCD image sensor; Fig. 33(b) is a conceptual diagram of a storage period of a signal charge of the CCD image sensor. FIG. 30(a) is a conceptual diagram of a general circuit configuration of a conventional CMOS image sensor; FIG. 30(b) is a conceptual diagram of a storage period of a signal charge of the CMOS image sensor. [Refer to Mi Ben and also "Basic and Application of CCD/CMOS Image Sensors" (CQ Press, 2003) 175 pages and 179 pages]

As shown in FIG. 33(a), the CCD image sensor is arranged in an array of a plurality of pixels, each of which includes a photodiode as a photoelectric conversion element, and stores therein in a plurality of photodiodes. The signal charge corresponding to the intensity of the illumination. The signal charges stored in the respective pixels, and the transfer gates (not shown) provided for the respective pixels are collectively read by the vertical CCDs arranged along the respective rows of the pixel array. The reading of the vertical CCD is generally performed together at the end of the vertical blanking period. The signal charges read by the vertical CCDs are sequentially transmitted to the common horizontal CCDs arranged along the array of pixels by the vertical transfer of the vertical CCD. In this way, the signal charge transmitted to the horizontal CCD is further horizontally transmitted to the output end by the horizontal CCD, and is amplified by the FD (Floating Diffusion) amplifier provided at the output end to become a signal output.

During the storage of the signal charge of the CCD image sensor, it can be easily understood from FIG. 33(b) that the pixels corresponding to the N scanning lines (1 to N) constituting the one frame respectively have the same During storage, in other words, the storage period is set at the same time. This phenomenon should be clarified by taking into account the action of the signal charge stored in each pixel being read by the vertical CCD.

On the other hand, in a conventional CMOS image sensor, as shown in FIG. 30( a ), a plurality of pixels arranged in an array shape respectively include a photodiode as a photoelectric conversion element, and are used to amplify An amplifier for signal charge stored by the photodiode. The selection of each pixel in the pixel array is performed by the vertical scanning circuit sequentially selecting the column selection lines, and the horizontal scanning circuit sequentially selects the row signal lines (that is, sequentially designating the X-Y addresses). In Fig. 30 (a), the state is indicated by a switch provided in each pixel and a switch provided in each row of signal lines. The CDS (Correlated Double Sampling) circuit, which is set on each line of signal lines, is used to remove noise from the signal charge flowing through each line of signals. The signal charges selected from the respective pixels in the above manner are sequentially sent to the common horizontal signal line, and are outputted as signals after passing through an output circuit connected to one end of the horizontal signal line.

During the storage period of the signal charge of the conventional CMOS image sensor, as shown in FIG. 30(b), it can be understood that the pixels corresponding to the N scanning lines (1 to N) constituting one frame respectively are stored. The time difference is sequentially generated along with the scanning time points of the respective scanning lines. The reason is that in the CMOS image sensor, unlike the CCD image sensor, there is a vertical register (vertical CCD). Therefore, if the signal charge of each pixel is reset, the signal charge is transmitted to There is a difference in the timing of the corresponding line signal.

Thus, in the conventional CMOS image sensor, the storage period of the signal charge varies with the scan line, and there is a difficulty in the simultaneous storage of the signal charge (in other words, simultaneous exposure), and therefore, if desired When a high-speed moving object is photographed, there is a problem that the image obtained is distorted. For example, if you want to photograph a blade that rotates at a high speed, it will cause a distorted image like Figure 34(b). On the other hand, if a CCD image sensor capable of simultaneously storing signal charges (simultaneous exposure) is used for photographing, the image in this case will be as shown in FIG. 34(a), and the obtained image will not occur. Distortion (Figure 34, based on the above "Basic and Application of CCD/CMOS Image Sensors" on page 180).

A second problem of the conventional CMOS image sensor is that the light-receiving area which is effective compared to the pixel area is narrow, in other words, there is a problem that the pixel has a low fill factor. The reason will be described below with reference to FIGS. 31 and 32. Fig. 31 is a schematic circuit diagram of a conventional CMOS image sensor; Fig. 32 is a cross-sectional view showing the principal part of a schematic device structure.

The circuit configuration shown in FIG. 31 is a CMOS image sensor having a 4-crystal type pixel, and includes four transistors (transfer gate, reset power) in addition to the photodiode in one pixel. Crystal, amplified transistor, and 4 MOS transistors for gate selection). The transistors such as these are formed and disposed on a p-type germanium (Si) substrate as shown in the device configuration of FIG. Furthermore, Vcc is the power supply voltage and V _RST is the reset voltage.

Taking the pixel (i, j) of the i-th column of the i-th column of FIG. 31 (where i and j are positive integers), the transfer gate is applied with a voltage pulse φ _Ti through the read control line of the i-th column. The signal is turned on, and the signal charge stored in the photodiode is transmitted to the node connecting the transfer gate, the reset transistor, and the amplifying transistor to each other at a predetermined timing. The transistor is reset, the voltage pulse φ _RST is applied through the reset line of the i-th column to be turned on, and the transmission gate that has become the conductive state is transmitted, and the signal charge stored in the photodiode is reset at the timed point ( A predetermined reset voltage V _{RST is} applied to the photodiode). The amplifying transistor connected to the node is configured as a source follower and has a function of amplifying the signal charge sent to the node. When the gate is selected, the voltage pulse φ _SEL1 is applied to the ON state through the column selection line (not shown) of the i-th column, and the amplified signal charge is transmitted to the corresponding j-th row signal at the predetermined timing. line. Furthermore, the C _SN connected to the node represents the parasitic capacitance generated by the node.

The circuit structure of the pixels of the CMO image sensor also has three transistor types. Among the three transistor types, one pixel includes three transistors (resetting the transistor, amplifying the transistor, and selecting the MO transistor for the gate) in addition to the photodiode. That is, it is a configuration in which the transfer gate is omitted from the configuration of the four transistor types.

The circuit configuration of Fig. 31 can specifically realize the configuration shown in Fig. 32. That is, in a surface region of a p-type germanium (Si) substrate, a plurality of device regions are divided by a component isolation insulating film to form a photodiode, a transfer gate, a reset transistor, an amplifying transistor, and The gate is selected to form four MOS transistors.

In the device configuration of the conventional CMOS image sensor, it can be understood from the cross-sectional view of the main part of FIG. 32 that four or three MOS transistors occupy the pixel area regardless of the 4-transistor type or the 3-transistor type. In most of the cases, the ratio of the area occupied by the photodiode (the opening portion) in the pixel area (that is, the "opening ratio") is relatively small. The aperture ratio of a conventional CMOS image sensor is generally as low as about 30%. Therefore, there is a problem that the sensitivity is low. If the problem of low sensitivity is to be removed, the pixel area (pixel size) must be enlarged, but this is contrary to the demand for miniaturization, rather than an ideal practice.

A CMOS image sensor disclosed in Patent Document 1 (JP-A-2004-266957) is an example of a CMOS sensor for solving the first problem, which can achieve simultaneous exposure of all pixels. The CMOS image sensor is characterized in that: a light receiving element is provided in the pixel; a first transfer mechanism for transmitting the signal charge generated by the light receiving element to the next segment; and the output of the first transfer mechanism is temporarily stored. a storage unit; an initialization mechanism for initializing charge of the light receiving element and the storage unit; a second transfer mechanism connected to the storage unit; and externally reading the charge from the second transfer unit as a voltage a charge detecting unit that reads the stored charge by the operation of the first transfer mechanism for all the pixels, and initializes the signal charge by the operation of the initialization mechanism for all the pixels (refer to Apply for patent scope 1). The effect of the invention is that "in the CMOS image sensor, all the pixels can be initialized electronically at the same time, and the pixel circuit can be simplistic in a simple process. Moreover, it can be enlarged in the pixel. To seek low noise (see paragraph 0036).

On the other hand, in recent years, a semiconductor device in which a plurality of semiconductor wafers are laminated to form a three-dimensional structure has been proposed. For example, in the "1999 IEDM technical digest" issued by Kurino et al. in 1999, there is proposed a "smart image sensor chip having a three-dimensional structure" (see Non-Patent Document 1).

The image sensor wafer has a four-layer structure, a processor array and an output circuit are disposed on the first semiconductor circuit layer, a data latch circuit and a shield circuit are disposed on the second semiconductor circuit layer, and a third semiconductor circuit layer is disposed on the third semiconductor circuit layer. An amplifier and an analog/digital converter; an image sensor array is disposed on the fourth semiconductor circuit layer. At the top of the image sensor array, it is covered with a quartz glass layer containing a microlens array, and a microlens array is formed on the surface of the quartz glass layer. In each of the image sensors in the image sensor array, a photodiode as a semiconductor light receiving element is formed. An adhesive is used to form a mechanical connection between each of the semiconductor circuit layers constituting the four-layer structure, and an electrical connection is made to each other by using a buried wiring using a conductive plug and a microbump electrode contacting the buried wiring. .

In addition, in "The Japanese Society of Applied Physics" issued by Lee et al. in April 2000, the "Development of 3D Layering Technology for Highly Parallel Image Processing Wafers" is proposed. An image processing wafer is proposed, which includes The image sensor is the same as the solid-state image sensor proposed by Kino et al. (see Non-Patent Document 2).

The image processing wafer of Lee et al. has substantially the same structure as the solid-state image sensor proposed by Liye et al. in the above paper.

The conventional image sensor wafer and image processing wafer disclosed in Non-Patent Documents 1 and 2 are a plurality of semiconductor wafers (hereinafter also referred to as wafers) having a desired semiconductor circuit therein. After laminating and fixing each other, the obtained wafer laminate is diced and divided into a plurality of wafer groups to be produced. That is, the semiconductor wafer in which the semiconductor circuit is formed is layered and integrated at a wafer level, and then formed into a three-dimensional laminated structure, and then divided to obtain an image sensor wafer or Image processing wafer.

Further, in the conventional image sensor wafer and image processing wafer, a plurality of semiconductor circuits stacked inside the wafer constitute a "semiconductor circuit layer".

[Non-Patent Document 1] Li Ye et al., "Smart Image Sensor Chip with Three-Dimensional Structure", 1999. IEDM Technical Abstracts 36.4.1~36.4.4 (H. Kurino et al., "Intelligent Image Sensor" Chip With Three Dimensional Structure", 1999 IEDM Technical Digest, pp. 36.4.1-36.4.4, 1999) [Non-Patent Document 2] Li et al., "Development of a three-dimensional integrated technique for highly parallel image processing wafers" "The Journal of Applied Physics of Japan", Vol. 39, p. 2473~2477, Part 1 4B, April 2004 (K. Lee et al., "Development of Three-Dimensional Integration Technology for Highly Parallel Image-Processing Chip", Jpn.J.Appl.Phys.Vol.39, pp.2474-2477, April 2000)

[Patent Document 1] Japanese Laid-Open Patent Publication No. 2004-266597 (Fig. 1 - Fig. 2, Fig. 8, Fig. 12, Fig. 15)

As described above, in the conventional CMOS (address-specified type) image sensor, there are two problems that the simultaneous storage of all the pixel signal charges (in other words, simultaneous exposure) and the low aperture ratio of the pixels are not possible.

In the conventional CMOS image sensor disclosed in Patent Document 1, simultaneous exposure of all pixels can be achieved. However, in each pixel, in addition to the light receiving element, a first transfer mechanism for transmitting the signal charge generated by the light receiving element to the next stage and temporarily storing the output of the first transfer mechanism are required. The storage unit, the initialization mechanism for initializing the charge of the light-receiving element and the storage unit, and the second transfer mechanism connected to the storage unit are added to the 3-transistor type CMOS image sensor. It is composed of a storage unit. Therefore, in the CMOS image sensor, there is a problem that the aperture ratio of the pixel is low.

In the image sensor wafer and the image processing wafer disclosed in Non-Patent Documents 1 and 2, only the semiconductor wafer or the semiconductor wafer is laminated and fixed to achieve a three-dimensional laminated structure, and the conventional CMOS is known. The above two problems of the (address-specified type) image sensor are not mentioned.

The present invention has been made in view of the above points, and an object thereof is to provide a sensor circuit and an address-specified image sensor capable of substantially simultaneously storing signal charges (substantially simultaneous exposure) for all pixels. Moreover, a higher pixel aperture ratio can be achieved compared to the conventional address-specific image sensor.

Another object of the present invention is to provide a sensor circuit and an address-specific image sensor, which can avoid image distortion seen in a conventional address-specific image sensor, and can be used for high-speed movement. Take pictures of the subject.

Another object of the present invention is to provide an address specifying image sensor that can achieve a high ratio of the total area of the light receiving area to the total area of the photographing area.

Other objects of the present invention, which are not explicitly described herein, may be apparent from the following description and the accompanying drawings.

(1) The sensor circuit of the first aspect of the present invention has a plurality of pixels arranged in an array, and is used for selecting an address-specific image sensor of each pixel by address designation, and is characterized by The method includes a plurality of pixel blocks, wherein the plurality of pixels are connected in parallel to the common node by a predetermined number; and the reset transistor is connected to a common node of each of the pixel blocks to reset the pixel block. a plurality of pixels; and an amplifying transistor connected to each of the plurality of common nodes of the pixel block for amplifying a signal sent by a plurality of pixels in the pixel block; in the pixel block, Each of the pixels includes a photoelectric conversion element that generates a signal charge corresponding to the illumination light, and a first gate element that is disposed between the photoelectric conversion element and a common node of the pixel block.

(2) The sensor circuit according to the first aspect of the present invention includes a plurality of pixel blocks, wherein the plurality of pixels are a predetermined number (for example, n, n is an integer of 2 or more). It is constructed by being connected in parallel to a common node. In each of the pixel blocks, each of the pixels includes a photoelectric conversion element that generates a signal charge corresponding to the illumination light, and a first gate element that is disposed between the photoelectric conversion element and a common node of the pixel block. Moreover, since the reset transistor and the amplifying transistor are connected to each common node of the pixel block, the reset transistor and the amplifying transistor can be shared in each of the pixel blocks. It means that inside the pixel, there is no reset transistor and a magnifying transistor.

In the sensor circuit, the generation, storage, and even signal output of the signal charge are performed in the following manner.

First, a reset transistor disposed in each of the pixel blocks is used to perform reset (initialization) (overall reset) for all of the pixels as a whole, so that the common node is set to a predetermined one for all the pixel blocks. Reset the voltage. At this time, all of the first gate elements provided in the photoelectric conversion element are turned on.

Next, the first gate element is turned off, and then light is applied to all of the pixels (photoelectric conversion elements) to generate and store signal charges integrally with the pixels.

Thereafter, in each of the pixel blocks, the first gate element is turned on in time, thereby, the signal corresponding to the signal charge stored in the pixel in the pixel block is time-dependently corresponding. The common node reads. This action is performed simultaneously in a plurality of blocks. At this time, from the beginning of the signal reading of one pixel in the pixel block until the signal of the other pixel is read, the reset transistor must be used to reset the common node during this period. The reason is that if the common node is not reset, it may be affected by the residual signal that is read first, and the subsequent signal changes.

The signals read in the above manner in each of the pixel blocks are sequentially or simultaneously amplified by the corresponding amplifying transistors, and then outputted from the output terminals thereof. That is, when the output end of the amplifying transistor is one, the signals sequentially sent from the plurality of pixels in the pixel block are sequentially outputted from the output terminal after being amplified by the amplifying transistor. . On the other hand, if the total number of output terminals of the amplifying transistor is equal to the total number of pixels in the pixel block, a plurality of output terminals of the amplifying transistor are output in parallel.

The fastest exposure speed (ie, the shortest signal charge storage period) is now (1/8000) seconds (=125 μ sec), so as long as the value of n is set in the following way, the signal charge for all of the pixels The storage (exposure) can be performed substantially simultaneously, that is, the time required for the resetting operation of the common node by the resetting transistor to reach the necessary number of times [for example, (n-1) times (total reset time) And the sum of the time required for the signal charge of the pixel in each pixel block to be amplified by the corresponding amplifying transistor (total amplification time) must be much smaller than the shortest signal charge storage period (=125 μ sensor) ). In other words, by using the sensor circuit, the signal charge of all of the pixels can be stored substantially simultaneously (substantially simultaneously exposed).

Moreover, since the simultaneous exposure can be performed by the above-described method, the image distortion of the conventional address-based image sensor does not occur, and the object to be moved at a high speed can be photographed.

Furthermore, in the sensor circuit of the first aspect of the present invention, for each of the pixel blocks, the reset transistor and the amplifying transistor are disposed outside the pixel block, and therefore, the pixel includes only one pixel. The photoelectric conversion element and one of the first gate elements (usually MOS transistors) may be used. Therefore, if the sensor circuit is used, a higher pixel opening can be realized compared to a conventional address-based image sensor that includes three or four MOS transistors in addition to the photoelectric conversion elements in the pixel. rate.

(3) A preferred embodiment of the sensor circuit of the first aspect of the present invention is such that the amplifying transistor has a single output terminal. The advantage of this situation is that a section of wiring that is connected to the output of the amplifying transistor tends to be simple.

In this example, it is preferable to further include: a storage capacitor element connected to an output end of the amplifying transistor; and an output transistor for controlling an output of the signal stored by the capacitor element. An advantage of this is that by using the output transistor, the signal stored in the capacitive element can be output at a different timing than when the first gate element is opened and closed.

In another preferred embodiment of the sensor circuit of the first aspect of the present invention, the amplifying transistor has an output of an equal number of pixels in the pixel block corresponding to the amplifying transistor, and is outputted at the same The second gate element is connected to the terminal. In this case, each of the second gate elements can be opened and closed in synchronization with the corresponding first gate element, whereby signals from a plurality of pixels in the pixel block can be outputted by the plurality of outputs. End and parallel output. As a result, there is an advantage that the signal processing of the next segment can be performed quickly.

In this embodiment, it is preferable to further comprise: a plurality of storage capacitor elements respectively connected to the plurality of output ends of the amplifying transistor; and a plurality of output transistors for controlling the output of the signals stored by the capacitor elements. The advantage of this case is that by using a plurality of the output transistors, the signals stored in the plurality of capacitor elements can be output at a different timing than when the first gate elements are opened and closed.

Another preferred embodiment of the sensor circuit of the first aspect of the present invention is to reset all of the pixels using all of the reset transistors before all of the pixels are generated and stored as signal charges. The pixel block, the signal corresponding to the signal charge stored by the pixel, is read by the corresponding common node in time series, and then transmitted to the corresponding amplifying transistor. The advantage of this situation is that it is easy to achieve substantially simultaneous exposure.

(4) A sensor circuit according to a second aspect of the present invention, comprising: a plurality of pixels arranged in an array, and an address specifying image sensor for selecting each of the pixels by address designation, wherein And having: a plurality of pixel blocks, wherein the plurality of pixels are connected in parallel to each common node by a predetermined number; and the amplifying transistor is connected to each of the plurality of common nodes of the pixel block for amplifying the pixel a plurality of signals sent by the pixel in the block; each pixel in the pixel block includes: a photoelectric conversion element that generates a signal charge corresponding to the illumination light; and a first gate element disposed on the photoelectric conversion element a path between the common node and the pixel block; and a reset transistor connected to the connection point of the photoelectric conversion element and the first gate element to perform resetting of the pixel.

(5) A sensor circuit according to a second aspect of the present invention, comprising a plurality of pixel blocks, wherein the plurality of pixel blocks are connected in parallel by a plurality of pixels (for example, n, n is an integer of 2 or more). It is composed of a common node. Each pixel in each of the pixel blocks includes, besides a photoelectric conversion element including a corresponding light to generate a signal charge, and a first gate element disposed in a path between the photoelectric conversion element and a common node of the pixel block, A reset transistor is further included, which is connected to a connection point of the photoelectric conversion element and the first gate element for resetting the pixel. Further, an amplifying transistor is connected to a common node of each of the pixel blocks. Therefore, the amplifying transistors can be shared in each of the pixel blocks. It means that no magnifying transistor is provided inside the pixel.

As described above, in the sensor circuit of the second aspect of the present invention, the configuration of the reset transistor is different from the sensor circuit of the first aspect of the present invention. That is, in the sensor circuit of the first aspect of the present invention, the reset transistor system is disposed in each of the pixel blocks (that is, the reset transistor system is disposed outside each pixel block), In contrast, in the sensor circuit of the second aspect of the present invention, the reset transistor is provided one by one for each of the pixels to which the pixel block belongs (that is, the reset transistor system is disposed on Each of the pixels). Therefore, the operation of generating, storing, and even signal output from the signal charge is performed in the following manner.

First, all the pixel blocks are reset (initialized) (overall reset) by using the reset transistor provided in each pixel, so that the common node is set to a predetermined weight for all the pixel blocks. Set the voltage. At this time, all of the first gate elements provided in the photoelectric conversion element are turned on.

Then, when the first gate element is maintained in the off state, the first gate element is turned off, and light is applied to all of the pixels (photoelectric conversion elements), so that the entire pixel can be generated and stored. Signal charge.

Then, in each of the pixel blocks, the first gate element is sequentially turned on according to the timing, whereby the signal corresponding to the signal charge stored by the pixel in the pixel block is time-dependent. The corresponding node is read in correspondence. This action is performed simultaneously in a plurality of blocks. At this time, from the beginning of one pixel reading signal in the pixel block, until the signal is read from another pixel, the first gate element needs to be temporarily turned on during the period to use the reset. The transistor resets the common node. The reason is that if the common node is not reset, it is feared that the residual influence of the signal read first will cause the subsequent signal to change.

In each of the pixel blocks, the signals read in the above manner are sequentially or simultaneously amplified by the corresponding amplifying transistors, and then outputted from the output terminals thereof. That is, when the amplifying transistor has an output terminal, the signals sequentially sent by the plurality of pixels in the pixel block are sequentially outputted by the output terminals in sequence after the amplifying transistor is amplified. On the other hand, if the total number of output terminals of the amplifying transistor is equal to the total number of pixels in the pixel block, a plurality of output terminals of the amplifying transistor are output in parallel. This point is the same as the sensor circuit of the first aspect of the present invention.

At present, the fastest exposure speed (that is, the shortest signal charge storage period) is (1/8000) seconds (=125 μ sec). Therefore, by setting the value of n in the following manner, all the signals of the pixel can be made. The storage (exposure) of charges is performed substantially simultaneously, that is, the time required to reset the common node by the reset transistor for a necessary number of times [for example, (n-1) times (total reset time), and The sum of the time required for the signal charge of the pixel in the pixel block to be amplified by the corresponding amplifying transistor (total amplification time) must be much smaller than the shortest signal charge storage period (=125 μsec). In other words, by using the sensor circuit, the signal charge for all of the pixels can be stored substantially simultaneously (substantially simultaneously exposed).

Moreover, since the image can be simultaneously exposed in the above manner, the image distortion of the conventional address-based image sensor does not occur, and the object to be photographed at high speed can be photographed.

Furthermore, in the sensor circuit of the second aspect of the present invention, for each of the pixel blocks, the amplifying transistor is disposed outside the pixel block, and therefore, only one of the pixels is included in the pixel. A photoelectric conversion element, a first gate element (typically a MOS transistor), and a reset transistor (typically a MOS transistor). Therefore, by using the sensor circuit, a higher pixel can be realized than a conventional address-specific image sensor including three or four MOS transistors in addition to the photoelectric conversion element in the pixel. Opening ratio.

(6) A preferred embodiment of the sensor circuit of the second aspect of the present invention is such that the amplifying transistor has a single output terminal. The advantage of this situation is that the wiring of the section below the output of the amplifying transistor tends to be simple.

Preferably, in this embodiment, the storage capacitor element connected to the output end of the amplifying transistor and the output transistor for controlling the output of the signal stored by the capacitor element are further provided. An advantage of this is that by using the output transistor, the signal stored in the capacitive element can be output at a different timing than when the first gate element is opened and closed.

In another preferred embodiment of the sensor circuit of the second aspect of the present invention, the amplifying transistor has an output of an equal number of pixels in a pixel block corresponding to the amplifying transistor, and at the output ends Connect the second gate components separately. In this case, each of the second gate elements can be opened and closed in synchronization with the corresponding first gate element, whereby signals from a plurality of pixels in the pixel block can be used by a plurality of the output terminals. Parallel output. As a result, there is an advantage that the signal processing of the next segment can be performed quickly.

In this example, it is preferable to further comprise: a plurality of storage capacitor elements respectively connected to the plurality of output ends of the amplifying transistor; and a plurality of output transistors for controlling the output of the signals stored by the capacitors. The advantage of this case is that by using a plurality of the output transistors, the signals stored in the plurality of capacitor elements can be output at a different timing than when the first gate elements are opened and closed.

Another preferred embodiment of the sensor circuit of the second aspect of the present invention is to reset all of the pixels as a whole by using all of the reset transistors before generating and storing the signal charges for all of the pixels. The pixel block, the signal corresponding to the signal charge stored by the pixel, is read by the corresponding common node in time series, and then transmitted to the corresponding amplifying transistor. The advantage of this situation is that it is easy to achieve substantially simultaneous exposure.

(7) The address specifying image sensor of the third aspect of the present invention includes a plurality of pixels arranged in an array, and each of the pixels is selected by address designation, and is characterized in that: a pixel block, wherein a plurality of the pixels are connected in parallel to the common node by a predetermined number; a reset transistor is connected to a common node of each of the pixel blocks to reset a plurality of the pixels in the pixel block; An amplifying transistor is connected to each of the plurality of common nodes of the pixel block for amplifying a signal sent by a plurality of the pixels in the pixel block; in each of the pixel blocks, each pixel comprises: photoelectric conversion The element generates a signal charge corresponding to the illumination light; and the first gate element is disposed between the photoelectric conversion element and the common node of the pixel block; and at least the photoelectric conversion element is formed in the first structure constituting the three-dimensional laminated structure In the semiconductor circuit layer, the first gate element, the reset transistor, and the amplifying transistor are formed in the second or third semiconductor circuit layer constituting the three-dimensional laminated structure.

(8) The address specifying image sensor of the third aspect of the present invention is the sensor circuit according to the first aspect of the present invention, wherein at least a plurality of the photoelectric conversion elements are formed in the three-dimensional layer. In the first semiconductor circuit layer of the structure, the first gate element, the reset transistor, and the amplifying transistor are formed in the second or third semiconductor circuit layer constituting the three-dimensional laminated structure.

Therefore, based on the same reason as described above for the sensor circuit of the first aspect of the present invention, the signal charges for all pixels can be stored substantially simultaneously (substantially simultaneously exposed), and compared to conventional addresses. Designated image sensor for high pixel aperture ratios. Moreover, the image distortion in the conventional address-specific image sensor does not occur, and the object to be photographed at high speed can be photographed.

Furthermore, since a conventional address-specified image sensor has a high pixel aperture ratio, the ratio of the total area of the light-receiving area to the total area of the photographing area can be increased.

(9) In a preferred embodiment of the address specifying image sensor of the third aspect of the present invention, in addition to the plurality of the photoelectric conversion elements, a plurality of the first gate elements are formed on the first semiconductor circuit layer. The plurality of the amplifying transistors and the plurality of the resetting transistors are formed in the second or third semiconductor circuit layer. In this case, in the first semiconductor circuit layer, a plurality of the first gate elements are stored in addition to the plurality of the photoelectric conversion elements. However, in addition to the photoelectric conversion elements, only the photoelectric conversion elements are included in each pixel. It is necessary to include a transistor constituting the first gate element, and therefore, a conventional address-based image sensor which includes four transistors or three transistors in addition to the photoelectric conversion element in each pixel Can increase the pixel aperture ratio.

According to another preferred embodiment of the address specifying image sensor of the third aspect of the present invention, in addition to the plurality of the photoelectric conversion elements, the plurality of the first gate elements and the plurality of reset transistors are formed. In the first semiconductor circuit layer, a plurality of the amplifying transistors are formed in the second or third semiconductor circuit layer. In this case, in the first semiconductor circuit layer, a plurality of the first gate elements and a plurality of reset transistors are included in addition to the plurality of the photoelectric conversion elements, but in each pixel, The photoelectric conversion element includes only one transistor constituting the first gate element, and the total number of the reset transistors may be (1/n) of the total number of pixels. Therefore, the pixel aperture ratio of each pixel can be improved as compared with the conventional address specifying image sensor which includes four transistors or three transistors in addition to the photoelectric conversion element.

Another preferred embodiment of the address specifying image sensor of the third aspect of the present invention is that the amplifying transistor has an output of an equal number of pixels in the pixel block corresponding to the amplifying transistor, and A second gate element (selective transistor) is connected to each of the output terminals. Further, in addition to the plurality of the photoelectric conversion elements, a plurality of the first gate elements, a plurality of the reset transistors, and a plurality of the amplifying transistors are formed in the first semiconductor circuit layer, and plural numbers are formed The second gate element (selective transistor) is formed in the second or third semiconductor circuit layer. In this case, in the first semiconductor circuit layer, a plurality of the first gate elements, a plurality of the reset transistors, and a plurality of the amplifying transistors are present in addition to the plurality of the photoelectric conversion elements. However, in addition to the photoelectric conversion element, each pixel includes only one transistor constituting the first gate element, and the total number of the reset transistor and the amplifying transistor requires only the total number of pixels (1/ n) OK. Therefore, the pixel aperture ratio of each pixel can be improved as compared with the conventional address specifying image sensor which includes four transistors or three transistors in addition to the photoelectric conversion element.

According to another preferred embodiment of the address specifying image sensor of the third aspect of the present invention, only a plurality of the photoelectric conversion elements are formed in the first semiconductor circuit layer, and the plurality of the first gate elements and the plurality of the first gate elements The reset transistor and a plurality of the amplifying transistors are formed in the second or third semiconductor circuit layer. In this case, in the first semiconductor circuit layer, only a plurality of the photoelectric conversion elements are formed, and each of the pixels completely contains no transistor. Therefore, the pixel aperture ratio of each pixel can be improved as compared with the conventional address specifying image sensor which includes four transistors or three transistors in addition to the photoelectric conversion element. In particular, the pixel aperture ratio is maximized.

In a preferred embodiment of the address specifying image sensor of the third aspect of the present invention, each of the amplifying transistors has a single output terminal. The advantage of this situation is that the wiring of the section below the output of the amplifying transistor tends to be simple.

Preferably, in the second or third semiconductor circuit layer, the storage capacitor element connected to the output end of the amplifying transistor and the output of the signal stored by the capacitor element are further provided. The output transistor. An advantage of this is that by using the output transistor, the signal stored in the capacitive element can be output at a different timing than when the first gate element is opened and closed.

Another preferred embodiment of the address specifying image sensor of the third aspect of the present invention is that each of the amplifying transistors has an output of an equal number of pixels in the pixel block corresponding to the amplifying transistor. And connected to the second gate element at the output terminals. In this case, each of the second gate elements can be opened and closed in synchronization with the corresponding first gate element, whereby signals from a plurality of pixels in the pixel block can be used by a plurality of the output terminals. Parallel output. As a result, there is an advantage that the signal processing of the next segment can be performed quickly.

In this embodiment, preferably, the second or third semiconductor circuit layer further includes: a plurality of storage capacitor elements respectively connected to the plurality of output ends of the amplifying transistor; and a capacitor for controlling the same A plurality of output transistors that output the signals stored by the component. The advantage of this case is that by using a plurality of the output transistors, the signals stored in the plurality of capacitor elements can be output at a different timing than when the first gate elements are opened and closed.

Another preferred example of the address specifying image sensor of the third aspect of the present invention is that all of the pixels are heavily weighted by using all of the reset transistors before all of the pixels are generated and stored. In each of the pixel blocks, a signal corresponding to the signal charge stored in the pixel is read by the corresponding common node in time series, and then transmitted to the corresponding amplifying transistor. The advantage of this situation is that it is easy to achieve substantially simultaneous exposure.

(10) The address specifying image sensor of the fourth aspect of the present invention includes a plurality of pixels arranged in an array, and each of the pixels is selected by address designation, and is characterized in that: a plurality of pixels are provided a pixel block, wherein a plurality of the pixels are connected in parallel to a common node by a predetermined number; and an amplifying transistor connected to each of the plurality of common nodes of the pixel block for amplifying a plurality of pixels in the pixel block a signal sent by the pixel; in each of the pixel blocks, each of the pixels includes: a photoelectric conversion element that generates a signal charge corresponding to the illumination light; and a first gate element disposed in common between the photoelectric conversion element and the pixel block a path between the nodes; and a reset transistor connected to a connection point of the photoelectric conversion element and the first gate element to perform resetting of the pixel; and at least forming the photoelectric conversion element in a structure constituting the three-dimensional laminated structure In the semiconductor circuit layer, the first gate element, the reset transistor, and the amplifying transistor are formed in the second or third semiconductor circuit constituting the three-dimensional laminated structure. In.

(11) The address specifying type image sensor according to the fourth aspect of the present invention is the sensor circuit according to the second aspect of the present invention, wherein at least a plurality of the photoelectric conversion elements are formed in the three-dimensional layer. In the first semiconductor circuit layer of the structure, the first gate element, the reset transistor, and the amplifying transistor are formed in the second or third semiconductor circuit layer constituting the three-dimensional laminated structure. .

Therefore, for the same reason as described above for the sensor circuit of the first aspect of the present invention, the signal charges for all the pixels can be stored substantially simultaneously (substantially simultaneously exposed), and compared to the conventional address designation. Image sensor for higher pixel aperture ratios. Moreover, the image distortion in the conventional address-specific image sensor does not occur, and the object to be photographed at high speed can be photographed.

Furthermore, since a conventional address-specified image sensor has a high pixel aperture ratio, the ratio of the total area of the light-receiving area to the total area of the photographing area can be increased.

(12) A preferred embodiment of the address specifying image sensor of the fourth aspect of the present invention is the same as the address specifying image sensor of the third aspect of the present invention. The only difference between the two is that in the address-specific image sensor of the third aspect of the present invention, the reset electro-crystal system is provided in each of the blocks (that is, the reset electro-crystal system is disposed at On the other hand, in the address specifying image sensor of the fourth aspect of the present invention, the reset crystal system is provided in a plurality of photoelectric conversion elements to which each of the blocks belongs.

In a preferred embodiment of the address specifying image sensor of the fourth aspect of the present invention, in addition to the plurality of the photoelectric conversion elements, a plurality of the first gate elements are formed on the first semiconductor circuit layer. The plurality of the amplifying transistors and the plurality of resetting transistors are formed in the second or third semiconductor circuit layer. In this case, in the first semiconductor circuit layer, a plurality of the first gate elements are stored in addition to the plurality of the photoelectric conversion elements. However, in addition to the photoelectric conversion elements, only the photoelectric conversion elements are included in each pixel. It is necessary to include a transistor constituting the first gate element, and therefore, a conventional address-based image sensor which includes four transistors or three transistors in addition to the photoelectric conversion element in each pixel Can increase the pixel aperture ratio.

According to another preferred embodiment of the address specifying image sensor of the fourth aspect of the present invention, in addition to the plurality of the photoelectric conversion elements, the plurality of the first gate elements and the plurality of reset transistors are formed. In the first semiconductor circuit layer, a plurality of the amplifying transistors are formed in the second or third semiconductor circuit layer. In this case, in the first semiconductor circuit layer, a plurality of the first gate elements and the plurality of reset transistors are included in addition to the plurality of the photoelectric conversion elements, but in each pixel, In addition to the photoelectric conversion element, only the transistor constituting the first gate element and the reset transistor are included. Therefore, the conventional method includes four transistors or three transistors in addition to the photoelectric conversion element. The address-specific image sensor can increase the pixel aperture ratio of each pixel.

In another preferred embodiment of the address specifying image sensor of the fourth aspect of the present invention, the amplifying transistor has an output of an equal number of pixels in the pixel block corresponding to the amplifying transistor, and A second gate element (selective transistor) is connected to each of the output terminals. Further, in addition to the plurality of the photoelectric conversion elements, a plurality of the first gate elements, a plurality of the reset transistors, and a plurality of the amplifying transistors are formed in the first semiconductor circuit layer, and plural numbers are formed The second gate element (selective transistor) is formed in the second or third semiconductor circuit layer. In this case, in the first semiconductor circuit layer, in addition to the plurality of the photoelectric conversion elements, a plurality of the first gate elements, the plurality of the reset transistors, and the plurality of the amplifying transistors are present. However, in addition to the photoelectric conversion element, each pixel includes only two transistors constituting the first gate element and the reset transistor, and the total number of the amplified transistors only needs the total number of pixels (1) /n) Just fine. Therefore, the pixel aperture ratio of each pixel can be improved as compared with the conventional address specifying image sensor which includes four transistors or three transistors in addition to the photoelectric conversion element.

According to another preferred embodiment of the address specifying image sensor of the fourth aspect of the present invention, only the plurality of the photoelectric conversion elements are formed in the first semiconductor circuit layer, and the plurality of the first gate elements and the plurality of the first gate elements The reset transistor and a plurality of the amplifying transistors are formed in the second or third semiconductor circuit layer. In this case, since only a plurality of the photoelectric conversion elements are formed in the first semiconductor circuit layer, the transistors are completely free of transistors. Therefore, the pixel aperture ratio of each pixel can be improved as compared with the conventional address specifying image sensor which includes four transistors or three transistors in addition to the photoelectric conversion element. In particular, the pixel aperture ratio is maximized.

In a preferred embodiment of the address specifying image sensor of the fourth aspect of the present invention, each of the amplifying transistors has a single output terminal. The advantage of this situation is that the wiring of the section below the output of the amplifying transistor tends to be simple.

Preferably, in the second or third semiconductor circuit layer, the storage capacitor element connected to the output end of the amplifying transistor and the signal for storing the capacitor element are preferably provided. Output output transistor. An advantage of this is that by using the output transistor, the signal stored in the capacitive element can be output at a different timing than when the first gate element is opened and closed.

In another preferred embodiment of the address specifying image sensor of the fourth aspect of the present invention, each of the amplifying transistors has an output of an equal number of pixels in the pixel block corresponding to the amplifying transistor. And connected to the second gate element at the output terminals. In this case, each of the second gate elements can be opened and closed in synchronization with the corresponding first gate element, whereby signals from a plurality of pixels in the pixel block can be used by a plurality of the output terminals. Parallel output. As a result, there is an advantage that the signal processing of the next segment can be performed quickly.

In this embodiment, preferably, the second or third semiconductor circuit layer further includes: a plurality of storage capacitor elements respectively connected to the plurality of output ends of the amplifying transistor; and a capacitor for controlling the same A plurality of output transistors that output the signals stored by the component. The advantage of this case is that by using a plurality of the output transistors, the signals stored in the plurality of capacitor elements can be output at a different timing than when the first gate elements are opened and closed.

Another preferred example of the address specifying image sensor of the fourth aspect of the present invention is that all of the pixels are heavily weighted by using all of the reset transistors before all of the pixels are generated and stored. And in each of the pixel blocks, the signal corresponding to the signal charge stored by the pixel is read by the corresponding common node in time series, and then transmitted to the corresponding amplifying transistor. The advantage of this situation is that it is easy to achieve substantially simultaneous exposure.

(13) In the sensor circuit according to the first and second aspects of the present invention, and the address specifying image sensor of the third and fourth aspects of the present invention, the "photoelectric conversion element" means that the irradiation can be performed. An element that generates light by light. The "photoelectric conversion element" is preferably a photodiode of a semiconductor element. However, the present invention is not limited thereto as long as the element has a function of generating electric charge corresponding to the irradiation light, and any type can be used. .

The "first gate element" refers to an element having a gate function, and is capable of opening and closing a plurality of connection paths of the photoelectric conversion element and a common node corresponding thereto. It is preferable to use a MOS transistor, but the present invention is not limited thereto.

"Reset the transistor" may be any transistor as long as it has a function in the transistor for resetting the signal charge generated by the plurality of pixels (the photoelectric conversion element) to which the block belongs. The MOS transistor is suitably used as a "reset transistor", but the present invention is not limited thereto.

"Amplifying the transistor", as long as the function of the transistor has a function, the corresponding signal of the signal charge generated by the plurality of pixels (the photoelectric conversion element) to which the pixel block belongs can be amplified according to the timing to generate an output signal. Any crystal can be used. The MOS transistor is suitably used as an "amplifying transistor", but the present invention is not limited thereto.

The "first semiconductor circuit layer" and the "second or third semiconductor circuit layer" respectively denote a layer of a semiconductor circuit, in other words, a semiconductor circuit formed in a layer shape. Generally, it includes a "semiconductor substrate" and "components" and "wirings" formed on the inside or the surface of the semiconductor substrate, but is not limited thereto. The material of the "semiconductor substrate" is not limited, and may be a germanium material, a compound semiconductor, or another semiconductor, as long as it can form a desired semiconductor element or circuit. The structure of the "semiconductor substrate" is not limited, and may be a single substrate made of a semiconductor, or may be a so-called SOI (silicon on Insulator) substrate.

"First semiconductor circuit layer" and "second or third semiconductor circuit layer" may be required (for example, only the first semiconductor circuit layer and the second or third semiconductor circuit layer cannot be obtained. In the case of rigidity, it is fixed to any "support substrate" which is rigid enough to support it. The material of the "support substrate" is not limited. That is, it may be a semiconductor, a glass, or another material. It may also be a semiconductor substrate in which a circuit is formed, that is, a so-called LSI wafer or LSI wafer.

The "embedded wiring" refers to a wiring or conductor for electrical connection that is embedded in the laminated direction of the "first semiconductor circuit layer" or the "second or third semiconductor circuit layer". In general, the "embedded wiring" is an "insulating film" that covers the entire inner wall surface of a "ditch" or a "through hole" formed in a semiconductor substrate, and is filled in (embedded in) the inner space of the insulating film. Conductive material". However, the constitution thereof is not limited to this.

Here, the "ditch" or "through hole" is not limited as long as it has a desired depth and can be used as a conductive material for embedding wiring. The depth, opening shape, opening size, and cross-sectional shape of the "ditch" or "through hole" may be appropriately set as needed. The method of forming the "ditch" or the "through hole" may be any method as long as it can be selectively removed from the surface side of the semiconductor substrate, and any method can be used. For example, an anisotropic etching method using a mask is quite suitable.

The "insulating film" covering the inner wall surface of the "ditch" or "through hole" may be electrically insulated from the semiconductor substrate and the "conductive material" filled in the "ditch" or "through hole". Any insulating film can be used. For example, cerium oxide (SiO ₂ ), cerium nitride (SiNx), and the like are quite suitable. The method of forming the "insulating film" is not limited.

Any material that can be used as a buried wiring (for example, a conductive plug) can be used as long as it can be used as a buried wiring or a through-hole. For example, a semiconductor such as polyfluorene, a metal such as tungsten (W), copper (Cu), or aluminum (Al) is quite suitable. The method of filling the "conductive material" may be any method as long as the "conductive material" can be filled into the "ditch" or the "through hole" from one side of the semiconductor substrate.

According to the sensor circuit of the present invention, the following effects can be obtained: (a) the signal charges for all the pixels can be stored substantially simultaneously (substantially simultaneously exposed), and compared with the conventional address-specific image sense The detector has a high pixel aperture ratio; (b) the image distortion in the conventional address-specific image sensor does not occur, and the object to be moved at high speed can be photographed.

According to the address specifying image sensor of the present invention, the following effects can be obtained: (a) the signal charges for all pixels can be stored substantially simultaneously (substantially simultaneously exposed), and compared to conventional addresses The specified image sensor has a higher pixel aperture ratio; (b) the image distortion in the conventional address-specific image sensor does not occur, and the object to be moved at a high speed can be photographed; The ratio of the total area of the light receiving area to the total area of the photographing area is high.

The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.

(First embodiment)

Fig. 2 is a block diagram showing the configuration of a main part of the sensor circuit 1 according to the first embodiment of the present invention. The functional block diagram of Fig. 1 shows the overall configuration of an address specifying type image sensor (hereinafter also referred to as a CMOS image sensor) using the sensor circuit 1. The sensor circuit 1 corresponds to the sensor circuit of the first aspect of the present invention.

The overall configuration of the image sensor of FIG. 1 is substantially the same as the conventional CMOS (address-specified type) image sensor shown in FIG. 30(a), and has m rows in (k×n) columns (k, Each of n and m is an array of two or more integers, and (k × n) × m pixels 11 are arranged (hereinafter, an array formed by the pixels 11 is also referred to as a "pixel array"). The difference from the conventional CMOS image sensor is that the pixels 11 of the pixels are divided into (k×m) pixel blocks 12; and the reset pixels are not included in each pixel 11. Crystal and amplifying the transistor. That is, in each of the pixel blocks 12, the pixels 11 belonging to the same row are connected in parallel to the common node in units of n (not shown in FIG. 1. Corresponding to the common node 13 in FIG. 2) To constitute the pixel block 12 (refer to FIG. 2). The pixel blocks 12 are also arranged in an array shape. The reset transistor Tr _RST and the amplifying transistor Tr _AMP are disposed outside the pixel block 12 and correspond to the respective pixel blocks 12. In other words, the reset transistor Tr _RST and the amplifying transistor Tr _AMP are shared by the n pixels 11 in each pixel block 12, respectively. Therefore, the total number of reset transistors Tr _RST is (k × m), and the total number of amplified transistors Tr _AMP is also (k × m).

In the vicinity of each pixel block 12, there are respectively m reset lines 31 which extend along corresponding rows of the pixel array. Since one reset transistor Tr _{RST is} provided for each pixel block 12, k reset transistors Tr _RST are connected to each reset line 31. At each of the output terminals of the reset transistor Tr _RST , an amplifying transistor Tr _{AMP is} connected. Each reset line 31 is used to reset the signal charge stored in the pixel 11 (i.e., the pixel 11 in the k pixel blocks 12 to which the row belongs). The application of the reset voltage for the pixels 11 thereof is controlled using the corresponding reset transistor Tr _RST . (When the signal charge of the pixel 11 is reset, the gate of the amplifying transistor Tr _AMP is also reset.) Each of the amplifying transistors Tr _AMP is used to amplify each pixel 11 in the corresponding pixel block 12. Read the signal. After each signal is amplified by the amplifying transistor Tr _AMP, through the output terminal of the amplifying transistor Tr _AMP, are sequentially supplied to the corresponding row signal line 37.

In the vicinity of each pixel block 12, (k x n) read control lines 32 are further formed, which respectively extend along corresponding columns of the pixel array. The setting of the read control line 32 is such that n pieces of m pixel blocks 12 belonging to the same column are respectively provided for reading signals from the n pixels 11 in each pixel block 12. In FIG. 1, the n read control lines 32 provided for the m pixel blocks 12 to which the same column belongs are integrated and illustrated by one line segment.

In the vicinity of the left end of the pixel array, a vertical scanning circuit 34 extending along the rows of the pixel array is provided. The vertical scanning circuit 34 sequentially scans (k×n) the read control lines 32 and selects them according to the sequence. At this time, in each of the read control lines 32, the selection signals of the n pixels 11 respectively included in the m pixel arrays 12 to which the corresponding columns belong are sequentially outputted (with the transfer gate control signal φ _{T1 of} FIG. 2). φ _Tn corresponds to).

In the vicinity of the lower end of the pixel array, a horizontal signal line 33 extending along the columns of the pixel array, a horizontal scanning circuit 35, and m CDS circuits 36 for removing noise are provided. The horizontal scanning circuit 35 selects the CDS circuit 36 by timing through m row selection signals 38.

The m CDS circuits 36 are respectively connected in parallel with the k line signal lines 37, and the k line signal lines 37 are respectively connected to the output terminals of the k amplifying transistors Tr _AMP to which the row belongs. Therefore, the k amplification transistors Tr _AMP to which the same column belongs, the k output signals are input in parallel to the corresponding CDS circuit 36. The output terminals of the m CDS circuits 36 are respectively connected to the horizontal signal lines 33, so that the output signals of the CDS circuits 36 are sequentially output to the outside of the image sensor through the horizontal signal lines 33.

Next, the sensor circuit 1 of the first embodiment, that is, the sensor circuit 1 for the address specifying image sensor having the above configuration, will be described below with reference to FIG. 2 .

2 is a circuit configuration of two pixel blocks 12 belonging to the jth row (i.e., i≦j≦m) of the pixel array. The upper pixel block 12 is tethered to the i-th item (where 1 ≦ i ≦ k) from the top; in the lower pixel block 12, the t ( i+1) item is counted from above. Therefore, the upper pixel block 12 is represented by 12 (i, j) as needed; and the lower pixel block 12 is represented by 12 (i+1, j).

The pixel 11 included in the upper pixel block 12 (i, j) is in the [n × (i-1) +1] column to the (n × i) column of the jth row. The pixel 11 included in the lower pixel block 12 (i+1, j) is the [n x i+1] column to the [n x (i+1)] column of the jth row. Since the above two pixel blocks 12(i, j) have the same configuration as 12(i+1, j), in the following description, mainly the upper pixel block 12 (i.j) will be described.

In the pixel block 12 (ij), n pixels 11 are included, and each pixel 11 includes a photodiode and a transfer gate. Therefore, each of the pixels 11 includes n photodiodes PD ₁ to PD _n and n transfer gates TG ₁ to TG _n . Each of the transfer gates TG ₁ to TG _n is composed of a MOS transistor. The anodes of the photodiodes PD ₁ to PD _n are connected to the source and drain regions of one of the transfer gates TG ₁ to TG _n . The cathode is a terminal or region that is commonly connected to a predetermined potential (usually a ground potential). The other source and drain regions of the respective transfer gates TG ₁ to TG _n are commonly connected to the common node 13 in the pixel block 12 (i, j). That is, the n pixels 11 in the pixel block 12 (i, j) are connected in parallel to the common node 13.

The common node 13 of the pixel block 12 (i, j) is connected by the node 14 to one of the common reset transistors Tr _RST provided in correspondence with the pixel block 12 (i, j). A source, a drain region, and a gate of a common amplifying transistor Tr _AMP disposed in correspondence with the pixel block 12 (i, j). The reset transistor Tr _RST and the amplifying transistor Tr _AMP are disposed outside the pixel block 12 (i, j). The other source and drain regions of the transistor Tr _RST are reset and connected to the reset voltage source (reset voltage = V _RST ). A source and drain region of the amplifying transistor Tr _AMP is connected to a DC power source (power supply voltage = Vcc), and the other source and drain regions (output side) are connected to the pixel block 12 (i, j). The output terminals (that is, the corresponding line signal lines 37) are connected. The output end of the amplifying transistor Tr _AMP (source and drain region on the output side) is connected to a terminal or region of a predetermined potential (usually a ground potential) through a resistor R to form an amplifier in the form of a source follower . The capacitor C _sn connected to the node 14 is the parasitic capacitance generated by the node 14. The node 14 is connected to a terminal or region of a predetermined potential (usually a ground potential) through the parasitic capacitance C _sn .

The output terminal of the amplifying transistor Tr _AMP (source and drain region on the output side), as shown in FIG. 1, can be connected to the corresponding signal line 37 to enable the output signal of the amplifying transistor Tr _AMP , That is, a serial type output signal of the n photodiodes PD ₁ to PD _n is transmitted to the corresponding CDS circuit 36 through the corresponding line signal line 37. Moreover, when the CDS circuit 36 is sent to the horizontal signal line 33, the line signal line 37 is selected by the m row selection signals 38 by the scanning of the horizontal scanning circuit 35, thereby transmitting the timing output signal to Horizontal signal line 33. Thereafter, it is transmitted to an output terminal (not shown) of the image sensor provided at one end of the horizontal signal line 33 (at the right end of FIG. 1).

All of the pixel blocks 12 other than the pixel block 12 (i, j) have the same configuration as the pixel block 12 (i, j), and therefore, the n photodiodes PD are the same as described above. The timing output signals of ₁ ~ PD _{n are} transmitted to the output terminals of the image sensor. In this way, photography of the object to be photographed can be performed.

Next, the operation of the address specifying image sensor including the sensor circuit 1 (that is, the sensor circuit having the above configuration) is provided (from the generation and storage of the signal charge until the signal is output).

1. Overall reset of all pixels (all photodiodes) First, the logic state of each pulse signal (transmission gate control signal) φ _T1 ~ φ _Tn applied to the gate of the MOS transistor becomes High (high) All the transfer gates TG ₁ to TG _{n are} turned on, and the MOS transistors are used to form the transfer gates TG ₁ to TG _n of the photodiodes PD ₁ to PD _n provided in all the pixels 11 , That is, the transistor of the first gate element).

Next, the transfer gates TG ₁ to TG _{n of} all the pixels 11 are kept in an on state, and the logic state of the pulse signal (reset pulse signal) φ _RST applied to the gate of the reset transistor Tr _RST becomes H. All of the reset transistors Tr _{RST are} turned on, and the reset transistors Tr _RST are disposed in the respective transistors of all the pixel blocks 12. As a result, a predetermined reset voltage V _RST, through 13, and the transfer gate 14, the common electrode node TG ₁ ~ TG _n, and simultaneously applied to all the pixels 11 of the photo diode PD ₁ ~ PD _n. As a result, the voltages of the photodiodes PD ₁ to PD _n applied to all the pixels 11 are substantially equal to the reset voltage V _RST , in other words, the photodiodes PD ₁ to PD _{n of} all the pixels 11 are reset. In this way, all of the pixels 11 are collectively reset at the same time, that is, "overall reset" is performed.

2. Exposure (charge storage) Next, the logic state of the transfer gate control signals φ _T1 to φ _Tn applied to the transfer gates TG ₁ to TG _n of all the pixels 11 becomes Low (L), so that all the transfer gates TG ₁ ~ TG _{n is} off. At the same time, the logic state of the reset control signal φ _RST is set to L, and all of the reset transistors Tr _{RST are} also turned off.

Thereafter, in this state, light is applied to the photodiodes PD ₁ to PD _{n of} all the pixels 11 to cause all of the photodiodes PD ₁ to PD _{n to} generate and store signal charges as a whole. The irradiation time is generally several hundred μsec or even several msec, which is very long.

At the same time as the generation and storage of the signal charge, the logic state of the reset control signal φ _RST is again made H, and all the reset transistors Tr _{RST are} turned on, and the predetermined time (for example, 1 μsec) is passed. The logic state of the reset control signal φ _RST becomes L again, and all of the reset transistors Tr _{RST are} turned off. Thus, the reset voltage V _RST can be temporarily applied to all of the nodes 14 (i.e., the gates of all the amplifying transistors Tr _AMP ) to set the gate voltages of all the amplifying transistors Tr _AMP to a predetermined reference voltage.

3. Reading of the signal and its amplification The amount of charge generated and stored in all of the photodiodes PD ₁ to PD _n in the above manner is proportional to the signal by the pixel 11 in the following manner. Read in, and then zoom in.

That is, first, by selecting the pixel block 12 by the vertical scanning circuit 34 and the horizontal scanning circuit 35, the logic states of the n transfer gate control signals φ _T1 ～ φ _Tn in the pixel block 12 are sequentially ordered by L. When it becomes H, the transfer gates TG ₁ to TG _{n are} sequentially turned on. Further, after maintaining the on state of the same state for a predetermined period of time (for example, 0.1 μsec), the logic state of the equal state is returned to L in order. Thus, the signals from all of the photodiodes PD ₁ -PD _n in the pixel block 12 are read at the node 14 in accordance with the timing. During this time, all of the reset transistors Tr _RST are kept in the off state.

The amplifying transistor Tr _AMP connected to the node 14 in the form of a source follower is connected to the node 14 by its gate, so that the voltage signal read at the node 14 is immediately amplified by the amplifying transistor Tr _AMP . Further, the amplified signal is outputted from the source and drain regions on the output terminal side of the amplifying transistor Tr _AMP to the line signal line 37.

When a signal is read from the n pixels 11 (ie, the photodiodes PD ₁ to PD _n ) in the pixel block 12 to be amplified, a pixel 11 (for example, a photodiode PD ₁ ) is read from The end of the action of the signal and the amplification thereof is started until the start of the signal reading of the next pixel 11 (for example, the photodiode PD ₂ ), and the pixel block 12 must be used to reset the transistor. Tr _{RST is} turned on to temporarily apply the reset voltage V _RST to the node 14, and all of the nodes 14 (gates of the amplifying transistor Tr _AMP ) are set to the reference potential (reset). The reason is that if this is not the case, I am afraid that the residual influence of the signal of the previous pixel 11 (for example, the photodiode PD ₁ ) may cause a signal error condition in the subsequent pixel (for example, the photodiode PD ₂ ).

Since there are n photodiodes PD ₁ to PD _n in the pixel block 12, the read operation by the transfer gate control signals φ _T1 ～ φ _{Tn is} performed n times; the amplified transistor Tr The amplification operation performed by the _AMP has a total of n times; the reset operation of the amplifying transistor Tr _AMP has a total number of times (n-1) times.

Specifically, for example, initially, the first transfer gate TG _{1 of} the pixel block 12 is temporarily turned on, and is proportional to the signal charge (that is, the signal charge stored in the first photodiode PD ₁ ). The voltage signal is read at node 14. The voltage signal is immediately amplified by the amplifying transistor Tr _AMP , and then the obtained amplified signal is transmitted to the signal line 37. Next, the reset transistor Tr _{RST is} temporarily turned on, and the gate (node 14) of the amplifying transistor Tr _AMP is reset to the reference potential. Thereafter, the voltage signal equal to the signal charge stored by the second photodiode PD ₂ is read by the node 14. The voltage signal is immediately amplified by the amplifying transistor Tr _AMP , and then the amplified signal is transmitted to the signal line 37. Next, the reset transistor Tr _{RST is} temporarily turned on, and the gate (node 14) of the amplifying transistor Tr _AMP is reset to the reference voltage. Next, the same operations as described above are repeated for the third photodiode PD ₃ , the fourth photodiode PD _{4 ,} and the like in order. Finally, a read operation and an amplification operation are performed on the nth photodiode PD _n , and then the processing of the pixel block 12 is ended.

In the image sensor of FIG. 1, the output terminal of the amplifying transistor Tr _AMP corresponding to the pixel block 12 is one, and therefore, all of the photodiodes PD ₁ to PD _{n in} the pixel block 12 are The obtained n signals are outputted from the source and drain regions on the output terminal side of the amplifying transistor Tr _AMP to the line signal line 37 in time series. That is, the signal outputted by the pixel block 12 is connected to the n pulse waveforms at a predetermined interval to reflect the amount of signal charge of the photodiodes PD ₁ to PD _n (the amount of illumination light) ) Timing signal.

Since the image sensor has a total of (k × m) pixel blocks 12, the above operation is repeated (k × m) times while scanning all the pixels 11.

The signal outputted by the pixel block 12, that is, a timing signal in which n signal pulses are connected at a predetermined interval, is sent to a well-known sample and hold circuit or analogy. , digital (A / D) conversion circuit for the intended signal processing.

The fastest exposure speed (ie, the shortest signal charge storage period) is now (1/8000) seconds (= 125 μ sec). Therefore, for (k × m) pixel blocks 12, if the n value (the total number of the pixels 11 in each pixel block 12) can be set in the following manner, the pixels 11 to which all the pixel blocks 12 belong can be made ( The signal charge storage (exposure) of the photodiodes PD ₁ to PD _n ) can be performed substantially simultaneously, that is, the reset of the node 14 (the gate of the amplifying transistor Tr _AMP ) by the reset transistor Tr _RST is obtained. The time required for the action to reach the predetermined number of times [ie, (n-1) times] (total reset time) is sent out with all the pixels 11 (all photodiodes PD ₁ to PD _n ) in the pixel block 12 The sum of the time (total amplification time) required for the signal to be amplified by the corresponding amplifying transistor Tr _AMP , and then the (k × m) times of the sum is much less than the shortest signal charge storage period (= 125 μ sec ). In other words, the signal charge of all of the pixels 11 can be stored substantially simultaneously (substantially simultaneously exposed).

Further, (k × m) output timing signals are independently outputted from all the pixel blocks 12, and therefore, analog output, digital (A/D) conversion, and the like can be performed in parallel for the output timing signals. Thereby, compared with the conventional CMOS image sensor, there is a higher speed data processing. This also benefits the realization of substantially simultaneous exposure.

It can be understood from the above actions that if viewed in a frame, the timing output signal outputted by each pixel block 12 is closer to the end of the scan time than the initial output during the scan period. The longer the charge storage period (although quite a small amount). Therefore, in order to obtain more accurate image data, or to have a large n value, a well-known circuit can be provided in the latter stage for signal correction in accordance with changes in charge storage period. Thereby, it is possible to suppress or avoid being affected by variations in charge storage period.

Since the image can be substantially simultaneously exposed by the above method, the image distortion of the conventional CMOS image sensor does not occur, and the object to be photographed at high speed can be photographed.

Furthermore, the common reset transistor Tr _RST and the common amplifying transistor Tr _AMP are disposed outside the pixel block 12 in a manner corresponding to each pixel block 12, and therefore, in the pixel block 12 Each pixel 11 in the middle only needs to include one photodiode and one gate element (MOS transistor). Therefore, a higher pixel aperture ratio (for example, about 60%) can be realized as compared with a conventional CMOS image sensor in which one photodiode has three or four MOS transistors in one pixel.

Furthermore, in the conventional CMOS image sensor, the signal processing is performed in time series according to the number of scanning lines, and a high-speed A/D conversion circuit is required, but the sensor of the first embodiment is used. In the image sensor of the circuit 1, the number of scan lines set by the n value is small, and the degree of parallel connection can be increased, so that the processing speeds of the slower timing output signals of the respective amplifying transistors Tr _AMP can be allowed. Therefore, it is possible to use an A/D conversion circuit which is simpler in construction, and this is also an effect.

Further, n output signals from the n photodiodes PD ₁ to PD _n are outputted in series by the respective amplifying transistors Tr _AMP , and thus are connected to the output terminals of the respective amplifying transistors Tr _AMP The wiring of a section will tend to be simple, and this is also the effect.

(Second embodiment)

Fig. 3 is a circuit configuration diagram of a sensor circuit 1A according to a second embodiment of the present invention. The address specifying image sensor of the sensor circuit 1A is used, and the overall configuration is the same as that shown in FIG. 1, and thus the description thereof will be omitted. The sensor circuit 1A corresponds to the sensor circuit of the first aspect of the present invention.

The circuit configuration of the sensor circuit 1A shown in FIG. 3 is substantially the same as that of the sensor circuit 1 (see FIG. 2) of the first embodiment, and the only difference is that it is in each pixel block. A storage capacitive element C _ST and an output transistor Tr _OUT are added to the output side of the amplifying transistor Tr _AMP corresponding to the 12-characteristic relationship. Therefore, the same components as those of the sensor circuit 1 of Fig. 2 are denoted by the same reference numerals and their description will be omitted.

The purpose of the storage capacitive element C _ST is to temporarily store the signal amplified by the corresponding amplifying transistor Tr _AMP , and one of the terminals is connected to the source and drain regions of the output side of the amplifying transistor Tr _AMP . The other terminal is connected to a terminal or region of a predetermined potential (usually a ground potential).

The purpose of outputting the transistor Tr _OUT is to cause the signal temporarily stored in the storage capacitive element C _ST to be transmitted to the corresponding line signal line 37, the source and drain regions of the output side, and the pixel. The output terminals of block 12 (line signal line 37) are connected. The output transistor Tr _OUT is turned on if the logic state of the output control signal φ _OUT applied to the gate thereof is H, and is turned off when it is L. Therefore, when the signal temporarily stored in the storage capacitive element C _ST is output to the line signal line 37, the opening and closing time of the output transistor Tr _OUT can be different from the transfer gates TG ₁ to TG _{n in} the pixel block 12 . Opening and closing time.

In the image sensor using the sensor circuit 1 of the first embodiment, the timing output signals from the n photodiodes PD ₁ to PD _{n in} the corresponding pixel block 12 are amplified in the transistor Tr _{After the AMP} is amplified, it is immediately output to the signal line 37. On the other hand, in the image sensor using the sensor circuit 1A of the second embodiment, the timing output signals from the n photodiodes PD ₁ to PD _{n in} the pixel block 12 are subjected to the amplified transistor. After amplification of the Tr _AMP , it is temporarily stored in the storage capacitive element C _ST . Therefore, by outputting the control signal φ _OUT , the output of the forward signal line 37 can be opened and closed with the transfer gates TG ₁ to TG _n . The time points (i.e., the points at which the signals are read by the photodiodes PD ₁ to PD _n ) are staggered from each other.

In the image sensor of the sensor circuit 1A of the second embodiment having the above-described configuration, the signal charges of all the pixels 11 can be substantially simultaneously stored (substantially simultaneously) for the same reason as in the case of the first embodiment. Exposure). Moreover, since the simultaneous exposure can be substantially performed in the above manner, the image distortion of the conventional CMOS image sensor does not occur, and the object to be moved at a high speed can be photographed.

Further, the common reset transistor Tr _RST and the common amplifying transistor Tr _AMP are provided outside the pixel block 12 so as to correspond to the respective pixel blocks 12, and therefore, each of the pixel blocks 12 The pixel 11 only needs to have one photodiode and one gate element (MOS transistor). Therefore, a higher pixel aperture ratio can be achieved compared to a conventional CMOS image sensor in which one or four MOS transistors are included in the photodiode in one pixel.

Furthermore, by outputting the control signal φ _OUT , the time at which the signal is outputted to the signal line 37 can be shifted from the opening and closing timing of the transmission gates TG ₁ to TG _n in the pixel block, and thus, compared with the use In the case of the sensor circuit 1 of the embodiment, high-speed photography can be performed, which is also the effect.

(Third embodiment)

Fig. 4 is a circuit configuration diagram of a sensor circuit 1B according to a third embodiment of the present invention. The address specifying image sensor of the sensor circuit 1B is used, and the overall configuration is the same as that shown in FIG. 1, and thus the description thereof will be omitted. The sensor circuit 1B corresponds to the sensor circuit of the first aspect of the present invention.

The circuit configuration of the sensor circuit 1B shown in FIG. 4 is substantially the same as the circuit configuration of the sensor circuit 1 (see FIG. 2) of the first embodiment, and the only difference is that the pixel block 12 is formed. The amplifying transistor Tr _AMP corresponding to the setting relationship is provided with n selection transistors Tr _SEL1 to Tr _SELn (second gate elements) connected in parallel with the source and drain regions on the output side thereof, from the enlarged The n output signals of the n photodiodes PD ₁ to PD _n are output in parallel to the line signal line 37 through the selection transistors Tr _SEL1 to Tr _SELn . When the transistors Tr _SEL1 to Tr _{SELn are selected} , if the logic state of the output selection signals φ _SEL1 to φ _SELn applied to the gates is H, each is turned on, and if L is turned off. Therefore, the same components as those of the sensor circuit 1 of Fig. 2 are denoted by the same reference numerals and their description will be omitted.

When the corresponding signal of the signal charge (that is, the signal charge generated and stored by the n photodiodes PD ₁ to PD _{n )} is read and amplified, n selection transistors Tr _SEL1 to Tr _SELn , and corresponding pixels The transfer gates TG ₁ to TG _n in the block 12 are opened and closed in a substantially synchronous manner. That is, for example, when the signal is read by the photodiode PD ₁ and amplified, the transfer gate TG ₁ is turned on (becomes in an on state), and the selective transistor Tr _SEL1 is also turned on (becomes turned on). State), therefore, the signal charge to be read is output to the line signal line 37 through the selection transistor Tr _SEL1 immediately after amplification by the amplifying transistor Tr _AMP .

In the image sensor including the sensor circuit 1B of the third embodiment configured as described above, the signal charges of all the pixels 11 can be substantially simultaneously stored (substantially simultaneously) for the same reason as in the case of the first embodiment. Exposure). Moreover, since the simultaneous exposure can be substantially performed in the above manner, the image distortion of the conventional CMOS image sensor does not occur, and the object to be moved at a high speed can be photographed.

Further, the common reset transistor Tr _RST and the common amplifying transistor Tr _AMP are provided outside the pixel block 12 so as to correspond to the respective pixel blocks 12, and therefore, each of the pixel blocks 12 The pixel 11 only needs to have one photodiode and one gate element (MOS transistor). Therefore, a higher pixel aperture ratio can be achieved compared to a conventional CMOS image sensor in which one or four MOS transistors are included in the photodiode in one pixel.

Furthermore, the n output signals from the amplified n photodiodes PD ₁ to PD _n are output through the parallel signal lines 37 connected in parallel through the corresponding n selection transistors Tr _SEL1 to Tr _SELn . It also has the effect of being able to quickly process the signal of the next paragraph.

(Fourth embodiment)

Fig. 5 is a circuit configuration diagram of a sensor circuit 1C according to a fourth embodiment of the present invention. The address specifying image sensor of the sensor circuit 1C is used, and the overall configuration is the same as that shown in FIG. 1, and thus the description thereof will be omitted. The sensor circuit 1C corresponds to the sensor circuit of the first aspect of the present invention.

The circuit configuration of the sensor circuit 1C shown in FIG. 5 is substantially the same as that of the sensor circuit 1B (see FIG. 4) of the third embodiment, and the only difference is that it is in each pixel block. 12 is an output side of the amplifying transistor Tr _AMP corresponding to the set relationship, and n selection transistors Tr _SEL1 to Tr _SELn (second gate) connected in parallel are added _thereto , and the transistors Tr _SEL1 to Tr _SELn are selected in the same _manner . On the output side, n storage capacitive elements C _ST1 to C _STn and n output transistors Tr _OUT1 to Tr _{OUTn are added} . Therefore, the same components as those of the sensor circuit 1C of FIG. 4 are denoted by the same reference numerals, and the description thereof will be omitted.

Wherein the storage capacitance element with object C _ST1 ~ C _STn, and for the temporary storage of the amplified signals ~ transistor Tr _AMP amplifies the n-th photodiode PD ₁ PD _n of; one of its terminals and the like, respectively, corresponding to The source and drain regions of the output transistors Tr _SEL1 to Tr _{SELn are} connected, and the other terminal is connected to a terminal or region of a predetermined potential (usually a ground potential).

The purpose of the output transistors Tr _OUT1 ~ Tr _OUTn is to _transmit the signals temporarily stored in the storage capacitive elements C _ST1 - C _STn in parallel to the corresponding line signal line 37, and the source side of the output side. The drain region is connected to the output terminal (line signal line 37) of the pixel block 12. The output transistor Tr _OUT1 ~ Tr _OUTn is turned on if the logic state of the output control signal φ _OUT1 ~ φ _OUTn applied to the gate of the gate is φ _OUT1 ~ φ _OUTn , and is turned off when it is L. When the amplification signals temporarily stored in the storage capacitive elements C _ST1 to C _STn are output to the line signal line 37 in parallel, the opening and closing _timings of the output transistors Tr _OUT1 to Tr _OUTn and the transmission gates in the pixel block 12 The points of opening and closing of TG ₁ to TG _n can be shifted from each other.

In the image sensor using the sensor circuit 1B of the third embodiment, n output signals from the n photodiodes PD ₁ to PD _{n in} the corresponding pixel block 12 are amplified. After amplification of the transistor Tr _AMP , it is immediately output in parallel to the signal line 37. On the other hand, in the image sensor using the sensor circuit 1C of the fourth embodiment, the output signals from the n photodiodes PD ₁ to PD _{n in} the pixel block 12 are subjected to the amplified transistor. After the amplification of the Tr _AMP is temporarily stored in the storage capacitive elements C _ST1 to C _STn , the output control signals φ _OUT1 to φ _OUTn are outputted in parallel to the time of the signal line 37, and the transfer gate can be connected to the transmission gate. The point at which the poles TG ₁ to TG _n are opened and closed (i.e., the point at which the signals are read from the photodiodes PD ₁ to PD _n ) are shifted from each other.

In the image sensor including the sensor circuit 1C of the fourth embodiment configured as described above, the signal charges of all the pixels 11 can be substantially simultaneously stored (substantially simultaneously) for the same reason as in the case of the first embodiment. Exposure). Moreover, since the simultaneous exposure can be performed in the above manner, the image distortion of the conventional CMOS image sensor does not occur, and the object to be photographed at high speed can be photographed.

Further, the common reset transistor Tr _RST and the common amplifying transistor Tr _AMP are provided outside the pixel block 12 so as to correspond to the respective pixel blocks 12, and therefore, each of the pixel blocks 12 The pixel 11 only needs to have one photodiode and one gate element (MOS transistor). Therefore, a higher pixel aperture ratio can be achieved compared to a conventional CMOS image sensor in which one or four MOS transistors are included in the photodiode in one pixel.

Furthermore, by outputting the control signals φ _OUT1 to φ _OUTn , the _{timing at} which the signals are outputted to the signal line 37 can be shifted from the opening and closing of the transmission gates TG ₁ to TG _{n in} the pixel block 12, and therefore, Compared with the case of using the sensor circuit 1B of the third embodiment, it is possible to have higher speed photography, and the effect thereof.

(Fifth Embodiment)

Fig. 6 is a circuit diagram showing a configuration of a main part circuit of the address specifying image sensor 2 according to the fifth embodiment of the present invention; and Fig. 8 is a cross-sectional view of an essential part of the actual structure of the image sensor 2. In the image sensor 2, the sensor circuit 1B (see FIG. 4) of the third embodiment is used, and the upper semiconductor circuit layer 21 and the lower semiconductor circuit layer 22 are laminated to form a two-dimensional three-layer laminated structure. . The image sensor 2 corresponds to the image sensor of the third aspect of the present invention.

The overall configuration and operation of the image sensor 2 are the same as those shown in FIG. 1, and the description thereof will be omitted. Further, the circuit configuration of Fig. 6 is the same as that of the sensor circuit 1B of the third embodiment shown in Fig. 4 (n selected transistors Tr _SEL1 to Tr _SELn are connected to the output ends of the respective amplifying transistors Tr _AMP , and The storage capacitor element is provided in the same manner as the output transistor, and the same reference numerals will be given to the same elements, and the description thereof will be omitted. However, in the image sensor 2, as will be described later, the well-known buried wiring 23 is used so that the common node 13 of each pixel block 12 formed in the upper semiconductor circuit layer 21 and the node 14 (formed in the lower semiconductor circuit) reset transistor _RST Tr layer 22 and amplification transistor Tr _AMP connection point) electrical connection, and therefore, in FIG. 6, the embedded wiring 23 is added, the resulting parasitic 23 disposed by this wiring resistance R _o With parasitic capacitances C _o1 and C _o2 . The buried wiring 23 is provided for each pixel block 12 (that is, n pixels 11).

Next, the actual configuration of the image sensor 2 will be described with reference to FIG.

As can be seen from FIG. 8, the image sensor 2 uses the buried wiring 23 and the fine bump electrode (for example, a laminate of indium (In) and gold (Au) or tungsten (W), etc.) and is electrically insulated. An adhesive (for example, polyimide) 91 causes the upper semiconductor circuit layer 21 to form a mechanical and electrical connection with the lower semiconductor circuit layer 22.

Further, a method for forming the buried wiring 23 and the bump electrode 90, and a method of mechanically connecting the upper semiconductor circuit layer 21 and the lower semiconductor circuit layer 22 by using the adhesive 91 are used by those skilled in the art, and thus are omitted. A description of them.

In the upper semiconductor circuit layer 21, (k × m) pixel blocks 12 are formed, that is, (k × n) × m pixels 11 are formed. Therefore, the upper semiconductor circuit layer 21 includes (k × n) × photodiodes (that is, photodiode groups PD ₁ to PD _n having (k × m) groups); and (k × n) ×m transfer gates (that is, transfer gate groups TG ₁ to TG _{n of} (k × m) groups). In the upper semiconductor circuit layer 21, (k × m) buried wirings 23 are further formed.

In the lower semiconductor circuit layer 22, (k × m) reset transistors Tr _RST ; (k × m) amplification transistors Tr _AMP ; and (k × n) × m selection transistors are formed That is, there are (k × m) groups of selected transistor groups Tr _SEL1 to Tr _SELn ).

In the upper semiconductor circuit layer 21, the element isolation insulating film 41 is formed in a predetermined pattern in the surface region of the p-type single crystal germanium (Si) substrate 40, whereby (k × n) × m pixels 11 are used. The element areas are connected in parallel in an array, as shown in the layout of Figure 1. The element regions thereof are respectively associated with one pixel 11. The configuration of the pixel block 12 is the same, and thus is described here by one pixel block 12 (i, j).

Inside the element region corresponding to the pixel block 12 (i, j), n photodiodes PD ₁ to PD _n and n transfer gates TG ₁ to TG _{n are formed} . For example, as shown in FIG. 8, the photodiode PD ₁ is composed of an n ⁺ -type region 42 formed on the p-type substrate 40 (that is, a photodiode PD ₁ -based p-n junction photodiode) ). The transfer gate TG ₁ is formed of a MOS transistor, and includes a gate 44 and an n ⁺ -type region 43 which is opposed to the n ⁺ -type region 42 with the gate 44 interposed therebetween. The gate TG _{1 is} transferred, because the n ⁺ -type region 42 of the photodiode PD ₁ is shared, and a source and drain region of the transfer gate TG ₁ are formed with the anode of the photodiode PD ₁ Electrical connections. The gate insulating film existing between the gate 44 and the surface of the substrate 40 has been omitted in FIG. (The presence of a gate insulating film between the gate 44 and the surface of the substrate 40 is quite clear, and therefore, the description of the gate insulating film is omitted in the following description). The gate 44 is electrically connected to the corresponding read control line 32 through the wiring formed in the wiring structure 47 on the surface of the substrate 40. Here, the wiring structure 47 includes the wiring conductor formed on the surface of the substrate 40 and the insulator including the same, and does not include the gate insulating film and the gate existing on the surface of the substrate 40. (This point is the same in the following embodiments.) The other photodiodes PD ₂ to PD _n and the transfer gates TG ₂ to TG _n are the same as the photodiode PD ₁ and the transfer gate TG ₁ , respectively. Composition.

Inside the wiring structure 47, a wiring film 46 is formed which is formed in a predetermined pattern; and n conductive contact plugs 45 for n n ⁺ -type regions 43 of the transfer gates TG ₁ to TG _n Electrical connection is made to the wiring film 46. The n transfer gates TG ₁ to TG, _n in the pixel block 12 (i, j) are electrically connected to the wiring film 46 by their contact plugs 45, thereby causing the transfer gates TG ₁ to TG _{n is} connected in parallel to the common node 13.

In the substrate 40, (k × m) through holes through which the element isolation insulating film 41 and the substrate 40 are inserted in the vertical direction (the direction orthogonal to the main surface of the substrate 40) are formed, and the formation positions are located, and transmitted. The overlapping position of the element isolation insulating film 41 adjacent to the n ⁺ -type region (source, drain region) of the gates TG ₁ to TG _n . In the through hole, it contacts the inner wall of the meandering portion of the substrate 40, and is covered by the insulating film 24 in a comprehensive manner. In the inside of the through hole (inside of the insulating film 24 and inside the element isolation insulating film 41), a conductive material such as polyfluorene is filled, and the buried wiring 23 is formed of the conductive material. The upper end of the buried wiring 23 is exposed by the surface of the substrate 40 (the element isolation insulating film 41), and is connected to the lower end of the conductive contact plug 23a formed inside the wiring structure 47. The upper end of the conductive contact plug 23a is connected to the wiring film 46 formed inside the wiring structure 47. Therefore, the buried wiring 23 is electrically connected to the corresponding wiring film 46 through the conductive contact plug 23a. As a result, the n ⁺ type regions (source, drain regions) 43 of the n transfer gates TG ₁ to TG _n of the pixel block 12 (i, j) are as shown in the circuit configuration of FIG. The corresponding buried wirings 23 are connected in common. The lower end of each buried wiring 23 is exposed from the inner surface of the substrate 40, and is mechanically and electrically connected to the bump electrode 90 corresponding to the lower end thereof.

In the lower semiconductor circuit layer 22, the element isolation insulating film 61 is formed in a predetermined pattern in the surface region of the p-type single crystal germanium substrate 60, thereby forming a predetermined number of element regions, a predetermined number for the reset transistor Tr _RST . The component region for amplifying the transistor Tr _AMP and the component region for a predetermined number of selected transistors Tr _SEL1 to Tr _SELn . Here, the description will be made in a corresponding configuration of one pixel block 12 (i, j).

As shown in FIG. 8, the reset transistor Tr _RST is composed of a MOS transistor, and includes a gate 63 and a pair of n ⁺ type regions (sources) formed on both sides with the gate 63 interposed therebetween , bungee area) 62. The gate 63 is electrically connected to the corresponding reset line 31 through the wiring formed in the wiring structure 74 formed on the surface of the substrate 60. Here, the wiring structure 74 includes a wiring conductor formed on the surface of the substrate 60 and an insulator including the same, and the gate insulating film and the gate which are present on the surface of the substrate 60 are not included (this point is also in the following embodiment) It is the same). An n ⁺ -type region 62 (source, drain region) is transmitted through the conductive contact plug 68 formed in the wiring structure 74, the wiring film 72, the conductive contact plug 74a, and the wiring film 75. The bump electrodes 90 form an electrical connection. As a result, a source and a drain region of the transistor Tr _RST are reset, and the corresponding buried wiring 23 is transmitted through the corresponding buried wiring 23 to correspond to the common node 13 (pixel block 12 (i, j)) corresponding to the upper semiconductor circuit layer 21. An electrical connection is formed (see Figure 6). The other n ⁺ -type region 62 (source, drain region) is applied with a reset voltage V _RST through a wiring (not shown).

The amplifying transistor Tr _AMP is composed of a MOS transistor, and includes a gate 65 and a pair of n ⁺ -type regions (source, drain regions) 64 formed on both sides with the gate 65 interposed therebetween. The gate 65 is electrically connected to the corresponding bump electrode 90 through the conductive contact plug 71 formed in the wiring structure 74, the wiring film 72, the conductive contact plug 74a, and the wiring film 75. As a result, the gate of the amplifying transistor Tr _AMP is electrically connected to the common node 13 (pixel block 12 (i, j)) corresponding to the upper semiconductor circuit layer 21 through the corresponding buried wiring 23 (refer to the figure). 6). Further, the other n ⁺ -type region 64 (source and drain region) is electrically connected to the wiring film 73 formed inside the wiring structure 74 through the conductive contact plug 69 formed inside the wiring structure 74. In another n ⁺ type region 64 (source, drain region), the supply voltage Vcc is applied through a wiring (not shown).

n selection transistors Tr _SEL1 to Tr _SELn each composed of a MOS transistor, including a gate 67, and a pair of n ⁺ -type regions (sources) formed on both sides with the gate 67 interposed therebetween , bungee area) 66. An n ⁺ -type region (source, drain region) 66 passes through the conductive contact plug 70 formed in the wiring structure 74, the wiring film 73, and the conductive contact plug 69, and the corresponding amplifying transistor One of the Tr _AMP n ⁺ -type regions (source, drain region) 64 forms an electrical connection. Another n ⁺ type region (source, drain region) 66 is connected to the corresponding output terminal of the image sensor 2. The gate 67 is electrically connected to the output selection line 39 through the wiring formed inside the wiring structure 74. In the gate 67 of each of the selection transistors Tr _SEL1 to Tr _SELn , the application of the predetermined output selection signals φ _SEL1 to φ _SELn is transmitted through the corresponding output selection line 39.

In the image sensor 2 of the fifth embodiment, as shown in FIG. 8, two adjacent selection transistors, for example, Tr _SEL1 and Tr _SEL2 , are formed in the same element region. This is to reduce the occupied area as much as possible. In the element region, three n ⁺ type regions (source, drain region) 66 are formed side by side with a predetermined distance therebetween, and the central n ⁺ type region 66 is composed of two selection transistors Tr _SEL1 And Tr _SEL2 is shared. Further, the shared n ⁺ -type region 66 is electrically connected to one of the corresponding amplifying transistors Tr _AMP n ⁺ -type regions 64. The unshared n ⁺ type regions 66 are respectively connected to corresponding output terminals.

N ⁺ type region within 21 upper semiconductor circuit layer 43 and the n ⁺ type region within the 22 lower bits of the semiconductor circuit layer 62 (lines through the embedded wiring 23 the electrically connected to each thereof, etc.), has a function FD (floating diffusion) region of the In other words, the function is to convert the signal charge amount stored in the photodiodes PD ₁ to PD _n into a voltage signal by photoelectric conversion.

Further, the method of forming the internal structure of the upper semiconductor circuit layer 21 and the lower semiconductor circuit layer 22 is well known to those skilled in the art, and the description thereof will be omitted.

As described above, in the image sensor 2 of the fifth embodiment shown in Figs. 6 and 8, the sensor circuit 1B of the third embodiment shown in Fig. 4 is used, which is (k × m) pixels. The block 12 (the block 12 includes n pixels 11 respectively) and the (k×m) buried wirings 23 are formed in the upper semiconductor circuit layer 21, and the (k×m) reset transistors Tr _RST and (k×m) amplifying transistors Tr _AMP and (k×m) groups of selected transistor groups Tr _SEL1 to Tr _{SELn are} formed in the lower semiconductor circuit layer 22 and further penetrate the buried wiring 23 and the bump electrodes 90, The pixel block 12 in the upper semiconductor circuit layer 21 and the corresponding reset transistor Tr _RST and the amplified transistor Tr _{AMP in the} lower semiconductor circuit layer 22 are electrically connected to each other.

Further, the main surface (the surface of the wiring structure 74) above the lower semiconductor circuit layer 22 is formed by the bump electrode 90 and the adhesive 91, and the lower surface of the upper semiconductor circuit layer 21 (the inside of the substrate 40). Since the electrical and mechanical connections are formed, the two circuit layers 21 and 22 constitute a two-stage semiconductor laminated structure (three-dimensional structure).

Therefore, based on the same reason as in the case of the sensor circuit 1B of the third embodiment described above, the signal charges of all the pixels 11 can be substantially simultaneously stored (substantially simultaneously exposed), and conventional CMOS images do not occur. The image distortion of the sensor enables photography of objects to be moved at high speed.

Moreover, each pixel 11 of the pixel block 12 only needs to have one photodiode and one gate element (MOS transistor), and therefore, three or four in addition to the photodiode in one pixel. A conventional CMOS image sensor of a MOS transistor can achieve a higher pixel aperture ratio (for example, up to about 60%), and the size of the pixel 11 itself can be reduced.

Furthermore, since the CMOS image sensor has a higher pixel aperture ratio than the conventional CMOS image sensor, the total area of the light receiving region (the opening portion of each photodiode) on the surface of the upper semiconductor 21 is relative to the photographing region. The ratio of the total area can be increased.

(Sixth embodiment)

Fig. 7 is a circuit diagram showing a circuit configuration of a main part of the address specifying image sensor 2A according to the sixth embodiment of the present invention; and Fig. 9 is a cross-sectional view of an essential part of the actual structure of the image sensor 2A. In the image sensor 2A, the sensor circuit 1C (see FIG. 5) of the fourth embodiment is used, and the upper semiconductor circuit layer 21 and the lower semiconductor circuit layer 22' are laminated to form a three-dimensional three-layer laminate. structure. The image sensor 2A corresponds to the image sensor of the third aspect of the present invention.

The overall configuration and operation of the image sensor 2A are the same as those shown in FIG. 1. Therefore, the description about them and the like is omitted. Further, the circuit configuration of Fig. 7 is the same as that of the sensor circuit 1C of the fourth embodiment shown in Fig. 5 (the n selection transistors Tr _SEL1 to Tr _SELn are connected to the output ends of the respective amplification transistors Tr _AMP . The output capacitors C _ST1 to C _STn and the output transistors Tr _OUT1 to Tr _OUTn are connected to each _other on the respective output sides of the transistors Tr _SEL1 to Tr _SELn . Therefore, the same reference numerals will be given to the same elements, and the description thereof will be omitted. However, in the image sensor 2A, as will be described later, the well-known buried wiring 23 is used so that the common node 13 of each pixel block 12 formed in the upper semiconductor circuit layer 21 and the node 14 (the node 14 The electrical connection is formed between the reset transistor Tr _RST and the connection point of the amplifying transistor Tr _AMP formed in the lower semiconductor circuit layer 22'. Therefore, in FIG. 7, the buried wiring 23 is added, and the wiring 23 is provided. The resulting parasitic resistance R _o and parasitic capacitances C _o1 and C _o2 . The buried wiring 23 is provided for each pixel block 12 (that is, n pixels 11).

Next, the actual configuration of the image sensor 2A will be described with reference to FIG.

As can be understood from FIG. 9, the image sensor 2A uses the buried wiring 23 and the fine bump electrode 90 and an electrically insulating adhesive (for example, polyimide) 91 to make the upper semiconductor circuit layer 21 and the lower semiconductor circuit layer 22 'Forms mechanical and electrical connections.

The upper semiconductor circuit layer 21 has the same configuration as that of the image sensor 2 (see FIG. 8) of the fifth embodiment, and is formed with (k × m) pixel blocks 12, that is, (k × n) × × pixels 11 and (k × m) buried wirings 23. The internal structure of the upper semiconductor circuit layer 21 is the same as that of the image sensor 2 of the fifth embodiment. Therefore, the same reference numerals are given to the fifth embodiment, and the detailed description thereof will be omitted.

The lower semiconductor circuit layer 22' has substantially the same configuration as the lower semiconductor circuit layer 22 of the image sensor 2 (see FIG. 8) of the fifth embodiment, but the difference is that the storage capacitive element C is added. _ST1 ~ C _STn and output transistors Tr _OUT1 ~ Tr _OUTn . That is, in the lower semiconductor circuit layer 22', in addition to (k × m) reset transistors Tr _RST , (k × m) amplified transistors Tr _AMP , and (k × m) group of selected transistors In addition to the group Tr _SEL1 to Tr _SELn , the storage capacitor element groups C _ST1 to C _STn of the (k × m) group and the output transistor group Tr _OUT1 to Tr _{OUTn of the} (k × m) group are additionally formed.

In the lower semiconductor circuit layer 22', the element isolation insulating film 61 is formed in a predetermined pattern in the surface region of the p-type single crystal germanium substrate 60, thereby forming a predetermined number of element regions for the reset transistor Tr _RST , The number of the component regions of the amplifying transistor Tr _AMP , the predetermined number of selected transistors Tr _SEL1 to Tr _SELn , the storage capacitive elements C _ST1 to C _STn , and the output region of the output transistors Tr _OUT1 to Tr _OUTn . Here, the description will be made in a corresponding configuration of one pixel block 12 (i, j).

The configuration of the reset transistor Tr _{RST is} the same as that of the image sensor 2 (see FIG. 8) of the fifth embodiment described above, and is composed of a MOS transistor, and includes a gate 63 and a gate therebetween. 63 is formed between the pair of n ⁺ type regions (source, drain region) 62 on both sides. The electrical connection of the reset transistor Tr _RST is also the same as that of the image sensor 2 (see Fig. 8) of the fifth embodiment.

The configuration of the amplifying transistor Tr _AMP is also the same as that of the image sensor 2 (see FIG. 8) of the fifth embodiment described above, and is composed of a MOS transistor, and includes a gate 65 and a gate therebetween. 65 is formed between the pair of n ⁺ type regions (source, drain region) 64 on both sides. The electrical connection of the amplifying transistor Tr _AMP is also the same as that of the image sensor 2 (see Fig. 8) of the fifth embodiment.

The configuration of the n selection transistors Tr _SEL1 to Tr _{SELn is} the same as that of the image sensor 2 (see FIG. 8) of the fifth embodiment, and is composed of a MOS transistor, and includes a gate 67, and The gate electrode 67 is formed between the pair of n ⁺ type regions (source, drain region) 66 on both sides. Further, the storage capacitor element and the output transistor are connected to the MOS transistor in a circuit configuration as shown in FIG.

For example, in the case of selecting the transistor Tr _SEL1 , an n ⁺ -type region (source, drain region) 66 is transmitted through the conductive contact plugs 70 and 69 and the wiring film 73 formed inside the wiring structure 74, and the phase An n ⁺ -type region (source, drain region) 64 of the corresponding amplifying transistor Tr _AMP forms an electrical connection. The gate 67 is electrically connected to the output selection line 39 through the wiring formed inside the wiring structure 74, and is applied by the output selection signal _φSEL1 . Another n ⁺ -type region (source, drain region) 66 of the transistor Tr _SEL1 is selected, together with the n ⁺ -type region 66a on the opposite side of the gate 67a, constituting the storage capacitive element C _ST1 function MOS capacitor. The n ⁺ -type region 66a, together with the gate 67b and the n ⁺ -type region 66a on the opposite side of the n ⁺ -type region 66a with the gate 67b as an axis, constitute a MOS having an output transistor Tr _OUT1 function Transistor. The gate 67a is connected to a terminal or region of a predetermined potential (usually a power supply voltage Vcc). The gate 67b is electrically connected to the output control line 39a via a wiring (not shown), and is applied with an output control signal φ _OUT1 .

As shown, in one element region, the selection transistor Tr _SEL1 and the storage capacitance element C _ST1 and the output transistor Tr _{OUT1 are formed} . This point is also the same in other selection transistors Tr _SEL2 ~ Tr _SELn .

As described above, in the image sensor 2 of the sixth embodiment shown in FIGS. 7 and 9, the sensor circuit 1C shown in FIG. 5 is used, which is (k × m) pixel blocks 12 ( Transmission gate groups TG ₁ to TG _n and (k × m) buried wirings 23 each including n pixels 11) and (k × m) are formed in the upper semiconductor circuit layer 21, and ×m) reset transistor Tr _RST , (k × m) amplifying transistor Tr _AMP , (k × m) group of selected transistor groups Tr _SEL1 to Tr _SELn , (k × m) group of storage capacitors The output transistor groups Tr _OUT1 to Tr _{OUTn of the} element groups C _ST1 to C _STn and (k×m) are formed in the lower semiconductor circuit layer 22 ′ and further penetrate the buried wiring 23 and the bump electrode 90 to The pixel block 12 in the upper semiconductor circuit layer 21 is electrically connected to the reset transistor Tr _RST and the amplifying transistor Tr _AMP in the lower semiconductor circuit layer 22'.

Therefore, based on the same reason as in the case of the sensor circuit 1C (see FIG. 5) of the fourth embodiment described above, the signal charges of all the pixels 11 can be substantially simultaneously stored (substantially simultaneously exposed) and does not occur. The image distortion of the conventional CMOS image sensor can capture the object to be moved at a high speed.

Moreover, each pixel 11 of the pixel block 12 only needs to have one photodiode and one gate element (MOS transistor), and therefore, three or four in addition to the photodiode in one pixel. A conventional CMOS image sensor of a MOS transistor can achieve a higher pixel aperture ratio (for example, up to about 60%), and the size of the pixel 11 itself can be reduced.

Furthermore, since the CMOS image sensor has a higher pixel aperture ratio than the conventional CMOS image sensor, the total area of the light receiving region (the opening portion of each photodiode) on the surface of the upper semiconductor 21 is relative to the photographing region. The ratio of the total area can be increased.

Furthermore, by controlling the output transistors Tr _OUT1 ~ Tr _OUTn by outputting the control signals φ _OUT1 ~ φ _OUTn , the signal is outputted to the signal line 37, and the gate TG ₁ is transmitted in the pixel block 12. Since the time at which the TG _n and the selected transistor groups Tr _SEL1 to Tr _SELn are opened and closed can be shifted from each other, it is possible to perform higher speed imaging than the image sensor 2 of the fifth embodiment.

(Seventh embodiment)

Fig. 10 is a circuit diagram showing the configuration of a main part circuit of the address specifying image sensor 2B according to the seventh embodiment of the present invention; and Fig. 11 is a cross-sectional view of an essential part of the actual structure of the image sensor 2B. In the image sensor 2B, the sensor circuit 1C (see FIG. 5) of the fourth embodiment is used, and the upper semiconductor circuit layer 21A and the lower semiconductor circuit layer 22' are laminated to form a three-dimensional three-layer laminate. structure. The image sensor 2B corresponds to the image sensor of the third aspect of the present invention.

The overall configuration and operation of the image sensor 2B are the same as those shown in FIG. 1. Therefore, the description of the circuit is omitted, and the circuit configuration shown in FIG. 10 is the same as the sensor circuit 1C of the fourth embodiment of FIG. 5 except that the buried wiring 23 is added. The same symbols are given and the description thereof is omitted.

As can be understood from FIGS. 10 and 11, in the configuration of the image sensor 2B, the buried semiconductor line 23, the fine bump electrode 90, and the electrically insulating adhesive 91 are used to make the upper semiconductor circuit layer 21A and the lower semiconductor circuit. Layers 22A' form a mechanical and electrical connection to each other. This configuration corresponds to shifting (k × m) reset transistors Tr _RST formed in the lower semiconductor circuit layer 22' in the image sensor 2A (see FIGS. 7 and 9) of the sixth embodiment. Up to the upper semiconductor circuit layer 21. That is, (k×n)×m photodiodes (that is, photodiode groups PD ₁ to PD _{n of the} (k×m) group) are formed in the upper semiconductor circuit layer 21A; ×n) × m transfer gates (that is, transfer gate groups TG ₁ to TG _{n of the} (k × m) group; (k × m) reset transistors Tr _RST ; and (k × m ) a buried wiring 23 . The configuration of the photodiodes PD ₁ to PD _n and the transfer gates TG ₁ to TG _{n is} the same as that of the image sensor 2A of the sixth embodiment, and thus the description thereof will be omitted.

The reset transistor Tr _RST is composed of a MOS transistor, as shown in FIG. 11, and includes a gate 49 and a pair of n ⁺ -type regions (sources) formed on both sides with the gate 49 interposed therebetween Extreme and bungee area) 48. The gate 49 is electrically connected to the corresponding reset line 31 through the wiring formed in the wiring structure 47 on the surface of the substrate 40. An n ⁺ -type region 48 (source, drain region) is transmitted through the conductive contact plug 50 formed in the wiring structure 47, the wiring film 46, the conductive contact plug 23a, and the buried wiring 23, corresponding thereto. The bump electrodes 90 form an electrical connection. As a result, the source and drain regions of the reset transistor Tr _RST are electrically connected to the gate 65 of the amplifying transistor Tr _AMP corresponding to the lower semiconductor circuit layer 22A'. When the other n ⁺ type region 48 (source, drain region) of the transistor Tr _RST is reset, the reset voltage V _RST is applied through a wiring (not shown).

In the lower semiconductor circuit layer 22A', there are: (k × m) amplification transistors Tr _AMP ; (k × m) group of selected transistor groups Tr _SEL1 to Tr _SELn ; (k × m) group of storage capacitors The component group C _ST1 ~ C _STn ; and the (k × m) group of output transistor groups Tr _OUT1 ~ Tr _OUTn . This configuration corresponds to the removal of (k × m) reset transistors Tr _{RST from the lower} semiconductor circuit layer 22' of the sixth embodiment (see FIGS. 7 and 9). The configuration of the amplifying transistor Tr _AMP and the selecting transistors Tr _SEL1 to Tr _{SELn is} the same as that of the sixth embodiment, and thus the description thereof will be omitted.

As described above, in the video sensor 2B of the seventh embodiment shown in FIG. 10 and FIG. 11, the sensor circuit 1C (see FIG. 5) of the fourth embodiment is used, and (k×m) is used. Pixel block 12 (n pixels 11 in each pixel block 12), transfer gate groups TG ₁ to TG _n of (k × m) groups, (k × m) reset transistors Tr _RST , and The k×m) buried wirings 23 are formed in the upper semiconductor circuit layer 21A, and are selected from (k×m) amplified transistors Tr _AMP and (k×m) groups of selected transistor groups Tr _SEL1 to Tr _SELn , The storage capacitor element groups C _ST1 to C _STn of the (k×m) group and the output transistor group Tr _OUT1 to Tr _{OUTn of the} (k×m) group are formed in the lower semiconductor circuit layer 22 ′ and further transmitted through The wiring 23 and the bump electrode 90 are buried so that the reset transistor Tr _RST in the upper semiconductor circuit layer 21 and the amplifying transistor Tr _{AMP of the} lower semiconductor circuit layer 22A' are electrically connected to each other.

Further, the main surface (the surface of the wiring structure 74) above the lower semiconductor circuit layer 22A' is formed by the bump electrode 90 and the adhesive 91, and the lower surface of the upper semiconductor circuit layer 21A (the substrate 40) Since the inner surface is electrically and mechanically connected, the two circuit layers 21A and 22A' constitute a two-stage semiconductor laminated structure (three-dimensional structure).

Therefore, based on the same reason as in the case of the sensor circuit 1C of the fourth embodiment, the signal charges of all the pixels 11 can be substantially simultaneously stored (substantially simultaneously exposed), and the conventional CMOS image perception does not occur. The image distortion of the detector can be used to photograph the object to be moved at a high speed.

Moreover, each pixel 11 of the pixel block 12 only needs to have one photodiode and one gate element (MOS transistor), and therefore, three or four in addition to the photodiode in one pixel. A conventional CMOS image sensor of a MOS transistor can achieve a higher pixel aperture ratio (for example, up to about 60%), and the size of the pixel 11 itself can be reduced.

Furthermore, since the CMOS image sensor has a higher pixel aperture ratio than the conventional CMOS image sensor, the total area of the light receiving region (the opening portion of each photodiode) on the surface of the upper semiconductor 21A is relative to the photographing region. The ratio of the total area can be increased.

Furthermore, by controlling the output transistors Tr _OUT1 ~ Tr _OUTn by outputting the control signals φ _OUT1 ~ φ _OUTn , the signal is outputted to the signal line 37, and the gate TG ₁ is transmitted in the pixel block 12. ~TG _n and the selection _period of the opening and closing of the transistor groups Tr _SEL1 to Tr _SELn can be shifted from each other, and therefore, compared with the case where the storage capacitive elements C _ST1 to C _STn and the output transistors Tr _OUT1 to Tr _{OUTn are} not present, It is possible to implement high-speed photography, and this is also the effect.

(Eighth embodiment)

Fig. 12 is a cross-sectional view of an essential part of an actual configuration of an address specifying image sensor 2C according to an eighth embodiment of the present invention. The image sensor 2C corresponds to the storage of the capacitive elements C _ST1 to C _STn and the output transistors Tr _OUT1 to Tr _{OUTn in} the image sensor 2B (see FIGS. 10 and 11 ) of the seventh embodiment. After the winner. The image sensor 2C corresponds to the address specifying image sensor of the third aspect of the present invention.

As can be seen from Fig. 12, in the configuration of the image sensor 2C of the eighth embodiment, the buried wiring 23, the fine bump electrode 90, and the electrically insulating adhesive 91 are used to make the upper semiconductor circuit layer 21A and the lower layer. The semiconductor circuit layer 22A forms a mechanical and electrical connection. The configuration of the upper semiconductor circuit layer 21A is the same as that of the image sensor 2B of the seventh embodiment. The configuration of the lower semiconductor circuit layer 22A corresponds to the removal of the storage capacitive elements C _ST1 to C _STn and the output transistors Tr _OUT1 to Tr _OUTn from the lower semiconductor circuit layer 22A' of the image sensor 2B of the seventh embodiment. By.

As described above, the sensor circuit 2C of the eighth embodiment can store the signal charges of all the pixels 11 substantially simultaneously (substantially simultaneously exposed) for the same reason as in the case of the image sensor 2B of the seventh embodiment. ), and the image distortion of the conventional CMOS image sensor does not occur, and the object to be photographed at high speed can be photographed.

Moreover, each pixel 11 of the pixel block 12 only needs to have one photodiode and one gate element (MOS transistor), and therefore, three or four in addition to the photodiode in one pixel. A conventional CMOS image sensor of a MOS transistor can achieve a higher pixel aperture ratio (for example, up to about 60%), and the size of the pixel 11 itself can be reduced.

Furthermore, since the CMOS image sensor has a higher pixel aperture ratio than the conventional CMOS image sensor, the total area of the light receiving region (the opening portion of each photodiode) on the surface of the upper semiconductor 21A is relative to the photographing region. The ratio of the total area can be increased.

(Ninth Embodiment)

Fig. 13 is a circuit diagram showing the configuration of a main part of the address specifying type image sensor 2D according to the ninth embodiment of the present invention; and Fig. 14 is a cross-sectional view showing the essential part of the actual structure of the image sensor 2D. In the image sensor 2D, the sensor circuit 1C (see FIG. 5) of the fourth embodiment described above is used, and the three-dimensional laminated structure of the two layers of the upper semiconductor circuit layer 21B and the lower semiconductor circuit layer 22B' is laminated. The image sensor 2B corresponds to the image sensor of the third aspect of the present invention.

The overall configuration and operation of the image sensor 2D are the same as those shown in Fig. 1, and the circuit configuration shown in Fig. 13 is similar to the fourth embodiment of Fig. 5 except that the buried wiring 23 is added. The detector circuit 1C is the same.

As can be understood from FIGS. 13 and 14, in the configuration of the image sensor 2D, the buried semiconductor 23, the fine bump electrode 90, and the electrically insulating adhesive 91 are used to make the upper semiconductor circuit layer 21B and the lower semiconductor circuit. Layer 22B' forms a mechanical and electrical connection with each other. This configuration corresponds to shifting (k × m) magnifying transistors Tr _AMP formed in the lower semiconductor circuit layer 22A' in the image sensor 2B (see FIGS. 10 and 11) of the seventh embodiment. This upper semiconductor circuit layer 21B.

That is, (k×n)×m photodiodes (that is, photodiode groups PD ₁ to PD _n having (k×m) groups) are formed in the upper semiconductor circuit layer 21B; k × n) × m transfer gates (that is, transfer gate groups TG ₁ to TG _{n of} (k × m) groups; (k × m) reset transistors Tr _RST ; (k × m) amplifying transistor Tr _AMP and (k × m) buried wiring 23. The configuration of the photodiode PD ₁ to PD _n and the transfer gates TG ₁ to TG _n and the reset transistor Tr _{RST is} the same as that of the image sensor 2B of the seventh embodiment, and therefore the description thereof will be omitted. .

As shown in FIG. 14, the amplifying transistor Tr _AMP is composed of a MOS transistor, and includes a gate 53 and a pair of n ⁺ -type regions (sources, respectively, formed on both sides with the gate 53 interposed therebetween) Bungee area) 52. The gate 53 is electrically connected to the reset transistor Tr _RST and the transfer gates TG ₁ to TG _n through the conductive contact plug 54 and the wiring film 46 formed inside the wiring structure 47. The n ⁺ -type region 52 (source, drain region) passes through the conductive contact plug 55 formed in the wiring structure 47, the wiring film 56, the conductive contact plug 23a, and the buried wiring 23, and the phase The corresponding bump electrodes 90 form an electrical connection. As a result, the source and drain regions of the transistor Tr _AMP are amplified, and an n ⁺ -type region 66 (source, drain region) of the selection transistors Tr _SEL1 to Tr _SELn corresponding to the lower semiconductor circuit layer 22B'. ) forming an electrical connection. When the other n ⁺ -type region 52 (source, drain region) of the transistor Tr _AMP is amplified, the supply voltage Vcc is applied through a wiring (not shown).

In the lower semiconductor circuit layer 22B', a selection transistor group Tr _SEL1 to Tr _SELn of the (k × m) group; a storage capacitor element group C _ST1 to C _{STn of the} (k × m) group; and (k ×) are formed. m) The output transistor group Tr _OUT1 ~ Tr _{OUTn of the} group. This configuration corresponds to the removal of (k × m) amplification transistors Tr _{AMP from the lower} semiconductor circuit layer 22A' of the seventh embodiment (see FIGS. 10 and 11). The configuration of the transistors Tr _SEL1 to Tr _SELn and the storage capacitive elements C _ST1 to C _STn and the output transistors Tr _OUT1 to Tr _{OUTn is} the same as that of the seventh embodiment, and the description thereof will be omitted.

As described above, in the video sensor 2D of the ninth embodiment shown in FIG. 13 and FIG. 14, the sensor circuit 1C (see FIG. 5) of the fourth embodiment is used, and (k×m) is used. Pixel block 12 (n pixels 11 in each pixel block 12), transfer gate groups TG ₁ to TG _n of (k × m) groups, (k × m) reset transistors Tr _RST , (k ×m) amplifying transistor Tr _AMP and (k×m) buried wirings 23 are formed in the upper semiconductor circuit layer 21B, and are selected from the (k×m) group of selected transistor groups Tr _SEL1 to Tr _SELn , The storage capacitor element groups C _ST1 to C _STn of the (k × m) group and the output transistor groups Tr _OUT1 to Tr _{OUTn of the} (k × m) group are formed in the lower semiconductor circuit layer 22B', and further transmitted. The wiring 23 and the bump electrode 90 are buried so that the amplifying transistor Tr _AMP in the upper semiconductor circuit layer 21B and the selection transistors Tr _SEL1 to Tr _{SELn in the} lower semiconductor circuit layer 22B' are electrically connected to each other.

Further, the main surface (the surface of the wiring structure 74) above the lower semiconductor circuit layer 22B' is formed by the bump electrode 90 and the adhesive 91, and the lower surface of the upper semiconductor circuit layer 21B (the substrate 40) Since the inner surface is electrically and mechanically connected, the two circuit layers 21B and 22B' constitute a two-stage semiconductor laminated structure (three-dimensional structure).

Therefore, based on the same reason as in the case of the sensor circuit 1C of the fourth embodiment, the signal charges of all the pixels 11 can be substantially simultaneously stored (substantially simultaneously exposed), and the conventional CMOS image perception does not occur. The image distortion of the detector can be used to photograph the object to be moved at a high speed.

Moreover, each pixel 11 of the pixel block 12 only needs to have one photodiode and one gate element (MOS transistor), and therefore, three or four in addition to the photodiode in one pixel. A conventional CMOS image sensor of a MOS transistor can achieve a higher pixel aperture ratio (for example, up to about 60%), and the size of the pixel 11 itself can be reduced.

Furthermore, since the CMOS image sensor has a higher pixel aperture ratio than the conventional CMOS image sensor, the total area of the light receiving region (the opening portion of each photodiode) on the surface of the upper semiconductor 21B is relative to the photographing region. The ratio of the total area can be increased.

Furthermore, by controlling the output transistors Tr _OUT1 ~ Tr _OUTn by outputting the control signals φ _OUT1 ~ φ _OUTn , the signal is outputted to the signal line 37, and the gate TG ₁ is transmitted in the pixel block 12. ~TG _n and the selection _period of the opening and closing of the transistor groups Tr _SEL1 to Tr _SELn can be shifted from each other, and therefore, compared with the case where the storage capacitive elements C _ST1 to C _STn and the output transistors Tr _OUT1 to Tr _{OUTn are} not present, It is possible to implement high-speed photography, and this is also the effect.

(Tenth embodiment)

Fig. 15 is a cross-sectional view of an essential part of an actual configuration of an address specifying image sensor 2E according to a tenth embodiment of the present invention. The image sensor 2E corresponds to the storage of the capacitive elements C _ST1 to C _STn and the output transistors Tr _OUT1 to Tr _{OUTn in} the image sensor 2C (see FIGS. 13 and 14 ) of the ninth embodiment. After the winner. The image sensor 2E corresponds to the address specifying image sensor of the third aspect of the present invention.

As can be seen from Fig. 15, in the configuration of the image sensor 2E of the tenth embodiment, the buried wiring 23, the fine bump electrode 90, and the electrically insulating adhesive 91 are used to make the upper semiconductor circuit layer 21B and the lower layer. The semiconductor circuit layer 22B forms a mechanical and electrical connection. The configuration of the upper semiconductor circuit layer 21B is the same as that of the image sensor 2D of the ninth embodiment. The configuration of the lower semiconductor circuit layer 22B corresponds to the removal of the storage capacitive elements C _ST1 to C _STn and the output transistors Tr _OUT1 to Tr _OUTn from the lower semiconductor circuit layer 22B' of the image sensor 2D of the ninth embodiment. By.

As described above, the sensor circuit 2E of the tenth embodiment can store the signal charges of all the pixels 11 substantially simultaneously (substantially simultaneously exposed) for the same reason as in the case of the image sensor 2D of the ninth embodiment. ), and the image distortion of the conventional CMOS image sensor does not occur, and the object to be photographed at high speed can be photographed.

Moreover, each pixel 11 of the pixel block 12 only needs to have one photodiode and one gate element (MOS transistor), and therefore, three or four in addition to the photodiode in one pixel. A conventional CMOS image sensor of a MOS transistor can achieve a higher pixel aperture ratio (for example, up to about 60%), and the size of the pixel 11 itself can be reduced.

Furthermore, since the CMOS image sensor has a higher pixel aperture ratio than the conventional CMOS image sensor, the total area of the light receiving region (the opening portion of each photodiode) on the surface of the upper semiconductor 21B is relative to the photographing region. The ratio of the total area can be increased.

(Eleventh embodiment)

Fig. 16 is a circuit diagram showing the configuration of a main part of the address specifying image sensor 2F according to the eleventh embodiment of the present invention. Fig. 17 is a cross-sectional view showing the essential part of the actual structure of the image sensor 2F. In the image sensor 2F, the sensor circuit 1C (see FIG. 5) of the fourth embodiment described above is used, and the three-dimensional laminated structure of the two layers of the upper semiconductor circuit layer 21C and the lower semiconductor circuit layer 22C' is laminated. The image sensor 2F corresponds to the image sensor of the third aspect of the present invention.

The overall configuration and operation of the image sensor 2F are the same as those shown in Fig. 1. The circuit configuration shown in Fig. 16 is the same as that of the fourth embodiment of Fig. 5 except that the buried wiring 23 is added. Circuit 1C is the same.

16 and FIG. 17, the configuration of the image sensor 2F uses the buried wiring 23, the fine bump electrode 90, and the electrically insulating adhesive 91 to make the upper semiconductor circuit layer 21C and the lower semiconductor circuit. Layers 22C' form a mechanical and electrical connection to each other. This configuration corresponds to the (k×m) group transfer gate groups TG ₁ to TG _n formed in the upper semiconductor circuit layer 21 in the image sensor 2A (see FIGS. 7 and 9 ) of the sixth embodiment. And moved to the lower semiconductor circuit layer 22'. Therefore, in the upper semiconductor circuit layer 21C, only (k × n) × photodiodes (that is, photodiode groups PD ₁ to PD _n having (k × m) groups), and (k ×) are formed. m) one buried wiring 23.

The configuration of the photodiodes PD ₁ to PD _n is substantially the same as that of the image sensor 2A (see FIGS. 7 and 9 ) of the sixth embodiment, but differs in the respective element regions of the substrate 40 . A photodiode is formed. For example, in the case of the photodiode PD ₁ , as shown in FIG. 17, one of a plurality of element regions formed in the surface region of the p-type substrate 40 by the element isolation insulating film 41 is used to span the entire surface. the manner n ⁺ region 42 is formed, it is formed photodiode PD ₁ in the n ⁺ region 42. In the substrate 40, a through hole for penetrating the element isolation insulating film 41 and the substrate 40 in the vertical direction (the direction orthogonal to the main surface of the substrate 40) is formed at an appropriate position overlapping the element isolation insulating film 41. The portion of the hole that is in contact with the substrate 40 has an insulating film 24 covering the entire surface of the inner wall. A conductive material is filled inside the through hole (inside of the insulating film 24 and inside the element isolation insulating film 41), and the buried wiring 23 is formed of the conductive material. The upper end of the buried wiring 23 is exposed by the surface of the substrate 40 (the element isolation insulating film 41), and is in contact with the lower surface of the wiring film 57 formed inside the wiring structure 47. The lower surface of the wiring film 57 is also connected to the surface of the corresponding n ⁺ region 42, so that the n ⁺ region 42 is electrically connected to the buried wiring 23. The lower end of the buried wiring 23 is exposed from the inner surface of the substrate 40 (the element isolation insulating film 41), and is mechanically and electrically connected to the corresponding bump electrode 90.

In the lower semiconductor circuit layer 22C', a transfer gate group TG ₁ to TG _n of (k × m) groups; (k × m) reset transistors Tr _RST ; (k × m) amplification power are formed. Crystal Tr _AMP ; (k × m) group of storage capacitor elements C _ST1 ~ C _STn ; and (k × m) group of output transistor groups Tr _OUT1 ~ Tr _OUTn . When the reset transistor Tr _RST , the amplifying transistor Tr _AMP , the storage capacitive elements C _ST1 to C _STn , and the output transistors Tr _OUT1 to Tr _{OUTn are} provided and the image sensor 2A of the sixth embodiment is provided (refer to FIG. 7) The same components are denoted by the same reference numerals, and the description thereof will be omitted. Further, in Fig. 17, the storage capacitive elements C _ST1 to C _STn and the output transistors Tr _OUT1 to Tr _OUTn have been omitted.

The transfer gates TG ₁ to TG _n have the following configurations. For example, in the case of the transfer gate TG ₁ , as shown in FIG. 17, it is composed of a MOS transistor, which includes a gate 77, and a pair of n ^{+ is} formed on both sides with the gate 77 interposed therebetween. Type area (source, drain area) 76. The gate 77 has a transfer gate control signal φ _T1 applied through a wiring (not shown). An n ⁺ -type region 76 (source, drain region), through the conductive contact plugs 78, 80, 82 formed inside the wiring structure 74, and wiring films 79, 81 and 83, and corresponding bump electrodes 90 forms an electrical connection. As a result, the source and drain regions in the transfer gate TG ₁ are electrically connected to the photodiode PD ₁ corresponding to the upper semiconductor circuit layer 21C through the buried wiring 23. The other n ⁺ -type region 76 (source and drain region) of the MOS transistor is transmitted through the conductive contact plug 78 formed in the wiring structure 74 and a wiring film (not shown), and the corresponding reset is performed. The transistor Tr _RST and the amplifying transistor Tr _AMP form an electrical connection. The transfer gates TG ₂ to TG _n have the same configuration as the transfer gate TG ₁ . As shown, the transfer gates TG ₁ to TG _n in the lower semiconductor circuit layer 22C' are electrically connected to the photodiodes PD ₁ to PD _{n in the} upper semiconductor circuit layer 21C through the buried wiring 23, respectively.

As described above, in the video sensor 2F of the eleventh embodiment shown in Figs. 16 and 17, the sensor circuit 1C (see Fig. 5) of the fourth embodiment is used, which is (k × m) The pixel block 12 (each pixel block 12 includes n pixels 11) and (k×m) buried wirings 23 are formed in the upper semiconductor circuit layer 21C, and are the transfer gate groups of the (k×m) group. TG ₁ ~ TG _n , (k × m) reset transistors Tr _RST , (k × m) amplification transistors Tr _AMP , (k × m) group of selected transistor groups Tr _SEL1 ~ Tr _SELn , (k The storage capacitor element groups C _ST1 to C _{STn of the} ×m) group and the output transistor groups Tr _OUT1 to Tr _{OUTn of the} (k×m) group are formed in the lower semiconductor circuit layer 22C′, and further through the buried wiring The bump electrode 90 and the pixel block 12 in the upper semiconductor circuit layer 21C are electrically connected to the transfer gates TG ₁ to TG _n r _AMP in the lower semiconductor circuit layer 22C'.

Further, the main surface (the surface of the wiring structure 74) above the lower semiconductor circuit layer 22C' is formed by the bump electrode 90 and the adhesive 91, and the lower surface of the upper semiconductor circuit layer 21C (the substrate 40) Since the inner surface is electrically and mechanically connected, the two circuit layers 21C and 22C' constitute a two-stage semiconductor laminated structure (three-dimensional structure).

Therefore, based on the same reason as in the case of the sensor circuit 1C of the fourth embodiment described above, the signal charges of all the pixels 11 can be substantially simultaneously stored (substantially simultaneously exposed), and conventional CMOS images do not occur. The image distortion of the sensor enables photography of objects to be moved at high speed.

Moreover, each pixel 11 of the pixel block 12 includes only one photodiode, and thus has a conventional CMOS image sense including three or four MOS transistors in addition to the photodiode in one pixel. The detector can achieve a higher pixel aperture ratio (for example, up to about 60%), and the size of the pixel 11 itself can also be reduced. In particular, it can be smaller than in the fifth embodiment to the tenth embodiment.

Furthermore, since the CMOS image sensor has a higher pixel aperture ratio than the conventional CMOS image sensor, the total area of the light receiving region (the opening portion of each photodiode) on the surface of the upper semiconductor 21C is relative to the photographing region. The ratio of the total area can be increased. In particular, it can be higher than in the fifth embodiment to the tenth embodiment.

Furthermore, by controlling the output transistors Tr _OUT1 ~ Tr _OUTn by outputting the control signals φ _OUT1 ~ φ _OUTn , the signal is outputted to the signal line 37, and the gate TG ₁ is transmitted in the pixel block 12. ~TG _n and the selection _period of the opening and closing of the transistor groups Tr _SEL1 to Tr _SELn can be shifted from each other, and therefore, compared with the case where the storage capacitive elements C _ST1 to C _STn and the output transistors Tr _OUT1 to Tr _{OUTn are} not present, It is possible to implement high-speed photography, and this is also the effect.

(Twelfth embodiment)

Fig. 18 is a cross-sectional view of an essential part of an actual configuration of an address specifying image sensor 2G according to a twelfth embodiment of the present invention. The image sensor 2G corresponds to the image sensor 2F (see FIGS. 16 and 17) of the eleventh embodiment, which holds the lower semiconductor circuit layer 22C' as it is, and the substrate in the upper semiconductor circuit layer 21C. 40 will be up and down. The image sensor 2G corresponds to the address specifying image sensor of the third aspect of the present invention.

The image sensor 2G of the twelfth embodiment can be understood from Fig. 18 by using the fine bump electrode 90 and the electrically insulating adhesive 91 to electrically connect the upper semiconductor circuit layer 21D and the lower semiconductor circuit layer 22D'. Mechanical connection. The configuration of the lower semiconductor circuit layer 21D' is the same as that of the lower semiconductor circuit layer 21C' of the image sensor 2F of the eleventh embodiment. In the image sensor 2G, unlike the above-described fifth to eleventh embodiments, the buried wiring 23 is not used.

The substrate 40 in the upper semiconductor circuit layer 21D is reversed from the upper semiconductor circuit layer 21C of the image sensor 2F of the eleventh embodiment, and the wiring structure 47 is positioned on the lower side, and the substrate 40 is positioned on the upper side. Since the external light passes through the substrate 40 and is irradiated to the photodiodes PD ₁ to PD _n , the thickness of the substrate 40 is thinner than that of the image sensor 2F of the eleventh embodiment.

Inside the wiring structure 47, conductive contact plugs 58 are formed, which are electrically and mechanically connected to respective surfaces of a plurality of n ⁺ -type regions 42 (to constitute photodiodes PD ₁ to PD _n ); And a plurality of wiring films 59 which are electrically and mechanically connected to their respective conductive contact plugs 58, respectively. The wiring film 59 is disposed in the vicinity of the surface of the wiring structure 47, and is electrically and mechanically connected to the corresponding bump electrode 90. As shown, the photodiodes PD ₁ to PD _n are transmitted through the corresponding bump electrodes 90, and electrically connected to the transfer gates TG ₁ to TG _n corresponding to the lower semiconductor circuit layers 22D'.

The image sensor 2G of the twelfth embodiment shown in Fig. 18 has the above-described configuration, and it is obvious that the image sensor 2G has the same effects as those described in the image sensor 2F of the eleventh embodiment.

(Thirteenth embodiment)

Fig. 20 is a circuit diagram showing the configuration of a main circuit of the sensor circuit 3 of the thirteenth embodiment of the present invention. Fig. 19 is a functional block diagram showing the overall configuration of an address specifying type image sensor of the sensor circuit 3. The sensor circuit 3 corresponds to the sensor circuit of the second aspect of the present invention.

The overall configuration of the image sensor of FIG. 19 is different from the address specifying image sensor shown in FIG. 1 in that each of the k pixel blocks 12a belonging to the same row is provided. Line 31 is set. That is, there are (k × n) × m pixels 11a arranged in an array of (k × n) columns m rows. In each of the pixel blocks 12a, n pixels 11a belonging to the same row are merged and connected in parallel to the common node 19 (not shown in Fig. 19. Corresponding to the common node 13a in Fig. 20).

In each of the pixel blocks 12a, m reset lines 31 are formed which extend along corresponding rows of the pixel array and penetrate the pixel block 12a to which the row belongs. Each of the pixels 11a in each of the reset lines 31 is connected to one reset transistor. In other words, reset transistors Tr _RST1 to Tr _RSTn are provided for the n pixels 11a to which the pixel block 12a belongs. The transistor Tr _{AMP is} amplified, one for each pixel block 12a. The n reset transistor groups Tr _RST1 to Tr _RSTn are respectively disposed inside the n pixels 11a in the corresponding pixel block 12a, and the amplifying transistor Tr _AMP is disposed in the corresponding pixel block 12a. external.

Each reset line 31 is used to reset the signal charge of the pixel 11a in the k pixel blocks 12a to which the corresponding row belongs. The application of the reset voltage V _{RST to} the pixel 11a is performed using the corresponding reset transistors Tr _RST1 to Tr _RSTn . Each of the amplifying transistors Tr _{AMP is} amplified for the signal read from the pixel 11a in the corresponding pixel block 12a, and then sent to the corresponding line signal line 37. The signals amplified by the respective amplifying transistors Tr _{AMP are} sequentially sent to the corresponding line signal lines 37.

Except for the configuration of the pixel 11a and the pixel block 12a and the arrangement of the reset line 31, the other configuration is the same as that of FIG. 1, and the description thereof will be omitted.

Hereinafter, the sensor circuit 3 of the thirteenth embodiment, that is, the sensor circuit for configuring the image sensor shown in Fig. 19, will be described with reference to Fig. 20 . Fig. 20 is a circuit configuration of two pixel blocks 12a(i, j) and 12a(i+1, j) to which the jth row belongs.

The pixel block 12 (i, j) located above includes pixels 11 belonging to the [n×(i-1)+1]th column to the (n×i)th column of the jth row. The pixel block 12 (i+1, j) located below includes pixels 11 belonging to the [n×i+1]th column to the [n×(i+1)]th column of the jth row. The two pixel blocks 12 (i, j) have the same configuration as 12 (i+1, j). Therefore, in the following description, the upper pixel block 12 (i, j) will be mainly described.

In the pixel block 12a(i, j), n pixels 11a are included. In other words, it includes: n photodiodes PD ₁ to PD _n , n transfer gates TG ₁ to TG _n , and n reset transistors Tr _RST1 to Tr _RSTn . Each of the pixels 11a includes a photodiode, a transfer gate, and a reset transistor. The transfer gates TG ₁ to TG _n are respectively composed of MOS transistors. The reset transistors Tr _RST1 ~ Tr _{RSTn are} also formed by MOS transistors, respectively. The anodes of the photodiodes PD ₁ to PD _n are connected to the node 15 (node 15, which is one of the source, the drain region, and the reset transistor Tr of the corresponding _one of the transfer gates TG ₁ to TG _n The connection point of one of the source and the drain region of the corresponding one of _RST1 to Tr _RSTn is connected to the terminal or region of the predetermined potential (usually the ground potential). The other source and drain regions of the reset transistors Tr _RST1 to Tr _RSTn are connected to the reset voltage source (reset voltage = V _RST ). The other source and drain regions of the transfer gates TG ₁ to TG _n are commonly connected to the common node 13a. As shown, n pixels 11a of the pixel block 12a(i, j) are connected in parallel to the common node 13a in the pixel 11a.

The common node 13a of the pixel block 12a (i, j) is connected to the gate of the corresponding amplifying transistor Tr _AMP . The amplifying transistor Tr _AMP is disposed outside the pixel block 12a (i, j). A source and drain region of the amplifying transistor Tr _AMP is connected to a DC power source (power supply voltage = Vcc), and the other source and drain regions (output side) are connected to the pixel block 12 (i, j). The output terminals (ie, the corresponding line signal lines 37) are connected. The output terminal (source and drain region on the output side) of the amplifying transistor Tr _AMP is connected to a terminal of a predetermined potential (usually a ground potential) through a resistor R, and constitutes an amplifier of a source follower type. Parasitic capacitance is generated in the node 15, but is omitted in FIG.

The source and drain regions on the output side of the amplifying transistor Tr _{AMP are} connected to the corresponding row signal line 37. Therefore, the output signals of the amplifying transistors Tr _AMP , that is, the serial output signals of the n photodiodes PD ₁ to PD _n are sequentially sent to the corresponding CDS circuits 36. Moreover, when the CDS circuit 36 is sent to the horizontal signal line 33, the line signal line 37 is selected by the m row selection signals 38 by the scanning of the horizontal scanning circuit 35, thereby transmitting the timing output signal to Horizontal signal line 33. Thereafter, it is transmitted to an output terminal (not shown) of the image sensor provided at one end of the horizontal signal line 33 (located at the right end in FIG. 19).

All of the pixel blocks 12a other than the pixel block 12a (i, j) have the same configuration as the pixel block 12a (i, j), and therefore, the timing of the n photodiodes PD ₁ to PD _{n is} the same as described above. The output signal is transmitted to the output terminal of the image sensor. This allows photography of the object to be taken.

Next, the following description will be given of the operation of the image sensor having the sensor circuit 3 configured as described above (from the generation and storage of the signal charge until the output of the signal).

1. Overall reset of all pixels (all photodiodes) First, the logic state of the transfer gate control signals φ _T1 ~ φ _Tn applied to the gates of the MOS transistors is H (high), so that all transfers The gates TG ₁ to TG _{n are} turned on (the MOS transistors have n, which are used to constitute the transfer gates TG ₁ to TG _n of the photodiodes PD ₁ to PD _n provided in all the pixels 11 a That is, the transistor of the first gate element).

Then, in this state, the logic state of the reset control signal φ _RST applied to the gates of the reset transistors Tr _RST1 to Tr _RSTn is H, and all the reset transistors Tr _RST1 to Tr _{RSTn are} turned on. (The reset transistors Tr _RST1 to Tr _{RSTn are} referred to as reset transistors of the pixels 11a provided in the respective pixel blocks 12a). As a result, the predetermined reset voltage V _{RST is} transmitted through the node 15 and applied to the photodiodes PD ₁ to PD _{n of} all the pixels 11 a at the same time. As shown, all of the pixels 11a are reset as a whole, that is, "overall reset" is performed. At this time, the voltages of the gates of all the amplifying transistors Tr _AMP are also reset.

2. Exposure (charge storage) Next, the logic state of the transfer gate control signals φ _T1 to φ _Tn applied to the transfer gates TG ₁ to TG _n is Low (L), so that all transfer gates TG ₁ to TG _n Become disconnected. At the same time, the logic state of the reset control signal φ _RST is set to L, and all of the reset transistors Tr _RST1 to Tr _{RSTn are} also turned off.

Thereafter, in this state, the light is irradiated in all pixels 11a of the photodiode PD ₁ ~ PD _n, so that all photodiode PD ₁ ~ PD _n to produce a whole, the charge storage signal. The irradiation time is generally several hundred μsec or even several msec, which is very long.

At the same time as the generation and storage of the signal charge, the logic state of the reset control signal φ _RST is made H, and all the reset transistors Tr _RST1 to Tr _{RSTn are} turned on as a whole, and the transfer gate control signal φ _T1 ~ is made. The logic state of φ _Tn is H, and all of the transfer gates TG ₁ to TG _{n are} turned on. After a predetermined time (for example, 1 μsec), the logic state of the reset control signal φ _RST is again set to L, so that all the reset transistors Tr _RST1 to Tr _{RSTn are} turned off as a whole, and at the same time, all The logic state of the transfer gate control signals φ _T1 to φ _Tn is again L, and all of the transfer gates TG ₁ to TG _{n are} turned off. Thus, the application of the reset voltage V _RST temporarily ~ all common nodes 13a (i.e., all the amplifying transistor Tr _AMP gate), to the gate voltages of all the amplifying transistor Tr _AMP is set (reset) to the predetermined reference Voltage.

3. Reading of the signal and amplifying the amount of charge generated and stored in all of the photodiodes PD ₁ to PD _n in the above manner, and the signal proportional to the voltage is obtained from the pixel 11a in the following manner Read and then zoom in.

That is, first, by selecting the pixel block 12a by the vertical scanning circuit 34 and the horizontal scanning circuit 35, the logical states of the n transfer gate control signals φ _T1 to φ _Tn in the pixel block 12a are sequentially ordered by L. When it becomes H, the transfer gates TG ₁ to TG _{n are} sequentially turned on. Further, after maintaining the on state of the same state for a predetermined period of time (for example, 0.1 μsec), the logic state of the equal state is returned to L in order. Thus, the signals from all of the photodiodes PD ₁ -PD _n in the pixel block 12a are read at the node 14 in accordance with the timing. During this time, all of the reset transistors Tr _RST1 to Tr _RSTn are kept in the off state.

The amplifying transistor Tr _AMP connected to the node 13a in the form of a source follower is connected to the node 13a, so that the voltage signal read to the node 13a is immediately amplified by the amplifying transistor Tr _AMP . Further, the amplified signal is outputted from the source and drain regions on the output terminal side of the amplifying transistor Tr _AMP to the line signal line 37.

When a signal is read from the n pixels 11a (ie, the photodiodes PD ₁ to PD _n ) in the pixel block 12a to be amplified, a pixel 11a (for example, a photodiode PD ₁ ) is read from The end of the action of the signal and the amplification thereof is started until the start of the signal reading of the next pixel 11a (for example, the photodiode PD ₂ ), as described above, the reset power must be used for the pixel 11a. The crystal Tr _{RST1 is} turned on to temporarily apply the reset voltage V _RST to the node 13a, and all of the nodes 13a (gates of the amplifying transistor Tr _AMP ) are set (reset) at the reference potential. The reason is that if this is not the case, it is feared that the residual influence of the signal of the previous pixel 11a (for example, the photodiode PD ₁ ) may cause a signal error condition of the subsequent pixel 11a (for example, the photodiode PD ₂ ).

Since there are n pixels 11a (n photodiodes PD ₁ to PD _n ) in the pixel block 12a, the read operation by the gate control signals φ _T1 to φ _{Tn is} performed n times. The amplification operation by the amplifying transistor Tr _AMP has a total of n times; the reset operation of the amplifying transistor Tr _AMP has a total number of times (n-1) times.

Specifically, for example, initially, the first transfer gate TG _{1 of} the pixel block 12a is temporarily turned on, and is proportional to the signal charge (that is, the signal charge stored in the first photodiode PD ₁ ). The signal is read at node 13a. The signal is immediately amplified by the amplifying transistor Tr _AMP , and then the obtained amplified signal is transmitted to the signal line 37. Next, the reset transistor Tr _RST1 connected to the photodiode PD ₁ is temporarily turned on, the reset voltage V _{RST is} temporarily applied to the node 13a, and the gates of all the amplifying transistors Tr _AMP (node 14) ) Reset to the reference potential.

Thereafter, the second transfer gate TG ₂ in the pixel block 12a is temporarily turned on, and the signal is proportional to the signal charge (that is, the signal charge stored in the second photodiode PD ₂ ) by the node 13a. . The signal is immediately amplified by the amplifying transistor Tr _AMP , and the resulting amplified signal is transmitted to the signal line 37. Next, the reset transistor Tr _RST2 connected to the photodiode PD ₂ is temporarily turned on, and the gate (node 14) of the amplifying transistor Tr _AMP is reset to the reference potential. Next, the same operation as described above is repeated for the third photodiode PD ₃ , the fourth photodiode PD _{4 ,} and the like. Finally, after the reading operation and the amplification operation are performed on the nth photodiode PD _n , the processing of the pixel block 12a is ended.

In the image sensor of FIG. 1, the output terminal of the amplifying transistor Tr _AMP corresponding to the pixel block 12a is one, and therefore, all of the photodiodes PD ₁ to PD _{n in} the pixel block 12a are used. The obtained n signals are outputted from the source and drain regions on the output terminal side of the amplifying transistor Tr _AMP to the line signal line 37 in time series. That is, the signal outputted by the pixel block 12a becomes a signal pulse amount (the amount of illumination light) for connecting the n pulse waveforms to reflect the photodiodes PD ₁ to PD _n with a predetermined interval therebetween. Timing signal.

The image sensor (see FIG. 19) has a total of (k × m) pixel blocks 12a. Therefore, during the scanning of all the pixels 11a, the above operation is repeated (k × m) times.

The signal outputted by the pixel block 12a, that is, a timing signal in which n pulses are connected at a predetermined interval, is sent to a well-known sample and hold circuit or A/D conversion circuit to Perform the intended signal processing.

The fastest exposure speed (ie, the shortest signal charge storage period) is now (1/8000) seconds (= 125 μ sec). Therefore, for the (k × m) pixel blocks 12a, if the n value (the total number of the pixels 11a in each pixel block 12a) can be set in the following manner, the pixels 11a to which all the pixel blocks 12a belong can be made ( The signal charge storage (exposure) of the photodiodes PD ₁ to PD _n ) can be performed substantially simultaneously, that is, the node 13a (the gate of the amplifying transistor Tr _AMP ) by the reset transistor Tr _RST1 to Tr _RSTn is obtained. The time required for the reset action to reach the necessary number of times (i.e., n times) (total reset time), and the signal sent from all the pixels 11a (photodiodes PD ₁ to PD _n ) in the pixel block 12a are The sum of the time (total amplification time) required to amplify the corresponding amplifying transistor Tr _AMP , and then make the sum (k × m) times much shorter than the shortest signal charge storage period (= 125 μ sec) . In other words, the signal charges of all of the pixels 11a can be stored substantially simultaneously (substantially simultaneously exposed).

Further, (k × m) output timing signals are independently outputted from all the pixel blocks 12a. Therefore, for the output timing signals, analogous, digital (A/D) conversion and the like can be performed in parallel. Thereby, compared with the conventional CMOS image sensor, there is a higher speed data processing. This also benefits the realization of substantially simultaneous exposure.

It can be understood from the above actions that if viewed in a frame, the timing output signal outputted by each pixel block 12a is closer to the end of the scanning time than that generated during the initial period of the scanning period. The longer the charge storage period (although quite a small amount). Therefore, in order to obtain more accurate image data, or to have a large n value, a well-known circuit can be provided in the latter stage for signal correction in accordance with changes in charge storage period. Thereby, it is possible to suppress or avoid being affected by variations in charge storage period.

Since the image can be substantially simultaneously exposed by the above method, the image distortion of the conventional CMOS image sensor does not occur, and the object to be photographed at high speed can be photographed.

Further, the common amplifying transistor Tr _AMP is disposed outside the pixel block 12a so as to correspond to each of the pixel blocks 12a. Therefore, each pixel 11a in the pixel block 12a need only be included. A photodiode with a gate element (MOS transistor) and a reset transistor (MOS transistor). Therefore, a higher pixel aperture ratio (for example, about 60%) can be realized as compared with a conventional CMOS image sensor in which one photodiode has three or four MOS transistors in one pixel. The pixel aperture ratio is compared with the image sensor (see FIGS. 1 and 2) using the sensor circuit 1 of the first embodiment (that is, the one including only one photodiode and one gate element). Because there is a reset transistor, it is correspondingly reduced.

Furthermore, in the conventional CMOS image sensor, the signal processing is performed in time series according to the number of scanning lines, and a high-speed A/D conversion circuit is required, but the sensor of the thirteenth embodiment is used. In the image sensor of the circuit 3, the number of scan lines set by the n value is small and the degree of parallel connection can be increased, so that the processing speeds of the slower timing output signals of the respective amplifying transistors Tr _AMP can be allowed. Therefore, it is possible to use an A/D conversion circuit which is simpler in construction, and this is also an effect.

Further, n output signals from the n photodiodes PD ₁ to PD _n are outputted in series by the respective amplifying transistors Tr _AMP , and thus are connected to the output terminals of the respective amplifying transistors Tr _AMP The wiring of a section will tend to be simple, and this is also the effect.

(Fourteenth embodiment)

Fig. 21 is a circuit diagram showing the configuration of a main part of the address specifying type image sensor 4 according to the fourteenth embodiment of the present invention. Fig. 23 is a cross-sectional view showing the essential part of the actual structure of the image sensor 4. The sensor circuit used in the image sensor 4 is an amplifying transistor Tr _AMP of the sensor circuit 3 (see FIG. 20) of the thirteenth embodiment (the amplifying transistor Tr _AMP is used for each pixel) The source and drain regions on the output side of the block 12a are provided in a corresponding manner, and n selection transistors Tr _SEL1 to Tr _SELn (second gate elements) are connected so that the n photodiodes after amplification are connected The n output signals of PD ₁ to PD _n are output in parallel by selecting the transistors Tr _SEL1 to Tr _{SELn ,} and the upper semiconductor circuit layer 21E and the lower semiconductor circuit layer 22E are laminated to form a three-dimensional laminated structure. The image sensor 4 corresponds to the image sensor of the fourth aspect of the present invention, and the sensor circuit used therein corresponds to the sensor circuit of the second aspect of the present invention.

The overall configuration and operation of the image sensor 4 are the same as those shown in FIG. 19, and the description thereof will be omitted. Further, in the circuit configuration of Fig. 21, in the sensor circuit 3 of the thirteenth embodiment of Fig. 20, n selection transistors Tr _SEL1 to Tr _SELn (second gate elements) are added (there are no storage capacitors therein). The components are the same as those of the output transistor, and therefore, the same reference numerals are given to the same components as those of FIG. 20, and the description thereof is omitted. In the image sensor 4, the common node 13a of each pixel block 12a formed in the upper semiconductor circuit layer 21E and the gate of the amplifying transistor Tr _AMP formed in the lower semiconductor circuit layer 22E In the meantime, the buried wiring 23 is known to be electrically connected to each other. Therefore, in FIG. 21, the buried wiring 23 and the parasitic resistance R _o and the parasitic capacitances C _o1 and C _o2 generated by the buried wiring 23 are added. The buried wiring 23 is provided for each of the pixel blocks 12a (that is, n pixels 11a).

Next, the actual configuration of the image sensor 4 will be described.

As can be seen from FIG. 23, the image sensor 4 uses the buried wiring 23, the fine bump electrode 90, and the electrically insulating adhesive 91 to form the upper semiconductor circuit layer 21E and the lower semiconductor circuit layer 22E as mechanical and electrical. connection.

In the upper semiconductor circuit layer 21E, (k × m) pixel blocks 12a are formed, that is, there are (k × n) × m pixels 11a. Therefore, the upper semiconductor circuit layer 21E includes: (k×n)×m photodiodes (that is, photodiode groups PD ₁ to PD _n having (k×m) groups); (k×n) ) × m transfer gates (that is, transfer gate groups TG ₁ to TG _{n of} (k × m) groups; and (k × n) × m reset transistors (ie, have (k × m) ) The reset transistor group Tr _RST1 ~ Tr _RSTn ). In the upper semiconductor circuit layer 21E, (k × m) buried wirings 23 are further formed.

In the lower semiconductor circuit layer 22E, (k × m) amplification transistors Tr _{AMP are formed} ; and (k × n) × m selection transistors (that is, there are (k × m) groups of selected transistor groups Tr _SEL1 ~ Tr _SELn ).

In the upper semiconductor circuit layer 21E, the element isolation insulating film 41 is formed in a predetermined pattern on the surface region of the p-type single crystal germanium substrate 40, whereby (k × n) × m element regions are formed side by side. Array-like, as shown in the layout of Figure 23. The element areas thereof correspond to one pixel 11a, respectively.

Inside the element region corresponding to the pixel block 12a(i, j), n photodiodes PD ₁ to PD _n ; n transfer gates TG ₁ to TG _n ; and n reset transistors are formed Tr _RST1 ~Tr _RSTn . Taking the photodiode PD ₁ as an example, as shown in FIG. 23, it is composed of an n ⁺ -type region 42 formed on the p-type substrate 40 (that is, a p-n junction photodiode). Transfer gate TG _1, is formed out of a MOS transistor, comprising a gate 44, and through the gate 44 and 42 therebetween to be the sum of n ⁺ type regions 43 and the ^{n +} type region. The gate TG _{1 is} transferred, and since the n ⁺ -type region 42 of the photodiode PD ₁ is shared, a source and a drain region of the gate TG ₁ are electrically connected to the anode of the photodiode PD ₁ . The gate insulating film existing between the gate electrode 44 and the surface of the substrate 40 is omitted in FIG. The gate 44 is electrically connected to the corresponding read control line 32 through the wiring in the wiring structure 47 formed on the surface of the substrate 40.

The reset transistor Tr _RST1 is formed of a MOS transistor and includes a gate 49 and an n ⁺ -type region 43a interposed therebetween with the gate 49 and opposed to the n ⁺ -type region 42. The transistor Tr _{RST1 is} reset, and since the n ⁺ type region 42 of the photodiode PD ₁ is shared, a source and a drain region of the transistor Tr _RST1 are reset, and an anode is formed with the anode of the photodiode PD ₁ . connection. In the n ⁺ -type region 43a (source, drain region), the reset voltage V _RST is applied through a wiring (not shown).

The other photodiodes PD ₂ to PD _n , the transfer gates TG ₂ to TG _n , and the reset transistors Tr _RST2 to Tr _RSTn are respectively associated with the photodiode PD ₁ , the transfer gate TG ₁ , and the reset The transistor Tr _RST1 has the same configuration.

Inside the wiring structure 47, a wiring film 46 formed in a predetermined pattern is formed; and n n ⁺ -type regions 43 of the transfer gates TG ₁ to TG _n are electrically connected to the wiring film 46. n conductive contact plugs 45. The n transfer gates TG ₁ to TG _n in the pixel block 12a (i, j) are electrically connected to the wiring film 46 by the contact plugs 45, respectively, and thus the transfer gate TG ₁ ~ The TG _n is connected in parallel to the common node 13a.

The n ⁺ -type region 43 in the upper semiconductor circuit layer 21E has a function of an FD (floating diffusion) region, that is, a function system that is stored in the photodiode PD ₁ -PD by photoelectric conversion. The signal charge of _n is converted into a voltage signal.

In the substrate 40, (k × m) through holes through which the element isolation insulating film 41 and the substrate 40 are penetrated in the vertical direction (the direction orthogonal to the main surface of the substrate 40) are formed, and the formation position is located adjacent to the transfer. The overlap of the element isolation insulating films 41 of the n ⁺ -type region (source, drain region) 43 of the gates TG ₁ to TG _n . The portion of the through hole that is in contact with the substrate 40 is covered by the insulating film 24 over the entire inner wall thereof. The inside of the through hole (the inside of the insulating film 24 and the inside of the element isolation insulating film 41) is filled with a conductive material, and the buried wiring 23 is formed of the conductive material. The upper end of the buried wiring 23 is exposed by the surface of the substrate 40 (the element isolation insulating film 41), and is connected to the lower end of the conductive contact plug 23a formed inside the wiring structure 47. The upper end of the conductive contact plug 23a is connected to the wiring film 46 formed inside the wiring structure 47. Therefore, the buried wiring 23 is electrically connected to the corresponding wiring film 46 through the conductive contact plug 23a. As a result, the n ⁺ type regions (source, drain regions) 43 of the n transfer gates TG ₁ to TG _n of the pixel block 12a (i, j) are as shown in the circuit configuration of FIG. The corresponding buried wiring 23 has a common electrical connection. The lower end of each buried wiring 23 is exposed from the inner surface of the substrate 40, and is mechanically and electrically connected to the corresponding bump electrode 90 at its lower end.

In the lower semiconductor circuit layer 22E, the element isolation insulating film 61 is formed in a predetermined pattern on the surface region of the p-type single crystal germanium substrate 60, thereby forming an element region for a predetermined number of the amplification transistor Tr _AMP , and The component area for the selected number of selected transistors Tr _SEL1 ~ Tr _SELn . Here, description will be made with a configuration corresponding to one pixel block 12a(i, j).

The amplifying transistor Tr _AMP is composed of a MOS transistor including a gate 65 and a pair of n ⁺ -type regions (source, drain region) formed on both sides with the gate 65 interposed therebetween . The gate 65 is electrically connected to the corresponding bump electrode 90 through the conductive contact plug 71 formed in the wiring structure 74, the wiring film 72, the conductive contact plug 74a, and the wiring film 75. As a result, the gate of the amplifying transistor Tr _AMP is electrically connected to the common node 13a (pixel block 12a(i, j)) corresponding to the upper semiconductor circuit layer 21 through the corresponding buried wiring 23 (refer to Figure 21). Further, an n ⁺ -type region 64 (source and drain region) is electrically connected to the wiring film 73 formed inside the wiring structure 74 through the conductive contact plug 69 formed inside the wiring structure 74. The other n ⁺ -type region 64 (source, drain region) is supplied with a power supply voltage Vcc through a wiring (not shown).

The n selection transistors Tr _SEL1 to Tr _{SELn are} each composed of a MOS transistor, and include a gate 67 and a pair of n ⁺ -type regions (sources, respectively, formed on both sides of the gate 67 via the gate 67 Bungee area) 66. An n ⁺ -type region (source, drain region) 66 transmits the conductive contact plug 70 and the wiring film 73 formed inside the wiring structure 74 to an n ^{+ of the} corresponding amplifying transistor Tr _AMP The type region (source, drain region) 64 forms an electrical connection. The gate 67 is electrically connected to the output selection line 39 through the wiring formed inside the wiring structure 74. The gates 67 of the transistors Tr _SEL1 to Tr _SELn are selected to have their respective output selection signals φ _SEL1 to φ _SELn transmitted through the corresponding output selection lines 39.

As described above, in the image sensor 4 of the fourteenth embodiment shown in Fig. 23, the sensor circuit shown in Fig. 21 is used, which is a group of photodiodes PD ₁ to PD of (k × m) group. _n , (k × m) group of transfer gate groups TG ₁ ~ TG _n , (k × m) group of reset transistor groups Tr _RST1 ~ Tr _RSTn , and (k × m) buried wiring 23, formed in In the upper semiconductor circuit layer 21E, (k × m) amplification transistors Tr _AMP and (k × m) groups of selected transistor groups Tr _SEL1 to Tr _{SELn are} formed in the lower semiconductor circuit layer 22E, and the buried wiring is buried. The bump electrode 90 and the pixel block 12a (transfer gate group TG ₁ to TG _n ) in the upper semiconductor circuit layer 21E and the amplifying transistor Tr _AMP in the lower semiconductor circuit layer 22E are electrically connected to each other.

Further, the main surface (the surface of the wiring structure 74) above the lower semiconductor circuit layer 22E is formed by the bump electrode 90 and the adhesive 91, and the lower surface of the upper semiconductor circuit layer 21E (the inside of the substrate 40) Since the surface is electrically and mechanically connected, the two circuit layers 21E and 22E constitute a two-stage semiconductor laminated structure (three-dimensional structure).

Therefore, based on the same reason as in the case of the sensor circuit 3 of the thirteenth embodiment, the signal charges of all the pixels 11a can be substantially simultaneously stored (substantially simultaneously exposed), and conventional CMOS images do not occur. The image distortion of the sensor enables photography of objects to be moved at high speed.

Further, each of the pixels 11a of the pixel block 12a includes only one photodiode, one gate element (MOS transistor), and one reset transistor (MOS transistor), and thus, in one pixel A conventional CMOS image sensor that includes three or four MOS transistors in addition to the photodiode can achieve a higher pixel aperture ratio (for example, up to about 60%), and the size of the pixel 11a itself can be reduced.

Furthermore, since the CMOS image sensor has a higher pixel aperture ratio than the conventional CMOS image sensor, the total area of the light receiving region (the opening portion of each photodiode) on the surface of the upper semiconductor 21E is relative to the photographing region. The ratio of the total area can be increased.

(Fifteenth Embodiment)

Fig. 22 is a circuit diagram showing the configuration of the main circuit of the address specifying image sensor 4A according to the fifteenth embodiment of the present invention. Fig. 24 is a cross-sectional view showing the principal part of the actual structure of the image sensor 4A. The image sensor 4A is used in each of the output sides of the n selection transistors Tr _SEL1 to Tr _SELn in the sensor circuit (see FIG. 21) used in the image sensor circuit 4 of the above-described fourteenth embodiment. _Further , a three-dimensional laminated structure in which the storage capacitor elements C _ST1 to C _STn and the output transistors Tr _OUT1 to Tr _{OUTn are} formed and the upper layer semiconductor circuit layer 21E and the lower semiconductor circuit layer 22E' are stacked is formed. The image sensor 4A corresponds to the image sensor of the fourth aspect of the present invention.

As can be seen from FIG. 24, the image sensor 4A uses the buried wiring 23, the fine bump electrode 90, and the electrically insulating adhesive 91 to form the upper semiconductor circuit layer 21E and the lower semiconductor circuit layer 22E' mechanically and electrically. connection.

The upper semiconductor circuit layer 21E has the same configuration as that of the image sensor 4 (see FIG. 23) of the above-described fourteenth embodiment. Therefore, the same reference numerals are given to the fourteenth embodiment, and the detailed description thereof will be omitted.

The lower semiconductor circuit layer 22E' has substantially the same configuration as the lower semiconductor circuit layer 22E of the image sensor 4 of the above-described fourteenth embodiment, but the only difference is that the storage capacitive element C _ST1 is additionally formed. C _STn , and output transistor Tr _OUT1 ~ Tr _OUTn . That is, in the lower semiconductor circuit layer 22E', in addition to (k × m) amplification transistors Tr _AMP and (k × m) groups of selected transistor groups Tr _SEL1 to Tr _SELn , (k × m) The storage capacitor group C _ST1 ~ C _{STn of the} group and the output transistor group Tr _OUT1 ~ Tr _{OUTn of the} (k × m) group.

As shown in FIG. 24, in the lower semiconductor circuit layer 22E', the element isolation insulating film 61 is formed in a predetermined pattern on the surface region of the substrate 60, thereby forming an element region for a predetermined number of the amplification transistor Tr _AMP , A predetermined number of selected transistor Tr _SEL1 ~ Tr _SELn , storage capacitive elements C _ST1 ~ C _STn , and component regions for output transistors Tr _OUT1 ~ Tr _OUTn .

The configuration of the amplifying transistor Tr _{AMP is} the same as that of the image sensor 4 (see FIG. 23) of the above-described fourteenth embodiment, and is composed of an MOS transistor, and includes a gate 65 and a gate 65 interposed therebetween. A pair of n ⁺ -type regions (source, drain regions) 64 are formed on both sides therebetween. The electrical connection of the amplifying transistor Tr _AMP is also the same as that of the image sensor 4 (see Fig. 21) of the fourteenth embodiment.

Each of the n selection transistors Tr _SEL1 to Tr _SELn has the same configuration as that of the image sensor 4 of the above-described fourteenth embodiment, and is composed of a MOS transistor, and includes: a gate 67; and The gate 67 has a pair of n ⁺ -type regions (source, drain regions) 66 formed on both sides therebetween. Further, the storage capacitive elements C _ST1 to C _STn and the output transistors Tr _OUT1 to Tr _OUTn are connected to the MOS transistor in the circuit configuration shown in FIG.

For example, in the case of selecting the transistor Tr _SEL1 , an n ⁺ -type region (source, drain region) 66 is transmitted through the conductive contact plugs 70, 69 and the wiring film 73 formed inside the wiring structure 74, An electrical connection is formed with an n ⁺ -type region (source, drain region) 64 of the corresponding amplifying transistor Tr _AMP . The gate 67 is electrically connected to the output selection line 39 through the wiring formed inside the wiring structure 74, and is applied by the output selection signal _φSEL1 . Another n ⁺ -type region (source, drain region) 66 of the transistor Tr _SEL1 is selected, together with the n ⁺ -type region 66a on the opposite side of the gate 67a, constituting the storage capacitive element C _ST1 Functional MOS capacitor. The n ⁺ -type region 66a, together with the gate 67b, and the n ⁺ -type region 66a which is located on the opposite side of the n ⁺ -type region 66a with respect to the gate 67b, constitute a MOS functioning as an output transistor Tr _OUT1 Transistor. The gate 67a is connected to a terminal of a predetermined potential (usually a ground potential). The gate 67b is electrically connected to the output control line 39a via a wiring (not shown), and has an output of the output control signal φ _OUT1 .

As shown, in one element region, a selection transistor Tr _SEL1 , a storage capacitive element C _ST1 , and an output transistor Tr _{OUT1 are formed} . This point is also the same for the other selection transistors Tr _SEL2 to Tr _SELn .

As described above, in the image sensor 4 of the fifteenth embodiment shown in Fig. 24, the sensor circuit shown in Fig. 22 is used, which is a group of photodiodes PD ₁ to PD of (k × m) groups. _n , (k × m) group of transfer gate groups TG ₁ ~ TG _n , (k × m) group of reset transistor groups Tr _RST1 ~ Tr _RSTn , and (k × m) buried wiring 23, formed in In the upper semiconductor circuit layer 21E, the (k×m) amplification transistor Tr _AMP , the (k×m) group of selected transistor groups Tr _SEL1 to Tr _SELn , and the (k×m) group of storage capacitor elements are grouped. The output transistor groups Tr _OUT1 to Tr _{OUTn of the} C _ST1 to C _STn and (k×m) groups are formed in the lower semiconductor circuit layer 22E′, and pass through the buried wiring 23 and the bump electrode 90 to make the upper semiconductor circuit layer 21E. The transfer gate groups TG ₁ to TG _n and the amplifying transistors Tr _AMP in the lower semiconductor circuit layer 22E' are electrically connected to each other.

Further, the main surface (the surface of the wiring structure 74) above the lower semiconductor circuit layer 22E' is formed by the bump electrode 90 and the adhesive 91, and the lower surface of the upper semiconductor circuit layer 21E (the substrate 40) Since the inner surface is electrically and mechanically connected, the two circuit layers 21E and 22E' constitute a two-stage semiconductor laminated structure (three-dimensional structure).

Therefore, based on the same reason as in the case of the sensor circuit 3 of the thirteenth embodiment, the signal charges of all the pixels 11a can be substantially simultaneously stored (substantially simultaneously exposed), and conventional CMOS images do not occur. The image distortion of the sensor enables photography of objects to be moved at high speed.

Further, each of the pixels 11a of the pixel block 12a includes only one photodiode, one gate element (MOS transistor), and one reset transistor (MOS transistor), and thus, in one pixel A conventional CMOS image sensor that includes three or four MOS transistors in addition to the photodiode can achieve a higher pixel aperture ratio (for example, up to about 60%), and the size of the pixel 11a itself can be reduced.

Furthermore, since the CMOS image sensor has a higher pixel aperture ratio than the conventional CMOS image sensor, the total area of the light receiving region (the opening portion of each photodiode) on the surface of the upper semiconductor 21E is relative to the photographing region. The ratio of the total area can be increased.

Furthermore, by controlling the output transistors Tr _OUT1 ~ Tr _OUTn by outputting the control signals φ _OUT1 ~ φ _OUTn , the signal is outputted to the signal line 37, and the gate TG ₁ is transmitted in the pixel block 12a. Since the time at which the TG _n and the selected transistor groups Tr _SEL1 to Tr _SELn are opened and closed can be shifted from each other, it is possible to perform high-speed photography as compared with the image sensor of the fourteenth embodiment.

(Sixth embodiment)

The address specifying type image sensors 2 to 2G of the fifth to twelfth embodiments and the address specifying type image sensors 4 and 4A of the fourteenth and fifteenth embodiments are both upper and lower positions. The semiconductor circuit layer is laminated to have a two-layer structure. However, the image sensor of the present invention is not limited to a two-layer structure. A semiconductor circuit layer of three or more layers may be laminated. An illustrative example is given below, which is composed of three layers of semiconductor circuits of upper, middle and lower layers.

Fig. 28 is a circuit diagram showing the configuration of a main part of the address specifying image sensor 2H according to the sixteenth embodiment of the present invention. Fig. 29 is a cross-sectional view showing the essential part of the actual image sensor 2H. In the image sensor 2H, the sensor circuit 1B (see FIG. 4) of the third embodiment is used, and the image of the three-dimensional laminated structure of the second embodiment of the fifth embodiment of the sensor circuit 1B is used. The sensor 2 (see FIGS. 6 and 8) has substantially the same configuration, but differs in that the upper semiconductor circuit layer 21F, the intermediate semiconductor circuit layer 22Fa, and the lower semiconductor circuit layer 22Fb are provided. A three-dimensional laminated structure composed of three layers. The image sensor 2H corresponds to the image sensor of the second aspect of the present invention.

The configuration of the upper semiconductor circuit layer 21F is the same as that described above for the upper semiconductor circuit layer 21 (see FIG. 8) of the image sensor 2 of the fifth embodiment.

The (k×m) group of reset transistors Tr _RST1 to Tr _RSTn and (k×m) amplification transistors Tr _AMP formed in the lower semiconductor circuit layer 22 in the image sensor 2 are formed at the middle position. Semiconductor circuit layer 22Fa. Each of the pixel blocks 12 in the upper semiconductor circuit layer 21F and the reset transistors Tr _RST1 to Tr _RSTn and the amplifying transistor Tr _AMP corresponding to the intermediate semiconductor circuit layer 22F are transmitted through the upper semiconductor circuit layer 21F. Corresponding buried wirings 23 are formed to form electrical connections with each other.

The (K × M) group of selection transistors Tr _SEL1 to Tr _SELn formed in the lower semiconductor circuit layer 22 in the image sensor 2 are formed in the lower semiconductor circuit layer 22Fb. Each of the amplifying transistors Tr _AMP in the intermediate semiconductor circuit layer 22Fa is formed through a corresponding transistor Tr _SEL1 to Tr _SELn corresponding to the lower semiconductor circuit layer 22Fb through the intermediate semiconductor circuit layer 22Fa. The buried wirings 23' are electrically connected to each other.

Next, the actual configuration of the image sensor 2H will be described with reference to FIG.

The configuration of the upper semiconductor circuit layer 21F is the same as that of the upper semiconductor circuit layer 21 (see FIG. 8) of the image sensor 2 of the fifth embodiment, and therefore the same reference numerals are given to the corresponding elements, and the description thereof is omitted. .

The intermediate semiconductor circuit layer 22Fa is similar to the configuration of the lower semiconductor circuit layer 22 of the image sensor 2 (refer to FIG. 8), and the element isolation insulating film 61 is formed in a predetermined pattern in the surface region of the p-type single crystal germanium substrate 60. Thereby, a predetermined number of element regions for resetting the transistor Tr _RST and a predetermined number of element regions for the amplifying transistor Tr _{AMP are} formed.

As shown in FIG. 29, the reset transistor Tr _RST is composed of a MOS transistor, and includes a gate 63 and a pair of n ⁺ -type regions (sources) formed on both sides with the gate 63 interposed therebetween Extreme and bungee area) 62. The gate 63 is electrically connected to the corresponding reset line 31 through the wiring formed in the wiring structure 74 on the surface of the substrate 60. An n ⁺ -type region 62 (source, drain region) is transmitted through the conductive contact plug 68 formed in the wiring structure 74, the wiring film 72, the conductive contact plug 74a, and the wiring film 75. The bump electrodes 90 form an electrical connection. As a result, one of the source and drain regions of the reset transistor Tr _RST is transmitted through the corresponding buried wiring 23 to the common node 13 corresponding to the upper semiconductor circuit layer 21F (pixel block 12 (i, j) )) Form an electrical connection (see Figure 6). The other n ⁺ -type region 62 (source, drain region) is applied with a reset voltage V _RST through a wiring (not shown).

The amplifying transistor Tr _AMP is composed of an MOS transistor, and includes: a gate 65; and a pair of n ⁺ type regions (source, drain region) formed on both sides with the gate 65 interposed therebetween 64. The gate 65 is electrically connected to the corresponding bump electrode 90 through the conductive contact plug 71 formed in the wiring structure 74, the wiring film 72, the conductive contact plug 74a, and the wiring film 75. As a result, the gate of the amplifying transistor Tr _AMP is electrically connected to the common node 13 (pixel block 12 (i, j)) corresponding to the upper semiconductor circuit layer 21 through the corresponding buried wiring 23 ( Refer to Figure 6). Further, an n ⁺ -type region 64 (source and drain region) is formed in the lower position through the conductive contact plug 69 formed in the wiring structure 74, the wiring film 73, and the conductive contact plug 23a. The conductive plug 23' of the semiconductor circuit layer 22FB forms an electrical connection. In another n ⁺ type region 64 (source, drain region), the supply voltage Vcc is applied through a wiring (not shown).

The lower semiconductor circuit layer 22Fb is formed by forming the element isolation insulating film 61' in a predetermined pattern in the surface region of the p-type single crystal germanium substrate 60', thereby forming an element region for a predetermined number of the selection transistors Tr _SEL1 to Tr _SELn . The selection transistors Tr _SEL1 to Tr _{SELn are} each composed of a MOS transistor, and include a gate 67 and a pair of n ⁺ -type regions (source and drain regions) formed on both sides with the gate 67 interposed therebetween ) 66. An n ⁺ -type region (source, drain region) 66 is a conductive contact plug 70 formed through the wiring structure 74', a wiring film 72a, a conductive contact plug 74a', and a wiring film 75'. And forming an electrical connection with the corresponding bump electrode 90'. Therefore, the n ⁺ -type region (source, drain region) 66 passes through the bump electrode 90' and the conductive plug 23' in the intermediate semiconductor circuit layer 22Fa, and the corresponding amplifying transistor Tr _AMP An n ⁺ -type region (source, drain region) 64 forms an electrical connection. Another n ⁺ type region (source, drain region) 66 is connected to the corresponding output terminal of the image sensor 2H. The gate 67 is electrically connected to the output selection line 39 through the wiring formed inside the wiring structure 74'. The gates 67 of the selected transistors Tr _SEL1 to Tr _SELn are each transmitted through a corresponding output select line 39 with a predetermined output selection signal φ _SEL1 φ φ _SELn applied.

The image sensor 2H of the sixteenth embodiment has the actual structure described above, but the operation and effects thereof are the same as those of the image sensor 2 (see FIGS. 6 and 8) of the fifth embodiment. Therefore, the description thereof will be omitted.

(Configuration example of storage capacitor element)

25 to 27 are configuration examples of the storage capacitor element used in the above embodiment. The storage capacitor element C _ST1 between the selection transistor Tr _SEL1 and the output transistor Tr _OUT1 is provided as shown in the figure.

The storage capacitive element C _{ST1 of} FIG. 25( a ) is provided inside the p-type germanium substrate 60 and has an n ⁺ region 66 (which is used to form the selective transistor Tr _SEL1 ) that connects the capacitive element C _ST1 side, and The n ⁺ region 66b formed by the n ⁺ region 66a on the side of the capacitive element C _ST1 (which is used to form the output transistor Tr _OUT1 ). If a reverse bias is applied between the substrate 60 and the n ⁺ region 66b, a p-n junction capacitance can be generated, and thus it can be used as the storage capacitive element C _ST1 .

FIG storage 25 (b) of the capacitive element C _ST1, based on selection transistor Tr _SEL1 is formed of n ⁺ region 66 is formed with the output transistor Tr _OUT1 between the n ⁺ regions 66a, through a gate having a gate insulating film (not The gate 67a is formed above the p-type germanium substrate 60. When the power supply voltage Vcc is applied to the gate 67a, an n-type or n ⁺ -type inversion layer L can be generated in the surface region of the substrate 60, and thus it can be used as the storage capacitive element _CST1 . This is a typical MOS capacitor and is used by the users of the above embodiments.

FIG 26 (a) capacitive storage element C _ST1, based on selection transistor Tr _SEL1 is formed an n ⁺ region 66 is formed with the output transistor Tr _OUT1 between the n ⁺ regions 66a, through a gate having a gate insulating film (not The gate 67a is formed above the p-type germanium substrate 60. In the inside of the substrate 60, the n ⁺ region 66 on the side of the capacitive element C _{ST1 for} forming the selection transistor Tr _SEL1 and the n ⁺ region 66a on the side of the capacitive element C _{ST1 for} forming the output transistor Tr _OUT1 are removed. The end portion on the capacitive element C _ST1 side of the gate 67 for forming the selection transistor Tr _SEL1 is placed above the gate 67a via an insulating film (not shown). Similarly, the end portion of the gate 67b of the output transistor Tr _OUT1 on the side of the capacitive element C _ST1 is placed on the gate 67a through the insulating film (not shown) on the opposite side of the gate 67. Above.

When the power supply voltage Vcc is applied to the gate electrode 67a, an inversion layer of an n-type or n ⁺ type is formed in the surface region of the substrate 60 as in the case of FIG. 25(b), so that it can be used as the storage capacitive element C. _ST1 is used. At this time, the end portion of the inversion layer on the gate 67 side functions as an n-type region or an n ⁺ -type region for selecting the transistor Tr _SEL1 . Further, the end portion of the inversion layer on the gate 67b side functions as an n-type region or an n ⁺ -type region for outputting the transistor Tr _OUT1 . This is a modification of the MOS capacitor.

The storage capacitive element C _{ST1 of} FIG. 26( b ) has a transmission gate insulating film (not shown) between the gate 67 of the selection transistor Tr _SEL1 and the gate 67b of the output transistor Tr _OUT1 . A gate 67a is formed above the ruthenium substrate 60. Inside the substrate 60, the n ⁺ region 66 for forming the capacitive element C _ST1 side of the selection transistor Tr _SEL1 and the n ⁺ region 66a for forming the output transistor Tr _OUT1 on the capacitive element C _ST1 side have been removed. One end of the gate 67a is placed on the gate 67 for forming the selective transistor Tr _SEL1 through an insulating film (not shown), and the other end is transmitted through an insulating film (not shown). It is carried over the gate 67b for forming the output transistor Tr _OUT1 .

When the power supply voltage Vcc is applied to the gate electrode 67a, an inversion layer of an n-type or n ⁺ type is formed in the surface region of the substrate 60 as in the case of FIG. 25(b), so that it can be used as the storage capacitive element C. _ST1 is used. At this time, the end portion of the inversion layer on the gate 67 side functions as an n-type region or an n ⁺ -type region for selecting the transistor Tr _SEL1 . Further, the end portion of the inversion layer on the gate 67b side functions as an n-type region or an n ⁺ -type region for outputting the transistor Tr _OUT1 . This is also a modification of the MOS capacitor.

The storage capacitive element C _{ST1 of} FIG. 27 is inside the substrate 60, and the n ⁺ region 66 on the side of the capacitive element C _{ST1 for} forming the selection transistor Tr _{SEL1 and} the capacitor for forming the output transistor Tr _{OUT1 are removed} . The n ⁺ region 66a on the side of the element C _ST1 . Instead, an n ⁺ -type region 66b is formed between the gate 67 of the transistor Tr _SEL1 and the gate 67b of the output transistor Tr _OUT1 . The gate 67 of the transistor Tr _SEL1 is selected to be disposed between the n ⁺ type region 66 and the n ⁺ type region 66b; the gate 67b of the output transistor Tr _OUT1 is disposed in the n ⁺ type region 66a and the n ⁺ type region Between 66b.

On the gate electrodes 67 and 67b, a capacitor element 67aa having a T-shaped cross-sectional structure is formed through a gate insulating film (not shown). The capacitor element 67aa has a C _ST1 function of the capacitor element, and includes a substantially T-shaped lower electrode 67aa1 in cross section, an insulating film 67aa2 formed over the lower electrode 67aa1, and a pattern formed above the insulating film 67aa2. The upper electrode 67aa3. The lower end of the lower electrode 67aa1 is in contact with the surface of the n ⁺ type region 66b by extending downward between the gates 67 and 67b. The upper electrode 67aa3 has an appropriate gate voltage Vc (0 to Vcc) applied.

As shown, the storage capacitive element C _ST1 can have various configurations.

(Modification)

The above-described first to sixteenth embodiments are examples of the present invention. Therefore, the present invention is not limited to the embodiments, and various modifications can be made without departing from the spirit of the invention. For example, in most of the above embodiments, the upper semiconductor circuit layer and the lower semiconductor circuit layer are electrically connected to each other using the bump electrode and the buried wiring, or the upper semiconductor circuit layer and the intermediate semiconductor circuit layer are formed. The bit semiconductor circuit layer and the lower semiconductor circuit layer are electrically connected to each other, but the present invention is not limited thereto. As described in the twelfth embodiment, the bump electrode and the wiring film can be used to electrically connect the upper semiconductor circuit layer and the lower semiconductor circuit layer to each other. The point is that any form can be used as long as it is a structure in which the upper semiconductor circuit layer and the lower semiconductor circuit layer can be electrically connected to each other.

In addition, most of the above-described embodiments are a two-layer laminated structure including a higher semiconductor circuit layer and a lower semiconductor circuit layer, and the peripheral circuits of the pixel array (vertical scanning circuit 34, horizontal scanning circuit 35, etc.) It is formed on the upper semiconductor circuit layer or the lower semiconductor circuit layer, but the present invention is not limited thereto. The peripheral circuit of the pixel array may be formed inside other semiconductor circuit layers, and then the semiconductor circuit layer is connected to the inner surface of the lower semiconductor circuit layer. This point is also applicable to a laminated structure of three layers composed of an upper semiconductor circuit layer, a neutral semiconductor circuit layer, and a lower semiconductor circuit layer, or a laminated structure of four or more layers.

In the above embodiment, each of the pixel blocks having a plurality of pixels is provided with one buried wiring, but the present invention is not limited thereto. Of course, one buried wiring can be provided for one pixel. For example, this can be achieved by setting the diameter (or one side) of each buried wiring to about 1 to 0.5 μm.

The upper semiconductor circuit layer and the lower semiconductor circuit layer may each be formed of a single semiconductor wafer or may be formed of a plurality of semiconductor wafers. In other words, the circuit elements to be formed in the semiconductor circuit layer may be formed entirely inside the single semiconductor wafer, or may be formed separately in the inside of the plurality of semiconductor wafers.

1, 1A, 1B, 1C. . . Sensor circuit

2, 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H. . . Address-specific image sensor

3. . . Sensor circuit

4, 4A. . . Address-specific image sensor

11, 11a. . . Pixel

12, 12a. . . Pixel block

13, 13a. . . Common node

14,15. . . node

21, 21A, 21B, 21C, 21D, 21E, 21F. . . Upper semiconductor circuit layer

22Fa. . . Median semiconductor circuit layer

22, 22', 22A, 22A', 22B, 22B', 22C, 22C', 22D', 22E, 22E', 22Fb. . . Lower semiconductor circuit layer

23, 23'. . . Buried wiring

23a, 23a'. . . Conductive contact plug

24, 24'. . . Insulating film

31. . . Reset line

32. . . Read control line

33. . . Horizontal signal line

34. . . Vertical scanning circuit

35. . . Horizontal scanning circuit

36. . . CDS circuit

37. . . Signal line

38. . . Row selection signal

39. . . Output selection line

39a. . . Output control line

39a. . . Output control line

40. . . P-type germanium substrate

41. . . Component separation insulating film

42, 43. . . n ⁺ type region

44. . . Gate

45. . . Conductive contact plug

46. . . Wiring film

47. . . Wiring member

48. . . n ⁺ type region

49. . . Gate

50. . . Conductive contact plug

52. . . n ⁺ type region

53. . . Gate

54, 55. . . Conductive contact plug

56, 57. . . Wiring film

58. . . Conductive contact plug

59. . . Wiring film

60, 60'. . . P-type germanium substrate

61, 61'. . . Component separation insulating film

62, 64, 66, 66a, 66b. . . n ⁺ type region

63, 65, 67, 67a, 67b. . . Gate

67aa. . . Capacitive component

68, 69, 70, 71. . . Conductive contact plug

72, 72a, 73. . . Wiring film

74, 74'. . . Wiring structure

74a, 74a'. . . Conductive contact plug

75, 75'. . . Wiring film

76. . . n ⁺ area

77. . . Gate

78, 80, 82. . . Conductive contact plug

79, 81, 83. . . Wiring film

90, 90'. . . Bump electrode

91, 91'. . . Electrical insulating adhesive

PD ₁ ~PD _n . . . Photodiode

TG ₁ ~ TG _n . . . Transfer gate

Tr _RST , Tr _RST1 ~ Tr _RSTn . . . Reset transistor

Tr _AMP . . . Amplifying the transistor

Tr _SEL1 ~ Tr _SELn . . . Select transistor

R. . . Resistor

C _ST , C _ST1 ~ C _STn . . . Storage capacitor

R _o . . . Parasitic resistance

C _sn , C _o1 , C _o2 . . . Parasitic capacitance

Fig. 1 is a functional block diagram showing the overall configuration of an address specifying image sensor using a sensor circuit according to a first embodiment of the present invention.

2 is a circuit diagram showing the configuration of a main part of the sensor circuit according to the first embodiment of the present invention, and shows a circuit configuration of two pixel blocks to which the jth row belongs.

Fig. 3 is a circuit diagram showing the configuration of a main part of a sensor circuit according to a second embodiment of the present invention (the same as Fig. 2).

Fig. 4 is a block diagram showing the configuration of a main part of a sensor circuit according to a third embodiment of the present invention (the same as Fig. 2).

Fig. 5 is a circuit diagram showing the configuration of a main part of a sensor circuit according to a fourth embodiment of the present invention (the same as Fig. 2).

Fig. 6 is a circuit diagram showing a circuit configuration of a main part of an address specifying image sensor according to a fifth embodiment of the present invention.

Fig. 7 is a circuit diagram showing a circuit configuration of a main part of an address specifying image sensor according to a sixth embodiment of the present invention.

Fig. 8 is a cross-sectional view of an essential part of an actual structure of an address specifying image sensor according to a fifth embodiment of the present invention.

Fig. 9 is a cross-sectional view of an essential part of an actual structure of an address specifying image sensor according to a sixth embodiment of the present invention.

Fig. 10 is a circuit diagram showing a circuit configuration of a main part of an address specifying image sensor according to a seventh embodiment of the present invention.

Figure 11 is a cross-sectional view of an essential part of an actual structure of an address specifying image sensor according to a seventh embodiment of the present invention.

Fig. 12 is a cross-sectional view of an essential part of an actual structure of an address specifying image sensor according to an eighth embodiment of the present invention.

Fig. 13 is a circuit diagram showing a circuit configuration of a main part of an address specifying image sensor according to a ninth embodiment of the present invention.

Figure 14 is a cross-sectional view of an essential part of an actual structure of an address specifying image sensor according to a ninth embodiment of the present invention.

Fig. 15 is a cross-sectional view of an essential part of an actual structure of an address specifying type image sensor according to a tenth embodiment of the present invention.

Fig. 16 is a circuit diagram showing a circuit configuration of a main part of an address specifying image sensor according to an eleventh embodiment of the present invention.

Figure 17 is a cross-sectional view of an essential part of an actual structure of an address specifying image sensor according to an eleventh embodiment of the present invention.

Fig. 18 is a cross-sectional view of an essential part of an actual structure of an address specifying image sensor according to a twelfth embodiment of the present invention.

Fig. 19 is a functional block diagram showing the overall configuration of an address specifying image sensor using the sensor circuit of the thirteenth embodiment of the present invention.

Fig. 20 is a circuit diagram showing the configuration of a main part of a sensor circuit according to a thirteenth embodiment of the present invention, showing a circuit configuration of two pixel blocks to which the jth row belongs.

Fig. 21 is a circuit diagram showing the circuit configuration of a main part of the address specifying image sensor of the fourteenth embodiment of the present invention.

Fig. 22 is a circuit diagram showing the circuit configuration of a main part of the address specifying image sensor of the fifteenth embodiment of the present invention.

Fig. 23 is a cross-sectional view of an essential part of an actual structure of an address specifying image sensor according to a fourteenth embodiment of the present invention.

Figure 24 is a cross-sectional view of an essential part of an actual structure of an address specifying image sensor of a fifteenth embodiment of the present invention.

25(a) and (b) are cross-sectional views of essential parts of a configuration of a storage capacitor element used in the address specifying image sensor of the present invention.

26 (a) and (b) are cross-sectional views of essential parts of another configuration example of the storage capacitor element used in the address specifying image sensor of the present invention.

Fig. 27 is a cross-sectional view of an essential part of another configuration example of a storage capacitor element used in the address specifying image sensor of the present invention.

Figure 28 is a circuit diagram showing the configuration of a main part of an address specifying image sensor of a sixteenth embodiment of the present invention.

Figure 29 is a cross-sectional view of an essential part of an actual structure of an address specifying image sensor of a sixteenth embodiment of the present invention.

Figure 30 (a) is a conceptual diagram of a general circuit configuration of a conventional CMOS (address-specific) image sensor; (b) is a conceptual diagram of a storage period of a signal charge of the image sensor.

Fig. 31 is a circuit diagram showing the configuration of a main circuit of a conventional CMOS (address-specified type) image sensor.

32 is a cross-sectional view of an essential part of a practical configuration of a conventional CMOS (address-specified type) image sensor.

Fig. 33(a) is a conceptual diagram showing a general circuit configuration of a conventional CCD (charge transfer type) image sensor; (b) is a conceptual diagram of a storage period of a signal charge of the image sensor.

Fig. 34 (a) is a conceptual diagram of an image obtained by photographing a blade rotating at a high speed by a CCD (charge transfer type) image sensor; (b) a conventional CMOS (address specifying type) image sense A conceptual diagram of the image obtained by the detector to capture the same leaf.

11. . . Pixel

12. . . Pixel block

1B. . . Sensor circuit

13. . . Common node

14. . . node

31. . . Reset line

PD ₁ ~PD _n . . . Photodiode

TG ₁ ~ TG _n . . . Transfer gate

Tr _SEL1 ~ Tr _SELn . . . Select transistor

Tr _AMP . . . Amplifying the transistor

C _sn . . . Parasitic capacitance

Tr _RST . . . Reset transistor

R. . . resistance

Claims (10)

An address-specific image sensor having a three-dimensional layered structure, having a plurality of pixels arranged in an array, and selecting each pixel by address designation, wherein: having a plurality of pixel blocks, a plurality of the pixels are connected in parallel to the common node by a predetermined number; a reset transistor is connected to a common node of each of the pixel blocks to reset a plurality of the pixels in the pixel block; and the amplifying transistor is connected to a plurality of common nodes of the pixel block for amplifying signals sent by a plurality of the pixels in the pixel block; in each of the pixel blocks, each pixel comprises: a photoelectric conversion element corresponding to the illumination light Generating a signal charge; and providing a first gate element between the photoelectric conversion element and a common node of the pixel block; and forming at least the photoelectric conversion element in the first semiconductor circuit layer constituting the three-dimensional laminated structure; The first gate element, the reset transistor, and the amplifying transistor are formed in the second or third semiconductor circuit layer constituting the three-dimensional laminated structure; In addition to the plurality of photoelectric conversion elements, a plurality of the first gate elements are formed in the first semiconductor circuit layer, and a plurality of the amplifying transistors and a plurality of reset transistors are formed in the second or the second 3 later in the semiconductor circuit layer. An address-specific image sensor having a three-dimensional layered structure, having a plurality of pixels arranged in an array, and selecting each by address designation a pixel, comprising: a plurality of pixel blocks, wherein the plurality of pixels are connected in parallel to the common node by a predetermined number; and the reset transistor is connected to a common node of each of the pixel blocks to reset the pixel a plurality of the pixels in the block; and an amplifying transistor connected to each of the plurality of common nodes of the pixel block for amplifying the signal sent by the plurality of pixels in the pixel block; In the block, each pixel includes: a photoelectric conversion element that generates a signal charge corresponding to the illumination light; and a first gate element disposed between the photoelectric conversion element and a common node of the pixel block; at least the photoelectric conversion element Formed in the first semiconductor circuit layer constituting the three-dimensional laminated structure, the first gate element, the reset transistor, and the amplifying transistor are formed after the second or third layer constituting the three-dimensional laminated structure In the semiconductor circuit layer, in addition to the plurality of the photoelectric conversion elements, a plurality of the first gate elements and a plurality of reset transistors are formed in the first semiconductor circuit layer, and A plurality of the amplifying transistors are formed in the second or third semiconductor circuit layer. An address-specific image sensor having a three-dimensional layered structure, having a plurality of pixels arranged in an array, and selecting each pixel by address designation, wherein: having a plurality of pixel blocks, a plurality of the pixels are connected in parallel to the common node by a predetermined number; Resetting the transistor, connecting to a common node of each of the pixel blocks, for resetting a plurality of the pixels in the pixel block; and amplifying the transistor, connecting to a plurality of common nodes of the pixel block, Amplifying a signal sent by a plurality of the pixels in the pixel block; in each of the pixel blocks, each pixel includes: a photoelectric conversion element that generates a signal charge corresponding to the illumination light; and a first gate element, the setting a path between the photoelectric conversion element and a common node of the pixel block; at least the photoelectric conversion element is formed in the first semiconductor circuit layer constituting the three-dimensional laminated structure, and the first gate element and the reset power are a crystal and the amplifying transistor are formed in the second or third semiconductor circuit layer constituting the three-dimensional laminated structure; the amplifying transistor has an equal number of pixels in the pixel block corresponding to the amplifying transistor An output terminal, and a second gate element (selective transistor) is respectively connected to the output terminals; in addition to the plurality of the photoelectric conversion elements, a plurality of the first gate elements and a plurality of the plurality of the first gate elements a reset transistor, and a plurality of the amplifying transistors are formed in the first semiconductor circuit layer, and a plurality of the second gate elements (selective transistors) are formed on the second or third semiconductor circuit layer in. An address-specific image sensor having a three-dimensional layered structure, having a plurality of pixels arranged in an array, and selecting each pixel by address designation, wherein: having a plurality of pixel blocks, a plurality of the pixels are connected in parallel to the common node by a predetermined number; Resetting the transistor, connecting to a common node of each of the pixel blocks, for resetting a plurality of the pixels in the pixel block; and amplifying the transistor, connecting to a plurality of common nodes of the pixel block, Amplifying a signal sent by a plurality of the pixels in the pixel block; in each of the pixel blocks, each pixel includes: a photoelectric conversion element that generates a signal charge corresponding to the illumination light; and a first gate element, the setting a path between the photoelectric conversion element and a common node of the pixel block; at least the photoelectric conversion element is formed in the first semiconductor circuit layer constituting the three-dimensional laminated structure, and the first gate element and the reset power are The crystal and the amplifying transistor are formed in the second or third semiconductor circuit layer constituting the three-dimensional laminated structure; and only a plurality of the photoelectric conversion elements are formed in the first semiconductor circuit layer, and the plurality of The first gate element, the plurality of reset transistors, and the plurality of the amplifying transistors are formed in the second or third semiconductor circuit layer. An address-specific image sensor according to any one of claims 1 to 4, wherein all of the pixels are used for all of the pixels before all of the pixels are generated and stored by the resetting transistor. In the pixel block, the signal corresponding to the signal charge stored in the pixel is read by the corresponding common node in time series, and then transmitted to the corresponding amplifying transistor. An address-specific image sensor having a three-dimensional layered structure, having a plurality of pixels arranged in an array, and selecting each by address designation a pixel, comprising: a plurality of pixel blocks, wherein a plurality of the pixels are connected in parallel to a common node by a predetermined number; and an amplifying transistor connected to each of the plurality of common nodes of the pixel block for Amplifying a signal sent by a plurality of the pixels in the pixel block; in each of the pixel blocks, each of the pixels includes: a photoelectric conversion element that generates a signal charge corresponding to the illumination light; and the first gate element is disposed at a path between the photoelectric conversion element and a common node of the pixel block; and a reset transistor connected to a connection point of the photoelectric conversion element and the first gate element to perform resetting of the pixel; at least the photoelectric conversion The element is formed in the first semiconductor circuit layer constituting the three-dimensional laminated structure, and the first gate element, the reset transistor, and the amplifying transistor are formed in the second or the third layer constituting the three-dimensional laminated structure. In the semiconductor circuit layer of the third embodiment, in addition to the plurality of the photoelectric conversion elements, a plurality of the first gate elements are formed in the first semiconductor circuit layer, and the plurality of the plurality of the first gate elements are placed in the first semiconductor circuit layer. And a plurality of transistors formed on the reset transistors of the subsequent second circuit or the third semiconductor layer. An address-specific image sensor having a three-dimensional layered structure, having a plurality of pixels arranged in an array, and selecting each pixel by address designation, wherein: having a plurality of pixel blocks, Plural of the pixels are formed in parallel with a common number of nodes; and The amplifying transistor is connected to each of the plurality of common nodes of the pixel block for amplifying the signal sent by the plurality of pixels in the pixel block; in each of the pixel blocks, each pixel comprises: photoelectric a conversion element that generates a signal charge corresponding to the illumination light; a first gate element disposed between the photoelectric conversion element and a common node of the pixel block; and a reset transistor coupled to the photoelectric conversion element and the first gate a connection point of the pole element to perform resetting of the pixel; at least the photoelectric conversion element is formed in the first semiconductor circuit layer constituting the three-dimensional laminated structure, and the first gate element, the reset transistor, And the amplifying transistor is formed in the second or third semiconductor circuit layer constituting the three-dimensional laminated structure; in addition to the plurality of the photoelectric conversion elements, the plurality of the first gate elements and the plurality of weights are also A transistor is formed in the first semiconductor circuit layer, and a plurality of the amplifying transistors are formed in the second or third semiconductor circuit layer. An address-specific image sensor having a three-dimensional layered structure, having a plurality of pixels arranged in an array, and selecting each pixel by address designation, wherein: having a plurality of pixel blocks, a plurality of the pixels are connected in parallel to the common node by a predetermined number; and the amplifying transistor is connected to each of the plurality of common nodes of the pixel block for amplifying the signal sent by the plurality of pixels in the pixel block ; In each of the pixel blocks, each of the pixels includes: a photoelectric conversion element that generates a signal charge corresponding to the illumination light; and a first gate element disposed between the photoelectric conversion element and a common node of the pixel block; and a transistor is connected to a connection point of the photoelectric conversion element and the first gate element to perform resetting of the pixel; and at least the photoelectric conversion element is formed in the first semiconductor circuit layer constituting the three-dimensional laminated structure, and The first gate element, the reset transistor, and the amplifying transistor are formed in a second or third semiconductor circuit layer constituting the three-dimensional laminated structure; the amplifying transistor and the amplifying power The crystal corresponds to an equal number of the total number of pixels in the pixel block, and the second gate element (selective transistor) is respectively connected to the output terminals; in addition to the plurality of the photoelectric conversion elements, the plurality of pixels a first gate element, a plurality of the reset transistors, and a plurality of the amplifying transistors are formed in the first semiconductor circuit layer, and a plurality of the second gate elements (selective transistors) are formed in the first semiconductor circuit layer After 2 or 3 of the semiconductor circuit layers. An address-specific image sensor having a three-dimensional layered structure, having a plurality of pixels arranged in an array, and selecting each pixel by address designation, wherein: having a plurality of pixel blocks, a plurality of the pixels are connected in parallel to the common node by a predetermined number; and the amplifying transistor is connected to each of the plurality of common nodes of the pixel block for amplifying the signal sent by the plurality of pixels in the pixel block ; In each of the pixel blocks, each of the pixels includes: a photoelectric conversion element that generates a signal charge corresponding to the illumination light; and a first gate element disposed between the photoelectric conversion element and a common node of the pixel block; and a transistor is connected to a connection point of the photoelectric conversion element and the first gate element to perform resetting of the pixel; and at least the photoelectric conversion element is formed in the first semiconductor circuit layer constituting the three-dimensional laminated structure, and The first gate element, the reset transistor, and the amplifying transistor are formed in the second or third semiconductor circuit layer constituting the three-dimensional laminated structure; and only a plurality of the photoelectric conversion element systems are Formed in the first semiconductor circuit layer, a plurality of the first gate elements, a plurality of the reset transistors, and a plurality of the amplifying transistors are formed in the second or third semiconductor circuit layer . An address-specific image sensor according to any one of claims 6 to 9, which uses all of the reset transistors to make all of the pixels as a whole before all of the pixels are generated and stored. In the pixel block, the signal corresponding to the signal charge stored in the pixel is read by the corresponding common node in time series, and then transmitted to the corresponding amplifying transistor.