WO2007105478A1

WO2007105478A1 - Layered type semiconductor device having integrated sensor

Info

Publication number: WO2007105478A1
Application number: PCT/JP2007/053557
Authority: WO
Inventors: Mitsumasa Koyanagi
Original assignee: Mitsumasa Koyanagi
Priority date: 2006-02-27
Filing date: 2007-02-27
Publication date: 2007-09-20
Also published as: JP2007228460A; TWI416948B; TW200803484A

Abstract

Provided is a sensor circuit and an address specification type image sensor capable of accumulating signal charges of all the pixels substantially simultaneously and realizing a high pixel numerical aperture. A plurality of pixels (11) arranged in a matrix are divided into groups of n pixels, which are connected in parallel to a common node (13) so as to constitute a plurality of pixel blocks (12). Each of the pixel blocks (12) includes: n photoelectric conversion elements (PD1 to PDn) connected in parallel to the common node (13); and n transfer gates (TG1 to TGn) for opening and closing channels connecting the photoelectric conversion elements (PD1 to PDn) and the common node (13). Outside of each of the pixel blocks (12), a common reset transistor (TrRST) for resetting all the pixels (11) and a common amplification transistor (TrAMP) for amplifying the signal read from the n pixels (11).

Description

Specification

Stacked semiconductor device with integrated sensor

Technical field

The present invention relates to a stacked semiconductor device equipped with an integrated sensor, and more specifically, a sensor circuit including a photoelectric conversion element, a transfer (transfer) gate, a reset transistor, and an amplification transistor, and using the sensor circuit The present invention relates to an addressable image sensor that enables simultaneous shuttering (global 'shutter, simultaneous exposure) for all pixels with a simple configuration.

Background art

Conventionally, as a solid-state imaging device, a CCD image sensor (charge transfer type) configured to transfer signal charges of all pixels arranged in a matrix using a CCD (Charge-Coupled Device). Many image sensors have been used. However, in recent years, the use of CMOS image sensors (XY addressing type image sensors) that select each of all the pixels arranged in a matrix by scanning in the horizontal and vertical directions has increased. It is also used in high-end SLR digital 'still' cameras and mobile phones. This is a system that can be manufactured with a standard CMOS (Complementary Metal-Oxide-Semiconductor) process, which requires only one power supply and has low power consumption compared to a CCD image sensor. This is probably because the advantages of CMOS image sensors such as on-chip are easy to realize.

[0003] However, the conventional general CMOS (addressing type) image sensor has the following two problems.

[0004] The first problem is that simultaneous accumulation of signal charges for all pixels (in other words, simultaneous or global shirt tie) is not possible.

[0005] That is, in the CCD image sensor, accumulation of signal charges is started at the same time for all pixels, and the accumulated signal charges are read and transferred simultaneously for each pixel force.

The signal charge accumulation period (which is equal to the exposure period) is the same for all pixels. This On the other hand, in the conventional CMOS image sensor, signal charge accumulation is started for each row of the pixel matrix or for each pixel, and the signal charge accumulated in each pixel is time-sequentially in order of each pixel force by addressing. Since it is read out, there is a temporal shift (timing shift) in the signal charge accumulation period of each pixel. Therefore, signal charge cannot be accumulated simultaneously as in a CCD image sensor. The reason is explained with reference to Fig. 33 and Fig. 30.

FIG. 33 (a) is a conceptual diagram showing a general circuit configuration of a CCD image sensor.

(b) is a conceptual diagram showing a signal charge accumulation period of the CCD image sensor. FIG. 30 (a) is a conceptual diagram showing a general circuit configuration of a conventional CMOS image sensor, and FIG. 30 (b) is a conceptual diagram showing a signal charge accumulation period of the CMOS image sensor. (See Kazuya Yonemoto, “CCD / CMOS Image 'Sensor Basics and Applications” (CQ Publisher, published in 2003) 17 pages 179 and 179).

In the CCD image sensor, as shown in FIG. 33 (a), each of a plurality of pixels arranged in a matrix includes a photodiode as a photoelectric conversion element, and each of these photodiodes is irradiated. An amount of signal charge corresponding to the intensity of the emitted light is accumulated. The signal charges accumulated in each pixel are simultaneously read out to vertical CCDs arranged along each column of the pixel matrix via a transfer gate (not shown) provided for each pixel. This readout to the vertical CCD is usually performed simultaneously at the end of the vertical blanking period. The signal charge read out to each vertical CCD is sequentially transferred to a common horizontal CCD arranged along the row of the pixel matrix by the vertical transfer action of the vertical CCD. The signal charges transferred to the horizontal CCD in this way are further transferred horizontally by the horizontal CCD toward the output end, and amplified by a FD (floating diffusion) amplifier provided at the output end for signal output. It becomes.

[0008] The signal charge accumulation period of the CCD image sensor is, as can be easily understood from FIG. 33 (b), the pixel corresponding to each of the N scanning lines (1 to N) constituting one frame. ! /, The accumulation period is the same, in other words, the accumulation period is set at the same timing. It will be clear that this is the case when considering the operation that the signal charge accumulated in each pixel is read out to the vertical CCD all at once. On the other hand, in the conventional CMOS image sensor, as shown in FIG. 30 (a), each of a plurality of pixels arranged in a matrix has a photodiode as a photoelectric conversion element, and the photodiode. And an amplifier for amplifying the signal charge accumulated by the. Each pixel in the pixel matrix is selected by sequentially selecting row selection lines in the vertical scanning circuit and sequentially selecting column signal lines in the horizontal scanning circuit (that is, designating XY addresses in order). . (In Fig. 30 (a), this is shown by the switch provided in each pixel and the switch provided in each column signal line.) CDS (Correlated Double) provided in each column signal line The Sampling (correlated double sampling) circuit is a circuit for removing signal charge power noise flowing through each column signal line. The signal charges selectively output from each pixel are sequentially sent to a common horizontal signal line, and become a signal output through an output circuit connected to one end of the horizontal signal line.

[0010] Regarding the signal charge accumulation period of the conventional CMOS image sensor, as shown in Fig. 30 (b), the pixel corresponding to each of the N scanning lines (1 to N) constituting one frame is arranged. ! / It can be seen that the current accumulation period is shifted in time in accordance with the scanning timing of each scanning line. This is because a CMOS image sensor does not have a vertical register (vertical CCD) like a CCD image sensor, so changing the timing of resetting the signal charge of each pixel changes the signal charge to the corresponding column signal. This is because the timing of sending to the line is shifted.

As described above, in the conventional CMOS image sensor, since the signal charge accumulation period is shifted for each scanning line, there is a problem in that the signal charge cannot be accumulated at the same time (in other words, simultaneous chattering). However, there is a drawback that when an object moving at high speed is imaged, the obtained image is distorted. For example, if a blade rotating at a high speed is imaged, a problem arises that the image becomes distorted as shown in FIG. 34 (b). In contrast, when a CCD image sensor capable of simultaneously accumulating signal charges (simultaneous shirting) is used, the image is as shown in Fig. 34 (a), and the resulting image is not distorted ( Fig. 34 is based on “CCDZC MOS Image 'Sensor Basics and Applications” page 180 above).

[0012] A second problem of the conventional CMOS image sensor is that the effective light receiving area is narrower than the pixel area, in other words, the pixel fill factor is low. So The reason for this will be described with reference to FIG. 31 and FIG. FIG. 31 is a circuit diagram showing a schematic circuit configuration of a conventional CMOS image sensor, and FIG. 32 is a cross-sectional view of an essential part showing the schematic device structure.

The circuit configuration shown in FIG. 31 is that of a CMOS image sensor having a 4-transistor type pixel. In addition to a photodiode, four transistors (transfer gate, reset transistor, Amplifying transistor, four MOS transistors for selection gate). These transistors are formed and arranged on a p-type silicon (Si) substrate as shown in the device structure of FIG. V is the power supply voltage and V is the reset voltage.

CC RST

The

[0014] The pixel (i, j) (where i and j are positive integers) in the i-th row and j-th column in FIG. 31 will be described. The transfer gate is connected to the voltage pulse via the i-th row read control line. By applying φ

Ti

It becomes conductive and sends the signal charge stored in the photodiode to the node where the transfer gate, reset transistor, and amplification transistor are interconnected at a specified timing. The reset transistor applies a voltage pulse Φ through the reset line in the i-th row

RST

By doing so, the signal charge accumulated in the photodiode is reset at a predetermined timing (applying a predetermined reset voltage V to the photodiode) via the transfer gate in the conductive state. Amplifying transistor connected to the node

RST

The star has a source follower configuration and amplifies the signal charge sent to the node. The selection gate is connected to a voltage pulse Φ through a row selection line (not shown) of the i-th row.

SE

Is applied, and the amplified signal charge is handled at a predetermined timing.

Li

To the j-th column signal line. Note that c connected to the node is the node sn

Shows the parasitic capacitance generated.

[0015] A circuit configuration of a pixel of a CMOS image sensor includes a three-transistor type. In the 3-transistor type, one pixel includes three transistors (a reset transistor, an amplifying transistor, and a MOS transistor for a select gate) in addition to a photodiode. In other words, the four-transistor type configuration gate and the transfer gate are omitted.

The circuit configuration of FIG. 31 is specifically realized as the structure shown in FIG. In other words, a plurality of element regions defined by element isolation insulating films on the surface region of a P-type silicon (Si) substrate. Within the region, there are formed four MOS transistors constituting a photodiode, a transfer gate, a reset transistor, an amplification transistor, and a selection gate.

In the conventional CMOS image sensor device structure, as is clear from the cross-sectional view of the main part of FIG. 32, four or three MOS transistors have a pixel area of either the four-transistor type or the three-transistor type. Therefore, the ratio of the area occupied by the photodiode (the opening) in the pixel area, that is, the “aperture ratio” is considerably small. The aperture ratio of conventional CMOS image sensors is usually as low as about 30%. For this reason, there is a problem that the sensitivity is lowered, and in order to eliminate the sensitivity reduction, it is necessary to increase the pixel area (pixel size).

[0018] An example of a CMOS image sensor that realizes simultaneous shirting of all pixels mentioned as the first problem is disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2004-266597). The CMOS image sensor includes, in a pixel, a light receiving element, a first transfer unit that transfers signal charges generated by the light receiving element to the next stage, a storage unit that temporarily stores an output of the first transfer unit, An initialization means for initializing the charge of the light receiving element and the storage section, a second transfer means connected to the storage section, and a charge detection section for reading the charge from the second transfer means as a voltage to the outside The stored charge is read by operating the first transfer means all at once for the pixels, and the signal charge is initialized by operating the initialization means for all the pixels all at once. (See claim 1). The effects of the invention are as follows: “In an CMOS image sensor, it is possible to perform an electronic shutter operation that simultaneously initializes all the pixels, and the pixel circuit is simple and the manufacturing process is simplified. Noise reduction can be achieved "(see paragraph 0036).

On the other hand, in recent years, semiconductor devices having a three-dimensional structure in which a plurality of semiconductor chips are stacked have been proposed. Kurino et al., For example, proposed an “intelligent 'image sensor chip with a three-dimensional structure” in the “1999 I'm D'em technical-digest” published in 1999! / Speak (see Non-Patent Document 1).

[0020] This image sensor chip has a four-layer structure in which a processor array and an output circuit are arranged in the first semiconductor circuit layer, and a data latch and a masking circuit are arranged in the second semiconductor circuit layer. An amplifier and an analog / digital converter are arranged in the third semiconductor circuit layer, and an image sensor array is arranged in the fourth semiconductor circuit layer. The uppermost surface of the image sensor array is covered with a quartz glass layer including the microlens array, and the microlens array is formed on the surface of the quartz glass layer. Image sensor A photodiode is formed as a semiconductor light receiving element in each image sensor in the array. The semiconductor circuit layers that constitute the four-layer structure are mechanically connected using an adhesive, and embedded wiring using conductive plugs and the micro-contacts that are in contact with the embedded wiring. It is electrically connected using bump electrodes.

[0021] In addition, Lee et al. In the “Journal of the Japan Society of Applied Physics” published in April 2000 titled “Development of 3D integration technology for highly parallel image processing chips” proposed by Kurino et al. An image processing chip including an image sensor similar to the above solid-state image sensor has been proposed (see Non-Patent Document 2).

[0022] The image processing chip of Lee et al. Has almost the same structure as the solid-state image sensor proposed by Kurino et al.

[0023] Both the conventional image sensor chip and the image processing chip disclosed in Non-Patent Documents 1 and 2 each include a plurality of semiconductor wafers (hereinafter also simply referred to as wafers) incorporating desired semiconductor circuits. After being stacked and fixed to each other, the obtained wafer stack is cut (diced) and divided into a plurality of chip groups. That is, a semiconductor wafer having a semiconductor circuit formed therein is laminated at the wafer level to form a three-dimensional laminated structure, which is divided to obtain an image sensor chip or an image processing chip. It is.

In these conventional image sensor chip and image processing chip, each of a plurality of stacked semiconductor circuits inside the chip constitutes a “semiconductor circuit layer”. Non-Patent Document 1: Kurino et al., “Intelligent 'Image Sensor' Chip with Three-dimensional Structure”, 1999 I'D. 1 D. 1-Tech. 'Digest' p. 36. 4.1 1-3 4 4 (H. Kunno et al., Intelligent Image Sensor Cnip with Three Dimensional Structure, 1999 IEDM Technical Digest, pp. 36.4.1-36.4.4, 1999)

Non-Patent Document 2: Lee et al., “Development of three-dimensional integration technology for highly parallel image processing chips”, “Japan Journal of the Japan Society of Applied Physics, Vol. 39, p. 2473-2477, Part 1 4B, April 2000, (K. Lee et al "Development of fhree—Dimensional Integration Technology ror Highly Paralle 1 Image-Processing Chip", (Jpn. J. Appl. Phys. Vol. 39, pp. 2474-2477, April 2000)

Patent Document 1: Japanese Patent Application Laid-Open No. 2004-266597 (FIG. 1—FIG. 2, FIG. 8, FIG. 12, FIG. 15) Disclosure of Invention

Problems to be solved by the invention

[0025] As described above, the conventional general CMOS (addressing type) image sensor cannot simultaneously store signal charges for all the pixels (in other words, simultaneous shirting), and has a low pixel aperture ratio. There are two problems.

[0026] In the conventional CMOS image sensor disclosed in Patent Document 1, all pixels can be simultaneously shirted. However, in each pixel, in addition to the light receiving element, a first transfer means for transferring the signal charge generated in the light receiving element to the next stage, a storage unit for temporarily storing the output of the first transfer means, Since it is necessary to provide an initialization means for initializing the charge of the light receiving element and the storage section and a second transfer means connected to the storage section, the storage section is provided in the 3-transistor type CMOS image sensor. This is an added configuration. Therefore, this CMOS image sensor still has the problem that the pixel aperture ratio is low.

[0027] The image sensor chip and the image processing chip disclosed in Non-Patent Documents 1 and 2 only disclose that a three-dimensional stacked structure can be realized by stacking and fixing semiconductor wafers or semiconductor chips. The above two problems of the conventional CMOS (addressable type) image sensor should be mentioned.

[0028] The present invention has been made in consideration of these points, and the object of the present invention is to allow substantially simultaneous accumulation of signal charges (substantially simultaneous shirting) for all pixels. Another object of the present invention is to provide a sensor circuit and an addressable image sensor that can realize a higher pixel aperture ratio than a conventional addressable image sensor.

[0029] Another object of the present invention is to provide a sensor circuit and an addressable image sensor that can image a subject moving at high speed without causing image distortion seen in a conventional addressable image sensor. There is. Still another object of the present invention is to provide an addressing type image sensor in which the ratio of the total area of the light receiving region to the total area of the imaging region is high.

[0031] Other objects of the present invention which are not specified here will become apparent from the following description and the accompanying drawings.

Means for solving the problem

[0032] (1) A sensor circuit according to a first aspect of the present invention comprises:

A sensor circuit having a plurality of pixels arranged in a matrix and used for an addressing type image sensor that selects each of the pixels by addressing.

A plurality of pixel blocks configured by connecting a plurality of the pixels in parallel to a common node every predetermined number, and a plurality of the pixels in the pixel block connected to the common node of each of the pixel blocks. A reset transistor for resetting;

An amplification transistor that is connected to the common node of each of the plurality of pixel blocks and that amplifies signals transmitted from the plurality of pixels in the pixel block, and in each of the pixel blocks, each of the pixels Includes a photoelectric conversion element that generates a signal charge according to the irradiated light, and a first gate element provided in a path between the photoelectric conversion element and the common node of the pixel block. It is characterized by being.

[0033] (2) A sensor circuit according to a first aspect of the present invention includes a plurality of pixels configured by connecting a plurality of pixels in parallel to a common node every predetermined number (for example, n, n is an integer of 2 or more). Has a pixel block. In each of the pixel blocks, each of the pixels is provided in a path between the photoelectric conversion element that generates a signal charge in response to irradiated light and the photoelectric conversion element and the common node of the pixel block. First gate element formed. Since the reset transistor and the amplification transistor are connected to the common node of each pixel block, the reset transistor and the amplification transistor can be shared by each pixel block. This means that a reset transistor and an amplification transistor are provided inside the pixel. [0034] In this sensor circuit, the signal charge generation / accumulation ability is operated up to the signal output as follows.

First, using the reset transistor provided for each of the pixel blocks, all of the pixels are collectively reset (initialized) (global reset), and all of the pixel blocks are Set the common node to a predetermined reset voltage. At this time, all the first gate elements provided for the photoelectric conversion elements are in a conductive state.

Next, after the first gate element is turned off, all of the pixels (photoelectric conversion elements) are irradiated with light, and signal charges are generated and accumulated collectively in the pixels.

[0037] After that, in each of the pixel blocks, the signal corresponding to the signal charge accumulated in the pixels in the pixel block is handled by sequentially turning on the first gate element in time series. To the common node to read in time series. This operation is performed in parallel in a plurality of the blocks. At this time, it is necessary to reset the common node using the reset transistor until the signal is read from one of the pixels in the pixel block and the signal is read from the other one of the pixels. The This is because if the common node is not reset, the influence of the signal read out first remains and the subsequent signal may fluctuate.

[0038] The signals read out in each of the pixel blocks are amplified in order or in parallel by the corresponding amplification transistors, and are output from the output terminals. In other words, when there is one output terminal of the amplification transistor, the signals sent in order from the plurality of pixels in the pixel block are amplified by the amplification transistor and then time-series from the output terminal. Are output in order. On the other hand, when the total number of output terminals of the amplification transistor is equal to the total number of the pixels in the pixel block, the signals are output in parallel from the plurality of output terminals of the amplification transistor.

[0039] Since the current realistic maximum shatter speed (that is, the shortest signal charge accumulation period) is (1Z800 00) seconds (= 125 sec), the reset operation of the common node by the reset transistor is required as many times as necessary. (E.g., (n-1) times) the time required for execution (total reset time) and the amplification transistor corresponding to the signal charge of the pixel in each of the pixel blocks If the n value is set so that the sum of the time required for amplification (total amplification time) is sufficiently smaller than the shortest signal charge accumulation period (= 125 sec), the signal for all of the pixels Charge accumulation (exposure) is performed substantially simultaneously. In other words, by using this sensor circuit, it is possible to store signal charges for all of the pixels substantially simultaneously (substantially simultaneous shirting).

[0040] In addition, by enabling simultaneous shirting in this manner, it is possible to capture a subject moving at high speed without causing image distortion in a conventional addressing type image sensor. Become.

[0041] Further, in the sensor circuit according to the first aspect of the present invention, the reset transistor and the amplification transistor are provided outside the block for each of the pixel blocks. It only needs to include one photoelectric conversion element and one first gate element (usually a MOS transistor). Therefore, if this sensor circuit is used, a higher pixel aperture ratio can be achieved compared to a conventional address-designated image sensor that includes three or four MOS transistors in addition to the photoelectric conversion element in the pixel. it can.

(3) In a preferred example of the sensor circuit according to the first aspect of the present invention, the amplification transistor has a single output terminal. In this case, there is an advantage that the wiring of the next stage connected to the output terminal of the amplification transistor is simplified.

In this example, it is preferable that a storage capacitive element connected to the output terminal of the amplification transistor and an output transistor for controlling the output of a signal stored in the capacitive element are further provided. In this case, by using the output transistor, there is an advantage that the signal stored in the capacitive element can be output at a timing different from the opening / closing of the first gate element.

In another preferable example of the sensor circuit according to the first aspect of the present invention, the amplification transistor has a number of output terminals equal to the total number of the pixels in the pixel block corresponding to the amplification transistor. And a second gate element is connected to each of the output terminals. In this case, by opening and closing each of the second gate elements in synchronization with the corresponding first gate element, signals from the plurality of pixels in the pixel block are output in parallel from the plurality of output terminals. can do. As a result, the next-stage signal processing is performed quickly. There is an advantage that

[0045] In this example, a plurality of storage capacitive elements respectively connected to the plurality of output terminals of the amplification transistor, and a plurality of output transistors for controlling the output of signals stored in the capacitive elements, It is preferable to further provide. In this case, by using a plurality of the output transistors, there is an advantage that the signals stored in the plurality of capacitive elements can be output at a timing different from the opening / closing of the first gate element.

[0046] In still another preferred example of the sensor circuit according to the first aspect of the present invention, all of the reset transistors are used before the signal charges are generated and accumulated all at once in the pixels. All of the pixels are collectively reset, and in each of the pixel blocks, signals corresponding to the signal charges accumulated in the pixels are read out in time series via the corresponding common nodes. It is sent to the corresponding amplification transistor. In this case, there is an advantage that substantial simultaneous shirting can be easily realized.

[0047] (4) A sensor circuit according to a second aspect of the present invention provides:

A plurality of pixel blocks configured by connecting a plurality of the pixels to a common node every predetermined number, and a plurality of the pixels in the pixel block connected to the common node of each of the plurality of pixel blocks In each of the pixel blocks, each of the pixels includes a photoelectric conversion element that generates a signal charge according to irradiated light, and the photoelectric conversion element. A reset for resetting the pixel connected to a connection point between the photoelectric conversion element and the first gate element, and a first gate element provided in a path between the pixel block and the common node. It is characterized by including a transistor.

[0048] (5) A sensor circuit according to a second aspect of the present invention includes a plurality of pixels configured by connecting a plurality of pixels in parallel to a common node every predetermined number (for example, n, n is an integer of 2 or more). Has a pixel block. In each of these pixel blocks, each of the pixels responds to irradiated light. In addition to the photoelectric conversion element that generates signal charges and the first gate element provided in the path between the photoelectric conversion element and the common node of the pixel block, the photoelectric conversion element and the first And a reset transistor connected to a connection point with the gate element for resetting the pixel. An amplifier transistor is connected to each common node of the pixel block. Therefore, each of the pixel blocks can share the amplification transistor. This means that an amplification transistor is provided inside the pixel.

Thus, in the sensor circuit according to the second aspect of the present invention, the configuration relating to the reset transistor is different from the sensor circuit according to the first aspect of the present invention. That is, in the sensor circuit according to the first aspect of the present invention, the reset transistor power is provided for each of the pixel blocks (that is, the reset transistor is provided outside each pixel block). In contrast, in the sensor circuit according to the second aspect of the present invention, the reset transistor power is provided for each of the plurality of pixels belonging to each of the pixel blocks (that is, the reset transistor is provided). Provided for each of the pixels). For this reason, the operation up to the signal charge generation / accumulation signal output is performed as follows.

[0050] First, using the reset transistor provided for each of the pixels, all the pixels are collectively reset (initialized), and (global reset) is performed. For all, the common node is set to a predetermined reset voltage. At this time, all the first gate elements provided for the photoelectric conversion elements are in a conductive state.

[0051] Next, with the first gate element kept in a cut-off state, the first gate element is put in a cut-off state, and then all of the pixels (photoelectric conversion elements) are irradiated with light, and the pixels are collectively collected. To generate and store signal charges.

[0052] After that, in each of the pixel blocks, the signal corresponding to the signal charge accumulated in the pixels in the pixel block is handled by sequentially turning on the first gate element in time series. To the common node to read in time series. This operation is performed in parallel in a plurality of the blocks. At this time, in the pixel block Before the signal is read from one of the pixels and the signal is read from the other one of the pixels, the first gate element is temporarily turned on, and the common node is turned on using the reset transistor. Need to reset. This is because if the common node is not reset, the influence of the signal read out may remain and the subsequent signal may fluctuate.

[0053] The signal thus read out in each of the pixel blocks is amplified in order or in parallel by the corresponding amplification transistor, and is output from the output end thereof. In other words, when there is one output terminal of the amplification transistor, the signals sent in order from the plurality of pixels in the pixel block are amplified by the amplification transistor and then time-series from the output terminal. Are output in order. On the other hand, when the total number of output terminals of the amplification transistor is equal to the total number of the pixels in the pixel block, the signals are output in parallel from the plurality of output terminals of the amplification transistor. This is the same as the sensor circuit according to the first aspect of the present invention.

[0054] Since the current realistic maximum shatter speed (that is, the shortest signal charge accumulation period) is (1Z800 00) seconds (= 125 sec), the reset operation of the common node by the reset transistor is required as many times as necessary. (E.g., (n-1) times) time required to execute (total reset time) and time required to amplify the signal charge of the pixel by the corresponding amplification transistor in each of the pixel blocks (total amplification time )), The signal charge accumulation (exposure) for all of the pixels is substantially simultaneously performed if the n value is set so that it is sufficiently smaller than the shortest signal charge accumulation period (= 1 25 sec). Will be done. In other words, by using this sensor circuit, it is possible to store signal charges for all of the pixels substantially simultaneously (substantially simultaneous shirting).

[0055] In addition, by enabling simultaneous shirting in this manner, it is possible to capture a subject that moves at high speed without causing image distortion in a conventional addressing image sensor. Become.

[0056] Further, in the sensor circuit according to the second aspect of the present invention, for each of the pixel blocks, since the amplification transistor is provided outside the block, the pixel includes one photoelectric conversion element. And one first gate element (usually a MOS transistor) and one It only needs to include a set transistor (usually a MOS transistor). Therefore, if this sensor circuit is used, a higher pixel aperture ratio can be realized compared to a conventional addressing type image sensor that includes three or four MOS transistors in a pixel. Can do.

(6) In a preferred example of the sensor circuit according to the second aspect of the present invention, the amplification transistor has a single output terminal. In this case, there is an advantage that the wiring of the next stage connected to the output terminal of the amplification transistor is simplified.

In this example, it is preferable to further include a storage capacitive element connected to the output terminal of the amplification transistor and an output transistor for controlling the output of the signal stored in the capacitive element. In this case, by using the output transistor, there is an advantage that the signal stored in the capacitive element can be output at a timing different from the opening / closing of the first gate element.

In another preferable example of the sensor circuit according to the second aspect of the present invention, the amplification transistor has a number of output terminals equal to the total number of the pixels in the pixel block corresponding to the amplification transistor. And a second gate element is connected to each of the output terminals. In this case, by opening and closing each of the second gate elements in synchronization with the corresponding first gate element, signals from the plurality of pixels in the pixel block are output in parallel from the plurality of output terminals. can do. As a result, there is an advantage that the next stage signal processing can be performed quickly.

[0060] In this example, a plurality of storage capacitive elements respectively connected to the plurality of output terminals of the amplification transistor, and a plurality of output transistors for controlling the output of signals stored in the capacitive elements, It is preferable to further provide. In this case, by using a plurality of the output transistors, there is an advantage that the signals stored in the plurality of capacitive elements can be output at a timing different from the opening / closing of the first gate element.

[0061] In still another preferable example of the sensor circuit according to the second aspect of the present invention, before the signal charges are generated and accumulated collectively in all of the pixels, the reset transistors are all used to generate and store the signal charges. All of the pixels are collectively reset, and in each of the pixel blocks, a signal corresponding to the signal charge accumulated in the pixel corresponds to the corresponding It is read out in time series through the common node and sent to the corresponding amplification transistor. In this case, there is an advantage that substantial simultaneous shirting can be easily realized.

(7) An addressing type image sensor according to a third aspect of the present invention provides:

An addressing type image sensor having a three-dimensional stacked structure, which has a plurality of pixels arranged in a matrix and selects each of the pixels by addressing.

A plurality of pixel blocks configured by connecting a plurality of the pixels in a predetermined number in parallel to a common node;

A reset transistor connected to the common node of each of the pixel blocks for resetting a plurality of the pixels in the pixel block;

An amplification transistor that is connected to the common node of each of the plurality of pixel blocks and that amplifies signals transmitted from the plurality of pixels in the pixel block, and in each of the pixel blocks, each of the pixels Includes a photoelectric conversion element that generates a signal charge according to the irradiated light, and a first gate element provided in a path between the photoelectric conversion element and the common node of the pixel block. And

At least the photoelectric conversion element is formed in a first semiconductor circuit layer constituting the three-dimensional laminated structure, and the first gate element, the reset transistor, and the amplification transistor constitute the three-dimensional laminated structure. It is characterized by being formed in the second or third or subsequent semiconductor circuit layer.

(8) An addressing type image sensor according to a third aspect of the present invention uses the sensor circuit according to the first aspect of the present invention described above, and includes at least a plurality of the photoelectric conversion elements in the three-dimensional stacked structure. The first gate element, the reset transistor, and the amplification transistor are formed in the first semiconductor circuit layer to be configured, and the second gate circuit, the reset transistor, and the amplification transistor are in the second or subsequent semiconductor circuit layers that constitute the three-dimensional stacked structure. It corresponds to what was formed.

[0064] Therefore, for the same reason as described for the sensor circuit according to the first aspect of the present invention, signal charges can be substantially simultaneously accumulated (substantially simultaneous shirting) for all the pixels. A pixel aperture ratio higher than that of the addressing type image sensor can be realized. In addition, image distortion in conventional addressing type image sensors It is possible to image a subject that moves at a high speed without occurring.

Furthermore, since a higher pixel aperture ratio than that of a conventional addressing type image sensor can be realized, the ratio of the total area of the light receiving region to the total area of the imaging region can be increased.

(9) In a preferred example of the addressing type image sensor according to the third aspect of the present invention, in addition to the plurality of photoelectric conversion elements, the plurality of first gate elements are included in the first semiconductor circuit layer. The plurality of amplification transistors and the plurality of reset transistors are formed in the second or third and subsequent semiconductor circuit layers. In this case, the first semiconductor circuit layer includes a plurality of the first gate elements in addition to the plurality of photoelectric conversion elements, but each pixel includes the first gate in addition to the photoelectric conversion elements. Since only one transistor constituting the element is included, the pixel aperture ratio is improved as compared with a conventional addressed image sensor in which each pixel includes four or three transistors in addition to the photoelectric conversion element.

[0067] In another preferred embodiment of the addressing type image sensor according to the third aspect of the present invention, in the example, in addition to the plurality of photoelectric conversion elements, the plurality of first gate elements and the plurality of reset transistors. Are formed in the first semiconductor circuit layer, and a plurality of amplification transistors are formed in the second or third and subsequent semiconductor circuit layers. In this case, the first semiconductor circuit layer includes a plurality of the first gate elements and a plurality of reset transistors in addition to the plurality of photoelectric conversion elements. In addition, only one transistor constituting the first gate element is included, and the total number of the reset transistors may be (lZn) of the total number of pixels. Therefore, the pixel aperture ratio is improved as compared with a conventional addressing type image sensor in which each pixel includes four or three transistors in addition to the photoelectric conversion element.

[0068] In still another preferable example of the addressing type image sensor according to the third aspect of the present invention, the number of output terminals equal to the total number of the pixels in the pixel block corresponding to the amplification transistor force is the amplification transistor force. And a second gate element (selection transistor) is connected to each of the output terminals. And a plurality of the photoelectric conversion elements, a plurality of the first gate elements, a plurality of the reset transistors and a plurality of the plurality of the photoelectric conversion elements. An amplification transistor is formed in the first semiconductor circuit layer, and a plurality of the second gate elements (selection transistors) are formed in the second or third and subsequent semiconductor circuit layers. In this case, the first semiconductor circuit layer includes a plurality of the first gate elements, a plurality of reset transistors, and a plurality of amplification transistors in addition to the plurality of photoelectric conversion elements. The pixel only includes one transistor that constitutes the first gate element in addition to the photoelectric conversion element, and the total number of the reset transistor and the amplification transistor is (lZn) of the total number of pixels. That's it. Therefore, the pixel aperture ratio is improved as compared with the conventional addressing type image sensor in which each pixel includes four or three transistors in addition to the photoelectric conversion element.

[0069] In still another preferable example of the addressing type image sensor according to the third aspect of the present invention, only a plurality of the photoelectric conversion elements are formed in the first semiconductor circuit layer, and the plurality of the first image sensors are formed. A gate element, a plurality of reset transistors, and a plurality of amplification transistors are formed in the second or third and subsequent semiconductor circuit layers. In this case, since only the plurality of photoelectric conversion elements are formed in the first semiconductor circuit layer, each pixel does not include any transistor. Therefore, the pixel aperture ratio is improved as compared with a conventional addressing type image sensor in which each pixel includes four or three transistors in addition to the photoelectric conversion element. In particular, the improvement in pixel aperture ratio is maximized.

[0070] In still another preferred example of the addressing type image sensor according to the third aspect of the present invention, each of the amplification transistors has a single output terminal. In this case, there is an advantage that the next-stage wiring connected to the output terminal of the amplification transistor is simplified.

[0071] In this example, a storage capacitor element connected to the output terminal of the amplification transistor and an output of a signal stored in the capacitor element are provided in the second or third and subsequent semiconductor circuit layers. It is preferable to further include an output transistor to be controlled. In this case, by using the output transistor, there is an advantage that the signal stored in the capacitive element can be output at a timing different from the opening / closing of the first gate element.

[0072] In still another preferable example of the addressing type image sensor according to the third aspect of the present invention, each of the amplification transistors is equal to the total number of the pixels in the pixel block corresponding to the amplification transistor. A number of outputs and each of these outputs Second gate elements are connected to each other. In this case, by opening and closing each of the second gate elements in synchronization with the corresponding first gate element, signals from the plurality of pixels in the pixel block are output in parallel from the plurality of output terminals. can do. As a result, there is an advantage that the next signal processing can be performed quickly.

[0073] In this example, a plurality of storage capacitive elements respectively connected to the plurality of output terminals of the amplification transistor in the second or third and subsequent semiconductor circuit layers, and the capacitance elements It is preferable to further include a plurality of output transistors for controlling the output of the stored signal. In this case, by using a plurality of the output transistors, there is an advantage that signals stored in a plurality of the capacitive elements can be output at a timing different from the opening / closing of the first gate element.

[0074] In still another preferred example of the addressing type image sensor according to the third aspect of the present invention, all of the reset transistors are set before generating and accumulating signal charges in all of the pixels. All of the pixels are collectively reset using a signal, and in each of the pixel blocks, a signal corresponding to the signal charge accumulated in the pixel is passed through the corresponding common node. After being read out in time series, it is sent to the corresponding amplification transistor. In this case, there is an IJ point that a substantial simultaneous shirting can be realized easily.

(10) An addressing type image sensor according to a fourth aspect of the present invention is:

An amplification transistor that is connected to the common node of each of the plurality of pixel blocks and that amplifies signals transmitted from the plurality of pixels in the pixel block, and in each of the pixel blocks, each of the pixels Includes a photoelectric conversion element that generates a signal charge according to the irradiated light, a first gate element provided in a path between the photoelectric conversion element and the common node of the pixel block, and the photoelectric conversion element. The conversion element and the first A reset transistor connected to a connection point with the gate element for resetting the pixel,

At least the photoelectric conversion element is formed in a first semiconductor circuit layer constituting the three-dimensional laminated structure, and the first gate element, the reset transistor, and the amplification transistor constitute the three-dimensional laminated structure. It is characterized by being formed in the second or subsequent semiconductor circuit layer.

(11) An addressing type image sensor according to a fourth aspect of the present invention uses the sensor circuit according to the second aspect of the present invention described above, and includes at least a plurality of the photoelectric conversion elements described above in the three-dimensional stack. The first gate element, the reset transistor, and the amplification transistor are formed in the first semiconductor circuit layer constituting the structure, and the second and subsequent semiconductor circuit layers constituting the three-dimensional stacked structure are formed. It corresponds to what was formed inside.

[0077] Therefore, for the same reason as described for the sensor circuit according to the second aspect of the present invention, signal charges can be accumulated substantially simultaneously (substantially simultaneous shirting) for all the pixels, A pixel aperture ratio higher than that of the addressing type image sensor can be realized. In addition, it is possible to image a subject that moves at high speed without causing image distortion in a conventional addressing type image sensor.

Furthermore, since a higher pixel aperture ratio than that of the conventional addressing type image sensor can be realized, it is possible to increase the ratio of the total area of the light receiving region to the total area of the imaging region.

[0079] (12) A preferred example of the addressing type image sensor according to the fourth aspect of the present invention is the same as that of the addressing type image sensor according to the third aspect of the present invention described above. This is because in the addressing type image sensor according to the third aspect of the present invention, a reset transistor is provided for each of the blocks (that is, a reset transistor is provided outside each block). On the other hand, in the addressing type image sensor according to the fourth aspect of the present invention, the reset transistor is provided for each of the plurality of photoelectric conversion elements belonging to each of the blocks, and therefore both are different. It is.

That is, in a preferred example of the addressing type image sensor according to the fourth aspect of the present invention. In addition to the plurality of photoelectric conversion elements, a plurality of first gate elements are formed in the first semiconductor circuit layer, and a plurality of amplification transistors and a plurality of reset transistors are provided in the second semiconductor circuit layer. Alternatively, it is formed in the third and subsequent semiconductor circuit layers. In this case, the first semiconductor circuit layer includes a plurality of the first gate elements in addition to the plurality of photoelectric conversion elements, but each pixel includes the first gate in addition to the photoelectric conversion elements. Since only one transistor constituting the element is included, the pixel aperture ratio is improved as compared with a conventional addressed image sensor in which each pixel includes four or three transistors in addition to the photoelectric conversion element.

In another preferred example of the addressing type image sensor according to the fourth aspect of the present invention, in addition to the plurality of photoelectric conversion elements, the plurality of first gate elements and the plurality of reset transistors are A plurality of amplification transistors are formed in the first semiconductor circuit layer, and a plurality of amplification transistors are formed in the second or third and subsequent semiconductor circuit layers. In this case, the first semiconductor circuit layer includes a plurality of the first gate elements and a plurality of reset transistors in addition to the plurality of photoelectric conversion elements. In addition, since it only includes two transistors, that is, the transistor constituting the first gate element and the reset transistor, each pixel has a conventional addressing type image sensor including four transistors or three transistors in addition to the photoelectric conversion element. Compared with pixel aperture ratio

[0082] In still another preferred example of the addressing type image sensor according to the fourth aspect of the present invention, the amplification transistor force is equal to the total number of the pixels in the pixel block corresponding to the amplification transistor. And a second gate element (selection transistor) is connected to each of the output terminals. A plurality of the first gate elements, a plurality of the reset transistors, and a plurality of the amplification transistors are formed in the first semiconductor circuit layer, and the plurality of the second gates are arranged on the plurality of the photoelectric conversion elements. An element (selection transistor) is formed in the second or third or subsequent semiconductor circuit layers. In this case, the first semiconductor circuit layer includes a plurality of the first gate elements, a plurality of reset transistors, and a plurality of amplification transistors in addition to the plurality of photoelectric conversion elements. A pixel constitutes the first gate element in addition to the photoelectric conversion element. There are only two transistors, the reset transistor and the reset transistor, and the total number of the amplification transistors may be (lZn) of the total number of pixels. Therefore, the pixel aperture ratio is improved as compared with a conventional addressing type image sensor in which each pixel includes four transistors or three transistors in addition to the photoelectric conversion element.

In still another preferred example of the addressing type image sensor according to the fourth aspect of the present invention, only a plurality of the photoelectric conversion elements are formed in the first semiconductor circuit layer, and a plurality of the first image sensors are formed. A gate element, a plurality of reset transistors, and a plurality of amplification transistors are formed in the second or third and subsequent semiconductor circuit layers. In this case, since only the plurality of photoelectric conversion elements are formed in the first semiconductor circuit layer, each pixel does not include any transistor. Therefore, the pixel aperture ratio is improved as compared with a conventional addressing type image sensor in which each pixel includes four or three transistors in addition to the photoelectric conversion element. In particular, the improvement in pixel aperture ratio is maximized.

[0084] In still another preferred example of the addressing type image sensor according to the fourth aspect of the present invention, each of the amplification transistors has a single output terminal. In this case, there is an advantage that the next-stage wiring connected to the output terminal of the amplification transistor is simplified.

In this example, a storage capacitive element connected to the output terminal of the amplification transistor and an output of a signal stored in the capacitive element are provided in the second or third and subsequent semiconductor circuit layers. It is preferable to further include an output transistor to be controlled. In this case, by using the output transistor, there is an advantage that the signal stored in the capacitive element can be output at a timing different from the opening / closing of the first gate element.

[0086] In still another preferable example of the addressing-type image sensor according to the fourth aspect of the present invention, each of the amplification transistors is equal to the total number of the pixels in the pixel block corresponding to the amplification transistor. The second gate element is connected to each of the output terminals. In this case, by opening and closing each of the second gate elements in synchronization with the corresponding first gate element, signals from the plurality of pixels in the pixel block are output in parallel from the plurality of output terminals. can do. As a result, there is an advantage that the next signal processing can be performed quickly.

[0087] In this example, the amplification transistor is included in the second or third and subsequent semiconductor circuit layers. It is preferable to further include a plurality of storage capacitive elements respectively connected to the plurality of output terminals of the star, and a plurality of output transistors for controlling the output of signals stored in these capacitive elements. In this case, by using a plurality of the output transistors, there is an advantage that signals stored in a plurality of the capacitive elements can be output at a timing different from the opening / closing of the first gate element.

[0088] In still another preferable example of the addressing type image sensor according to the fourth aspect of the present invention, all the reset transistors must be connected before generating and accumulating signal charges all over the pixels. All of the pixels are collectively reset using a signal, and in each of the pixel blocks, a signal corresponding to the signal charge accumulated in the pixel is passed through the corresponding common node. After being read out in time series, it is sent to the corresponding amplification transistor. In this case, there is an IJ point that a substantial simultaneous shirting can be realized easily.

(13) In the sensor circuit according to the first and second aspects of the present invention and the addressing type image sensor according to the third and fourth aspects of the present invention, the “photoelectric conversion element” was irradiated. It means an element that generates a charge in response to light. As the “photoelectric conversion element”, a photodiode, which is a semiconductor element, can be suitably used. However, the present invention is not limited to this as long as the element has a function of generating electric charge according to irradiated light. Anything can be used.

The “first gate element” means an element having a gate function for opening and closing a path connecting each of the plurality of photoelectric conversion elements and the corresponding common node. Force that MOS transistor can be used suitably The present invention is not limited to this.

As the “reset transistor”, any transistor can be used as long as it has a function of resetting signal charges generated in the plurality of pixels (the photoelectric conversion elements) belonging to the group. . The “reset transistor” is a power that can be suitably used as a MOS transistor. The present invention is not limited to this.

The “amplifying transistor” has a function of amplifying signals corresponding to signal charges generated by the plurality of pixels (the photoelectric conversion elements) belonging to the pixel block in time series to generate an output signal. Any transistor can be used as long as it has a transistor. "Increase As the “width transistor”, a MOS transistor can be suitably used. The present invention is not limited to this.

“First semiconductor circuit layer” and “second or third and subsequent semiconductor circuit layers” mean semiconductor circuit layers, in other words, semiconductor circuits formed in layers. Usually, it includes, but is not limited to, “semiconductor substrate” and “elements” and “wirings” formed inside or on the surface of the semiconductor substrate. The material of the “semiconductor substrate” is arbitrary, and may be silicon, a compound semiconductor, or other semiconductors as long as a desired semiconductor element or circuit can be formed. The structure of the “semiconductor substrate” is arbitrary, and may be a simple plate made of a semiconductor or a so-called SOI (Silicon On Insulator) substrate.

[0094] The "first semiconductor circuit layer" and the "second or third and subsequent semiconductor circuit layers" are defined as necessary (for example, the first semiconductor circuit layer and the second or third and subsequent semiconductor circuit layers alone If the desired stiffness is not obtained, it is fixed to any “support substrate” that is rigid enough to support them. The material of the “support substrate” is arbitrary. That is, it may be a semiconductor, glass, or other material. A semiconductor substrate having a circuit formed therein, that is, a so-called LSI wafer or LSI chip may be used.

“Embedded wiring” refers to a wiring or conductor for electrical connection in the stacking direction embedded in “first semiconductor circuit layer” or “second or third or subsequent semiconductor circuit layers”. . “Built-in wiring” is usually filled with (insulating film) and “insulating film” that covers the entire inner wall surface of “trench” or “through hole” formed in the semiconductor substrate, and the space inside the insulating film. ) "Conductive material" and force are also composed. However, it is not necessarily limited to this configuration.

Here, the “trench” or “through hole” may have any desired configuration as long as it has a desired depth and accommodates a conductive material to be an embedded wiring. The depth, opening shape, opening size, cross-sectional shape, etc. of the “trench” or “through hole” can be arbitrarily set as required. As a method for forming “trench” or “through hole”, any method can be used as long as it can be formed by selectively removing the semiconductor substrate from the surface side. For example, an anisotropic etching method using a mask can be suitably used.

The “insulating film” covering the inner wall surface of the “trench” or “through hole” electrically connects the semiconductor substrate and the “conductive material” filled in the “trench” or “through hole”. If it can be insulated, Any insulating film can be used. For example, silicon dioxide (SiO 2), silicon nitride (SiN)

2

Etc. can be used suitably. A method of forming the “insulating film” is arbitrary.

As the “conductive material” filled in the “trench” or “through hole”, any material can be used as long as it can be used as a buried wiring (for example, a conductive plug). For example, semiconductors such as polysilicon, metals such as tungsten (W), copper (Cu), and aluminum (A1) can be preferably used. As the filling method of the “conductive material”, any method can be used as long as the “conductive material” can be filled into the “trench” or “through hole” from one side of the semiconductor substrate.

The invention's effect

According to the sensor circuit of the present invention, (a) signal charges can be substantially simultaneously accumulated (substantially simultaneous shirting) for all the pixels, and moreover than a conventional addressed image sensor. It is possible to achieve a high pixel aperture ratio, and (b) to image a subject moving at high speed without causing image distortion in a conventional addressing type image sensor.

[0100] According to the addressing type image sensor of the present invention, (a) signal charges can be substantially simultaneously accumulated (substantially simultaneous shirting) for all pixels, and moreover than a conventional addressing type image sensor. Can achieve high pixel aperture ratios, (b) can capture high-speed moving subjects without image distortion in conventional addressing-type image sensors, and (c) receive light with respect to the total area of the imaging area The effect is that the ratio of the total area of the region is high.

Brief Description of Drawings

FIG. 1 is a functional block diagram showing an overall configuration of an addressing type image sensor in which a sensor circuit according to a first embodiment of the present invention is used.

FIG. 2 is a diagram showing a main circuit configuration of the sensor circuit according to the first embodiment of the present invention, and shows a circuit configuration of two pixel blocks belonging to the j-th column.

FIG. 3 is a view similar to FIG. 2 showing a principal circuit configuration of a sensor circuit according to a second embodiment of the present invention.

FIG. 4 is the same as FIG. 2 showing the main circuit configuration of the sensor circuit according to the third embodiment of the present invention. FIG.

[5] FIG. 5 is a view similar to FIG. 2 showing a principal circuit configuration of a sensor circuit according to a fourth embodiment of the present invention.

6] A circuit diagram showing a main circuit configuration of an addressing type image sensor according to a fifth embodiment of the present invention.

7] A circuit diagram showing the main circuit configuration of the addressing type image sensor according to the sixth embodiment of the present invention.

[8] FIG. 8 is a cross-sectional view of a main part showing an actual structure of an addressing type image sensor according to a fifth embodiment of the present invention.

9] It is a sectional view of the main part showing the actual structure of the addressing type image sensor according to the sixth embodiment of the present invention.

10] A circuit diagram showing the main circuit configuration of the addressing type image sensor according to the seventh embodiment of the present invention.

[11] FIG. 11 is a cross-sectional view of a principal part showing an actual structure of an addressing type image sensor according to a seventh embodiment of the present invention.

12] A cross-sectional view of the essential part showing the actual structure of the addressing type image sensor according to the eighth embodiment of the present invention.

13] A circuit diagram showing the main circuit configuration of the addressing type image sensor according to the ninth embodiment of the present invention.

14] A cross-sectional view of the essential part showing the actual structure of the addressing type image sensor according to the ninth embodiment of the present invention.

15] A cross-sectional view of the essential part showing the actual structure of the addressing type image sensor according to the tenth embodiment of the present invention.

FIG. 16 is a circuit diagram showing the main circuit configuration of the addressing type image sensor according to the eleventh embodiment of the present invention.

圆 17] It is a sectional view of the main part showing the actual structure of the addressing type image sensor according to the eleventh embodiment of the present invention.

[18] An actual structure of an addressing type image sensor according to a twelfth embodiment of the present invention is shown. FIG.

FIG. 19 is a functional block diagram showing an overall configuration of an addressing type image sensor in which a sensor circuit according to a thirteenth embodiment of the present invention is used.

20] A diagram showing a main circuit configuration of a sensor circuit according to a thirteenth embodiment of the present invention, showing the circuit configuration of two pixel blocks belonging to the j-th column.

21] A circuit diagram showing the main circuit configuration of the addressing type image sensor according to the fourteenth embodiment of the present invention.

22] A circuit diagram showing the main circuit configuration of the addressing type image sensor according to the fifteenth embodiment of the present invention.

圆 23] A sectional view of the principal part showing the actual structure of the addressing type image sensor according to the fourteenth embodiment of the present invention.

24] A sectional view of the principal part showing the actual structure of the addressing type image sensor according to the fifteenth embodiment of the present invention.

[25] FIG. 25 is a cross-sectional view of a main part showing a configuration example of a storage capacitor element used in the addressing type image sensor of the present invention.

FIG. 26 is a cross-sectional view of the principal part showing another configuration example of the storage capacitor element used in the addressing type image sensor of the present invention.

[27] FIG. 27 is a cross-sectional view of the principal part showing still another configuration example of the storage capacitor element used in the addressing type image sensor of the present invention.

[28] FIG. 28 is a circuit diagram showing a main circuit configuration of an addressing type image sensor according to a sixteenth embodiment of the present invention.

[29] FIG. 29 is a cross-sectional view of an essential part showing the actual structure of the addressing type image sensor according to the sixteenth embodiment of the present invention.

[FIG. 30] (a) is a conceptual diagram showing a general circuit configuration of a conventional CMOS (addressing type) image sensor, and (b) is a conceptual diagram showing a signal charge accumulation period of the image sensor. 31] A circuit diagram showing a main circuit configuration of a conventional CMOS (addressing type) image sensor. FIG. 32 is a cross-sectional view of an essential part showing the actual structure of a conventional CMOS (addressing type) image sensor.

[FIG. 33] (a) is a conceptual diagram showing a general circuit configuration of a conventional CCD (charge transfer type) image sensor, and (b) is a conceptual diagram showing a signal charge accumulation period of the image sensor.

[Fig. 34] (a) is a conceptual diagram showing an image obtained by imaging a high-speed rotating blade with a CCD (charge transfer type) image sensor. The same blade is imaged with a conventional CMOS (addressing type) image sensor. It is a conceptual diagram which shows the image obtained in this way.

Explanation of symbols

1, 1A, 1B, 1C sensor circuit

2, 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H Addressable image sensor

3 Sensor circuit

4, 4A addressable image sensor

11, 11a pixel

12, 12a pixel block

13, 13a Common node

14, 15 nodes,

21, 21A, 21B, 21C, 21D, 21E, 21F Upper semiconductor circuit layer

22Fa Middle semiconductor circuit layer

22, 22 ', 22A, 22A', 22B, 22B ', 22C', 22D ', 22E, 22E', 22Fb Lower semiconductor circuit layer

23, 23 'Embedded wiring

23a, 23a 'Conductive contact plug

24, 24 'insulation film

31 Reset line

32 Read control line

33 Horizontal signal line

34 Vertical scanning circuit

35 Horizontal scanning circuit CDS circuit

Column signal line

Column selection signal

Output selection line

a Output control line

p-type silicon substrate

Element isolation insulating film

43 n + type region

Gate electrode

Conductive 14 contact plug

Wiring film

Wiring structure

n + type region

Gate electrode

Conductive ¾ Contact plug

n + type region

Gate electrode

, 55 Conductive contact plug, 57 Wiring film

Conductive contact plug

Wiring film

60 'p-type silicon substrate

, 61 '' element isolation insulating film

64, 66, 66a, 66b n + type region, 65, 67, 67a, 67b Gate electrode aa capacitor

69, 70, 71 Conductive contact plug, 72a, 73 74, 74 'wiring structure

74a, 74a, 74a 'conductive contact plug

75, 75 'wiring film

76 n ⁺ type region

77 Gate electrode

78, 80, 82 Conductive contact plug

79, 81, 83 Wiring film

90, 90 '

Bump electrode

91, 91 'electrical insulating adhesive

PD to PD photodiode

TG to TG transfer gate

Tr, Tr to Tr reset transistor

RST RST1 RSTn

Tr

P amplification transistor

AM

Tr to Tr selection transistor

SELl SELn

R resistor

c,

ST c ~

ST1 c STn Memory capacitor

R

0 Parasitic resistance

C, C, C parasitic capacitance

sn 01 02

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0104] (First embodiment)

FIG. 2 is a diagram showing a main circuit configuration of the sensor circuit 1 according to the first embodiment of the present invention. FIG. 1 is a functional block diagram showing an overall configuration of an addressing type image sensor (hereinafter also referred to as a CM OS image sensor) in which the sensor circuit 1 is used. This sensor circuit 1 corresponds to the sensor circuit according to the first aspect of the present invention.

[0105] The overall configuration of the image sensor in Fig. 1 is the conventional CMOS (address specification) shown in Fig. 30 (a). Type) Almost the same as an image sensor, & 11) arranged in a matrix of rows and 111 columns (n and m are integers greater than or equal to 2) (k X n) 111 pixels 11 (hereinafter these The matrix formed by the pixels 11 is also referred to as a “pixel matrix”). However, these pixels 11 are divided into (k X m) pixel blocks 12 (blocky), and each pixel 11 does not include a reset transistor and an amplification transistor. Different from conventional C MOS image sensors. That is, in each pixel block 12, n pixels 11 belonging to the same column are grouped every n and connected in parallel to a common node (not shown in FIG. 1 and corresponding to the common node 13 in FIG. 2) This constitutes a pixel block 12 (see FIG. 2). The pixel blocks 12 are also arranged in a matrix.

[0106] The reset transistor Tr and the amplification transistor Tr are provided outside the pixel block 12.

RST AMP

One pixel block 12 is provided. In other words, the reset transistor Tr and the amplifying transistor Tr are respectively n pixels 1 in each pixel block 12.

RST AMP

Shared for 1. Therefore, the total number of reset transistors Tr is (k X m).

RST

Therefore, the total number of amplification transistors Tr is also (k X m).

AMP

In the vicinity of each pixel block 12, m reset lines 31 are formed, each extending along a corresponding column of the pixel matrix. Since one reset transistor Tr is provided for each pixel block 12, each reset line 31 has k reset transistors.

RST

The transistor Tr is connected. Each output terminal of the reset transistor Tr

RST RST

Is connected to one amplifying transistor Tr. Each reset line 31 corresponds to

AMP

Used to reset the signal charge accumulated in pixel 11 in k pixel blocks 12 belonging to the column. Application of the reset voltage to these pixels 11 is controlled using the corresponding reset transistor Tr. (When resetting the signal charge of pixel 11,

RST

The gate electrode of the transistor Tr is also reset. ) Each amplification transistor Tr corresponds to

AMP AMP

Used to amplify the signal read from each pixel 11 in the pixel block 12. The signal amplified by each amplification transistor Tr is the output of the amplification transistor Tr.

AMP AMP

The signals are sequentially sent to the corresponding column signal lines 37 via the ends.

In the vicinity of each pixel block 12, (k X n) read control lines 32 each extending along a corresponding row of the pixel matrix are formed. These read control lines 32 Are provided for each of m pixel blocks 12 belonging to the same row, and each force of n pixels 11 in each pixel block 12 is also used for reading out a signal. In FIG. 1, n readout control lines 32 provided for m pixel blocks 12 belonging to the same row are collectively shown as a single line.

[0109] In the vicinity of the left end of the pixel matrix, one vertical scanning circuit 34 extending along the column of the pixel matrix is provided. The vertical scanning circuit 34 sequentially scans (k X n) read control lines 32 and selects them in time series. At this time, each readout control line 32 is supplied with a signal for selecting the n pixels 11 included in each of the m pixel blocks 12 belonging to the corresponding row in time series (the transfer gate in FIG. 2). Supports control signals φ to φ

Tl Τη) is sent out.

[0110] In the vicinity of the lower end of the pixel matrix, one horizontal signal line 33 and one horizontal scanning circuit 35 extending along the row of the pixel matrix and m CDS circuits 36 for noise removal are provided. It has been. The horizontal scanning circuit 35 selects these CDS circuits 36 in time series by m column selection signals 38.

[0111] Each of the m CDS circuits 36 includes k amplification transistors Tr belonging to the column.

AMP

K column signal lines 37 respectively connected to the output terminals are connected in parallel. Therefore, the k output signals of k amplification transistors Tr belonging to the same row correspond to the corresponding CD.

AMP

Input to S circuit 36 in parallel. Since the output terminals of the m CDS circuits 36 are connected to the horizontal signal line 33, the output signals of the CDS circuits 36 are sequentially output to the outside of the image sensor via the horizontal signal line 33. The

Next, the sensor circuit 1 according to the first embodiment used in the addressing type image sensor having the above configuration will be described with reference to FIG.

[0113] FIG. 2 shows a circuit configuration of two pixel blocks 12 belonging to the j-th column (where l≤j≤m) of the pixel matrix. The upper pixel block 12 has the upper force located at the i-th (where l≤i≤k), and the lower pixel block 12 has the upper force located at the (i + 1) -th. Therefore, the upper pixel block 12 is displayed as 12 (i, j) and the lower pixel block 12 is displayed as 12 (i + 1, j) as necessary.

[0114] The upper pixel block 12 (i, j) belongs to the [n X (i— 1) + 1] row to the (n X i) row of the j-th column. Pixel 11 to be included. The lower pixel block 12 (i + 1, j) includes pixels 11 belonging to the [nX i + 1] row to the [n X (i + 1)] row of the jth column. Since these two pixel blocks 12 (i, j) and 12 (i + 1, j) have the same configuration, in the following description, the upper pixel block 12 (i, j) will be mainly described.

In the pixel block 12 (i, j), n pixels 11 are included, and each pixel 11 includes one photodiode and one transfer gate. Accordingly, each pixel 11 includes n photodiodes PD to PD and n transfer gates TG to TG. Each of the transfer gates TG to TG is composed of a MOS transistor. The anode of each photodiode PD to PD is connected to one of the source and drain regions of the corresponding one of the transfer gates TG to TG. Has been. The other source and drain regions of each of the transfer gates TG to TG are commonly connected to a common node 13 in the pixel block 12 (i, j). That is, n pixels 11 in the pixel block 12 (i, j) are connected in parallel to the common node 13.

[0116] The common node 13 of the pixel block 12 (i, j) has one source'drain region of the common reset transistor T provided corresponding to the pixel block 12 (i, j) and the pixel block 12

RST

No common is applied to the gate electrode of the common amplifying transistor T provided corresponding to the clock 12 (i, j).

AMP

Are connected at the same time. These reset transistor T and amplification transistor T are

RST AMP

Both are provided outside the pixel block 12 (i, j). Other than reset transistor T

RST

The source and drain regions are connected to the reset voltage source (reset voltage = v)

RST

. One source / drain region of the amplification transistor T is connected to a DC power supply (power supply voltage).

AMP = v CC

And the other source / drain region (output side) is connected to the output terminal of the pixel block 12 (i, j) (that is, the corresponding column signal line 37). The output terminal of the amplifying transistor T (source side / drain region on the output side) is connected to a predetermined potential (through

AMP

It is normally connected to the terminal or area of the ground potential) and constitutes a source follower type amplifier. The capacitance C connected to the node 14 is a parasitic capacitance generated at the node 14 and is sn

is there. Node 14 is connected to a terminal of a predetermined potential (usually ground potential) or sn through parasitic capacitance C.

Connected to the region. [0117] The output terminal of the amplifying transistor T (the source-drain region on the output side) is shown in Fig. 1.

AMP

Thus, the output signal of the amplification transistor T is connected to the corresponding column signal line 37.

AMP

That is, the serial (time-series) output signals of the n photodiodes PD to PD are sent to the corresponding CDS circuit 36 via the corresponding column signal line 37. Then, when being sent from the CDS circuit 36 to the horizontal signal line 33, the column signal line 37 is selected via the m column selection signals 38 by the scanning of the horizontal scanning circuit 35, whereby the serial output signal is sent. The signal is sent to the horizontal signal line 33. Thereafter, the signal is sent to the output terminal (not shown) of the image sensor provided at one end of the horizontal signal line 33 (the right end in FIG. 1).

[0118] All the pixel blocks 12 other than the pixel block 12 (i, j) have the same configuration as the pixel block 12 (i, so that n photodiodes are formed in the same manner as described above. The serial output signal from PD to PD is sent to the output terminal of the image sensor, so that the subject can be imaged.

Next, the operation of the addressing type image sensor including the sensor circuit 1 having the above configuration (from signal charge generation / accumulation to output signal output) will be described.

[0120] 1. Global reset of all pixels (all photodiodes)

First, pulse signals (transfer) respectively applied to the gate electrodes of the MOS transistors constituting the transfer gates TG to TG (first gate elements) provided for the photodiodes PD to PD of all the pixels 11. Gate control signal) φ

The logical state of Tl φ Τη

High (H), all the transfer gates TG to TG are turned on.

[0121] Next, a pulse applied to the gate electrode of the reset transistor Tr provided for each of all the pixel blocks 12 with the transfer gates TG to TG of all the pixels 11 open.

RST

The logic state of the signal (reset control signal) φ is H, and all reset transistors Tr

RST RST

To the continuity state. As a result, a common node with a predetermined reset voltage V 1S node 14

RST

It is simultaneously applied to the photodiodes PD to PD of all the pixels 11 through the node 13 and the transfer gates TG to TG. As a result, the voltage applied to the photodiodes PD to PD of all the pixels 11 is made approximately equal to the reset voltage V, in other words, the photo diodes of all the pixels 11.

RST

Diode PD ~ PD power ^ set. In this way, all pixels 11 are simultaneously reset, that is, “global reset” is performed. [0122] 2. Exposure (Charge accumulation)

Next, the logic state of the transfer gate control signals φ to φ applied to the transfer gates TG to TG of all the pixels 11 is set to Low (L), and all the transfer gates TG to TG are set.

Tl Tn 1 is turned off. At the same time, the logic state of the reset control signal φ is set to L, and n RST

All reset transistors Tr are also shut off at the same time.

RST

Thereafter, in this state, the photodiodes PD to PD of all the pixels 11 are irradiated with light, and signal charges are generated and accumulated all at once in all the photodiodes PD to PD. The irradiation time is usually several hundreds / z sec to several msec and is very long.

[0124] As soon as signal charge generation 'accumulation is completed, the logic state of reset control signal φ

RST

Again set to H and all reset transistors Tr are turned on all at once for a predetermined time (for example,

RST

1 μsec), the logic state of the reset control signal φ is set to L again and all reset transitions

RST

Shut down all the star transistors. Thus, all nodes 14 (i.e. all amplified transistors)

RST

The reset voltage V is temporarily applied to the gate electrode of the transistor Tr, and all the amplification transistors T

AMP RST

The gate voltage of r is set to a predetermined reference voltage.

AMP

[0125] 3. Signal readout and amplification

A signal proportional to the amount of charge generated and accumulated in all the photodiodes PD to PD as described above is read out from each pixel 11 in the form of voltage and amplified as follows.

That is, first, when one pixel block 12 is selected by the vertical scanning circuit 34 and the horizontal scanning circuit 35, n transfer gate control signals φ ~ in the pixel block 12 are selected.

T1

The logic state of Φ is changed from L to H in order, and the transfer gates TG to TG are turned on sequentially.

Tn I n

I will make it. Then, after maintaining these conduction states for a predetermined time (for example, 0.1 μsec), the logic states are returned to L in order. Thus, all the photodiodes PD to PD force signal force 14 in the pixel block 12 are read out in time series. In the meantime, all reset transistors Tr are held off.

RST

[0127] The amplification transistor Tr connected to the node 14 in the form of a source follower has its gate

AMP

Since the electrode is connected to the node 14, the voltage signal read to the node 14 is immediately amplified by the amplification transistor Tr. The amplified signal is then transferred to the amplified traffic.

AMP The source / drain region force on the output terminal side of the transistor Tr is also output toward the column signal line 37.

AMP

It is.

[0128] When reading and amplifying n pixels 11 in the pixel block 12, that is, photodiode PD to PD force signals, reading and amplification of signals from one pixel 11 (for example, photodiode PD) are performed. After the completion, the reset transition for the pixel block 12 is started after the signal readout of the next pixel 11 (for example, the photodiode PD) starts.

2

The reset voltage V is temporarily applied to node 14 by turning on the transistor Tr.

RST RST

Therefore, the node 14 (the gate electrode of the amplification transistor Tr) is set to the reference potential.

AMP

It is necessary to reset (reset). Otherwise, the influence of the signal from the previous pixel 11 (e.g. photodiode PD) remains and the next pixel 11 (e.g. photodiode PD)

This is because there is a possibility that an error may occur in a signal with 1 or 2 power.

[0129] Since there are n photodiodes PD to PD in the pixel block 12, the total number of read operations by the transfer gate control signals φ to φ is η, and the amplification transistor Τ

Tl Τη

The total number of amplification operations by r is n, and the total number of reset operations of the amplification transistor Tr

AMP AMP

Is (n— 1) times.

More specifically, for example, first, the first transfer gate TG of the pixel block 12 is temporarily turned on, and the voltage proportional to the signal charge accumulated in the first photodiode PD is set. Read the signal to node 14. The voltage signal is immediately amplified by the amplifying transistor Tr, and the obtained amplified signal is sent to the column signal line 37.

AMP

Subsequently, the reset transistor Tr is temporarily turned on, and the amplification transistor Tr

RST AMP

Reset the gate electrode (node 14) to the reference potential. Thereafter, a voltage signal proportional to the signal charge accumulated in the second photodiode PD is read out to the node 14. Its voltage

2

The signal is immediately amplified by the amplifying transistor Tr, and the obtained amplified signal is the column signal line 37.

AMP

Sent to. Subsequently, the reset transistor Tr is temporarily turned on and increased.

RST

Reset the gate electrode (node 14) of the width transistor Tr to the reference potential. Sarako, No. 3

AMP

Same operation as above for the photodiode PD of the eye and the photodiode PD of the fourth

3 4

Are repeated in order. Finally, when the reading operation and the amplifying operation for the nth photodiode PD are executed, the processing for the pixel block 12 is completed. In the image sensor of FIG. 1, the amplification transistor Tr corresponding to the pixel block 12

AMP

Since there is only one output terminal, n signals from which all the photodiodes PD to PD in the pixel block 12 can also be obtained are connected to the source terminal n AMP on the output terminal side of the amplification transistor Tr.

The rain region force is also output in sequence toward the column signal line 37 in time series. In other words, the signal output from the pixel block 12 is a signal in which n pulse waveforms that reflect the amount of signal charges (the amount of irradiated light) of the photodiodes PD to PD are connected at a predetermined interval. One serial signal.

[0132] Since the image sensor has (k X m) pixel blocks 12 in total, the above-described operation is repeated (k X m) times while all the pixels 11 are scanned. .

[0133] A signal output from the pixel block 12, that is, one serial signal in which n signal pulses are connected at a predetermined interval, is a known sample and hold circuit, The signal is sent to an analog-to-digital (AZD) conversion circuit and subjected to predetermined signal processing.

[0134] The current realistic maximum shatter speed (that is, the shortest signal charge accumulation period) is (1Z80 00) seconds (= 125 sec). Therefore, for each of (k X m) pixel blocks 12, node 14 (gate electrode of amplification transistor Tr) by reset transistor Tr

RST AMP

Required to execute the reset operation for the required number of times (ie, (n-1) times) (total reset time) and the signal from all pixels 11 (all photodiodes PD to PD) in the pixel block 12 Of the time (total amplification time) required to amplify the signal with the corresponding amplification transistor Tr

AMP

And set the n value (total number of pixels 11 in each pixel block 12) to be sufficiently smaller than the shortest signal charge accumulation period (= 125 sec). Then, accumulation (exposure) of signal charges for pixels 11 (photodiodes PD to PD) belonging to all pixel blocks 12 is performed substantially simultaneously. In other words, the signal charges for all the pixels 11 can be accumulated substantially simultaneously (substantially simultaneous shirting).

[0135] In addition, each force of all pixel blocks 12 outputs (k X m) output serial signals independently, so that these output serial signals are processed by analog-digital (AZD) conversion and the like. Can be done in parallel. Therefore, data processing can be performed at a higher speed than that in the conventional CMOS image sensor. This also contributes to the realization of practical simultaneous shirting. Is.

[0136] As is apparent from the above-described operation, when viewed within one frame, the serial output signal output from each pixel block 12 is generated at the beginning of the scanning period as the closer to the end of the scanning period, ' The charge accumulation period is slightly longer than the output one. For this reason, when it is desired to obtain image data with higher fidelity or to increase the n value, a known circuit that performs signal correction in accordance with the change in the charge accumulation period may be provided in the subsequent stage. This is because the influence of fluctuations in the charge accumulation period can be suppressed or avoided.

[0137] In this way, it becomes possible to capture a subject moving at high speed without causing image distortion in a conventional CMOS image sensor by enabling simultaneous shirting. .

Furthermore, since each pixel block 12 is provided with a common reset transistor Tr and a common amplification transistor Tr outside the pixel block 12, the pixel block 12

RST AMP

Each pixel 11 in the lock 12 only needs to include one photodiode and one gate element (MOS transistor). Therefore, in addition to the photodiode in one pixel, there are three! Compared with a conventional CMOS image sensor including four MOS transistors, a high pixel aperture ratio (for example, about 60%) can be realized.

Note that in the conventional CMOS image sensor, since signal processing is performed serially according to the number of scanning lines, the power required for a high-speed AZD conversion circuit is required. The sensor circuit 1 of the first embodiment is In image sensors, the processing speed of each serial output signal of the amplifying transistor Tr is increased by increasing the parallelism by setting the n value to be smaller than the number of scanning lines.

AMP

It becomes possible to slow down. For this reason, there is an effect that an AZD conversion circuit having a simpler configuration can be used.

[0140] In addition, n output signal powers of n photodiodes PD to PD force are output from each of the amplification transistors Tr in a serially connected form, so that the amplification transistor Tr

AMP AM

There is also an effect that the next-stage wiring connected to each of the output terminals is simplified.

P

[0141] (Second Embodiment)

FIG. 3 is a circuit diagram showing a configuration of a sensor circuit 1A according to the second embodiment of the present invention. Since the entire configuration of the addressing type image sensor using this sensor circuit 1A is the same as that shown in FIG. 1, its description is omitted. This sensor circuit 1A corresponds to the sensor circuit according to the first aspect of the present invention.

[0142] The circuit configuration of the sensor circuit 1A shown in FIG. 3 is substantially the same as the circuit configuration of the sensor circuit 1 according to the first embodiment (see FIG. 2), and the amplification provided for each pixel block 12 A storage capacitor C and an output transistor Tr are added to the output side of the transistor Tr.

AMP ST OUT

The only difference is that Therefore, the same elements as those of the sensor circuit 1 in FIG.

[0143] The storage capacitor element C temporarily receives the signal amplified by the corresponding amplification transistor Tr.

ST AMP

One terminal is the output side of the amplifying transistor Tr

AMP

The other terminal is connected to a terminal or region having a predetermined potential (usually ground potential).

[0144] The output transistor Tr was temporarily stored in the storage capacitor C.

OUT ST

The signal is sent to the corresponding column signal line 37, and the output side source / drain region is connected to the output terminal (column signal line 37) of the pixel block 12. The output transistor Tr sets the logic state of the output control signal φ applied to its gate electrode to H.

OUT OUT

By doing this, it becomes conductive, and by rubbing it, it becomes cut-off. Therefore, when the signal temporarily stored in the storage capacitor C is output to the column signal line 37,

ST

In addition, the output transistor Tr opens the transfer gates TG to TG in the pixel block 12.

It can be opened and closed at a different timing from OUT 1 n closing.

In the image sensor using the sensor circuit 1 of the first embodiment described above, the serial output signals of the n photodiodes PD to PD force in the corresponding pixel block 12 are amplified by the amplification transistor Tr. Immediately after that, it is output toward the column signal line 37. to this

AMP

On the other hand, in the image sensor using the sensor circuit 2 of the second embodiment, the serial output signals from the n photodiodes PD to PD in the pixel block 12 are the amplification transistors Tr.

After being amplified by I n A, it is temporarily stored in the storage capacitor element c.

MP ST

The signal φ is used to read signals from the photodiodes PD to PD.

OUT 1 n

The opening and closing of the transfer gates TG to TG are shifted in timing and output toward the column signal line 37. You can make it stronger.

In the image sensor including the sensor circuit 1A according to the second embodiment having the above configuration, the signal charges for all the pixels 11 are substantially simultaneously accumulated (substantially) for the same reason as in the first embodiment. Simultaneous simultaneous shots). In addition, since it is possible to make a substantially simultaneous shutter in this way, it is possible to image a subject that moves at high speed without causing image distortion in a conventional CMOS image sensor.

Further, since each pixel block 12 is provided with a common reset transistor Tr and a common amplification transistor Tr outside the pixel block 12, the pixel block 12

RST AMP

Each pixel 11 in the gate 12 only needs to include one photodiode and one gate element (MOS transistor). Therefore, a higher pixel opening ratio can be realized as compared with a conventional CMOS image sensor that includes three or four MOS transistors in addition to a photodiode in one pixel.

Furthermore, the transfer gates TG to T in the pixel block 12 are controlled by the output control signal φ.

OUT 1

Since the signal can be output to the column signal line 37 at a different timing from the opening and closing of G, there is also an effect that imaging can be performed at a higher speed than when the sensor circuit 1 of the first embodiment is used.

[0149] (Third embodiment)

FIG. 4 is a circuit diagram showing a configuration of a sensor circuit 1B according to the third embodiment of the present invention. Since the entire configuration of the addressing type image sensor using this sensor circuit 1B is the same as that shown in FIG. 1, its description is omitted. This sensor circuit 1B corresponds to the sensor circuit according to the first aspect of the present invention.

[0150] The circuit configuration of the sensor circuit 1B shown in FIG. 4 is substantially the same as the circuit configuration of the sensor circuit 1 (see FIG. 2) according to the first embodiment, and the amplification provided for each pixel block 12 N select transistors Tr to Tr in the source and drain regions on the output side of the transistor Tr

AMP SEL1 SE

(Second gate element) connected in parallel and amplified n photodiodes PD

Ln 1

N output signal force of PD force Select transistor Tr n In parallel via Tr n SEL1 SELn

The only difference is that it is output to the column signal line 37. Select transistors Tr to Tr

SEL1 SELn

The logic states of the output selection signals φ to φ applied to the gate electrodes are set to H, respectively.

SEL1 SELn By doing this, it becomes conductive, and by rubbing it, it becomes cut-off. Therefore, the same elements as those of the sensor circuit 1 in FIG.

[0151] When reading and amplifying a signal corresponding to the signal charge generated and accumulated in n photodiodes PD to PD, n selection transistors Tr to Tr correspond to corresponding pixels.

SEL1 SELn

It is opened and closed almost synchronously with the transfer gates TG to TG in block 12. That is, for example, when a signal having a photodiode PD power is read out and amplified, the transfer gate TG is opened (becomes conductive), but the selection transistor Tr is opened (conducting state is substantially synchronized). Therefore, the read signal charge is

SEL1

Immediately after being amplified by the transistor Tr, the column signal line 37 is passed through the selection transistor Tr.

AMP SEL1

Is output.

[0152] In the image sensor including the sensor circuit 1B according to the third embodiment having the above configuration, the signal charges for all the pixels 11 are substantially simultaneously accumulated (substantially) for the same reason as in the first embodiment. Simultaneous simultaneous shots). In addition, since it is possible to make a substantially simultaneous shutter in this way, it is possible to image a subject that moves at high speed without causing image distortion in a conventional CMOS image sensor.

RST AMP

Each pixel 11 of the lock 12 only needs to include one photodiode and one gate element (MOS transistor). Therefore, a higher pixel aperture ratio can be realized compared to a conventional CMOS image sensor that includes three or four MOS transistors in addition to a photodiode in one pixel.

Note that n output signal forces of n photodiodes PD to PD forces that have been amplified are directed to the column signal line 37 in parallel via the corresponding n select transistors Tr to Tr.

SEL1 SELn

Since it is output, there is also an effect that signal processing of the next stage can be performed quickly.

[0155] (Fourth embodiment)

FIG. 5 is a circuit diagram showing a configuration of a sensor circuit 1C according to the fourth embodiment of the present invention. Since the entire configuration of the addressing type image sensor using the sensor circuit 1C is the same as that shown in FIG. 1, its description is omitted. This sensor circuit 1C is the first of the present invention. It corresponds to the sensor circuit from the viewpoint of 1.

The circuit configuration of the sensor circuit 1C shown in FIG. 5 is substantially the same as the circuit configuration of the sensor circuit 1B according to the third embodiment (see FIG. 4), and the amplification provided for each pixel block 12 N selection transistors Tr to Tr (second gate element) on the output side of the transistor Tr

AMP SEL1 SELn are connected in parallel, and n transistors are connected to the output side of the selection transistors Tr to Tr.

SEL1 SELn

Storage capacitors C to C and n output transistors Tr to Tr are added.

ST1 STn OUT1 OUTn

The only difference is that Therefore, the same elements as those of the sensor circuit 1C in FIG.

[0157] The storage capacitor elements C to C include n photodiodes amplified by the amplification transistor Tr.

ST1 STn AMP

This is to temporarily store the PD PD to PD force signals, one of which is the source-drain on the output side of the corresponding selection transistor Tr to Tr.

SEL1 SELn

[0158] The output transistors Tr to Tr are temporarily connected to the storage capacitors C to C.

OUT1 OUTn ST1 STn

The stored signal is sent in parallel to the corresponding column signal line 37, and the source and drain regions on the output side are connected to the output terminal (column signal line 37) of the pixel block 12. Has been. The output transistors Tr to Tr are marked on their gate electrodes.

OUT1 OUTn

The conduction state is established by setting the logic state of the applied output control signal φ to Φ Γ to Η

OUT1 OUTn

It becomes the interruption state by rubbing U. Memory capacitor c ~ Temporary

ST1 c

STn

When the amplified signal stored in is output to the column signal line 37 in parallel, the output transistors Tr to Tr are different from the open / close states of the transfer gates TG to TG in the pixel block 12.

OUTl OUTn 1 n

It is possible to open and close at the timing.

In the image sensor using the sensor circuit 1B of the third embodiment described above, n output signals from the n photodiodes PD to PD in the corresponding pixel block 12 are amplified by the transistor Tr. Immediately after being amplified, the signals are output in parallel toward the column signal line 37. This

AMP

On the other hand, in the image sensor using the sensor circuit 1C of the fourth embodiment, the output signals from the n photodiodes PD to PD in the pixel block 12 are amplified transistors Tr.

After being amplified by 1 n AMP, it is temporarily stored in storage capacitors c to c, respectively.

ST1 STn In response to the output control signal φ to φ, the photodiode PD to PD force

OUTl OUTn 1 η

The transfer gates for reading the signals can be output in parallel toward the column signal line 37 at different timings from the opening and closing of the transfer gates TG to TG.

[0160] In the image sensor including the sensor circuit 1C according to the fourth embodiment having the above-described configuration, the signal charges for all the pixels 11 are substantially simultaneously accumulated (substantially) for the same reason as in the first embodiment. Simultaneous simultaneous shots). In addition, since simultaneous shirt tying is possible in this manner, it is possible to image a subject that moves at a high speed that causes image distortion in a conventional CMOS image sensor.

[0161] Also, since each pixel block 12 is provided with a common reset transistor Tr and a common amplification transistor Tr outside the pixel block 12, the pixel block 12

RST AMP

[0162] Furthermore, transfer gates in the pixel block 12 are controlled by the output control signals φ to φ.

OUTl OUTn

Since the signal can be output to the column signal line 37 at a different timing from the opening / closing of TG to TG, it is possible to take an image at a higher speed than when the sensor circuit 1B of the third embodiment is used. is there.

[0163] (Fifth embodiment)

FIG. 6 is a circuit diagram showing the circuit configuration of the main part of the addressing type image sensor 2 according to the fifth embodiment of the present invention, and FIG. 8 is a cross-sectional view of the main part showing the actual structure of the image sensor 2. It is. This image sensor 2 uses the sensor circuit 1B of the third embodiment described above (see FIG. 4). The upper semiconductor circuit layer 21 and the lower semiconductor circuit layer 22 are stacked to form a two-stage three-dimensional stack. It is structured. This image sensor 2 corresponds to the image sensor according to the third aspect of the present invention.

[0164] Since the overall configuration and operation of the image sensor 2 are the same as those shown in FIG. 1, the description thereof will be omitted. In addition, the circuit configuration of FIG. 6 is the same as that of the sensor circuit 1B of the third embodiment shown in FIG. Tr is connected and does not have a storage capacitor and output transistor)

SELn

Therefore, the same symbols are attached to the same elements, and the description thereof is omitted. However, in the image sensor 2, as described later, the common node 13 of each pixel block 12 formed in the upper semiconductor circuit layer 21 and the reset transistor Tr formed in the lower semiconductor circuit layer 22 are used.

R

And the node 14 which is the connection point of the amplification transistor Tr

ST AMP

Since the known embedded wiring 23 is used, the embedded wiring 23 and the parasitic resistance R and parasitic capacitances C and C generated by the embedded wiring 23 are added to FIG. Embedded wiring 23

0 01 02

Is provided for each pixel block 12 (that is, n pixels 11).

[0165] Next, the actual structure of the image sensor 2 will be described with reference to FIG.

As is apparent from FIG. 8, the image sensor 2 includes an upper semiconductor circuit layer 21 and a lower semiconductor circuit layer 22, embedded wiring 23, fine bump electrodes (for example, indium (In) and gold ( Au) laminate, or tungsten (W), etc.) 90 and an electrically insulating adhesive (eg, polyimide) 91, and mechanically and electrically connected. Yes.

Note that a method for forming the embedded wiring 23 and the bump electrode 90 and a method for mechanically connecting the upper semiconductor circuit layer 21 and the lower semiconductor circuit layer 22 using an adhesive 91 are known in the art. Since those can be used, the description about them is omitted.

In the upper semiconductor circuit layer 21, (k X m) pixel blocks 12, that is, (k X n) X m pixels 11 are formed. Therefore, the upper semiconductor circuit layer 21 includes (k X n) X m photodiodes (that is, (k X m) sets of photodiode groups PD to PD) and (k X n) X m transfer gates. (That is, (k X m) sets of transfer gate groups TG to TG). In the upper semiconductor circuit layer 21, (k × m) embedded wirings 23 are further formed.

[0169] The lower semiconductor circuit layer 22 includes (k X m) reset transistors Tr and (k X m)

RST

Amplifying transistor Tr and (k X n) X m select transistors (ie, (k X m) pairs

AMP

A selection transistor group Tr-Tr) is formed!

SEL1 SELn

[0170] In the upper semiconductor circuit layer 21, the element isolation insulating film 41 is formed in a predetermined pattern on the surface region of the p-type single crystal silicon (Si) substrate 40, so that the layout of FIG. 1 is obtained. In addition, element regions for (k X n) X m pixels 11 are formed in a matrix. Yes. Each of these element regions corresponds to one pixel 11. Since all the pixel blocks 12 have the same configuration, only one pixel block 12 (i, j) will be described here.

[0171] In the element region corresponding to the pixel block 12 (i, j), n photodiodes PD to PD and n transfer gates TG to TG are formed. For example, as shown in FIG. 8, the photodiode PD is composed of an n + type region 42 formed on the p-type substrate 40 (that is, the photodiode PD is a p-n junction photodiode). The transfer gate TG is formed of a MOS transistor including a gate electrode 44 and an n + type region 43 facing the n + type region 42 with the gate electrode 44 interposed therebetween. Since the transfer gate TG shares the n + type region 42 of the photodiode PD, one source / drain region force of the transfer gate TG is electrically connected to the anode of the photodiode PD. The gate insulating film existing between the gate electrode 44 and the surface of the substrate 40 is omitted in FIG. (Since the existence of the gate insulating film between the gate electrode 44 and the surface of the substrate 40 is self-explanatory, the description of the gate insulating film is omitted in the following description as well.) The gate electrode 44 is formed on the surface of the substrate 40. The wiring structure 47 is electrically connected to the corresponding read control line 32 via the wiring. Here, the wiring structure 47 includes a wiring conductor formed on the surface of the substrate 40 and an insulator including the conductor, and does not include a gate insulating film and a gate electrode existing on the surface of the substrate 40. (This also applies to the following embodiments.) Other photodiodes PD to PD and transfer gates TG to TG

2 n 2 n Each has the same configuration as the photodiode PD and transfer gate TG.

[0172] Inside the wiring structure 47, there are a wiring film 46 formed in a predetermined pattern, and n n + -type regions 43 of the transfer gates TG to TG are electrically connected to the wiring film 46. The conductive contact plug 45 is formed. Since the n transfer gates TG to TG in the pixel block 12 (i, j) are electrically connected to the wiring film 46 by the contact plugs 45, the transfer gates TG to TG are common nodes. 13 is connected in parallel.

[0173] In the substrate 40, the element isolation insulating film 41 and the substrate 40 are arranged in the up and down direction so as to overlap with the element isolation insulating film 41 adjacent to the n + type regions (source and drain regions) 43 of the transfer gates TG to TG. (K X m) through-holes are formed (in a direction perpendicular to the main surface of the substrate 40). ing. The entire inner wall of the portion of the through hole that contacts the Si portion of the substrate 40 is covered with an insulating film 24. The inside of the through hole (the inside of the insulating film 24 and the inside of the element isolation insulating film 41) is filled with a conductive material such as polysilicon, and the conductive material forms the embedded wiring 23. The upper end of the embedded wiring 23 also exposes the surface force of the substrate 40 (element isolation insulating film 41), and is connected to the lower end of the conductive contact plug 23a formed inside the wiring structure 47. The upper end of the conductive contact plug 23 a is connected to a wiring film 46 formed inside the wiring structure 47. Therefore, the embedded wiring 23 is electrically connected to the corresponding wiring film 46 through the conductive contact plug 23a. As a result, the n + type regions (source and drain regions) 43 of the n transfer gates TG to TG of the pixel block 12 (i, j) are correspondingly embedded as in the circuit configuration shown in FIG. The wiring 23 is electrically connected in common. At the lower end of each embedded wiring 23, the back surface force of the substrate 40 is also exposed, and mechanically and electrically connected to the corresponding bump electrode 90 across the lower end!

[0174] In the lower semiconductor circuit layer 22, an element isolation insulating film 61 is formed in a predetermined pattern on the surface region of the p-type single crystal Si substrate 60, whereby a predetermined number of elements for the reset transistor T r are formed. Region, element region for a predetermined number of amplification transistors Tr, and a predetermined number of elements.

RST AMP

Element regions for the select transistors Tr to Tr are formed. Here one pixel

SEL1 SELn

The configuration corresponding to block 12 (i, j) will be described.

As shown in FIG. 8, the reset transistor Tr includes a gate electrode 63 and the gate electrode 63.

RST

And a pair of n + -type regions (source and drain regions) 62 formed on both sides of the MOS transistor. The gate electrode 63 is electrically connected to the corresponding reset line 31 via the wiring in the wiring structure 74 formed on the surface of the substrate 60. Here, the wiring structure 74 includes a wiring conductor formed on the surface of the substrate 60 and an insulating body that includes the wiring conductor, and does not include a gate insulating film and a gate electrode existing on the surface of the substrate 60 (this). The same applies to the following embodiments). One n + type region 62 (source / drain region) has a corresponding bump through the conductive contact plug 68, the wiring film 72, the conductive contact plug 74a, and the wiring film 75 formed in the wiring structure 74. Electrically connected to electrode 90. As a result, one source 'drain region of the reset transistor Tr corresponds to the corresponding one.

RST

The corresponding common node 13 (pixel block) of the upper semiconductor circuit layer 21 through the embedded wiring 23 12 (i, j)) (see Fig. 6). The reset voltage V is applied to the other n + type region 62 (source / drain region) via a wiring (not shown).

RST

[0176] The amplification transistor Tr is formed on both sides of the gate electrode 65 with the gate electrode 65 interposed therebetween.

AMP

A MOS transistor force including a pair of n + type regions (source / drain regions) 64 is also formed. The gate electrode 65 is electrically connected to the corresponding bump electrode 90 through the conductive contact plug 71, the wiring film 72, the conductive contact plug 74a, and the wiring film 75 formed inside the wiring structure 74. Yes. As a result, the gate electrode of the amplification transistor Tr

AMP

Is electrically connected to the corresponding common node 13 (pixel block 12 (i, j)) of the upper semiconductor circuit layer 21 through the corresponding embedded wiring 23 (see FIG. 6). One n + type region 64 (source / drain region) is electrically connected to the wiring film 73 formed in the wiring structure 74 through the conductive contact plug 69 formed in the wiring structure 74. It is connected to the. The power supply voltage V is applied to the other n + type region 64 (source / drain region) via a wiring (not shown).

CC

[0177] Each of the n selection transistors Tr 1 to Tr 4 includes a gate electrode 67 and a gate electrode 6

SELl SELn

A MOS transistor force including a pair of n + -type regions (source and drain regions) 66 formed on both sides of 7 is also formed. One n + type region (source / drain region) 66 is connected to one of the corresponding amplifying transistors Tr via the conductive contact plug 70, the wiring film 73, and the conductive contact plug 69 formed in the wiring structure 74. N + region (source '

AMP

Drain region) 64 is electrically connected! The other n + type region (source / drain region) 66 is connected to the corresponding output terminal of the image sensor 2. The gate electrode 67 is electrically connected to the output selection line 39 via a wiring formed inside the wiring structure 74. The corresponding output selection is applied to the gate electrode 67 of the selection transistors Tr to Tr.

SELl SELn

Predetermined output selection signals φ to φ are applied via selection lines 39, respectively.

SELl SELn

In the image sensor 2 according to the fifth embodiment, as shown in FIG. 8, two adjacent selection transistors, for example, Tr and Tr, are formed in the same element region. This is fortune-telling

SELl SEL2

This is to make the area as small as possible. In the element region, three n + regions (source and drain regions) 66 are formed in parallel at a predetermined distance, and the central n + region 66 is shared by the two selection transistors Tr and Tr. is doing. And shared

SELl SEL2 N-type region 66 is electrically connected to one n-type region 64 of the corresponding amplification transistor Tr.

AMP

Connected with care. Each non-shared n + region 66 is connected to the corresponding output terminal.

[0179] The n + type region 43 in the upper semiconductor circuit layer 21 and the n + type region 62 in the lower semiconductor circuit layer 22

(These are electrically interconnected via the embedded wiring 23) is a function of the FD (floating diffusion) region, that is, the signal charge accumulated in the photodiodes PD to PD by photoelectric conversion. Has the function of converting to a signal!

[0180] The method of forming the internal structures of the upper semiconductor circuit layer 21 and the lower semiconductor circuit layer 22 is well known in the art, and a description thereof will be omitted.

[0181] As described above, the image sensor 2 according to the fifth embodiment shown in FIGS. 6 and 8 is an application of the sensor circuit 1B of the third embodiment shown in FIG. (k X m) pixel blocks 12 (each block 12 includes n pixels 11) and (k X m) embedded wirings 23 are formed in the upper semiconductor circuit layer 21, and ( (k X m) reset transistors Tr, (k X m) amplifier transistors Tr, and (k X m) selected transistor groups Tr

RST AMP SEL1

~ Tr is formed in the lower semiconductor layer 22 and further, the embedded wiring 23 and the bump electrode 90

SELn

The pixel block 12 in the upper semiconductor circuit layer 21 is electrically connected to the corresponding reset transistor Tr and amplification transistor Tr in the lower semiconductor circuit layer 22 via

RST AMP

ing.

[0182] The upper main surface of the lower semiconductor circuit layer 22 (the surface of the wiring structure 74) is formed below the upper main surface of the upper semiconductor circuit layer 21 (the back surface of the substrate 40) by the bump electrode 90 and the adhesive 91. Since both are electrically and mechanically connected to each other, the circuit layers 21 and 22 form a two-stage semiconductor laminated structure (three-dimensional structure).

Therefore, for the same reason as described for the sensor circuit 1B of the third embodiment described above, the signal charges for all the pixels 11 are substantially simultaneously accumulated (substantially simultaneous shirt tie). It is possible to image a subject that moves at a high speed that causes image distortion in a conventional CMOS image sensor.

[0184] Further, each pixel 11 of the pixel block 12 only needs to include one photodiode and one gate element (MOS transistor). Compared to a conventional CMOS image sensor including three or four MOS transistors, it can achieve a high pixel aperture ratio (eg, about 60%) and can reduce the size of the pixel 11 itself. It becomes possible.

[0185] Furthermore, since a higher pixel aperture ratio than that of a conventional CMOS image sensor can be realized, the total area of the light receiving region (opening portion of each photodiode) with respect to the total area of the imaging region on the surface of the upper semiconductor circuit layer 21 is reduced. It becomes possible to increase the ratio.

[0186] (Sixth embodiment)

FIG. 7 is a circuit diagram showing the circuit configuration of the main part of the addressing type image sensor 2A according to the sixth embodiment of the present invention, and FIG. 9 is a cross-sectional view of the main part showing the actual structure of the image sensor 2A. FIG. This image sensor 2A uses the sensor circuit 1C of the fourth embodiment described above (see FIG. 5). The upper semiconductor circuit layer 21 and the lower semiconductor circuit layer 22 ′ are stacked to form a two-stage three-dimensional stack. It is structured. This image sensor 2A corresponds to the image sensor according to the third aspect of the present invention.

[0187] The overall configuration and operation of the image sensor 2A are the same as those shown in FIG. Therefore, the explanation about them is omitted. In addition, the circuit configuration shown in FIG. 7 corresponds to the sensor circuit 1C of the fourth embodiment shown in FIG. 5 (n selected transistors at the output terminal of each amplification transistor Tr).

AMP

Transistors Tr to Tr are connected, and the output side of these selection transistors Tr to Tr

SEL1 SELn SEL1 SELn is connected to storage capacitors C to C and output transistors Tr to Tr, respectively.

ST1 STn OUT1 OUTn), the same reference numerals are assigned to the same elements, and descriptions thereof are omitted. However, in the image sensor 2A, as will be described later, the common node 13 of each pixel block 12 formed in the upper semiconductor circuit layer 21, the reset transistor Tr and the amplification transistor Tr formed in the lower semiconductor circuit layer 22 ′. Node 14 that is the connection point of

RST AMP

Since the well-known embedded wiring 23 is used for air connection, the embedded wiring 23 and the parasitic resistance R and the parasitic capacitances C and C generated by the embedded wiring 23 are additionally shown in FIG.

0 01 02

Has been. One embedded wiring 23 is provided for each pixel block 12 (that is, n pixels 11).

[0188] Next, the actual structure of the image sensor 2A will be described with reference to FIG.

[0189] As is apparent from FIG. 9, the image sensor 2A includes the upper semiconductor circuit layer 21 and the lower semiconductor. The circuit layer 22 'is mechanically and electrically connected using the embedded wiring 23, the fine bump electrode 90, and an electrically insulating adhesive (for example, polyimide) 91. .

[0190] The upper semiconductor circuit layer 21 has the same configuration as that of the image sensor 2 (see FIG. 8) of the fifth embodiment described above. & 111) 12 pixel blocks & 11) Xm pixels 11 and (k X m) embedded wirings 23 are formed. Since the internal configuration of the upper semiconductor circuit layer 21 is the same as that of the image sensor 2 of the fifth embodiment described above, the same reference numerals as those in the case of the fifth embodiment are given and detailed description thereof is omitted.

[0191] The lower semiconductor circuit layer 22 'has substantially the same configuration as the lower semiconductor circuit layer 22 of the image sensor 2 (see Fig. 8) of the fifth embodiment described above, but outputs the storage capacitors C to C and outputs.

ST1 STn The difference is that transistors Tr to Tr are additionally formed. Ie, below

OUT1 OUTn

In the potential semiconductor circuit layer 22 ′, (k X m) reset transistors Tr and (k X m) additional transistors are provided.

RST

In addition to the width transistor Tr and (k X m) sets of selection transistor groups Tr to Tr, (k

AMP SEL1 SELn

Xm) sets of storage capacitor groups C to C and (kXm) sets of output transistor groups Tr

ST1 STn OUT1

~ Tr is additionally formed.

OUTn

As shown in FIG. 9, in the lower semiconductor circuit layer 22 ′, the element isolation insulating film 61 is formed in a predetermined pattern in the surface region of the p-type single crystal Si substrate 60, thereby Element regions for a number of reset transistors Tr and a number of elements for amplifying transistors Tr

RST AMP

Region, a predetermined number of selection transistors Tr to Tr, storage capacitors C to C and

Element regions for SEL1 SELn ST1 STn and output transistors Tr to Tr are formed. Here is one

OUT1 OUTn

A configuration corresponding to the pixel block 12 (i, j) will be described.

[0193] The configuration of the reset transistor Tr is the same as that of the image sensor 2 of the fifth embodiment (Fig. 8).

RST

The MOS transistor force including a gate electrode 63 and a pair of n + type regions (source / drain regions) 62 formed on both sides of the gate electrode 63 is also configured. The electrical connection of the reset transistor Tr is also the image sensor of the fifth embodiment.

RST

This is the same as in case 2 (see Fig. 8).

[0194] The configuration of the amplification transistor Tr is the same as that of the image sensor 2 of the fifth embodiment described above (see Fig. 8).

AMP

The MOS transistor force including the gate electrode 65 and a pair of n + type regions (source / drain regions) 64 formed on both sides of the gate electrode 65 is also configured. It is. The electrical connection of the amplification transistor Tr is also the same as that of the image sensor 2 (

AMP

This is the same as in the case of FIG.

[0195] The configuration of each of the n selection transistors Tr to Tr is the same as that of the fifth embodiment described above.

SEL1 SELn

As in the case of the image sensor 2 (see FIG. 8), the MOS transistor stacker includes a gate electrode 67 and a pair of n + type regions (source and drain regions) 66 formed on both sides of the gate electrode 67. It is configured. A storage capacitor and an output transistor are connected to the MOS transistor so as to have a circuit configuration as shown in FIG.

[0196] For example, for the select transistor Tr, one n + type region (source 'drain)

SEL1

(Region) 66 is one n + type region (source drain) of the corresponding amplifying transistor Tr via the conductive contact plugs 70 and 69 formed in the wiring structure 74 and the wiring film 73.

AMP

Is electrically connected to 64). The gate electrode 67 is electrically connected to the output selection line 39 via a wiring formed inside the wiring structure 74, and the output selection signal φ

S

Is applied. The other n + type region (source / drain region) of select transistor Tr 6

ELI SEL1

6 constitutes a MOS capacitor that functions as a storage capacitor C together with an n + -type region 66a formed on the opposite side of the gate electrode 67a. This n + region 6

ST1

6a is a MOS transistor that functions as an output transistor Tr together with a gate electrode 67b and an n + region 66a formed on the opposite side of the gate electrode 67b from the n + region 66a.

OUT1

Construct a transistor. The gate electrode 67a is at the end of a predetermined potential (usually the power supply voltage V).

CC

Connected to a child or region. The gate electrode 67b is electrically connected to the output control line 39a via a wiring (not shown), and the output control signal φ is applied.

OUT1

Thus, in one element region, the select transistor Tr, the storage capacitor element C,

SEL1 ST1 Output transistor Tr is formed. This is because the other selection transistors Tr to Tr

The same applies to OUT1 SEL2 S.

ELn

[0198] As described above, the image sensor 2 according to the sixth embodiment shown in FIGS. 7 and 9 applies the sensor circuit 1C shown in FIG. 5, and & 111) pixels. Block 12 (each including 11 pixels), (k X m) pairs of transfer gates TG to TG) and (k X m) embedded wirings 23 are formed in the upper semiconductor circuit layer 21 In addition, (k X m) reset transistors Tr, (k X m) amplifier transistors Tr, and (k X m) sets of selection transistors

RST AMP Storage Capacitor Groups C to C and (kX m) Sets of Transistor Groups Tr to Tr and (kX m) Sets

SEL1 SELn ST1 STn

Output transistor groups Tr to Tr are formed in the lower semiconductor layer 22 ′ and further embedded.

OUT1 OUTn

Via the embedded wiring 23 and the bump electrode 90, the pixel block 12 in the upper semiconductor circuit layer 21 and the reset transistor Tr and amplification transistor Tr in the lower semiconductor circuit layer 22 ′ are connected.

RST AMP

Are electrically interconnected.

[0199] The main surface above the lower semiconductor circuit layer 22 '(the surface of the wiring structure 74) is formed on the main surface below the upper semiconductor circuit layer 21 (the back surface of the substrate 40) by the bump electrode 90 and the adhesive 91. ) Are electrically and mechanically connected to each other, so that both circuit layers 21 and 22 'constitute a two-stage semiconductor laminated structure (three-dimensional structure).

[0200] Therefore, for the same reason as explained for the sensor circuit 1C of the fourth embodiment (see Fig. 5), it is possible to store signal charges for all the pixels 11 substantially simultaneously (substantially simultaneous shirt tying). In addition, it is possible to capture a subject that moves at high speed without causing image distortion in a conventional CMOS image sensor.

[0201] Since each pixel 11 in the pixel block 12 only needs to include one photodiode and one gate element (MOS transistor), three to four pixels are arranged in one pixel. Compared to a conventional CMOS image sensor including MOS transistors, a high pixel aperture ratio (for example, about 60%) can be realized, and the size of the pixel 11 itself can be reduced.

[0202] Furthermore, since a higher pixel aperture ratio than a conventional CMOS image sensor can be realized, the total area of the light receiving region (opening portion of each photodiode) with respect to the total area of the imaging region on the surface of the upper semiconductor circuit layer 21 It becomes possible to increase the ratio.

[0203] Further, output transistors Tr to Tr are controlled by output control signals φ to φ.

OUTl OUTn OUT1 OUTn

As a result, the transfer gates TG to TG and the selection transistor groups T r to Tr in the pixel block 12 can be output to the column signal line 37 at different timings.

SEL1 SELn

Therefore, it is possible to obtain an effect that imaging can be performed at a higher speed than the image sensor 2 of the fifth embodiment.

[0204] (Seventh embodiment)

FIG. 10 shows the main part of the addressing type image sensor 2B according to the seventh embodiment of the invention. FIG. 11 is a circuit diagram showing a circuit configuration, and FIG. 11 is a cross-sectional view of a principal part showing an actual structure of the image sensor 2B. This image sensor 2B uses the sensor circuit 1C of the fourth embodiment (see FIG. 5). The upper semiconductor circuit layer 21A and the lower semiconductor circuit layer 22A ′ are stacked to form a two-dimensional three-dimensional image sensor 2B. It is a laminated structure. The image sensor 2B corresponds to the image sensor according to the third aspect of the present invention.

[0205] The overall configuration and operation of the image sensor 2B are the same as those shown in FIG. Therefore, the description regarding them is omitted. The circuit configuration shown in FIG. 10 is the same as the sensor circuit 1C of the fourth embodiment in FIG. 5 except that the embedded wiring 23 is added. The description is omitted.

As is apparent from FIGS. 10 and 11, the image sensor 2B includes an upper semiconductor circuit layer 21A and a lower semiconductor circuit layer 22A ′, an embedded wiring 23, a fine bump electrode 90, and an electrically insulating material. It is configured to be mechanically and electrically connected using an adhesive 91. The configuration is that the image sensor 2A of the sixth embodiment (see FIGS. 7 and 9) is formed in the lower semiconductor circuit layer 22 ′, and (k X m) reset transistors Tr are connected to the upper semiconductor circuit layer 21. inside

RST

It corresponds to the transferred one. That is, the upper semiconductor circuit layer 21A includes (k X n) X m photodiodes (that is, (k X m) photodiode groups PD to PD) and (k X n) X m photodiodes. Transfer gates (that is, (k X m) pairs of transfer gates TG to TG), (k X m) reset transistors Tr, and (k X m) embedded wirings 23 are formed.

RST

The Since the configurations of the photodiodes PD to PD and the transfer gates TG to TG are the same as those of the image sensor 2A of the sixth embodiment, description thereof will be omitted.

As shown in FIG. 11, the reset transistor Tr includes the gate electrode 49 and the gate electrode 4

RST

A MOS transistor force including a pair of n + type regions (source / drain regions) 48 formed on both sides of 9 is also formed. The gate electrode 49 is electrically connected to the corresponding reset line 31 via the wiring in the wiring structure 47 formed on the surface of the substrate 40. One n + type region 48 (source and drain region) is supported by the conductive contact plug 50, the wiring film 46, the conductive contact plug 23a, and the embedded wiring 23 formed in the wiring structure 47. The bump electrode 90 is electrically connected. As a result, the source “drain region” of the reset transistor Tr corresponds to the corresponding amplification transistor of the lower semiconductor circuit layer 22A. It is electrically connected to the gate electrode 65 of the transistor Tr. Reset run

AMP

The other n + type region 48 (source / drain region) of the transistor Tr

RST

_C reset voltage V is applied to

RST

[0208] The lower semiconductor circuit layer 22A 'includes (k X m) amplifier transistors Tr and (k X m) pairs.

AMP

Selected transistor groups Tr to Tr and (k X m) sets of memory capacitor groups C to C

SEL1 SELn ST1 STn and (k X m) sets of output transistor groups Tr to Tr are formed. This configuration is

OUT1 OUTn

This corresponds to a configuration in which (k × m) reset transistors Tr are removed from the lower semiconductor circuit layer 22 ′ of the sixth embodiment (see FIGS. 7 and 9). Amplifying transistor Tr and select transistor

RST AMP

Since the configuration of the transistors Tr to Tr is the same as that of the sixth embodiment,

SEL1 SELn

The description is omitted.

[0209] As described above, the image sensor 2B according to the seventh embodiment shown in FIGS. 10 and 11 is an application of the sensor circuit 1C (see FIG. 5) of the fourth embodiment. (k X m) pixel blocks 12 (each block 12 includes n pixels 11), (k X m) transfer gate groups TG to TG) and (k X m) reset transistors Tr ( k X m) buried

1 n RST

The embedded wiring 23 is formed in the upper semiconductor circuit layer 21A, and (k X m) amplification transistors Tr and (k X m) sets of selection transistor groups Tr to Tr and (k X m) sets are used for storage. Yong

AMP SEL1 SELn

Quantum element groups C to C and (k X m) output transistor groups Tr to Tr

ST1 STn OUT1 OUTn

The reset transistor Tr in the upper semiconductor circuit layer 21 and the amplification transistor in the lower semiconductor circuit layer 22A ′ are formed in the body layer 22A ′ and further passed through the embedded wiring 23 and the bump electrode 90.

RST

Connect the transistor Tr electrically.

AMP

[0210] In addition, the upper main surface (surface of the wiring structure 74) of the lower semiconductor circuit layer 22A is separated from the lower main surface (back surface of the substrate 40) by the bump electrode 90 and the adhesive 91. Both circuit layers 21A and 22A constitute a two-stage semiconductor multilayer structure (three-dimensional structure).

[0211] Therefore, for the same reason as described for the sensor circuit 1C of the fourth embodiment, signal charges for all the pixels 11 can be substantially simultaneously accumulated (substantially simultaneous chattering), and a conventional CMOS can be used. An object that moves at high speed without causing image distortion in the image sensor can be captured. [0212] Since each pixel 11 in the pixel block 12 only needs to include one photodiode and one gate element (MOS transistor), three to four pixels can be arranged in one pixel. Compared to a conventional CMOS image sensor including MOS transistors, a high pixel aperture ratio (for example, about 60%) can be realized, and the size of the pixel 11 itself can be reduced.

[0213] Furthermore, since a higher pixel aperture ratio than a conventional CMOS image sensor can be realized, the total area of the light-receiving region (opening portion of each photodiode) relative to the total area of the imaging region on the surface of the upper semiconductor circuit layer 21A It is possible to increase the ratio of.

[0214] Further, output transistors Tr to Tr are controlled by output control signals φ to φ.

OUTl OUTn OUT1 OUTn

SEL1 SELn

Storage capacitors C to C and output transistors Tr to Tr

ST1 STn OUTl OUTn

There is also an effect that high-speed imaging is possible.

[0215] (Eighth embodiment)

FIG. 12 is a cross-sectional view of the main part showing the actual structure of the addressing type image sensor 2C according to the eighth embodiment of the present invention. This image sensor 2C is the same as the output of the storage capacitors C to C in the image sensor 2B of the seventh embodiment described above (see FIGS. 10 and 11).

ST1 STn Corresponds to the one without transistors Tr to Tr. This image sensor 2C

OUTl OUTn

This corresponds to the addressing type image sensor according to the third aspect of the present invention.

As is apparent from FIG. 12, the image sensor 2C according to the eighth embodiment includes an upper semiconductor circuit layer 21A and a lower semiconductor circuit layer 22A, an embedded wiring 23, a fine bump electrode 90, and an electrical isolation. It is configured to be mechanically and electrically connected using an edge adhesive 91. The configuration of the upper semiconductor circuit layer 21A is the same as that of the image sensor 2B of the seventh embodiment. The configuration of the lower semiconductor circuit layer 22A is such that the memory capacitors C to C and the output transistors Tr to Tr are deleted from the lower semiconductor circuit layer 22A ′ of the image sensor 2B of the seventh embodiment.

ST1 STn OUTl OUTn Equivalent to the configuration divided by OUTn.

[0217] As described above, in the image sensor 2C according to the eighth embodiment, the signal charges of all the pixels 11 are reduced for the same reason as described in the image sensor 2B of the seventh embodiment. Substantially simultaneous storage (substantially simultaneous shirting) is possible, and a moving subject can be imaged at high speed without causing image distortion in a conventional CMOS image sensor.

[0218] Since each pixel 11 in the pixel block 12 only needs to include one photodiode and one gate element (MOS transistor), three to four pixels can be arranged in one pixel. Compared to a conventional CMOS image sensor including MOS transistors, a high pixel aperture ratio (for example, about 60%) can be realized, and the size of the pixel 11 itself can be reduced.

[0219] Furthermore, since a higher pixel aperture ratio than a conventional CMOS image sensor can be realized, the total area of the light receiving region (opening portion of each photodiode) with respect to the total area of the imaging region on the surface of the upper semiconductor circuit layer 21A It is possible to increase the ratio of.

[0220] (Ninth embodiment)

FIG. 13 is a circuit diagram showing the circuit configuration of the main part of the addressing type image sensor 2D according to the ninth embodiment of the present invention, and FIG. 14 is a cross-sectional view of the main part showing the actual structure of the image sensor 2D. . This image sensor 2D uses the sensor circuit 1C of the fourth embodiment (see FIG. 5). The upper semiconductor circuit layer 21B and the lower semiconductor circuit layer 22B ′ are stacked to form a two-stage three-dimensional stack. It is structured. The image sensor 2B corresponds to the image sensor according to the third aspect of the present invention.

[0221] The overall configuration and operation of the image sensor 2D are the same as those shown in FIG. 1, and the circuit configuration shown in FIG. 13 is the same as that shown in FIG. This is the same as the sensor circuit 1C of the fourth embodiment in FIG.

As is apparent from FIGS. 13 and 14, the image sensor 2D includes an upper semiconductor circuit layer 21B and a lower semiconductor circuit layer 22B ′, an embedded wiring 23, a fine bump electrode 90, and an electrically insulating material. It is configured to be mechanically and electrically connected using an adhesive 91. The configuration is such that (k X m) amplifying transistors Tr formed in the lower semiconductor circuit layer 22A ′ in the image sensor 2B of the seventh embodiment (see FIGS. 10 and 11) are connected to the upper semiconductor circuit.

AMP

Corresponds to that transferred into layer 21A.

That is, the upper semiconductor circuit layer 21B has (k X n) X m photodiodes (ie, That is, (k X m) sets of photodiode groups PD to PD), (k X n) X m transfer gates (that is, (k X m) sets of transfer gate groups TG to TG), (K X m) reset transistors Tr, (k X m) amplifier transistors Tr, and (k X m) embedded wirings 23

RST AMP

Is formed. The configuration of the photodiodes PD to PD, transfer gates TG to TG, and reset transistor Tr is the same as that of the image sensor 2B of the seventh embodiment.

RST

Therefore, the description regarding them is omitted.

[0224] As shown in FIG. 14, the amplification transistor Tr includes a gate electrode 53 and a gate electrode 53.

AMP

And a pair of n + -type regions (source and drain regions) 52 formed on both sides of the MOS transistor. The gate electrode 53 is connected to the reset transistor Tr and the transformer via the conductive contact plug 54 and the wiring film 46 formed in the wiring structure 47.

RST

Fagates are electrically connected to TG to TG. One n + type region 52 (source / drain region) is supported through the conductive contact plug 55, the wiring film 56, the conductive contact plug 23a, and the buried wiring 23 formed in the wiring structure 47. The bump electrode 90 is electrically connected. As a result, the source / drain region of the amplification transistor Tr

AMP

Area corresponds to the corresponding selection transistor Tr in the lower semiconductor circuit layer 22B ′.

One of SEL1 to Tr

This means that it is electrically connected to the SELn n + region 66 (source and drain regions). The other n + type region 52 (source / drain region) of the amplifying transistor Tr is connected to

AMP

Then, the power supply voltage V is applied.

CC

[0225] The lower semiconductor circuit layer 22B 'includes (k X m) sets of select transistor groups Tr T

SEL1-r,

SELn

(k X m) sets of memory capacitor groups C to C and (k X m) sets of output transistor groups Tr

ST1 STn OU

~ Tr is formed. This configuration is the same as that of the seventh embodiment (see FIGS. 10 and 11).

Tl OUTn

Lower semiconductor circuit layer 22A 'and others (k X m) amplifying transistors Tr are removed

AMP

Equivalent to. Select transistor Tr

SEL1 to Tr and memory capacitor C

SELn ST1 to C and output traffic

The structure of STn transistor Tr is

OUT1 to Tr are the same as in the seventh embodiment.

OUTn

The explanation about it is omitted.

As described above, the image sensor 2D according to the ninth embodiment shown in FIGS. 13 and 14 is an application of the sensor circuit 1C (see FIG. 5) of the fourth embodiment, ( k x m) pixel blocks 12 (each block 12 contains n pixels 11) and (k X m) Sfagate group TG to TG) and (k X m) reset transistors Tr

RST

Form width transistor Tr and (k X m) buried wirings 23 in upper semiconductor circuit layer 21B

AMP

In addition, (k X m) sets of selection transistor groups Tr to Tr and (k X m) sets of memory capacity

SEL1 SELn

Quantum element groups C to C and (k X m) output transistor groups Tr to Tr

ST1 STn OUT1 OUTn

The amplification transistor Tr in the upper semiconductor circuit layer 21B and the selection transistor in the lower semiconductor circuit layer 22B ′ are formed in the body layer 22B ′ through the embedded wiring 23 and the bump electrode 90.

AMP

Transistors Tr to Tr are electrically interconnected.

SEL1 SELn

[0227] The upper main surface (the surface of the wiring structure 74) of the lower semiconductor circuit layer 22B 'is formed on the lower main surface (the back surface of the substrate 40) by the bump electrode 90 and the adhesive 91. The circuit layers 21B and 22B 'constitute a two-stage semiconductor multilayer structure (three-dimensional structure).

Therefore, for the same reason as described for the sensor circuit 1C of the fourth embodiment, signal charges for all the pixels 11 can be substantially simultaneously accumulated (substantially simultaneous chattering), and a conventional CMOS can be used. An object that moves at high speed without causing image distortion in the image sensor can be captured.

[0229] Since each pixel 11 in the pixel block 12 only needs to include one photodiode and one gate element (MOS transistor), three to four pixels can be arranged in one pixel. Compared to a conventional CMOS image sensor including MOS transistors, a high pixel aperture ratio (for example, about 60%) can be realized, and the size of the pixel 11 itself can be reduced.

[0230] Furthermore, since a higher pixel aperture ratio than the conventional CMOS image sensor can be realized, the total area of the light receiving region (opening portion of each photodiode) with respect to the total area of the imaging region on the surface of the upper semiconductor circuit layer 21B It becomes possible to increase the ratio.

[0231] Further, output transistors Tr to Tr are controlled by output control signals φ to φ.

OUTl OUTn OUT1 OUTn

SEL1 SELn

Storage capacitors C to C and output transistors Tr to Tr

ST1 STn OUTl OUTn

There is also an effect that high-speed imaging is possible. [0232] (Tenth embodiment)

FIG. 15 is a cross-sectional view of the principal part showing the actual structure of the addressing type image sensor 2E according to the tenth embodiment of the present invention. The image sensor 2E includes storage capacitors C to C in the image sensor 2C of the ninth embodiment described above (see FIGS. 13 and 14).

ST1 STn Corresponds to the transistor transistors Tr to Tr deleted. This image sensor 2E

OUT1 OUTn

As is apparent from FIG. 15, the image sensor 2 イメージ of the tenth embodiment includes an upper semiconductor circuit layer 21B and a lower semiconductor circuit layer 22Β, embedded wiring 23, fine bump electrodes 90, and electrical insulation. The adhesive 91 is used to mechanically and electrically connect. The configuration of the upper semiconductor circuit layer 21B is the same as that of the image sensor 2D of the ninth embodiment. The structure of the lower semiconductor circuit layer 22Β is composed of the storage capacitor elements C to C and the output transistors Tr to Tr from the lower semiconductor circuit layer 22B ′ of the image sensor 2D of the ninth embodiment.

ST1 STn OUT1 OUTn Same as deleted configuration.

[0234] As described above, in the image sensor 2E according to the tenth embodiment, for the same reason as described in the image sensor 2D according to the ninth embodiment, the signal charges of all the pixels 11 are substantially equal. Simultaneous storage (substantially simultaneous shirting) is possible, and it is possible to image a subject moving at high speed without causing image distortion in a conventional CMOS image sensor.

[0235] Further, each pixel 11 of the pixel block 12 only needs to include one photodiode and one gate element (MOS transistor), so three or four pixels can be arranged in one pixel. Compared to a conventional CMOS image sensor including MOS transistors, a high pixel aperture ratio (for example, about 60%) can be realized, and the size of the pixel 11 itself can be reduced.

[0236] Furthermore, since a higher pixel aperture ratio than a conventional CMOS image sensor can be realized, the total area of the light receiving region (opening portion of each photodiode) with respect to the total area of the imaging region on the surface of the upper semiconductor circuit layer 21B It becomes possible to increase the ratio.

[0237] (Eleventh embodiment)

FIG. 16 shows the main part of the addressing type image sensor 2F according to the eleventh embodiment of the present invention. FIG. 17 is a cross-sectional view of the main part showing the actual structure of the image sensor 2F. This image sensor 2F uses the sensor circuit 1C of the fourth embodiment (see FIG. 5). The upper semiconductor circuit layer 21C and the lower semiconductor circuit layer 22C ′ are stacked to form a two-stage three-dimensional stack. It is structured. The image sensor 2F corresponds to an image sensor according to the third aspect of the present invention.

[0238] The overall configuration and operation of the image sensor 2F are the same as those shown in FIG. 1, and the circuit configuration shown in FIG. 16 is the same as that shown in FIG. 5 except that an embedded wiring 23 is added. This is the same as the sensor circuit 1C of the fourth embodiment.

As is apparent from FIGS. 16 and 17, the image sensor 2F includes an upper semiconductor circuit layer 21C and a lower semiconductor circuit layer 22C ′, an embedded wiring 23, a fine bump electrode 90, and an electrically insulating layer. It is configured to be mechanically and electrically connected using an adhesive 91. The configuration is such that (k X m) sets of transfer gate groups TG to TG formed in the upper semiconductor circuit layer 21 in the image sensor 2A according to the sixth embodiment (see FIGS. 7 and 9), It corresponds to the one moved into the lower semiconductor circuit layer 22 ′. Therefore, the upper semiconductor circuit layer 21C includes (k X n) X m photodiodes (that is, (k X m) sets of photodiode groups PD to PD) and (k X m) embedded wirings. Only 23 are formed.

[0240] The configuration of the photodiodes PD to PD is almost the same as that of the image sensor 2A of the sixth embodiment (see Figs. 7 and 9), but one photodiode is provided in each element region of the substrate 40. Is different. For example, in the case of the photodiode PD, as shown in FIG. 17, an n + region 42 is formed over the entire surface of one of a plurality of element regions formed on the surface region of the p-type substrate 40 by the element isolation insulating film 41. The n + region 42 forms the photodiode PD. In the substrate 40, a through-hole penetrating the element isolation insulating film 41 and the substrate 40 in the vertical direction (in a direction perpendicular to the main surface of the substrate 40) is formed at an appropriate position overlapping the element isolation insulating film 41. The entire inner wall of the through hole in contact with the substrate 40 is covered with an insulating film 24. The inside of the through hole (the inside of the insulating film 24 and the inside of the element isolation insulating film 41) is filled with a conductive material, and the conductive material forms the embedded wiring 23. The upper end of the embedded wiring 23 is exposed from the surface of the substrate 40 (element isolation insulating film 41) and is connected to the lower surface of the wiring film 57 formed inside the wiring structure 47. Has been. Since the lower surface of the wiring film 57 is also connected to the surface of the corresponding n + region 42, the n + region 42 is electrically connected to the embedded wiring 23. The lower end of the embedded wiring 23 is exposed from the back surface of the substrate 40 (element isolation insulating film 41) and is mechanically and electrically connected to the corresponding bump electrode 90 !.

[0241] The lower semiconductor circuit layer 22C 'includes (k X m) sets of transfer gate groups TG to TG, and (k

X m) reset transistors Tr, (k X m) amplifier transistors Tr, and (k X m

RST AMP

) Sets of memory capacitor groups C to C and (k X m) sets of output transistor groups Tr to Tr

ST1 STn OUT1 is formed. Reset transistor Tr, amplification transistor Tr and memory capacity

OUTn RST AMP

The quantum elements C to C and the output transistors Tr to Tr are the same as those in the sixth embodiment.

ST1 STn OUT1 OUTn

Since it has the same configuration as that of the disensor 2A (see FIGS. 7 and 9), the same elements are denoted by the same reference numerals and the description thereof is omitted. In FIG. 17, the storage capacitive elements C to C and

ST1 STn Output transistors Tr to Tr are omitted.

OUT1 OUTn

[0242] The transfer gates TG to TG have the following configuration. For example, with regard to the transfer gate TG, as shown in FIG. 17, a MOS transistor including a gate electrode 77 and a pair of n + type regions (source and drain regions) 76 formed on both sides of the gate electrode 77 is sandwiched. Jistaka et al. A transfer gate control signal φ is applied to the gate electrode 77 via a wiring (not shown). One n + region 76 (source and drain regions)

T1

The conductive bumps 90 are electrically connected to the corresponding bump electrodes 90 through the conductive contact plugs 78, 80 and 82 formed in the line structure 74 and the wiring films 79, 81 and 83. As a result, the source / drain region of the transfer gate TG is electrically connected to the corresponding photodiode PD of the upper semiconductor circuit layer 21 C through the buried wiring 23. The other n + type region 76 (source / drain region) of the MOS transistor is amplified with the corresponding reset transistor Tr via a conductive contact plug 78 formed inside the wiring structure 74 and a wiring film (not shown). It is electrically connected to the transistor Tr.

RST AMP

The transfer gates TG to TG have the same structure as the transfer gate TG. this

2 n 1

In this way, the transfer gates TG to TG in the lower semiconductor circuit layer 22C ′ are electrically connected to the photodiodes PD to PD in the upper semiconductor circuit layer 21C through the embedded wiring 23, respectively. [0243] As described above, the image sensor 2F according to the eleventh embodiment shown in FIGS. 16 and 17 is an application of the sensor circuit 1C (see FIG. 5) of the fourth embodiment. (K X m) pixel blocks 12 (each block 12 includes n pixels 11) and (k X m) embedded wirings 23 are formed in the upper semiconductor circuit layer 21C, and (k X m) thread gate transfer gate group TG to TG), (k X m) reset transistors Tr and (k X m) amplification transistors

1 n RST

Transistor Tr and (k X m) set of select transistor groups Tr to Tr and (k X m) set of memory

AMP SEL1 Capacitance element group for SELn C to C and (k X m) output transistor group Tr to Tr

ST1 STn OUT1 OUTn Formed in the semiconductor circuit layer 22C ', and further through the embedded wiring 23 and the bump electrode 90, the pixel block 12 in the upper semiconductor circuit layer 21C and the lower semiconductor circuit layer 22C' The transfer gates TG to TG are electrically interconnected.

Further, the main surface above the lower semiconductor circuit layer 22C ′ (the surface of the wiring structure 74) is formed on the main surface below the upper semiconductor circuit layer 21C (the back surface of the substrate 40) by the bump electrode 90 and the adhesive 91. Both circuit layers 21C and 22C constitute a two-stage semiconductor multilayer structure (three-dimensional structure).

[0246] Also, each pixel 11 of the pixel block 12 includes only one photodiode, so that one pixel includes three or four MOS transistors in addition to the photodiode, compared to a conventional CMOS image sensor. Therefore, a high pixel aperture ratio (for example, about 60%) can be realized, and the size of the pixel 11 itself can be reduced. In particular, it can be made smaller than in the case of the fifth to tenth embodiments.

[0247] Furthermore, since a higher pixel aperture ratio than a conventional CMOS image sensor can be realized, the total area of the light receiving region (opening portion of each photodiode) with respect to the total area of the imaging region on the surface of the upper semiconductor circuit layer 21C It is possible to increase the ratio of. In particular, it can be made higher than in the case of the fifth to tenth embodiments.

[0248] Further, output transistors Tr to Tr are controlled by output control signals φ to φ.

OUT1 OUTn OUT1 OUTn As a result, the transfer gates TG to TG and the selection transistor groups T r to Tr in the pixel block 12 can be output to the column signal line 37 at different timings.

SEL1 SELn

Storage capacitors C to C and output transistors Tr to Tr

ST1 STn OUT1 OUTn

There is also an effect that high-speed imaging is possible.

[0249] (Twelfth embodiment)

FIG. 18 is a cross-sectional view of the principal part showing the actual structure of the addressing type image sensor 2G according to the twelfth embodiment of the present invention. This image sensor 2G is the same as the image sensor 2F of the eleventh embodiment described above (see FIGS. 16 and 17), with the lower semiconductor circuit layer 22C ′ being left as it is, and the substrate 40 in the upper semiconductor circuit layer 21C being turned upside down. Corresponds to the orientation. This image sensor 2G corresponds to the addressing type image sensor according to the third aspect of the present invention.

As is apparent from FIG. 18, the image sensor 2G according to the twelfth embodiment includes an upper semiconductor circuit layer 21D and a lower semiconductor circuit layer 22D ′, a fine bump electrode 90, and an electrically insulating adhesive. 91 and mechanically and electrically connected. The configuration of the lower semiconductor circuit layer 21 D ′ is the same as that of the lower semiconductor circuit layer 21 C ′ of the image sensor 2F of the eleventh embodiment. In this image sensor 2G, unlike the above-described fifth to eleventh embodiments, the embedded wiring 23 is not used.

[0251] In the upper semiconductor circuit layer 21D, the substrate 40 is turned upside down with respect to the upper semiconductor circuit layer 21C of the image sensor 2F of the eleventh embodiment, the wiring structure 47 is on the lower side, and the substrate 40 is on the upper side. Is located. Since external light passes through the substrate 40 and is irradiated to the photodiodes PD to PD, the thickness of the substrate 40 is made thinner than in the case of the image sensor 2F of the eleventh embodiment.

[0252] Inside the wiring structure 47, there are conductive contact plugs 58 electrically and mechanically connected to the respective surfaces of the plurality of n + type regions 42 constituting the photodiodes PD to PD, and those A plurality of wiring films 59 that are electrically and mechanically connected to the conductive contact plug 58 are formed. These wiring films 59 are disposed in the vicinity of the surface of the wiring structure 47 and are electrically and mechanically connected to the corresponding bump electrodes 90. In this way, the photodiodes PD to PD correspond to the corresponding bump electrodes. The corresponding transfer gates TGi and TGj in the lower semiconductor circuit layer 22D ′ are electrically connected through 90.

[0253] Since the image sensor 2G according to the twelfth embodiment shown in FIG. 18 has the above-described configuration, the same effect as described in the image sensor 2F according to the eleventh embodiment can be obtained. Is clear.

[0254] (Thirteenth embodiment)

FIG. 20 is a diagram showing a main circuit configuration of the sensor circuit 3 according to the thirteenth embodiment of the present invention. FIG. 19 is a functional block diagram showing the overall configuration of an addressing type image sensor in which the sensor circuit 3 is used. This sensor circuit 3 corresponds to the sensor circuit according to the second aspect of the present invention.

The overall configuration of the image sensor of FIG. 19 is the addressing type image sensor shown in FIG. 1 except that each reset line 31 is provided through k pixel blocks 12a belonging to the same column. Is identical to that of That is, (k X n) X m pixels 11a arranged in a matrix of (k X n) rows and m columns are provided. In each pixel block 12a, n pixels 11a belonging to the same column are grouped and connected in parallel to a common node (not shown in FIG. 19, corresponding to the common node 13a in FIG. 20).

[0256] In each pixel block 12a, m reset lines 31 each extending along a corresponding column of the pixel matrix are formed so as to penetrate through the pixel block 12a belonging to the column. Each reset line 31 is connected to one reset transistor for each pixel 11a. In other words, the n transistors 11a belonging to the pixel block 12a are connected to the reset transistor Tr.

RST1

~ Tr are provided. The amplification transistor T is connected to each pixel block 12a.

RSTn AMP

One is provided for each. n reset transistor groups T to Tr are the corresponding pixels

RST1 RSTn

An amplifying transistor T is arranged in each of the n pixels 11a in the block 12a.

AMP

Are arranged outside the corresponding pixel block 12a.

[0257] Each reset line 31 is used to reset the signal charge of the pixel 1la in the k pixel blocks 12a belonging to the corresponding column. The reset voltage V to those pixels 11a

RST

The application is performed using the corresponding reset transistors T to Tr. Each amplification run

RST11 RSTn

The register T increases the signal read from the pixel l la in the corresponding pixel block 12a.

AMP Width is used to send to the corresponding column signal line 37. Each amplification transistor Tr

A

The signals amplified in (1) are sent to the corresponding column signal lines 37 in order.

MP

[0258] Except for the configuration of the pixel 11a and the pixel block 12a and the arrangement of the reset line 31, it is the same as the configuration of FIG.

Next, a sensor circuit 3 according to a thirteenth embodiment used for an image sensor having the configuration of FIG. 19 will be described with reference to FIG. FIG. 20 shows a circuit configuration of two pixel blocks 12a (i, j) and 12a (i + 1, j) belonging to the j-th column.

[0260] The upper pixel block 12 (i, j) includes pixels 11 belonging to the [ _n x (i−1) +1] row to the (n X i) row of the j-th column. The lower pixel block 12 (i + 1, j) includes pixels 11 belonging to the [n X i + 1] row to the [n X (i + 1)] row of the j th column. Since these two pixel blocks 12 (i, j) and 12 (i + 1, j) have the same configuration, in the following description, the upper pixel block 12 (i, j) will be mainly described.

[0261] The pixel block 12a (i, j) includes n pixels 11a. In other words, _n photodiodes PD to PD, n transfer gates TG to TG, and n reset transistors Tr to Tr are included. Each pixel 11a has one photo diode

RSTl RSTn

And one transfer gate and one reset transistor. Each of the transfer gates TG to TG is composed of a MOS transistor. Reset transistor Tr

1 n RSTl

Each of .about.Tr is also composed of MOS transistors. Photodiode PD ~ P

RSTn 1

Each anode of D is one source of the corresponding one of the transfer gates TG to TG 'the drain region and one source of the corresponding one of the reset transistors Tr to Tr'

RSTl RSTn

The force sword is connected in common to a terminal or region having a predetermined potential (usually ground potential). Reset transistor T to Tr

RSTl RSTn The other source 'drain region is connected to the reset voltage source (reset voltage = v)

RST

Yes. The other source'drain region of each of the transfer gates TG to TG is commonly connected to the common node 13a. Thus, the n pixels 1 la in the pixel block 12a (i, j) are connected in parallel to the common node 13a in the pixel 11a.

[0262] The common node 13a of the pixel block 12a (i, j) is the gate of the corresponding amplification transistor T.

AMP

Connected to the electrode. The amplification transistor T is provided outside the pixel block 12a (i, j).

AMP I was kicked. One source / drain region of the amplification transistor T is connected to a DC power source (electrical

AMP

Source voltage = v), and the other source / drain region (output side)

CC

It is connected to the output terminal of block 12 (i, j) (ie, the corresponding column signal line 37). The output terminal (source-drain region on the output side) of the amplification transistor T is connected via a resistor R

AMP

It is connected to a terminal of a predetermined potential (usually ground potential), and constitutes a source follower type amplifier. The power at which parasitic capacitance is generated at node 15 is omitted in FIG.

[0263] The source-drain region on the output side of the amplification transistor T is connected to the corresponding column signal line 37.

AMP

It is connected. Therefore, the output signal of the amplification transistor T, i.e.

AMP

The serial (time-series) output signals of the photodiodes PD to PD are sequentially sent to the corresponding CDS circuit 36. Then, when sent from the CDS circuit 36 to the horizontal signal line 33, the column signal line 37 is selected via the m column selection signals 38 by the scanning of the horizontal scanning circuit 35, whereby the serial output signal is Sent to horizontal signal line 33. Thereafter, the signal is sent to an output terminal (not shown) of the image sensor provided at one end (right end in FIG. 19) of the horizontal signal line 33.

[0264] All the pixel blocks 12a other than the pixel block 12a (i, j) have the same configuration as the pixel block 12a (i, j). The serial output signals of the photodiodes PD to PD are sent to the output terminal of the image sensor. Thus, the subject can be imaged.

[0265] Next, the operation of the image sensor including the sensor circuit 3 having the above-described configuration (signal charge generation / accumulation ability up to signal output) will be described.

[0266] 1. Global reset of all pixels (all photodiodes)

First, the transfer gate control signal applied to the gate electrodes of the n MOS transistors constituting the transfer gates TG to TG (first gate elements) provided for the photodiodes PD to PD of all the pixels 11a. Let H be the logical state of φ to φ

Tl Tn

Transfer gates TG to TG are turned on.

[0267] Next, in that state, a reset control signal applied in common to the gate electrodes of the reset transistors Tr to Tr provided for each of the pixels 11a in each pixel block 12a

RST1 RSTn

The logic state of φ is set to H, and all reset transistors Tr to Tr are turned on.

RST RST1 RSTn To do. As a result, the photodiodes of all the pixels 11a are passed through a predetermined reset voltage V 1S node 15.

RST

The diodes are applied simultaneously to PD PD. Thus, a batch reset of all the pixels 11a, that is, a “global reset” is performed. At this time, the gain of all amplifying transistors Tr

AMP

The voltage at the gate electrode is also reset.

[0268] 2. Exposure (charge accumulation)

Next, the transfer gate control signal φ to be applied to the transfer gates TG to TG

1 n T1

The logic state of Φ is set to L, and all transfer gates TG to TG are turned off.

Tn I n

At the same time, the logic state of the reset control signal φ

RST

The transistors Tr to Tr are also shut off.

RST1 RSTn

[0269] After that, in this state, the photodiodes PD to PD of all the pixels 11a are irradiated with light, and signal charges are generated and accumulated in all the photodiodes PD to PD collectively. The irradiation time is usually several hundred μsec to ¾Cmsec.

[0270] At the same time as signal charge generation 'accumulation is completed, reset control signal φ

The logic state of RST is set to H, all reset transistors Tr to Tr are turned on at once, and

RST1 RSTn

The logic state of the gate control signals φ to φ is H, and all the transfer gates TG to TG are

Tl Tn I n Turns on. After a predetermined time (for example, 1 μsec), the reset control signal φ

The RST logic state is set to L again and all reset transistors Tr to Tr are turned off at once.

RST1 RSTn

At the same time, the transfer gate control signals φ to φ

Tl Tn The logic state is set to L again to turn off all the transfer gates TG to TG. Thus, the reset voltage V is temporarily applied to all the common nodes 13a (that is, the gate electrodes of all the amplifying transistors Tr) to

AMP RST

Set (reset) the gate voltage of the transistor Tr to the specified reference voltage.

AMP

[0271] 3. Reading and amplifying the signal

A signal proportional to the amount of charge generated and accumulated in all the photodiodes PD to PD as described above is read out from each pixel 11a and amplified in the form of voltage as follows.

That is, first, when one pixel block 12a is selected by the vertical scanning circuit 34 and the horizontal scanning circuit 35, n transfer gate control signals φ in the pixel block 12a are selected.

Tl

Change the logic state of ~ φ to L force H in order, and turn on transfer gates TG ~ TG in order

Go to Tn I n state. These conduction states are maintained for a predetermined time (for example, 0.1 μsec). After that, the logical state is returned to L in order. In this way, all the photodiodes PD to PD in the pixel block 12 are also read out in time series as the signal force 14. In the meantime, all the reset transistors Tr to Tr are held in the cut-off state.

RST1 RSTn

[0273] The amplification transistor Tr connected to the node 13a in the source follower form is the gate of the amplification transistor Tr.

AMP

Since the electrode is connected to the node 13a, the signal read out to the node 13a is immediately amplified by the amplification transistor Tr. The amplified signal is then transferred to the amplification transistor.

AMP

The source / drain region force on the output terminal side of the transistor Tr is output toward the column signal line 37.

AMP

The

[0274] When reading and amplifying a signal from n pixels l la in the pixel block 12a, that is, the photodiode PD to PD force, the signal of one pixel 11a (for example, photodiode PD) force is read out. As described above, after the amplification is completed and before reading of the signal of the next pixel 11a (for example, photodiode PD) starts,

2

The reset voltage V is applied to the node 1 by turning on the reset transistor Tr.

RST1 RST

3a is temporarily applied, so that the node 13a (the gate electrode of the amplification transistor Tr)

AMP

It is necessary to set (reset) the reference potential. Otherwise, the influence of the signal from the previous pixel l la (for example, photodiode PD) may remain and an error may occur in the signal of the next pixel 11a (for example, photodiode PD). It is.

2

[0275] Since there are n pixels 11a (n photodiodes PD to PD) in the pixel block 12a, the total number of read operations by the transfer gate control signals φ to φ is η times.

Tl Τη

The total number of amplification operations by the amplification transistor Tr is n.

AMP AMP

The total number of set operations is n.

[0276] Specifically, for example, first, the first transfer gate TG of the pixel block 12a is temporarily turned on, and the signal proportional to the signal charge accumulated in the first photodiode PD. To node 13a. The signal is immediately amplified by the amplification transistor Tr, and the obtained amplified signal is sent to the column signal line 37. Continued

AMP

The reset transistor Tr connected to this photodiode PD is temporarily turned on.

1 RST1

The reset voltage V is temporarily applied to the node 13a, so that the amplification transistor Tr

RST AM

Reset the gate electrode (node 14) to the reference potential. [0277] After that, the second transfer gate TG of the pixel block 12a is temporarily turned on.

2

A signal proportional to the signal charge stored in the second photodiode PD.

2

Read to mode 13a. The signal is immediately amplified by the amplifying transistor Tr and obtained.

AMP

The amplified signal is sent to the column signal line 37. Next, contact the photodiode PD.

2 The connected reset transistor Tr is temporarily turned on, and the amplification transistor Tr

Reset the gate electrode (node 14) of RST2 A to the reference potential. In addition, the third photodio

MP

The same operation as above is repeated in order, such as PD and fourth photodiode PD.

3 4

The Finally, when the read operation and amplification operation for the nth photodiode PD are executed, the processing for the pixel block 12a is completed.

In the image sensor of FIG. 1, the amplification transistor Tr corresponding to the pixel block 12a

AMP

Since there is only one output terminal, n signals from which all the photodiodes PD to PD in the pixel block 12a can also be obtained are connected to the source terminal n AMP on the output terminal side of the amplification transistor Tr.

The rain region force is also output in sequence toward the column signal line 37 in time series. In other words, the signal output from the pixel block 12a is a signal in which n pulse waveforms reflecting the amount of signal charges (the amount of irradiated light) of the photodiodes PD to PD are connected at a predetermined interval. One serial signal.

[0279] Since the image sensor (see Fig. 19) has a total of (kXm) pixel blocks 12a, the above-described operation is repeated (kXm) times while all the pixels 11a are scanned. It will be.

[0280] A signal output from the pixel block 12a, that is, one serial signal in which n pulses are connected at a predetermined interval, is sent to a known sample 'and' hold circuit or AZD conversion circuit. Predetermined signal processing is performed.

[0281] The current realistic maximum shatter speed (that is, the shortest signal charge accumulation period) is (1Z80 00) seconds (= 125 sec). Therefore, for each of the (kXm) pixel blocks 12a, the node 13a (of the amplifying transistor Tr) is formed by the reset transistors Tr to Tr.

RSTl RSTn AMP gate electrode) reset operation required number of times (that is, n times) (total reset time) and the time from all the pixels 11a (photodiodes PD to PD) in the pixel block 12a Time required to amplify the signal with the corresponding amplification transistor Tr (total amplification time) N times (total number of pixels 11a in each pixel block 12a) so that it is sufficiently smaller than the shortest signal charge accumulation period (= 125 sec) Is set, signal charge accumulation (exposure) is performed substantially simultaneously on the pixels 11a (photodiodes PD to PD) belonging to all the pixel blocks 12a. In other words, the signal charges for all the pixels 11a can be accumulated substantially simultaneously (substantially simultaneous shirting).

[0282] In addition, each power of all pixel blocks 12a outputs (k X m) output serial signals independently, so that these output serial signals are processed by analog-digital (AZD) conversion and the like. Can be done in parallel. Therefore, data processing can be performed at a higher speed than that in the conventional CMOS image sensor. This also contributes to the realization of practical simultaneous shirting.

As is clear from the above-described operation, when viewed within one frame, the serial output signal output from each pixel block 12a is generated at the beginning of the scanning period as the closer to the end of the scanning period, ' The charge accumulation period is slightly longer than the output one. For this reason, when it is desired to obtain image data with higher fidelity or to increase the n value, a known circuit that performs signal correction in accordance with the change in the charge accumulation period may be provided in the subsequent stage. This is because the influence of fluctuations in the charge accumulation period can be suppressed or avoided.

[0284] By enabling simultaneous shirting in this manner, it is possible to capture a subject moving at high speed without causing image distortion in a conventional CMOS image sensor. .

[0285] Furthermore, since a common amplification transistor Tr is provided outside the pixel block 12a for each pixel block 12a, each pixel 11a in the pixel block 12a is assigned to one pixel block 12a.

AMP

It only needs to include one photodiode, one gate element (MOS transistor) and one reset transistor (MOS transistor). Therefore, a high pixel aperture ratio (for example, about 60%) can be realized as compared with a conventional CMOS image sensor that includes three or four MOS transistors in addition to a photodiode in one pixel. This pixel aperture ratio includes only one photodiode and one gate element in the first embodiment. Compared to an image sensor using the sensor circuit 1 (see Fig. 1 and Fig. 2), it is lower by the reset transistor.

In the conventional CMOS image sensor, signal processing is performed serially in accordance with the number of scanning lines. Therefore, a force that requires a high-speed AZD conversion circuit is required. In the image sensor used, the processing speed of each serial output signal of the amplification transistor Tr is increased by setting the n value to be smaller than the number of scanning lines and increasing the parallelism.

AMP

[0287] In addition, n output signal powers of n photodiodes PD to PD force are output from each of the amplification transistors Tr in a serially connected form, so that the amplification transistor Tr

AMP AM

P

[0288] (Fourteenth embodiment)

FIG. 21 is a circuit diagram showing the circuit configuration of the main part of the addressing type image sensor 4 according to the fourteenth embodiment of the present invention, and FIG. 23 is a cross-sectional view of the main part showing the actual structure of the image sensor 4. . The image sensor 4 includes an amplification transistor Tr provided for each pixel block 12a in the sensor circuit 3 (see FIG. 20) of the thirteenth embodiment described above.

AMP

In the source and drain regions on the output side, n select transistors Tr to Tr (second gate

SELl SELn

Device) and n output signals from n photodiodes PD to PD amplified are output in parallel via select transistors Tr to Tr

SELl SELn

A sensor circuit is used, and the upper semiconductor circuit layer 21E and the lower semiconductor circuit layer 22E are stacked to form a two-stage three-dimensional stacked structure. The image sensor 4 corresponds to the image sensor according to the fourth aspect of the present invention, and the sensor circuit used therein corresponds to the sensor circuit according to the second aspect of the present invention.

[0289] The overall configuration and operation of the image sensor 4 are the same as those shown in FIG. 19, and a description thereof will be omitted. The circuit configuration of FIG. 21 is obtained by adding n selection transistors Tr to Tr (second gate elements) to the sensor circuit 3 of the thirteenth embodiment of FIG.

SELl SELn

(There is no storage capacitor and no output transistor), so the same elements as in FIG. However, this image sensor 4 The common node 13a of each pixel block 12a formed in the semiconductor circuit layer 21E is electrically connected to the gate electrode of the amplification transistor Tr formed in the lower semiconductor circuit layer 22E.

AMP

In order to continue, since the well-known embedded wiring 23 is used, the embedded wiring 23 and the parasitic resistance R and the parasitic capacitances C and C caused by the embedded wiring 23 are added to FIG.

0 01 02

The One embedded wiring 23 is provided for each pixel block 12a (ie, n pixels 11a).

Next, the actual structure of the image sensor 4 will be described.

As is apparent from FIG. 23, the image sensor 4 includes an upper semiconductor circuit layer 21E and a lower semiconductor circuit layer 22E, embedded wiring 23, fine bump electrodes 90, and an electrically insulating adhesive. 91, and mechanically and electrically connected.

[0292] In the upper semiconductor circuit layer 21E, (kXm) pixel blocks 12a, that is, (kXn) Xm pixels 11a are formed. Therefore, the upper semiconductor circuit layer 21E includes (kXn) Xm photodiodes (that is, (kXm) photodiode groups PD to PD) and (k Xn) Xm transfer gates (that is, (kXm) groups. Transfer gate groups TG to TG) and (kXn) Xm reset transistors (that is, (kXm) sets of reset transistor groups Tr 1 to Tr 3). The upper semiconductor circuit layer 21E further includes (kX

RST1 RSTn

m) The embedded wiring 23 is formed.

[0293] The lower semiconductor circuit layer 22E includes (kXm) amplifying transistors Tr and (kXn) Xm

AMP

Select transistors (that is, (kXm) sets of select transistor groups Tr to Tr)

SEL1 SELn is formed.

[0294] In the upper semiconductor circuit layer 21E, the element isolation insulating film 41 is formed in a predetermined pattern on the surface region of the p-type single crystal Si substrate 40, so that the layout of FIG. (KXn) Xm element regions are formed in a matrix. Each of these element regions corresponds to one pixel 11a.

[0295] Inside the element region corresponding to the pixel block 12a (i, j), n photodiodes PD

~ PD, n transfer gates TG ~ TG, n reset transistors Tr ~

I n I n RST1

Tr is formed. For example, the photodiode PD is a p-type as shown in FIG.

RSTn 1

N + region 42 formed on substrate 40 (ie p-n junction photodiode) Is). The transfer gate TG is formed of a MOS transistor including a gate electrode 44 and an n + type region 43 facing the n + type region 42 with the gate electrode 44 interposed therebetween. Since the transfer gate TG shares the n + type region 42 of the photodiode PD, it is electrically connected to the anode of the photodiode PD of one source'drain region force of the transfer gate TG. The gate insulating film existing between the gate electrode 44 and the surface of the substrate 40 is omitted in FIG. The gate electrode 44 is electrically connected to the corresponding read control line 32 via the wiring in the wiring structure 47 formed on the surface of the substrate 40.

[0296] The reset transistor Tr is composed of a gate electrode 49 and an n + type sandwiching the gate electrode 44 therebetween.

RST1

This is formed by a MOS transistor including an n + type region 43a facing the region 42. The reset transistor Tr shares the n + region 42 of the photodiode PD.

RST1 1

Therefore, one source / drain region of the reset transistor Tr is connected to the photodiode PD.

RST1

Being electrically connected to the anode of this, it is quite different. The n + type region 43a (source / drain region) is applied with a reset voltage V via a wiring (not shown).

RST

[0297] Other photodiodes PD to PD and transfer gate TG to TG and reset transistor

2 n 2 n

Tr to Tr are the photodiode PD, transfer gate TG, and reset transistor, respectively.

RST2 RSTn 1 1 Has the same configuration as the transistor Tr.

RST1

[0298] Inside the wiring structure 47, there are n wiring films 46 formed in a predetermined pattern and n n + type regions 43 of the transfer gates TG to TG are electrically connected to the wiring film 46. The conductive contact plug 45 is formed. Since the n transfer gates TG to TG in the pixel block 12a (i, j) are electrically connected to the wiring film 46 by the contact plugs 45, the transfer gates TG to TG are common. This means that it is connected to node 13a in parallel.

[0299] The n + type region 43 in the upper semiconductor circuit layer 21E is a function of the FD (floating diffusion) region, that is, a function of converting the signal charge accumulated in the photodiodes PD to PD into a voltage signal by photoelectric conversion. have.

[0300] The element isolation insulating film 41 and the substrate 40 are placed on the substrate 40 at a position overlapping the element isolation insulating film 41 adjacent to the n + type regions (source and drain regions) 43 of the transfer gates TG to TG. There are (k X m) through holes penetrating downward (in a direction perpendicular to the main surface of the substrate 40). The entire inner wall of the portion of the through hole in contact with the substrate 40 is covered with the insulating film 24. The inside of the through hole (the inside of the insulating film 24 and the inside of the element isolation insulating film 41) is filled with a conductive material, and the conductive material forms the embedded wiring 23. The upper end of the embedded wiring 23 is exposed from the surface of the substrate 40 (element isolation insulating film 41) and is connected to the lower end of the conductive contact plug 23a formed inside the wiring structure 47. . The upper end of the conductive contact plug 23 a is connected to a wiring film 46 formed inside the wiring structure 47. Therefore, the embedded wiring 23 is electrically connected to the corresponding wiring film 46 through the conductive contact plug 23a. As a result, the n + type regions (source and drain regions) 43 of the n transfer gates TG to TG of the pixel block 12a (i, j) correspond to the corresponding embedded wirings 23 as in the circuit configuration shown in FIG. Are electrically connected to each other. At the lower end of each embedded wiring 23, the back surface force of the substrate 40 is also exposed, and mechanically and electrically connected to the corresponding bump electrode 90 at the lower end.

[0301] In the lower semiconductor circuit layer 22E, the element isolation insulating film 61 is formed in a predetermined pattern on the surface region of the p-type single crystal Si substrate 60, and accordingly, a predetermined number of amplification transistors T r are used. An element area and an element area for a predetermined number of select transistors Tr to Tr are formed.

AMP SEL1 SELn

It is made. Here, the configuration corresponding to one pixel block 12a (i, j) will be described.

[0302] The amplification transistor Tr is formed on both sides of the gate electrode 65 with the gate electrode 65 interposed therebetween.

AMP

Is electrically connected to the corresponding common node 13 a (pixel block 12 a (i, j)) of the upper semiconductor circuit layer 21 via the corresponding embedded wiring 23 (see FIG. 21). . One n + type region 64 (source / drain region) is electrically connected to the wiring film 73 formed in the wiring structure 74 through the conductive contact plug 69 formed in the wiring structure 74. It is connected to the. The other n + type region 64 (source / drain region) has a layout (not shown). The supply voltage V is applied via the line.

CC

[0303] Each of the n selection transistors Tr 1 to Tr 4 includes a gate electrode 67 and a gate electrode 6

SELl SELn

A MOS transistor force including a pair of n + -type regions (source and drain regions) 66 formed on both sides of 7 is also formed. One n + type region (source / drain region) 66 is connected to one n + type region (source) of the corresponding amplifying transistor Tr via the conductive contact plug 70 and the wiring film 73 formed in the wiring structure 74. 'Drain region) 64 to electrical

AMP

It is connected to the. The gate electrode 67 is electrically connected to the output selection line 39 via a wiring formed inside the wiring structure 74. Select transistor Tr to Tr gate

The SELl SELn electrode 67 has a predetermined output selection signal φ to φ via the corresponding output selection line 39.

SELl SEL is applied respectively.

[0304] As described above, the image sensor 4 according to the fourteenth embodiment shown in FIG. 23 applies the sensor circuit shown in FIG. 21, and includes (k X m) sets of photodiode groups. PD to PD and (k X m) transfer gate groups TG to TG and (k X m) reset transistor groups Tr to Tr and (k X m) embedded wirings 23 are connected to the upper semiconductor circuit layer 21E. Formed in

RST1 RSTn

In addition, (k X m) amplifying transistors Tr and (k X m) selection transistor groups Tr

AMP

~ Tr are formed in the lower semiconductor layer 22E, and the embedded wiring 23 and the bump

SELl SELn

Via the pole 90, the pixel block 12a (transfer gate group T G to TG) in the upper semiconductor circuit layer 21E and the amplification transistor Tr in the lower semiconductor circuit layer 22E are electrically interconnected.

1 n AMP

It continues.

[0305] The main surface above the lower semiconductor circuit layer 22E (the surface of the wiring structure 74) is formed on the main surface below the upper semiconductor circuit layer 21E (the back surface of the substrate 40) by the bump electrode 90 and the adhesive 91. Since the circuit is electrically and mechanically connected, both circuit layers 21E and 22E form a two-stage semiconductor stacked structure (three-dimensional structure).

Therefore, for the same reason as described for the sensor circuit 3 of the thirteenth embodiment, signal charges for all the pixels 11a can be substantially simultaneously accumulated (substantially simultaneous shirting), and a conventional CMOS can be used. An object that moves at high speed without causing image distortion in the image sensor can be captured.

[0307] Each pixel 11a of the pixel block 12a includes one photodiode and one gate element ( MOS transistor) and one reset transistor (MOS transistor) only need to be included, so the pixel aperture is higher than that of a conventional CMOS image sensor that includes three or four MOS transistors in addition to a photodiode in one pixel. The rate (for example, about 60%) can be realized, and the force can also reduce the size of the pixel 1 la itself.

[0308] Furthermore, since a higher pixel aperture ratio than that of a conventional CMOS image sensor can be realized, the total area of the light receiving region (opening portion of each photodiode) with respect to the total area of the imaging region on the surface of the upper semiconductor circuit layer 21E. It is possible to increase the ratio of.

[0309] (Fifteenth embodiment)

FIG. 22 is a circuit diagram showing the circuit configuration of the main part of the addressing type image sensor 4A according to the fifteenth embodiment of the present invention, and FIG. 24 is a cross-sectional view of the main part showing the actual structure of the image sensor 4A. is there. This image sensor 4A includes n selection transistors Tr in the sensor circuit (see FIG. 21) used in the image sensor 4 of the fourteenth embodiment described above.

SE

~ Tr storage elements C to C and output transistors Tr on the output side of Tr

LI SELn ST1 STn OU

~ Tr

A sensor circuit to which Tl OUTn is additionally connected is used, and an upper semiconductor circuit layer 21E and a lower semiconductor circuit layer 22E ′ are stacked to form a two-stage three-dimensional stacked structure. This image sensor 4Α corresponds to the image sensor according to the fourth aspect of the present invention.

[0310] As is apparent from FIG. 24, the image sensor 4A has an upper semiconductor circuit layer 21E and a lower semiconductor circuit layer 22E ', an embedded wiring 23, a fine bump electrode 90, and an electrically insulating adhesive. It is configured to be mechanically and electrically connected using the agent 91.

[0311] Since the upper semiconductor circuit layer 21E has the same configuration as that of the image sensor 4 (see FIG. 23) of the fourteenth embodiment described above, the same reference numerals as those in the fourteenth embodiment are used for detailed description thereof. Is omitted.

[0312] The lower semiconductor circuit layer 22E 'has substantially the same configuration as the lower semiconductor circuit layer 22Ε of the image sensor 4 of the fourteenth embodiment described above, but the storage capacitor elements C to C and the output capacitor

ST1 STn

The difference is that the transistors Tr to Tr are additionally formed. That is, the lower half

OUT1 OUTn

The conductor circuit layer 22E ′ includes (k X m) amplification transistors Tr and (k X m) sets of selection transistors.

AMP

In addition to the transistor groups Tr to Tr, (k X m) sets of memory capacitor groups C to C and (

SEL1 SELn ST1 STn k X m) sets of output transistor groups Tr to Tr are formed!

OUT1 OUTn [0313] As shown in FIG. 24, in the lower semiconductor circuit layer 22E ', an element isolation insulating film 61 is formed in a predetermined pattern on the surface region of the substrate 60, and thereby a predetermined number of amplification transistors Tr are formed. Element region and a predetermined number of selection transistors Tr to Tr, storage capacity

AMP SEL1 SELn Element areas for elements C to C and output transistors Tr to Tr are formed.

ST1 STn OUT1 OUTn

The

The configuration of the amplification transistor Tr is the same as that of the image sensor 4 of the fourteenth embodiment described above (FIG. 23).

AMP

The MOS transistor force including the gate electrode 65 and a pair of n + type regions (source / drain regions) 64 formed on both sides of the gate electrode 65 is also configured. The electrical connection of the amplifying transistor Tr is the same as that of the image

AMP

This is the same as the case of service 4 (see Fig. 21).

[0315] The configuration of each of the n selection transistors Tr to Tr is the same as that of the fourteenth embodiment described above.

SEL1 SELn

As in the case of the image sensor 4, a MOS transistor including a gate electrode 67 and a pair of n + type regions (source and drain regions) 66 formed on both sides of the gate electrode 67 is also configured. Yes. And, for the MOS transistor, the storage capacitive element C

ST

~ C and output transistor Output transistor Tr ~ Tr and force as shown in Figure 24

1 STn OUT1 OUTn

Connected to form a circuit configuration.

[0316] For example, for the select transistor Tr, one n + type region (source and drain)

SEL1

AMP

S

ELI SEL1

ST1

OUT1

It constitutes a transistor. The gate electrode 67a is connected to a terminal having a predetermined potential (usually a ground potential). The gate electrode 67b is electrically connected to the output control line 39a via a wiring (not shown). And an output control signal Φ is applied.

OUT1

[0317] Thus, in one element region, the selection transistor Tr, the storage capacitor element C, and

The same applies to OUT1 SEL2 S.

ELn

[0318] As described above, the image sensor 4 according to the fifteenth embodiment shown in FIG. 24 applies the sensor circuit shown in FIG. 22, and includes (k X m) sets of photodiode groups. PD to PD and (k X m) transfer gate groups TG to TG and (k X m) reset transistor groups Tr to Tr and (k X m) embedded wirings 23 are connected to the upper semiconductor circuit layer 21E. Formed in

RST1 RSTn

AMP

~ Tr and (k X m) set of storage capacitor elements C ~ C and (k X m) set of output capacitors

SEL1 SELn ST1 STn

Distor groups Tr to Tr are formed in the lower semiconductor layer 22E ′, and embedded wiring 23

OUT1 OUTn

And the bump electrode 90, the transfer gate groups TG to TG in the upper semiconductor circuit layer 21E are electrically connected to the amplification transistor Tr in the lower semiconductor circuit layer 22E ′.

is doing.

[0319] In addition, the upper main surface of the lower semiconductor circuit layer 22E '(the surface of the wiring structure 74) is formed on the lower main surface of the upper semiconductor circuit layer 21E (the back surface of the substrate 40) by the bump electrode 90 and the adhesive 91. The circuit layers 21E and 22E 'form a two-stage semiconductor multilayer structure (three-dimensional structure).

[0320] Therefore, for the same reason as that described for the sensor circuit 3 of the thirteenth embodiment, signal charges for all the pixels 11a can be substantially simultaneously accumulated (substantially simultaneous chattering), and a conventional CMOS can be used. An object that moves at high speed without causing image distortion in the image sensor can be captured.

[0321] Further, each pixel 11a of the pixel block 12a only needs to include one photodiode, one gate element (MOS transistor), and one reset transistor (MOS transistor). In addition, compared to conventional CMOS image sensors that include three or four MOS transistors, it can achieve a high pixel aperture ratio (for example, about 60%) and reduce the size of the pixel 1 la itself. It becomes possible.

[0322] Furthermore, because it can achieve a higher pixel aperture ratio than conventional CMOS image sensors, It is possible to increase the ratio of the total area of the light receiving region (opening portion of each photodiode) to the total area of the imaging region on the surface of the upper semiconductor circuit layer 21E.

[0323] Further, output transistors Tr to Tr are controlled by output control signals φ to φ.

OUTl OUTn OUT1 OUTn can be used to output signals to the column signal line 37 at different timings from the opening and closing of the transfer gates TG to TG and the selection transistor groups Tr to Tr in the pixel block 12a.

SEL1 SELn

Therefore, there is also an effect that imaging can be performed at a higher speed than the image sensor 4 of the fourteenth embodiment.

[0324] (Sixteenth embodiment)

The addressing-type image sensors 2 to 2G according to the fifth to twelfth embodiments described above and the addressing-type image sensors 4 and 4A according to the fourteenth and fifteenth embodiments include two semiconductors whose V-deviation is higher and lower. Although it has a two-layer structure in which circuit layers are laminated, the image sensor of the present invention is not limited to a two-layer structure. It is also possible to stack three or four or more semiconductor circuit layers. As an example, an example composed of upper, middle and lower three semiconductor circuit layers will be described below.

FIG. 28 is a circuit diagram showing the circuit configuration of the main part of the addressing type image sensor 2H according to the sixteenth embodiment of the present invention. FIG. 29 shows the main part of the actual structure of the image sensor 2H. It is sectional drawing. This image sensor 2H uses the sensor circuit 1B (see FIG. 4) of the third embodiment described above, and has the two-stage three-dimensional laminated structure of the fifth embodiment using the sensor circuit 1B. It has almost the same configuration as image sensor 2 (see Fig. 6 and Fig. 8), but the upper semiconductor circuit layer 21F, the middle semiconductor circuit layer 22Fa, and the lower semiconductor circuit layer 22 2Fb are stacked to form a three-dimensional three-dimensional stack. The structure is different in that it is different. This image sensor 2H corresponds to the image sensor according to the second aspect of the present invention.

The configuration of the upper semiconductor circuit layer 21F is the same as that of the upper semiconductor circuit layer 21 (see FIG. 8) of the image sensor 2 of the fifth embodiment described above.

[0327] In image sensor 2, (k X m) sets of reset transistors Tr to Tr and (kX m) amplification transistors T formed in lower semiconductor circuit layer 22 are intermediate semiconductor circuits.

RST1 RSTn AMP layer is formed on 22Fa. Each pixel block 12 in the upper semiconductor circuit layer 21F and the corresponding reset transistor Tr to Tr and amplification transistor in the middle semiconductor circuit layer 22Fa

RST1 RSTn The register T is connected to the corresponding embedded wiring 23 formed in the upper semiconductor circuit layer 21F.

AMP

And are electrically interconnected.

[0328] In the image sensor 2, the (kXm) sets of selection transistors Tr to Tr are formed in the lower semiconductor circuit layer 22 and are formed in the lower semiconductor circuit layer 22Fb. Middle

SEL1 SELn

Each amplification transistor T in the semiconductor circuit layer 22Fa and the lower semiconductor circuit layer 22Fb

AMP

The corresponding selection transistors Tr to Tr are formed in the middle semiconductor circuit layer 22Fa.

SEL1 SELn

Are electrically interconnected via corresponding embedded wiring 23 '.

Next, the actual structure of the image sensor 2H will be described with reference to FIG.

[0330] The configuration of the upper semiconductor circuit layer 21F is the same as that of the upper semiconductor circuit layer 21 (see FIG. 8) of the image sensor 2 of the fifth embodiment described above. The description thereof is omitted.

[0331] The middle semiconductor circuit layer 22Fa is similar to the structure of the lower semiconductor circuit layer 22 of the image sensor 2 (see Fig. 8), and is arranged in a predetermined pattern on the surface region of the p-type single crystal Si substrate 60. A separation insulating film 61 is formed, so that a predetermined number of reset transistors Tr are provided.

RST

An element region and an element region for a predetermined number of amplification transistors Tr are formed.

AMP

[0332] The reset transistor Tr includes a gate electrode 63 and a gate electrode 6 as shown in FIG.

RST

The MOS transistor cover includes a pair of n + -type regions (source and drain regions) 62 formed on both sides of 3. The gate electrode 63 is electrically connected to the corresponding reset line 31 via the wiring in the wiring structure 74 formed on the surface of the substrate 60. One n + type region 62 (source / drain region) has a corresponding bump through the conductive contact plug 68, the wiring film 72, the conductive contact plug 74a, and the wiring film 75 formed in the wiring structure 74. It is electrically connected to the electrode 90. As a result, one source / drain region of the reset transistor Tr is connected to the upper semiconductor via the corresponding buried wiring 23.

RST

It is electrically connected to the corresponding common node 13 (pixel block 12 (i, j)) of the circuit layer 21F (see FIG. 6). The reset voltage V is applied to the other n + type region 62 (source / drain region) via a wiring not shown.

RST

[0333] The amplification transistor Tr is formed on both sides of the gate electrode 65 and the gate electrode 65.

AMP

MOS transistor power including a pair of n + type regions (source / drain regions) 64 formed Has been. The gate electrode 65 is electrically connected to the corresponding bump electrode 90 through the conductive contact plug 71, the wiring film 72, the conductive contact plug 74a, and the wiring film 75 formed in the wiring structure 74. Yes. As a result, the gate electrode of the amplification transistor Tr

AMP

Is electrically connected to the corresponding common node 13 (pixel block 12 (i, j)) of the upper semiconductor circuit layer 21 through the corresponding embedded wiring 23 (see FIG. 6). One n + type region 64 (source / drain region) is connected to the lower semiconductor circuit via the conductive contact plug 69, the wiring film 73, and the conductive contact plug 23a ′ formed in the wiring structure 74. The conductive plug 23 'formed in the layer 22Fb is electrically connected. The power supply voltage V is applied to the other n + type region 64 (source and drain regions) via wiring not shown.

CC

Is done.

In the lower semiconductor circuit layer 22Fb, an element isolation insulating film 61 ′ is formed in a predetermined pattern on the surface region of the p-type single crystal Si substrate 60 ′, and thereby a predetermined number of select transistors Tr˜ An element region for Tr is formed. Select transistor Tr to Tr

Each of SEL1 SELn SEL1 SELn is composed of a MOS transistor including a gate electrode 67 and a pair of n + type regions (source / drain regions) 66 formed on both sides of the gate electrode 67. It has been. One n + type region (source and drain region) 66 is connected to the wiring structure 74 ′ through the conductive contact plug 70, the wiring film 72a, the conductive contact plug 74a ′, and the wiring film 75 ′. It is electrically connected to the corresponding bump electrode 90 '. Therefore, the n + type region (source 'drain region) 66 is connected to one n of the corresponding amplifying transistor Tr via the bump electrode 90' and the conductive plug 23 'in the middle semiconductor circuit layer 22Fa.

AMP

+ Shape region (source / drain region) 64 electrically connected! The other n + type region (source / drain region) 66 is connected to the corresponding output terminal of the image sensor 2. The gate electrode 67 is electrically connected to the output selection line 39 via a wiring formed inside the wiring structure 74 ′. The gate electrode 67 of the selection transistors Tr to Tr

SEL1 SELn

The predetermined output selection signals φ to φ are respectively transmitted via the corresponding output selection lines 39.

SEL1 SELn

Applied.

[0335] The image sensor 2H of the sixteenth embodiment has the actual structure as described above, but the operation and effect thereof are the image sensor 2 of the fifth embodiment described above (see FIGS. 6 and 8). )of It is the same as the case. Therefore, the description regarding them is omitted.

[0336] (Configuration example of storage capacitor)

FIG. 25 to FIG. 27 show a configuration example of the storage capacitor element used in the above-described embodiment. In these figures, they are provided between the select transistor Tr and the output transistor Tr.

SEL1 OUT1

The storage capacitor element c is shown.

ST1

[0337] The storage capacitor C in FIG. 25 (a) is a selective transistor within the p-type Si substrate 60.

ST1

The n + region 66 on the capacitive element C side that forms the star transistor and the output transistor Tr

SEL1 ST1 OUT1 The n + region 66b is formed to connect the n + region 66a on the capacitive element C side.

ST1

It is. By applying a reverse bias between the substrate 60 and the n + region 66b, a pn junction capacitance is generated, which is used as the storage capacitor element C.

ST1

[0338] The storage capacitor C in FIG. 25 (b) has an n + region 66 forming the selection transistor Tr.

ST1 SEL1

And the n + region 66a that forms the output transistor Tr

OUT1

A gate electrode 67a formed above the p-type Si substrate 60. By applying the power supply voltage V to the gate electrode 67a, the n-type or

CC

Since the n + type inversion layer L is generated, it is used as the storage capacitor element C. This

ST1

This is a typical MOS capacitor and is used in each of the embodiments described above.

[0339] The storage capacitor C in FIG. 26 (a) has an n + region 66 that forms the selection transistor Tr.

ST1 SEL1

And the n + region 66a that forms the output transistor Tr

OUT1

A gate electrode 67a formed above the p-type Si substrate 60. Inside the substrate 60, an n + region 66 on the capacitive element C side that forms the selection transistor Tr, and

SEL1 ST1

The n + region 66a on the capacitive element C side that forms the output transistor Tr is removed.

OUT1 ST1

. The end on the capacitive element C side of the gate electrode 67 that forms the selection transistor Tr

SEL1 ST1

It is placed on the gate electrode 67a through an edge film (not shown). Similarly, the end on the capacitive element C side of the gate electrode 67b that forms the output transistor Tr is the gate electrode 67b.

OUT1 ST1

Is placed on the gate electrode 67a via an insulating film (not shown).

[0340] By applying the power supply voltage V to the gate electrode 67a, as in the case of FIG.

CC

An n-type or n + -type inversion layer is generated in the surface area of the plate 60, which is stored in the storage space. Used as ί element C. At this time, the end of the inversion layer on the gate electrode 67 side is selected.

ST1

Functions as an n-type region or n + -type region for transistor Tr. Also, the inversion

SEL1

End force on the gate electrode 67b side of layer n-type region or n + type for output transistor Tr

OUT1

Act as a region. This is a modification of the MOS capacitor.

[0341] The memory capacitor C in FIG. 26 (b) is connected to the gate electrode 67 of the selection transistor Tr and the output.

ST1 SEL1

A gate insulating film (not shown) is interposed between the gate electrodes 67b of the transistor Tr.

OUT1

And a gate electrode 67a formed above the p-type Si substrate 60. Inside the substrate 60, the n + region 66 on the capacitive element C side forming the selection transistor Tr and the output transistor

SEL1 ST1

The n + region 66a on the capacitive element C side forming the star transistor Tr is removed. Gate electrode

OUT1 ST1

One end of 67a is insulated on the gate electrode 67 forming the select transistor Tr

SEL1

The other end forms an output transistor Tr.

OUT1 is placed on the formed gate electrode 67b through an insulating film (not shown).

[0342] By applying the power supply voltage V to the gate electrode 67a, as in the case of FIG.

CC

Since an n-type or n + -type inversion layer is generated in the surface region of the plate 60, it is used as the storage capacitor element C. At this time, the end of the inversion layer on the gate electrode 67 side is selected.

ST1

SEL1

OUT1

Act as a region. This is also a modification of the MOS capacitor.

[0343] The memory capacitor C in FIG. 27 forms the selection transistor Tr inside the substrate 60.

ST1 SEL1 Capacitor that forms the n + region 66 on the C side and the capacitor that forms the output transistor Tr

ST1 OUT1

C side n + region 66a has been removed. Instead, select transistor Tr

ST1 SEL1 n + type region 6 between the gate electrode 67 and the gate electrode 67b of the output transistor Tr

OUT1

6b is formed! The gate electrode 67 of the selection transistor Tr is composed of an n + type region 66 and an n +

SEL1

The gate electrode 67b of the output transistor Tr is disposed between the n type regions 66b

OUT1

It is arranged between 66a and n + type region 66b.

A capacitive element 67aa having a T-shaped cross section is formed on gate electrodes 67 and 67b via a gate insulating film (not shown). This capacitive element 67aa is used as capacitive element C.

ST1 Functional, lower electrode 67aal with a substantially T-shaped cross section and lower electrode 67 The insulating film 67aa2 formed on the aal and the upper electrode 67aa3 formed on the insulating film 67aa2 are in force. The lower end of the lower electrode 67aal extends downward between the gate electrodes 67 and 67b and is in contact with the surface of the n + type region 66b. An appropriate gate voltage V (0 to V) is applied to the upper electrode 67aa3.

G CC

[0345] The storage capacitor element C can have various configurations as described above.

ST1

[0346] (Modification)

The first to sixteenth embodiments described above show specific examples of the present invention. Therefore, the present invention is not limited to these embodiments and departs from the spirit of the present invention. It goes without saying that various modifications can be made without any problem. For example, in most of the above-described embodiments, the upper semiconductor circuit layer and the lower semiconductor circuit layer, or the upper semiconductor circuit layer and the intermediate semiconductor circuit layer, and the intermediate semiconductor circuit layer and the lower semiconductor circuit layer are respectively connected to the bump electrode and the embedded wiring. The force electrically connected to each other using the present invention is not limited to this. As in the twelfth embodiment described above, the upper semiconductor circuit layer and the lower semiconductor circuit layer may be electrically connected to each other using a bump electrode and a wiring film. In short, any structure can be used as long as the upper semiconductor circuit layer and the lower semiconductor circuit layer are electrically connected to each other.

[0347] Further, in most of the above-described embodiments, a two-layer stacked structure including an upper semiconductor circuit layer and a lower semiconductor circuit layer is used, and peripheral circuits of the pixel matrix (vertical scanning circuit 34, horizontal scanning circuit 35, etc.) Is formed in the upper semiconductor circuit layer or the lower semiconductor circuit layer. The present invention is not limited to this. A peripheral circuit of the pixel matrix may be formed inside another semiconductor circuit layer, and the semiconductor circuit layer may be connected to the back surface of the lower semiconductor circuit layer. This is the same even in the case of a three-layer stacked structure consisting of an upper semiconductor circuit layer, a middle semiconductor circuit layer and a lower semiconductor circuit layer, or a stacked structure of four or more layers

In the above-described embodiment, the power of providing one embedded wiring for each pixel block including a plurality of pixels. The present invention is not limited to this. Needless to say, one embedded wiring may be provided for one pixel. This can be realized, for example, by setting the diameter (or one side) of each embedded wiring to about 1 to 0.5 m. Each of the upper semiconductor circuit layer and the lower semiconductor circuit layer may be formed of a single semiconductor wafer or a plurality of semiconductor chips. In other words, the circuit elements to be formed in the semiconductor circuit layer may be collectively formed inside a single semiconductor wafer, or divided into a plurality of semiconductor chips. You can do it.

Industrial application fields

The present invention is applicable to any addressing type image sensor and any sensor circuit used in the image sensor.

Claims

The scope of the claims

[1] A sensor circuit having a plurality of pixels arranged in a matrix and used for an addressing type image sensor that selects each of the pixels by addressing.

In each of the plurality of pixels in the pixel block connected to the common node of each of the plurality of pixel blocks, each of the pixels generates a photoelectric charge that generates a signal charge according to the irradiated light. An amplifying transistor that amplifies a signal to be sent out, and includes the pixel block replacement element and a first gate element provided in a path between the photoelectric conversion element and the common node of the pixel block. A sensor circuit characterized by this.

2. The sensor circuit according to claim 1, wherein the amplification transistor has a single output terminal.

[3] The sensor circuit according to [1], further comprising: a storage capacitive element connected to an output terminal of the amplification transistor; and an output transistor that controls output of a signal stored in the capacitive element.

[4] The amplification transistor has a number of output terminals equal to the total number of the pixels in the pixel block corresponding to the amplification transistor, and a second gate element is connected to each of the output terminals. The sensor circuit according to claim 1.

[5] The apparatus further comprises a plurality of storage capacitors connected to the plurality of output terminals of the amplification transistor, and a plurality of output transistors for controlling the output of signals stored in the capacitors. The sensor circuit according to claim 4.

[6] Before all signal charges are generated and accumulated in all of the pixels, all of the pixels are reset in a batch using all of the reset transistors. The signal corresponding to the signal charge accumulated in the pixel in each pixel block is read out in time series through the corresponding common node and sent to the amplification transistor corresponding to the force. 6. The sensor circuit according to any one of 5 above.

[7] A sensor circuit having a plurality of pixels arranged in a matrix and used for an addressing type image sensor that selects each of the pixels by addressing,

A plurality of pixel blocks configured by connecting a plurality of the pixels to a common node every predetermined number, and a plurality of the pixels in the pixel block connected to the common node of each of the plurality of pixel blocks In each of the pixel blocks, each of the pixels includes a photoelectric conversion element that generates a signal charge according to irradiated light, and the photoelectric conversion element. A reset for resetting the pixel connected to a connection point between the photoelectric conversion element and the first gate element, and a first gate element provided in a path between the pixel block and the common node. A sensor circuit including a transistor.

8. The sensor circuit according to claim 7, wherein the amplification transistor has a single output terminal.

[9] The sensor circuit according to [7], further comprising: a storage capacitive element connected to an output terminal of the amplification transistor; and an output transistor that controls output of a signal stored in the capacitive element.

[10] The amplification transistor has a number of output terminals equal to the total number of the pixels in the pixel block corresponding to the amplification transistor, and a second gate element is connected to each of the output terminals. The sensor circuit according to claim 7.

[11] A plurality of storage capacitor elements respectively connected to the plurality of output terminals of the amplification transistor, and a plurality of output transistors for controlling the output of signals stored in these capacitor elements are further provided. The sensor circuit according to claim 10.

[12] Signal charges are generated collectively for all of the pixels. * Before accumulation, all of the pixels are reset collectively using all of the reset transistors, The signal corresponding to the signal charge accumulated in the pixel in each pixel block is read out in time series via the corresponding common node and sent to the amplification transistor corresponding to the force. : The sensor circuit according to any one of L 1.

[13] An addressing-type image sensor having a three-dimensional stacked structure that has a plurality of pixels arranged in a matrix and selects each of the pixels by addressing.

At least the photoelectric conversion element is formed in a first semiconductor circuit layer constituting the three-dimensional laminated structure, and the first gate element, the reset transistor, and the amplification transistor constitute the three-dimensional laminated structure. An addressing type image sensor characterized in that it is formed in a second, third or later semiconductor circuit layer.

[14] In addition to the plurality of photoelectric conversion elements, a plurality of the first gate elements are formed in the first semiconductor circuit layer, and the plurality of amplification transistors and the plurality of reset transistors are the second or The addressing type image sensor according to claim 13, wherein the addressing type image sensor is formed in a third or later semiconductor circuit layer.

[15] In addition to the plurality of photoelectric conversion elements, a plurality of first gate elements and a plurality of reset transistors are formed in the first semiconductor circuit layer, and a plurality of amplification transistors are provided in the second semiconductor circuit layer. The addressable image sensor according to claim 13, wherein the addressable image sensor is formed in a third or subsequent semiconductor circuit layer!

[16] The amplification transistor is arranged in front of the pixel block corresponding to the amplification transistor. A number of output terminals equal to the total number of pixels, and a second gate element is connected to each of the output terminals,

In addition to the plurality of photoelectric conversion elements, a plurality of first gate elements, a plurality of reset transistors, and a plurality of amplification transistors are formed in the first semiconductor circuit layer, and a plurality of the second photoelectric conversion elements are formed. 14. The addressable image sensor according to claim 13, wherein a gate element is formed in the second or third semiconductor circuit layer.

[17] Only a plurality of the photoelectric conversion elements are formed in the first semiconductor circuit layer, a plurality of the first gate elements, a plurality of the reset transistors, and a plurality of the amplification transistors are the second or the third or later. 14. The addressing type image sensor according to claim 13, wherein the addressing type image sensor is formed in a semiconductor circuit layer.

18. The address designation type image sensor according to claim 13, wherein each of the amplification transistors has a single output terminal.

[19] A storage capacitive element connected to the output terminal of the amplification transistor in the second or third and subsequent semiconductor circuit layers, and an output transistor for controlling the output of a signal stored in the capacitive element The addressable image sensor according to claim 18, further comprising:

[20] Each of the amplification transistors has a number of output terminals equal to the total number of the pixels in the pixel block corresponding to the amplification transistor, and a second gate element is connected to each of the output terminals. 19. The addressable image sensor according to claim 18,

[21] In the second or third and subsequent semiconductor circuit layers, a plurality of storage capacitive elements respectively connected to the plurality of output ends of the amplification transistor, and signals stored in these capacitive elements 21. The addressable image sensor according to claim 20, further comprising a plurality of output transistors for controlling output.

[22] Generating signal charges in all of the pixels collectively * Before accumulating, all of the reset transistors are collectively performed using all of the reset transistors, and in each of the pixel blocks, A signal corresponding to the signal charge accumulated in the pixel is read out in time series through the corresponding common node, and the force The addressing type image sensor according to any one of claims 13 to 21, which is sent to a transistor.

[23] An addressing type image sensor having a three-dimensional stacked structure that has a plurality of pixels arranged in a matrix and selects each of the pixels by addressing.

An amplification transistor that is connected to the common node of each of the plurality of pixel blocks and that amplifies signals transmitted from the plurality of pixels in the pixel block, and in each of the pixel blocks, each of the pixels Includes a photoelectric conversion element that generates a signal charge according to the irradiated light, a first gate element provided in a path between the photoelectric conversion element and the common node of the pixel block, and the photoelectric conversion element. A reset transistor connected to a connection point between the conversion element and the first gate element for resetting the pixel,

At least the photoelectric conversion element is formed in a first semiconductor circuit layer constituting the three-dimensional laminated structure, and the first gate element, the reset transistor, and the amplification transistor constitute the three-dimensional laminated structure. An addressing type image sensor characterized by being formed in a second or later semiconductor circuit layer.

[24] In addition to the plurality of photoelectric conversion elements, a plurality of the first gate elements are formed in the first semiconductor circuit layer, and the plurality of amplification transistors and the plurality of reset transistors are the second or The addressable image sensor according to claim 23, wherein the addressable image sensor is formed in a semiconductor circuit layer after the third!

[25] In addition to the plurality of photoelectric conversion elements, a plurality of the first gate elements and a plurality of the reset transistors are formed in the first semiconductor circuit layer, and a plurality of the amplification transistors are provided in the second semiconductor circuit layer. 24. The addressable image sensor according to claim 23, wherein the addressable image sensor is formed in a semiconductor circuit layer after the third!

[26] The amplifying transistor has a number of output terminals equal to the total number of the pixels in the pixel block corresponding to the amplifying transistor, and each of the output terminals has a second output terminal. The gate element is connected,

In addition to the plurality of photoelectric conversion elements, a plurality of first gate elements, a plurality of reset transistors, and a plurality of amplification transistors are formed in the first semiconductor circuit layer, and a plurality of the second photoelectric conversion elements are formed. 24. The addressable image sensor according to claim 23, wherein a gate element is formed in the second or third and subsequent semiconductor circuit layers.

[27] Only a plurality of the photoelectric conversion elements are formed in the first semiconductor circuit layer, and the plurality of the first gate elements, the plurality of reset transistors, and the plurality of amplification transistors are the second or third and the subsequent. 24. The addressing type image sensor according to claim 23, wherein the addressing type image sensor is formed in a semiconductor circuit layer.

28. The address designation type image sensor according to claim 23, wherein each of the amplification transistors has a single output terminal.

[29] A storage capacitive element connected to an output terminal of the amplification transistor in the second or third and subsequent semiconductor circuit layers, and an output transistor for controlling the output of a signal stored in the capacitive element The addressable image sensor according to claim 28, further comprising:

[30] Each of the amplification transistors has a number of output terminals equal to the total number of the pixels in the pixel block corresponding to the amplification transistor, and a second gate element is connected to each of the output terminals. 24. The addressable image sensor according to claim 23.

[31] In the second or third and subsequent semiconductor circuit layers, a plurality of storage capacitive elements respectively connected to the plurality of output ends of the amplification transistor, and signals stored in these capacitive elements 31. The addressing type image sensor according to claim 30, further comprising a plurality of output transistors for controlling output.

[32] Generating signal charges in all of the pixels collectively * Before accumulating, all of the pixels are reset in a batch using all of the reset transistors, and in each of the pixel blocks, 32. The signal according to any one of claims 23 to 31, wherein a signal corresponding to the signal charge accumulated in the pixel is read out in time series via the corresponding common node and sent to the corresponding amplification transistor. Addressing type image as described in Disensor,