JP6255527B1 - Solid-state imaging device - Google Patents

Abstract

A solid-state imaging device capable of reading out the charge of each pixel even when a row selection wiring fails. A solid-state imaging device 1A includes a light receiving unit 20, a vertical shift register unit 60A, first row selection wirings QA1 to QAM, and second row selection wirings QB1 to QBM. The vertical shift register unit 60A provides common row selection signals VSAm and VSBm to the m-th row selection wirings QAm and QBm. [Selection] Figure 4

Description

  The present invention relates to a solid-state imaging device.

  Patent Document 1 describes a technique related to a radiation imaging apparatus. This apparatus includes a sensor array in which a plurality of pixels including a conversion element that converts radiation from a subject into an electric signal and a transfer switch that transfers the electric signal to the outside are two-dimensionally arranged. In addition, the device includes a plurality of gate lines that connect the pixels of the sensor array in the row direction, and a gate driving device that drives the gate lines to read out electrical signals of the pixels connected to the gate lines. And a plurality of signal lines connecting the pixels of the sensor array in the column direction, and a plurality of amplifiers provided corresponding to the signal lines and amplifying and reading out the electric signals transferred from the transfer switches. .

JP 2007-50053 A

  The solid-state imaging device has a light receiving unit in which a plurality of pixels are two-dimensionally arranged over a plurality of rows and a plurality of columns. Each pixel is provided with a photodiode for converting incident light into electrons. The photodiode of each pixel is connected to the readout wiring arranged for each column via a switch circuit (for example, a transistor), and the charge accumulated in the photodiode becomes conductive. This flows out to the readout wiring. The electric charge reaches the integrating circuit through the readout wiring and is converted into a voltage signal in the integrating circuit. A control terminal (for example, a gate terminal) for controlling the conduction state of the switch circuit of each pixel is connected to a row selection wiring arranged for each row. Then, a signal (row selection signal) from the shift register is supplied to the control terminal of each switch circuit via the row selection wiring, so that charge is read from each pixel for each row.

  In such a solid-state imaging device, the read operation of charges from each pixel also serves as a reset operation to prepare for charge accumulation in the next frame. However, when a failure such as disconnection occurs in the row selection wiring, the row selection signal does not reach the previous pixel from the failure location, and the switch circuit does not operate. In that case, the charge of the pixel continues to be accumulated in the photodiode, and the charge overflows to pixels in another row adjacent to the row. As a result, an abnormality occurs not only in the row in which the failure occurs in the row selection wiring but also in other adjacent rows. If the output abnormality due to the failure of the row selection wiring is only one row, for example, the output value of the row can be interpolated using the pixel value of the adjacent row. However, when output abnormalities occur in a plurality of adjacent rows as described above, it is difficult to interpolate the output values of those rows.

  In order to solve such a problem, a shift register may be provided at both ends of the row selection wiring. According to such a configuration, even when a disconnection occurs at a certain location of the row selection wiring, a row selection signal can be supplied from both sides of the failure location, and the switch circuit of each pixel is suitable. Can be operated. However, the failure mode of the row selection wiring includes a short circuit to a neighboring wiring in addition to the disconnection. When the row selection wiring is short-circuited to a neighboring wiring at a certain location, even if a row selection signal is supplied from the shift register (in the vicinity of the short occurrence point), the potential of the row selection wiring does not become a predetermined potential, As a result, the switch circuit cannot operate and charges are continuously accumulated in the photodiode. Therefore, the above problem still remains.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a solid-state imaging device that can read out the charge of each pixel even when a row selection wiring fails. .

  In order to solve the above-described problems, a solid-state imaging device according to the present invention includes one photodiode, and first and second switch circuits each having one end connected to the one photodiode, each having M rows. A light receiving unit having M × N pixels two-dimensionally arranged in N columns (M and N are integers of 2 or more), and the first light detector arranged in each column and included in the pixels in the corresponding column. And N readout wirings connected to the other ends of the second switch circuit, and arranged for each row and connected to the control terminal of the first switch circuit included in the pixel of the corresponding row. M first row selection wirings and M second row selections arranged for each row and connected to the control terminal of the second switch circuit included in the pixel of the corresponding row Wiring and the open / closed state of the first and second switch circuits for each row Generating a row selection signal for controlling, characterized in that it comprises a shift register unit for providing the row select signal to the first and second row selection wiring.

  In this solid-state imaging device, two switch circuits (a first switch circuit and a second switch circuit) are provided for each pixel. These switch circuits are connected in parallel with each other between one photodiode and the readout wiring. Accordingly, the charge accumulated in the photodiode flows out to the readout wiring through the two switch circuits. The control terminals of the two switch circuits are connected to separate row selection wirings (first row selection wiring and second row selection wiring). Since these row selection wirings are provided with a common row selection signal from the shift register unit, the two switch circuits perform opening / closing operations at the same timing.

  According to the above solid-state imaging device, even if a failure such as a disconnection or a short circuit occurs in one of the first and second row selection wirings, the other row selection wiring is used. Thus, a row selection signal can be provided to each pixel, and at least one switch circuit can be suitably operated. Therefore, even when the row selection wiring is out of order, the charge of each pixel can be read out, and the overflow of the charge to the pixels in other rows can be suppressed.

  Further, the solid-state imaging device may be characterized in that the first and second row selection wirings are disposed in a region between the pixels. Accordingly, it is possible to prevent the row selection wiring from interfering with the light incident on each pixel, and to increase the light incident efficiency on each pixel. Further, it is possible to keep the row selection wiring away from the photodiode of each pixel, and to suppress the fluctuation of the charge amount in the photodiode due to the voltage fluctuation of the row selection wiring.

  Also, in the solid-state imaging device, one of the first and second row selection wirings is disposed in an area between the pixels, and the other row selection wiring is disposed on the pixels. It is good also as a feature. Thus, the two row selection wirings can be arranged apart from each other, and the yield when manufacturing the solid-state imaging device can be increased. In this case, a reference potential wiring is disposed between the other row selection wiring and the pixel in order to suppress the fluctuation in the amount of charge in the photodiode due to the voltage variation of the other row selection wiring. It is even better if there is.

  The solid-state imaging device may be characterized in that the first and second switch circuits of each pixel are arranged side by side in the column direction.

  The solid-state imaging device includes: a first buffer having each output terminal connected to each of the first row selection wiring; and a second buffer having each output terminal connected to each of the second row selection wiring. A buffer, and the shift register unit has two signal output terminals provided for each row in order to output the row selection signal. In each row, the two signal output terminals One of the signal output terminals may be connected to the input terminal of the first buffer, and the other signal output terminal may be connected to the input terminal of the second buffer. In this case, since a buffer is provided for each of the first and second row selection wirings, one of the first and second row selection wirings is short-circuited with a neighboring wiring. Even so, the other row selection wiring can transmit the row selection signal without being affected by it.

  The solid-state imaging device further includes a buffer having output terminals connected to both the first row selection wiring and the second row selection wiring, and the shift register unit includes: In order to output a row selection signal, one signal output terminal is provided for each line, and each signal output terminal is connected to an input terminal of the buffer of the corresponding line. Also good.

  The solid-state imaging device may be characterized in that the row selection signal is input at the same timing to the first and second row selection wirings in the same row in at least some rows.

  In the solid-state imaging device, the shift register unit may include the same number of shift register circuits as the number of rows, and the shift register circuits may be connected to each other in series.

  According to the solid-state imaging device according to the present invention, the charge of each pixel can be read even when the row selection wiring fails.

It is a top view which shows the structure of a solid-state imaging device. It is the top view to which a part of solid-state imaging device was expanded. It is a sectional side view which shows the cross section along the II line | wire of FIG. It is a figure which shows the internal structure of a solid-state imaging device. It is a figure which shows the detailed circuit structural example of a pixel, an integration circuit, and a holding circuit. It is a circuit diagram which shows the internal structural example of a buffer. It is a circuit diagram which shows the detailed structure of a vertical shift register part. It is a timing chart which shows operation | movement of a vertical shift register part. It is a timing chart of each signal. FIG. 6 is a circuit diagram illustrating a detailed configuration of a vertical shift register unit as a first modification. It is a circuit diagram which shows the structure of a 2nd modification. FIG. 10 is a circuit diagram illustrating a detailed configuration of a vertical shift register unit as a third modification. It is a top view which expands and shows a part of light-receiving part as a 4th modification.

  Embodiments of a solid-state imaging device according to the present invention will be described below in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  The solid-state imaging device according to the present embodiment is used in, for example, a medical X-ray imaging system. 1 and 2 are diagrams showing a configuration of a solid-state imaging device 1A according to the present embodiment. FIG. 1 is a plan view showing the solid-state imaging device 1A, and FIG. 2 is an enlarged plan view of a part of the solid-state imaging device 1A. 1 and 2 also show the XYZ orthogonal coordinate system for easy understanding.

  As shown in FIG. 1, the solid-state imaging device 1A includes a light receiving unit 20, a readout circuit unit 40, and a vertical shift register unit 60A. The light receiving unit 20, the readout circuit unit 40, and the vertical shift register unit 60 </ b> A are fabricated on the main surface of the silicon substrate 12. The vertical shift register unit 60A is arranged side by side with respect to the light receiving unit 20 in the X-axis direction. The readout circuit unit 40 includes a plurality of integration circuits provided corresponding to each of the plurality of columns of the light receiving unit 20, and the plurality of integration circuits correspond to the amount of charge output from the pixels in the corresponding column. Each voltage value is generated. The read circuit unit 40 holds the voltage value output from each integrating circuit, and sequentially outputs the held voltage value.

The light receiving unit 20 is configured by two-dimensionally arranging a plurality of pixels P _{1,1 to} P _{M, N} over M rows and N columns (M and N are integers of 2 or more). In FIG. 2, six pixels P _{m, n−1} , P _{m, n} , P _{m, n + 1} , P _{m + 1, n−1} , P are representative of the plurality of pixels P _{1,1 to} P _{M, N. m + 1, n} and P _{m + 1, n + 1} are shown. For example, the pixel P _{m, n} is a pixel located in the m-th row and the n-th column (m is an integer of 1 to M and n is an integer of 1 to N). 1 and 2, the column direction matches the Y-axis direction, and the row direction matches the X-axis direction. Each of the pixels P _{1,1 to} P _{M, N} included in the light receiving unit 20 includes transistors 21 and 22 and one photodiode 23. The transistors 21 and 22 are the first and second switch circuits in the present embodiment, respectively. The transistors 21 and 22 are preferably configured by field effect transistors (FETs), but may be configured by bipolar transistors. In the following description, the transistors 21 and 22 are assumed to be FETs. In this case, the control terminal means a gate. When the transistors 21 and 22 are bipolar transistors, the control terminal means a base.

  The photodiode 23 generates an amount of charge corresponding to the incident light intensity, and accumulates the generated charge in the junction capacitor. One end (for example, these source regions) of the transistors 21 and 22 is electrically connected to the photodiode 23. A scintillator (not shown) is provided on the light receiving unit 20. The scintillator generates scintillation light according to the incident X-ray, converts the X-ray image into an optical image, and outputs this optical image to the photodiode 23.

The solid-state imaging device 1A includes M first row selection wirings QA _{1 to} QA _M (represented by QA _m and QA _{m + 1} in FIG. 2) arranged for each row, and arranged for each row. M second row selection wirings QB _{1 to} QB _M (represented by QB _m and QB _{m + 1} in FIG. 2 as representative) and a plurality of readout wirings R arranged for each column _{1 to} R _N (in FIG. 2, R _n−1 , R _n , and R _{n + 1} are representatively shown). The first row selection wiring QA _m of the m-th row has a control terminal (for example, a gate terminal) for controlling the open / close state of the transistors 21 included in the pixels P _{m, 1 to} P _{m, N} of the corresponding row. The vertical shift register unit 60A is electrically connected to each other. Further, the second row selection wiring QBm of the _m-th row has a control terminal (for example, a gate terminal) for controlling the open / close state of the transistors 22 included in the pixels Pm _{, 1 to} Pm _{, N} of the corresponding row. ) And the vertical shift register unit 60A are electrically connected to each other.

The vertical shift register unit 60A, and generates a row select signal for controlling for each row of the open or closed state of the transistors 21 and 22, a common row selection signal to the m-th row of the row selecting wiring QA _m and QB _m I will provide a. The readout wiring Rn in the _nth column is electrically connected to the other ends (for example, these drain regions) of the transistors 21 and 22 included in the pixels P1 _{, n to} PM _{, n} in the corresponding column. . Row selecting wiring _QA 1 _{~QA M} and _QB 1 _{~QB M,} and the readout wiring _R 1 to R _N, for example made of metal.

  FIG. 3 is a side sectional view showing a section taken along the line II in FIG. 2, and shows an enlarged sectional structure of the light receiving unit 20. As shown in FIG. 3, a p-type well layer 14 is provided on the entire main surface of the silicon substrate 12. The p-type well layer 14 is formed by implanting p-type impurities into the main surface of the silicon substrate 12, for example. The transistors 21 and 22 and the photodiode 23 are formed on the surface of the p-type well layer 14.

  The photodiode 23 is preferably configured by a high-concentration n-type region 23 a formed near the surface layer of the p-type well layer 14. That is, the photodiode 23 generates a charge corresponding to the incident light intensity in the high-concentration n-type region 23 a and generates the generated charge in the junction capacitance portion between the high-concentration n-type region 23 a and the p-type well layer 14. accumulate.

  The transistor 21 has a source region 21a and a drain region 21b made of a high concentration n-type semiconductor. The source region 21 a is formed integrally with the high concentration n-type region 23 a of the photodiode 23. A gate electrode 21c is provided on the p-type well layer 14 between the source region 21a and the drain region 21b, and an insulating film 16 is interposed between the gate electrode 21c and the p-type well layer 14. ing.

On the drain region 21b of the transistor 21, the metal conductors 24a and the metal layer 25a, through 25b, the branch portions 27 of the readout wiring _R 1 to R _N are provided. Drain region 21b, a metal conductor 24a, a metal layer 25a and 25b, and is the column readout wiring _R 1 to R _N electrically connected through the branch portion 27.

Transistor gate electrode 21c of the 21 is the row selecting wiring _QA 1 _{~QA M} and electrically connected in the row. Row selecting wiring QA ₁ ~QA _M is disposed in the region between adjacent pixels, for example, in this embodiment, it is disposed on the pixel isolation region 18 provided between adjacent pixels Yes. The pixel isolation region 18 is made of, for example, a high concentration p-type semiconductor. In a layer between the row selecting wiring QA ₁ ~QA _M and the pixel isolation region 18 is disposed the reference potential wiring 15, the potential of the reference potential wiring 15 is kept at a reference potential (ground potential) Yes. In other words, the row selection wiring QA _m and the reference potential wiring 15 are arranged in this order as viewed from the radiation incident direction. Further, the reference potential wiring 15 and the pixel isolation region 18 are electrically connected to each other through a metal conductor 24b. Preferably, the lateral direction of width of the reference potential wiring 15 as viewed from the thickness direction of the silicon substrate 12 is wider than the width of the row selecting wiring QA ₁ ~QA _M.

  The transistor 22 has a source region 22a and a drain region 22b made of a high concentration n-type semiconductor. The source region 22 a is formed integrally with the high concentration n-type region 23 a of the photodiode 23. A gate electrode 22c is provided on the p-type well layer 14 between the source region 22a and the drain region 22b, and an insulating film 16 is interposed between the gate electrode 22c and the p-type well layer 14. ing.

On the drain region 22b of the transistor 22, the metal conductors 24a and the metal layer 25a, through 25b, the branch portions 27 of the readout wiring _R 1 to R _N are provided. The drain region 22b is electrically connected to the readout wirings R _{1 to} R _{N of the} column via the metal conductor 24a, the metal layers 25a and 25b, and the branch portion 27.

Transistor gate electrode 22c of the 22 is the row selecting wiring _QB 1 _{~QB M} and electrically connected in the row. Row selecting wiring _QB 1 _{~QB M} is disposed on the pixel, for example, the row selecting wiring QB _m of the m rows, photo included each pixel in the row _P m, 1 _{to P m,} the _N The high-concentration n-type region 23a of the diode 23 is disposed. In a layer between the row selecting wiring QB ₁ ~QB _M and the high concentration n-type region 23a is disposed the reference potential wiring 19, the coercive the potential of the reference potential wiring 19 is a reference potential (ground potential) I'm leaning. In other words, the row selection wiring QB _m and the reference potential wiring 19 are arranged in this order as viewed from the radiation incident direction. Preferably, the lateral direction of width of the reference potential wiring 19 as viewed from the thickness direction of the silicon substrate 12 is wider than the width of the row selecting wiring QB ₁ ~QB _M.

  Each wiring described above is covered with an insulating layer 17. A scintillator 13 is provided on the insulating layer 17 so as to cover the entire surface of the silicon substrate 12. The scintillator 13 generates scintillation light according to the incident X-ray, converts the X-ray image into an optical image, and outputs the optical image to the photodiode 23.

Next, the circuit configuration of the solid-state imaging device 1A will be described in detail. FIG. 4 is a diagram illustrating an internal configuration of the solid-state imaging device 1A. As shown in the figure, the solid-state image pickup device 1A, the first row selection wiring the M _QA 1 ～QA _M first buffer _BA 1 ～BA _M of M which output terminals are connected to each And M second buffers BB _{1 to} BB _M each having an output terminal connected to each of the _M second row selection wirings QB _{1 to} QB _M. The vertical shift register unit 60A receives row selection signals VS _{1 to} VS _M for controlling the open / closed states of the transistors 21 and 22 (see FIG. 2) of the pixels P _{1,1 to} P _{M, N} for each row. Generate. The row selection signals VS _{1 to} VS _M are signals common to the transistors 21 and 22.

The vertical shift register 60A has M signal output terminals 62 provided for each row in order to output the row selection signals VS _{1 to} VS _M. It is connected to the input terminal of the buffer _BA 1 _{~BA M} and _BB 1 _{~BB M} rows that. The vertical shift register unit 60A provides the row selection signal VS _m for the m-th row to each input terminal of the first buffer BA _m and the second buffer BB _m . From the first buffer BA _m, row selection signal VSA _m based on the row select signal VS _m is output. From the second buffer BB _m, row selection signal VSB _m based on the row select signal VS _m is output. In the vertical shift register unit 60A, the row selection signals VS _{1 to} VS _M are sequentially set to significant values.

The read circuit unit 40 includes N integration circuits 42 provided for each column and N holding circuits 44. The integrating circuit 42 and the holding circuit 44 are connected to each other in series for each column. The N is the integration circuit 42 each have an input terminal connected to the respective readout wiring R ₁ to R _N, accumulates charges input from the readout wiring R ₁ to R _N, the accumulated charge A voltage value corresponding to the amount is output from the output terminal to each of the N holding circuits 44. Further, each of the N integration circuits 42 is connected to a reset wiring 46 provided in common to the N integration circuits 42.

Each of the N holding circuits 44 has an input terminal connected to the output terminal of the integrating circuit 42, holds a voltage value input to this input terminal, and uses the held voltage value for voltage output from the output terminal. Output to the wiring 48. Each of the N holding circuits 44 is connected to a holding wiring 45 provided in common to the N holding circuits 44. Further, each of the N holding circuits 44 is connected to a horizontal shift register 61 through the respective first row selection wiring U _{1 ~} N-th column selection wiring U _N.

The horizontal shift register unit 61 provides a column select signal _HS 1 _{~HS n,} to each of the N holding circuits 44 via line _U 1 ~U _n for the column selection. The column selection signals HS _{1 to} HS _n are sequentially set to significant values. Each of the N integrating circuits 42 is provided with a reset control signal RE via a reset wiring 46. A holding control signal Hd is provided to each of the N holding circuits 44 via the holding wiring 45.

FIG. 5 is a diagram illustrating a detailed circuit configuration example of the pixel P _{m, n} , the integration circuit 42, and the holding circuit 44. Here, a circuit diagram of the pixel P _{m, n in} the _m- th row and the n-th column is shown as a representative of the M × N pixels P _{1,1 to} P _{M, N.}

As shown in FIG. 5, the anode terminal of the pixel P _{m, n} of the photodiode 23 is grounded, the cathode terminal is connected to the readout wiring R _n via the transistors 21 and 22. The selection signal VSA _m is provided from the first buffer BA _m to the transistor 21 of the pixel P _{m, n} via the first selection wiring QA _m . The selection signal VSA _m instructs the opening / closing operation of the transistors 21 included in _{the N} pixels P _{m, 1 to} P _{m, N} in the m-th row. Further, the selection signal VSB _m is provided from the second buffer BB _m to the transistor 22 of the pixel P _{m, n} via the second selection wiring QB _m . The selection signal VSB _m instructs the opening / closing operation of the transistors 22 included in _{the N} pixels P _{m, 1 to} P _{m, N} in the m-th row.

Selection signal VSA when _m and VSB _m is a non-significant value (off voltage of the control terminal of the transistors 21 and 22), the charge generated in the photodiode 23, the photodiode 23 without being output to the readout wiring _{R n} Is accumulated in the junction capacitor. On the other hand, when the selection signals VSA _m and VSB _m are significant values (the ON voltages of the control terminals of the transistors 21 and 22), the transistors 21 and 22 are connected. At this time, charges accumulated in the junction capacitance portion of the photodiode 23 is output via the transistors 21 and 22 to the readout wiring R _n. The charge output from the photodiode 23 of the pixel P _{m, n} is sent to the integration circuit 42 through the readout wiring R _n . Since the selection signals VSA _m and VSB _m are generated from the common selection signal VS _m , their insignificant value / significant value switching timings coincide with each other.

The integration circuit 42 has a so-called charge integration type configuration including an amplifier 42a, a capacitive element 42b, and a discharge switch 42c. The capacitive element 42b and the discharge switch 42c are connected in parallel to each other and are connected between the input terminal and the output terminal of the amplifier 42a. Input terminal of the amplifier 42a is connected to the readout wiring line R _n. A reset control signal RE is provided to the discharge switch 42 c via the reset wiring 46.

  The reset control signal RE instructs the opening / closing operation of the discharge switch 42c of each of the N integration circuits 42. For example, when the reset control signal RE is an insignificant value (for example, high level), the discharging switch 42c is closed, the capacitive element 42b is discharged, and the output voltage value of the integrating circuit 42 is initialized. When the reset control signal RE is a significant value (for example, low level), the discharge switch 42c is opened, and the charge input to the integration circuit 42 is accumulated in the capacitive element 42b. The voltage value is output from the integration circuit 42.

The holding circuit 44 includes an input switch 44a, an output switch 44b, and a capacitive element 44c. One end of the capacitive element 44c is grounded. The other end of the capacitive element 44c is connected to the output end of the integrating circuit 42 through the input switch 44a, and is connected to the voltage output wiring 48 through the output switch 44b. A holding control signal Hd is given to the input switch 44 a via the holding wiring 45. The holding control signal Hd instructs the opening / closing operation of the input switch 44 a of each of the N holding circuits 44. The output switch 44b of the holding circuit 44, the n-th column selection signal HS _n via the n-th column selecting wiring _{U n} is given. The selection signal HS _n instructs the opening / closing operation of the output switch 44b of the holding circuit 44.

For example, when the holding control signal Hd changes from the high level to the low level, the input switch 44a changes from the closed state to the open state, and the voltage value input to the holding circuit 44 at that time is held in the capacitive element 44c. The Further, the n-th column selecting signal HS _n Turning from the low level to the high level, closes the output switch 44b, a voltage value held in the capacitor 44c is outputted to the voltage output wiring 48.

FIG. 6 is a circuit diagram illustrating an internal configuration example of the buffers BA _m and BB _m . The buffers BA _m and BB _m are impedance converters that output an input signal with a low impedance, and are supplied with a power supply voltage and correspond to the power supply voltage regardless of the magnitude of the input signal (selection signal VS _m ). Output signals (selection signals VSA _m , VSB _m ) are generated. For example, the buffers BA _m and BB _m shown in FIG. 6 include two stages of amplifier circuits B1 and B2, and each of the amplifier circuits B1 and B2 is configured by a CMOS inverter.

Specifically, each of the amplifier circuits B1 and B2 includes two MOS FETs (p-MOSFET 51 and n-MOSFET 52). The drain terminal of the p-MOSFET 51 and the drain terminal of the n-MOSFET 52 are connected to each other, the source terminal of the p-MOSFET 51 is connected to the positive power supply potential Vdd, and the source terminal of the n-MOSFET 52 is a negative power supply. It is connected to the potential Vss. The selection signal VS _m is input to the gate terminals of the p-MOSFET 51 and the n-MOSFET 52 of the amplifier circuit B1. The drain terminals of the p-MOSFET 51 and the n-MOSFET 52 of the amplifier circuit B1 are connected to the gate terminals of the p-MOSFET 51 and the n-MOSFET 52 of the amplifier circuit B2. Then, signals from the drain terminals of the p-MOSFET 51 and the n-MOSFET 52 of the amplifier circuit B2 are output as selection signals VSA _m and VSB _m .

The first row selection wiring _QA 1 _{~QA M,} and the second row selection wiring _QB 1 _{~QB M} capacitance, resistance are large. Therefore, in order to switch the voltage values of the selection signals VSA _m and VSB _m within a predetermined time, it is desirable that the buffers BA _m and BB _m can output a large current. Since the CMOS inverter as described above has a low output impedance, the buffers BA _m and BB _m capable of outputting a large current can be suitably realized by applying the CMOS inverter to the amplifier circuits B1 and B2.

FIG. 7 is a circuit diagram showing a detailed configuration of the vertical shift register unit 60A of the present embodiment. As shown in FIG. 7, the vertical shift register unit 60A includes a shift register array 41 and M logic circuits LO _{1 to} LO _M (in the figure, LO ₁ to LO ₄ are shown as representatives). ing.

  The shift register array 41 is configured by connecting M shift register circuits 43 in series. These shift register circuits 43 are arranged one for each row. The shift register circuit 43 is composed of, for example, a plurality of FETs having the same structure as the transistors 21 and 22 shown in FIG. Each shift register circuit 43 is connected to a clock line Lc, and a clock signal clk having a fixed period is provided from the clock line Lc to each shift register circuit 43.

M logic circuits LO _{1 to} LO _M are arranged corresponding to each row, and an output terminal of the logic circuit LO _{m in} the m-th row is connected via a signal output terminal 62 provided for each row. Are connected to the input ends of the buffers BA _m and BB _m described above. Moreover, to one input of the logic circuit _LO 1 _{~LO M} is connected to the enable line En, the control input signal enable is provided from the enable line En to the logic circuit _LO 1 _{~LO M.} The logic circuit LO ₁ ~LO _M respective other input terminal, an output terminal of the shift register circuit 43 corresponding to the row is connected.

Each of the M logic circuits LO _{1 to} LO _M closes the transistors 21 and 22 when the control input signal enable and the output signals Sout _{1 to} Sout _M from the corresponding shift register circuit 43 are both significant values. In this manner, the row selection signals VS _{1 to} VS _M are output. For example, when the significant value of the control input signal enable is high level and the significant values of the output signals Sout _{1 to} Sout _M from the shift register circuit 43 are high level, the logic circuit LO _{m in} the m-th row is A logical product (AND) of the control input signal enable and the output signal Sout _m from the shift register circuit 43 is output. Although the logic circuit _LO 1 _{~LO M} with a symbol representing the AND circuit 7 is shown, the logic circuit _LO 1 _{~LO M} may be constituted by a combination of various other logic circuits.

FIG. 8 is a timing chart showing the operation of the vertical shift register unit 60A of the present embodiment. In FIG. 8, in order from the top, (a) start signal Start, (b) clock signal clk, (c) output signal Sout ₁ from the shift register circuit 43 in the first row, (d) shift register in the second row. Output signal Sout ₂ from the circuit 43, (e) Output signal Sout ₃ from the shift register circuit 43 in the third row, (f) Output signal Sout ₄ from the shift register circuit 43 in the fourth row, (g) Control input Signal enable, (h) first row selection signal VSA ₁ , (i) first row selection signal VSB ₁ , (j) second row selection signal VSA ₂ , (k) second row selection signal VSB ₂ , (l) The third row selection signal VSA ₃ , (m) the third row selection signal VSB ₃ , (n) the fourth row selection signal VSA ₄ , and (o) the fourth row selection signal VSB ₄ are shown.

First, a period of from the time _{t 10} to the time _{t 13,} the start signal Start is set to the high level. During this time, when the clock signal clk rises, the output signal Sout ₁ from the shift register circuit 43 in the first row rises (time t ₁₁ ). This output signal Sout ₁ falls in response to the rise of the next clock signal clk (time t ₁₅ ). Then, the control input signal enable is set to high level within a predetermined period (time t _{12 to} t ₁₄ ) included between time t ₁₁ and time t ₁₅ when the output signal Sout ₁ is high level. As a result, the first row selection signals VSA ₁ and VSB ₁ become high level, and the transistors 21 and 22 included in the pixels P _{1,1 to} P _{1, N} in the first row are turned on.

At the same time as the output signal Sout ₁ from the shift register circuit 43 in the first row falls, the output signal Sout ₂ from the shift register circuit 43 in the second row rises (time t ₁₅ ). The output signal Sout ₂ falls in response to the rising edge of the next clock signal clk (time t ₁₈ ). Then, the output signal Sout ₂ is within a predetermined period included in the period from time _{t 15} at a high level until the time _{t 18} (time _t 16 _{~t 17),} the control input signal enable is high level again. As a result, the second row selection signals VSA ₂ and VSB ₂ become high level, and the transistors 21 and 22 included in the pixels P _{2,1 to} P _{2 and N} in the second row are connected. Thereafter, by the same operation as in the second row, the selection signals VSA _m and VSB _m in the third row and thereafter are sequentially set to the high level, and the transistors 21 and 22 included in each pixel are sequentially connected to each row.

1 A of solid-state imaging devices of this embodiment provided with the above structure operate | move as follows. FIG. 9 is a timing chart of each signal. In FIG. 9, in order from the top, (a) reset control signal RE, (b) first row selection signal VSA ₁ , (c) first row selection signal VSB ₁ , (d) second row selection signal VSA ₂ , (E) second row selection signal VSB ₂ , (f) Mth row selection signal VSA _M , (g) Mth row selection signal VSB _M , (h) holding control signal Hd, and (i) first column selection signal. HS ₁ to N-th column selection signal HS _N are shown.

As shown in FIG. 9, first, a period from time t ₂₀ to the time t _21, the reset control signal RE is set to the high level. As a result, in each of the N integration circuits 42, the discharge switch 42c is closed, and the capacitive element 42b is discharged.

Period from the time _{t 22} after the time _{t 21} to time _{t 23,} the first row selection signal VSA ₁ and VSB ₁ is set to the high level by the operation shown in FIG. As a result, the transistors 21 and 22 are connected in the pixels P _{1,1 to} P _{1, N} in the first row, and the charges accumulated in the photodiodes 23 of the pixels P _{1,1 to} P _{1, N} are read out. wiring through _R 1 to R _N is output to the integrating circuit 42 is accumulated in the capacitor 42b. The integration circuit 42 outputs a voltage value having a magnitude corresponding to the amount of charge accumulated in the capacitive element 42b. Incidentally, after the time _{t 23,} the pixel _P 1, 1 _{to P 1} of the first _row, the _N respective transistors 21 and 22 are disconnected.

Then, during a period from time t ₂₄ to time t ₂₅ after time t ₂₃ , the holding control signal Hd is set to the high level, whereby the input switch 44 a is connected in each of the N holding circuits 44. The voltage value output from the integrating circuit 42 is held by the capacitive element 44c.

Subsequently, during a period from time t ₂₆ to time t ₂₇ after time t ₂₅ , the horizontal shift register 61 sequentially sets the first column selection signal HS ₁ to the Nth column selection signal HS _N to the high level. As a result, the output switches 44b of the N holding circuits 44 are sequentially closed, and the voltage value held in the capacitive element 44c is sequentially output to the voltage output wiring 48. During this time, the reset control signal RE is set to the high level, and the capacitive element 42b of the integrating circuit 42 is discharged.

Subsequently, during a period from time t ₂₈ to time t ₂₉ after time t ₂₇ , the second row selection signals VSA ₂ and VSB ₂ are set to the high level. As a result, the transistors 21 and 22 are connected in the pixels P _{2,1 to} P _{2, N} in the second row, and the charges accumulated in the photodiodes 23 of the pixels P _{2,1 to} P _{2, N} are read out. wiring through _R 1 to R _N is output to the integrating circuit 42 is accumulated in the capacitor 42b. Thereafter, by the same operation as in the first row, a voltage value having a magnitude corresponding to the amount of charge accumulated in the capacitor element 42 b is sequentially output from the N holding circuits 44 to the voltage output wiring 48. The charges accumulated in the pixels in the third to Mth rows are also converted into voltage values by the same operation as in the first row, and sequentially output to the voltage output wiring 48. Thus, reading of image data for one imaging frame from the light receiving unit 20 is completed.

The effects obtained by the solid-state imaging device 1A of the present embodiment described above will be described. As described above, the charge read operation from each of the pixels P _{1,1 to} P _{M, N} also serves as a reset operation for preparing for charge accumulation in the next frame. However, in the conventional solid-state imaging device, when a failure such as a short circuit occurs in the row selection wiring, the row selection signal does not reach the previous pixel from the failure location, and the switch circuit does not operate. In that case, the charge of the pixel continues to be accumulated in the photodiode, and the charge overflows to pixels in another row adjacent to the row. As a result, an abnormality occurs not only in the row in which the failure occurs in the row selection wiring but also in other adjacent rows. In particular, in order to form a laminated structure of metal wirings as shown in FIG. 3, that is, a first layer for forming a reference potential line, a second layer for forming a row selection wiring, and a reading wiring. When the solid-state imaging device has a structure in which the third layer is stacked, the first layer reference potential line and the second layer row selection wiring may be short-circuited with each other.

In response to the above problem, in this solid-state imaging device 1A, two switch circuits (transistors 21 and 22) are provided for each of the pixels _{P1,1 to} PM _{, N.} Then, the pixel _P 1, n _{to P M} of the n-th _column, the transistor 21 and 22 of _n in between the photodiode 23 and the readout wiring _{R n,} are connected in parallel with each other. Thus, charge accumulated in the photodiode 23 flows out through the transistors 21 and 22 to the readout wiring R _n. The control terminals of the transistors 21 and 22 of the pixels P _{m, 1 to} P _{m, N in} the _m-th row are connected to separate row selection wirings QA _m and QB _m , respectively. Since the row selection wirings QA _m and QB _m are respectively provided with the common row selection signals VSA _m and VSB _m from the vertical shift register unit 60A, the transistors 21 and 22 perform the opening / closing operation at the same timing. .

According to such a solid-state imaging device 1A, even if one of the row selection wirings QA _m and QB _m has a failure such as a disconnection or a short circuit, the other row selection wiring The row selection signal VSA _m or VSB _m can be provided to each of the pixels P _{m, 1 to} P _{m, N} via the at least one transistor 21 or 22 and the at least one transistor 21 or 22 can be suitably operated. Therefore, even if one of the row selection wirings QA _m or QB _m fails _, the charge of each pixel P _{m, 1 to} P _{m, N} can be read out, and the charge is transferred to the pixels in the other adjacent rows. Can be effectively prevented from overflowing. In particular, in this embodiment the solid-state imaging device 1A, since each buffer BA _m and BB _m each row selecting wiring QA _m and QB _m are provided, row one of the selecting wiring QA _m and QB _m Even when the row selection wiring is short-circuited with a neighboring wiring, the other row selection wiring can transmit the row selection signal VSA _m or VSB _m without being affected by the other. Note that when both the row selection wirings QA _m and QB _m are short-circuited at the same time, there is almost no problem because the probability is extremely low.

Further, as shown in FIGS. 2 and 3, the row selecting wiring QA _m of one of the row selecting wiring QA _m and QB _m are disposed in a region between pixels other row selecting wiring QB _m may be arranged on the pixels P _{m, 1 to} P _{m, N.} Thus, release the row selecting wiring QA _m and QB _m from each other can be disposed, it is possible to increase the yield in manufacturing the solid-state image pickup device 1A. Further, unlike the fourth modification described later, the row selection wirings QA _m and QB _m can be formed in the same layer. As described above, when one row selection wiring QA _m is arranged in the region between the pixels and the other row selection wiring QB _m is arranged on the pixels P _{m, 1 to} P _{m, N} , order to suppress small variations in the amount of charge in the photodiode 23 due to the voltage variation of the other row selecting wiring QB _m, as in the present embodiment, other row selecting wiring QB _m and the pixel P _{m, 1} It is desirable that a reference potential wiring 19 is disposed between Pm _{and N.} In the present embodiment because a portion of each pixel is covered by the row selecting wiring QB _m, the aperture ratio is reduced slightly. However, for example, if the pixel size is 100 μm square or more on one side, the decrease in the aperture ratio is as small as about 3%, which is hardly a problem.

(First modification)
FIG. 10 is a circuit diagram showing a detailed configuration of the vertical shift register unit 60B as a first modification of the embodiment. As shown in FIG. 10, the vertical shift register unit 60B includes a shift register array 41, M logic circuits LOA _{1 to} LOA _M (represented in the figure as representative of LOA ₁ to LOA ₄ ), and M pieces of logic circuits. Logic circuits LOB _{1 to} LOB _M (in the figure, LOB ₁ to LOB ₄ are representatively shown). The configuration of the shift register array 41 is the same as that of the above-described embodiment.

The M logic circuits LOA _{1 to} LOA _M are arranged corresponding to each row, and the output terminal of the m-th row logic circuit LOA _m is one of the signal output terminals 63 provided two for each row. through, and is connected to an input terminal of the buffer BA _m. M logic circuits LOB _{1 to} LOB _M are also arranged corresponding to each row, and the output ends of the m-th row logic circuit LOB _m are signal output ends 63 provided for each row. The other end is connected to the input end of the buffer BB _m .

The first enable wiring En _A is connected to one input terminal of the logic circuits LOA _{1 to} LOA _M , and the first control input signal enable ₁ is provided from the enable wiring En _A to the logic circuits LOA _{1 to} LOA _M. Is done. The output terminal of the shift register circuit 43 corresponding to the row is connected to the other input terminal of each of the logic circuits LOA _{1 to} LOA _M. In addition, the second enable wiring En _B is connected to one input terminal of the logic circuits LOB _{1 to} LOB _M , and the second control input signal enable ₂ is transmitted from the enable wiring En _B to the logic circuits LOB _{1 to} LOB _M. Provided to. The output terminal of the shift register circuit 43 corresponding to the row is connected to the other input terminal of each of the logic circuits LOB _{1 to} LOB _M.

Each of the logic circuits LOA _{1 to} LOA _M selects a row so as to close the transistor 21 when the control input signal enable ₁ and the output signals Sout _{1 to} Sout _M from the corresponding shift register circuit 43 are both significant values. Each of the signals VSA _{1 to} VSA _M is output. Similarly, each of the logic circuits LOB _{1 to} LOB _M closes the transistor 22 when the control input signal enable ₂ and the output signals Sout _{1 to} Sout _M from the corresponding shift register circuit 43 are both significant values. The row selection signals VSB _{1 to} VSB _M are output to In FIG. 10, logic circuits LOA _{1 to} LOA _M and LOB _{1 to} LOB _M are shown with symbols representing AND circuits, but the logic circuits LOA _{1 to} LOA _M and LOB _{1 to} LOB _M are various other types. You may comprise by the combination of a logic circuit.

The operation of the vertical shift register unit 60B is the same as the operation of the vertical shift register unit 60A shown in FIG. However, the signal waveforms of the first and second control input signals enable ₁ and enable ₂ may be the same as the signal waveform of the control input signal enable in FIG.

  In the above embodiment, the vertical shift register unit 60B of this modification can be applied in place of the vertical shift register unit 60A. Even in that case, the same effects as in the above embodiment can be suitably achieved.

(Second modification)
FIG. 11 is a circuit diagram showing a configuration of a second modification of the embodiment. In this modification, unlike the above embodiment, one buffer is provided for each row. Specifically, the solid-state imaging device includes M first row selection wirings QA _{1 to} QA _M and M second row selection wirings QB _{1 to} QB _M, respectively. M buffers B _{1 to} B _M having output terminals connected thereto are provided.

The vertical shift register 60A has M signal output terminals 62 provided for each row in order to output the row selection signals VS _{1 to} VS _M. Are connected to the input terminals of the buffers B _{1 to} B _M of the row to be processed. Then, the vertical shift register unit 60A provides the row selection signal VS _m of the m-th row to the input end of the buffer BA _m . Output signals from the buffer BA _m are provided to the row selection wirings QA _m and QB _m as row selection signals VSA _m and VSB _m .

Even in the case where one buffer is provided for each row and the output signal is branched into row selection signals VSA _m and VSB _m as in this modification, the same effects as in the above-described embodiment are suitably achieved. be able to. However, if a buffer is provided for each row selection wiring QA _m and QB _m as in the above embodiment, the influence on the other row selection wiring due to a short failure of one row selection wiring is further reduced. Therefore, the form of the said embodiment is more preferable.

(Third Modification)
FIG. 12 is a circuit diagram showing a detailed configuration of a vertical shift register unit 60C as a third modification of the embodiment. The vertical shift register unit 60C of the present modification differs from the vertical shift register unit 60B of the first modification in the following points.

As shown in FIG. 12, the vertical shift register unit 60C of the present modification includes a first shift register array 41A and a second shift register array 41B instead of the shift register array 41 in the first modification. Have. The shift register array 41A is, M number of shift register circuit 43 disposed one by one in each row is constituted by connecting in series, the clock wire Lc ₁ is connected to a respective shift register circuits 43 Thus, a clock signal clk ₁ having a constant period is provided from the clock wiring Lc ₁ to each shift register circuit 43. The shift register array 41B is constructed by M pieces of the shift register circuit 43 disposed one by one in each row are connected in series, the clock wire Lc ₂ is connected to the shift register circuit 43 The clock signal clk ₂ having a constant period is provided from the clock line Lc ₂ to each shift register circuit 43. Note that the clock signals clk ₁ and clk ₂ are preferably clock signals having the same cycle and operate at the same timing.

The first enable wiring En _A is connected to one input terminal of the logic circuits LOA _{1 to} LOA _M , and the first control input signal enable ₁ is provided from the enable wiring En _A to the logic circuits LOA _{1 to} LOA _M. Is done. The output terminal of the shift register circuit 43 corresponding to the row of the first shift register array 41A is connected to the other input terminal of each of the logic circuits LOA _{1 to} LOA _M. In addition, the second enable wiring En _B is connected to one input terminal of the logic circuits LOB _{1 to} LOB _M , and the second control input signal enable ₂ is transmitted from the enable wiring En _B to the logic circuits LOB _{1 to} LOB _M. Provided to. The output terminal of the shift register circuit 43 corresponding to the row of the second shift register array 41B is connected to the other input terminal of each of the logic circuits LOB _{1 to} LOB _M.

Each of the logic circuits LOA _{1 to} LOA _M selects a row so as to close the transistor 21 when the control input signal enable ₁ and the output signals SAout _{1 to} SAout _M from the corresponding shift register circuit 43 are both significant values. Each of the signals VSA _{1 to} VSA _M is output. Similarly, each of the logic circuits LOB _{1 to} LOB _M closes the transistor 22 when the control input signal enable ₂ and the output signals SBout _{1 to} SBout _M from the corresponding shift register circuit 43 are both significant values. The row selection signals VSB _{1 to} VSB _M are output to

The operation of the vertical shift register unit 60C is the same as that of the vertical shift register unit 60A shown in FIG. However, the signal waveforms of the start signals Start ₁ and Start ₂ input to the shift register arrays 41A and 41B may be the same as the signal waveform of the start signal Start in FIG. The signal waveforms of the clock signals clk ₁ and clk ₂ may be the same as the signal waveform of the clock signal clk in FIG. The signal waveforms of the first and second control input signals enable ₁ and enable ₂ may be the same as the signal waveform of the control input signal enable in FIG.

  In the above embodiment, the vertical shift register unit 60C of this modification can be applied instead of the vertical shift register unit 60A. Even in that case, the same effects as in the above embodiment can be suitably achieved.

(Fourth modification)
FIG. 13 is an enlarged plan view showing a part of the light receiving unit as a fourth modification of the embodiment. As shown in FIG. 13, in the present modification, unlike the above embodiment, both of the row selecting wiring _QA 1 _{~QA M} and _QB 1 _{~QB M,} are disposed in a region between pixels. Specifically, the row selection wirings QA _m and QB _m in the m-th row include the pixels P _{m, 1 to} P _{m, N} in the m-th row and the pixels P _{m + 1,1 to} P _{m + 1 in} the (m + 1) -th row. _{, N.}

According to such a configuration of the present modification, to avoid that each pixel _P 1, 1 _{to P M,} the incidence of light row selecting wiring _QA 1 _{~QA M} or _QB 1 _{~QB M} to _N hamper Thus, the light incident efficiency to each of the pixels P _{1,1 to} P _{M, N} can be increased. The row selecting wiring _QA 1 _{~QA M} and _QB 1 _~QB each pixel _{M P} 1, 1 _{to P M,} away from the photodiode 23 of _N, the row selection wiring _QA 1 _{~QA M} and _QB 1 ~ it is possible to suppress the variation of the amount of charge in the photodiode 23 due to the voltage variation of the QB _M.

Incidentally, the row selecting wiring _QA 1 _{~QA M,} and the row selecting wiring _QB 1 _{~QB M,} may be juxtaposed in the stacking direction. For example, the wiring layers including the row selecting wiring _QB 1 _{~QB M,} may be added on top of the wiring layer including the row selecting wiring _QA 1 _{~QA M.} Thus, wider spacing between the row selecting wiring QB ₁ ~QB _M and the reference potential line, and the row selecting wiring QB ₁ ~QB _M and the reference potential line can be reduced the probability of a short circuit.

  The solid-state imaging device according to the present invention is not limited to the above-described embodiment, and various other modifications are possible. For example, the light receiving section shown in the above embodiment may have a configuration in which polycrystalline silicon or amorphous silicon is formed on a glass substrate. In this case, the transistors 21 and 22 are preferably realized by thin film transistors. Alternatively, the light receiving portion may be fabricated on a single crystal silicon substrate.

Further, two row select lines _QA m in the same row in the above embodiments, the row selection signal to the QB _{m VSA} m, although the VSB _m inputs at the same timing, the first modification and the third modification In addition, at least part of the row selection signals VSA _m and VSB _m may be input at the same timing with respect to the two row selection wirings QA _m and QB _m in the same row, or may be input at different timings. Good.

(Appendix)
The solid-state imaging device of the above embodiment is
Each includes one photodiode and first and second switch circuits each having one end connected to the one photodiode, and is two-dimensionally arranged in M rows and N columns (M and N are integers of 2 or more). A light receiving unit having M × N pixels;
N readout wirings arranged for each column and connected to the other ends of the first and second switch circuits included in the pixels of the corresponding column;
M first row selection wirings arranged for each row and connected to a control terminal of the first switch circuit included in the pixel of the corresponding row;
M first buffers each having an output terminal connected to each of the M first row selection wirings;
M second row selection wirings arranged for each row and connected to a control terminal of the second switch circuit included in the pixel of the corresponding row;
M second buffers each having an output terminal connected to each of the M second row selection wirings;
A row selection signal for controlling the open / close state of the first and second switch circuits for each row is generated, and the row selection signal common to the input ends of the first and second buffers is provided. A shift register unit,
The shift register unit has M signal output terminals, one for each row, for outputting the row selection signal, and each signal output terminal is connected to the first and second signals in the corresponding row. It is connected to the input terminal of the second buffer.

DESCRIPTION OF SYMBOLS 1A ... Solid-state imaging device, 12 ... Silicon substrate, 13 ... Scintillator, 15, 19 ... Reference potential wiring, 18 ... Pixel separation area, 20 ... Light-receiving part, 21 ... Transistor (1st switch circuit), 22 ... Transistor (1st 2), 23... Photodiode, 40... Readout circuit section, 41, 41 A, 41 B... Shift register array, 42... Integration circuit, 43. ... reset wiring 48 ... voltage output wiring 60A-60C ... vertical shift register section, 61 ... horizontal shift register, 62 and 63 ... signal output _{terminal, BA 1 ~BA M, BB 1} ~BB M ... buffer, P _1,1 ~P _{M, N ...} pixel, _QA 1 ~QA M _... first row selecting wiring, _QB 1 ~QB M _... second row selecting _wiring, R 1 to R _N Readout wiring, _VS 1 ~VS M _... row selection _signal, VSA 1 _~VSA M _... first row selection _signal, VSA m _~VSB m _... second row selection signal.

Claims (9)

Each includes one photodiode and first and second switch circuits each having one end connected to the one photodiode, and is two-dimensionally arranged in M rows and N columns (M and N are integers of 2 or more). A light receiving unit having M × N pixels;
N readout wirings arranged for each column and connected to the other ends of the first and second switch circuits included in the pixels of the corresponding column;
M first row selection wirings arranged for each row and connected to a control terminal of the first switch circuit included in the pixel of the corresponding row;
M second row selection wirings arranged for each row and connected to a control terminal of the second switch circuit included in the pixel of the corresponding row;
A shift register that generates a row selection signal for controlling the open / close state of the first and second switch circuits for each row and provides the row selection signal to the first and second row selection wirings A solid-state imaging device.   The solid-state imaging device according to claim 1, wherein the first and second row selection wirings are disposed in a region between the pixels.   One of the first and second row selection wirings is disposed in the region between the pixels, and the other row selection wiring is disposed on the pixel. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is characterized.   The solid-state imaging device according to claim 3, further comprising a reference potential wiring disposed between the other row selection wiring and the pixel.   5. The solid-state imaging device according to claim 1, wherein the first switch circuit and the second switch circuit of each pixel are arranged side by side in a column direction. A first buffer having each output terminal connected to each of the first row selection wirings;
A second buffer having each output terminal connected to each of the second row selection wirings,
The shift register unit has two signal output terminals provided for each row in order to output the row selection signal, and one signal output terminal of the two signal output terminals in each row. 6 is connected to the input terminal of the first buffer, and the other signal output terminal is connected to the input terminal of the second buffer. The solid-state imaging device according to item. A buffer having output terminals connected to both the first row selection wiring and the second row selection wiring;
The shift register unit has a signal output end provided for each row in order to output the row selection signal, and each signal output end is connected to an input end of the buffer in a corresponding row. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is provided.   The row selection signal is input at the same timing to the first and second row selection wirings in the same row in at least some of the rows. The solid-state imaging device according to one item.   The solid state according to any one of claims 1 to 8, wherein the shift register section includes the same number of shift register circuits as the number of rows, and the shift register circuits are connected to each other in series. Imaging device.

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