TW200803484A - Stack-type semiconductor device with integrated sensors - Google Patents

Abstract

Provided is a sensor circuit and an address specification type image sensor capable of accumulating signal charges of all the pixels substantially simultaneously and realizing a high pixel numerical aperture. A plurality of pixels (11) arranged in a matrix are divided into groups of n pixels, which are connected in parallel to a common node (13) so as to constitute a plurality of pixel blocks (12). Each of the pixel blocks (12) includes: n photoelectric conversion elements (PD1 to PDn) connected in parallel to the common node (13); and n transfer gates (TG1 to TGn) for opening and closing channels connecting the photoelectric conversion elements (PD1 to PDn) and the common node (13). Outside of each of the pixel blocks (12), a common reset transistor (TrRST) for resetting all the pixels (11) and a common amplification transistor (TrAMP) for amplifying the signal read from the n pixels (11).

Description

200803484 IX. Description of the invention: [Technical field to which the invention belongs]

The address sensor type image sensor can be configured to reset the transistor and amplify the sensor circuit of the transistor to form an address-capable image sensor that enables all pixels to be shuttered. The present invention relates to a laminated type semi-conductor loaded with an integrated body sensor' more specifically related to the inclusion of a photoelectric conversion element, a transfer interpole, and the use of the sense of simultaneous exposure (global [previous technique]

Advanced single-eye digital cameras and even mobile phones, which have been used, are because they have the following advantages: compared to CCD image sensors, the cm〇s image sensing state has the following advantages: only one power supply is needed to save power consumption. A CCD image sensor (charge transfer type image sensor) that transmits a signal charge of all pixels arranged in an array using a CCD (Charge_cQupied Device) in the conventional solid-state imaging device. It is often profitable. However, in recent years, #〇 影像 影像 影像 影像 选择 选择 选择 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由Increasingly, it is made from standard CMOS (Complementary Metal-Oxide-Semiconductor: ^Complementary Metal Oxide Semiconductor) and easy to implement system on chip. ..., and, in the conventional general CM〇S (address-specific type) image sensor, the following two problems exist. The first problem is that the signal charges of all the pixels cannot be simultaneously stored (in other words, simultaneously exposed). 5 200803484, / In the CCD image sensor, all the pixels are stored at the same time, and the stored signal charge is read from each pixel and then transmits the signal of 'so' all pixels. The storage period of the charge (this is equivalent to the exposure period) is the same. In contrast, in a conventional CMOS image sensor, the storage of the No. 2 charge is performed for each column or each pixel of the pixel array, and the signal charge stored in each pixel is received from each pixel by the bit. According to the sequential reading, there is a time error (time point error) during the storage of the signal of each pixel: Therefore, it is impossible to use the same power as the LCD image sensor. The reason will be described below using Fig. 33A and Fig. 30. /, Fig. 33(a) is a conceptual diagram of the general circuit configuration of the CCD image sensor, and Fig. 33(b) is a schematic diagram of the storage period of the signal charge of the CCD image sensor. Figure 3 (4), is a conceptual diagram of a conventional (10) image sensor with a = path composition +; the target 3 (b) is a conceptual diagram of the storage period of the cM〇s image sensor / 遽 charge . [Refer to Mi Ben and also the basis and application of CCD/CMOS image sensor" (9) Press, which is issued on the 175 pages and 179 pages of the 3rd year] "sensors like the one shown in Figure 33(4), configuration A plurality of pixels in an array form, respectively, include a photodiode as a photoelectric conversion element, and in the photodiode of the same, respectively, the amount corresponding to the irradiation intensity is stored. The signal charge stored in each pixel is transmitted through a vertical CCD arranged along each row of the pixel array through a transfer interpole (not shown) provided for each pixel. The reading of the vertical ccd is generally performed at the end of the vertical blanking period. The 6 200803484 signal charge read by each vertical ccd is sequentially transmitted to the common horizontal CCD arranged along the array of pixels by the vertical transfer of the vertical CCD. In this way, the signal charge that is transmitted to the horizontal CCD is further horizontally transmitted at the output end thereof by the horizontal CCD, and amplified by the FD (Fl〇ating Diffusi〇n: Floating Diffusion) amplifier disposed at the output end. And become the signal output.

The storage of the signal charge of the CCD image sensor can be easily understood and constructed by Figure 33(b)! The N corresponding scan lines of the frame 汾_) have the same storage period, in other words, the storage period is set at the same time. This phenomenon should be clarified by taking into account the action of the signal stored in each pixel being read by the vertical CCD. On the other hand, in the conventional CMOS image sensor, as shown in FIG. 3A (checked, a plurality of pixels arranged in an array, respectively containing photodiodes as photoelectric conversion elements, and for amplifying An amplifier for signal charge stored in the photodiode. The selection of each pixel in the pixel array is performed by a vertical scanning circuit to sequentially select column selection lines, and the horizontal scanning circuit sequentially selects the signal lines (ie, sequentially In the figure, the switch is set in each pixel and the switch provided in each row of signal lines is used to indicate its state. CDS (CGrrelated) is set in each line of signal lines.

Double Sampling: A circuit that is used to remove noise from the signal charge flowing through each signal line. The signal charges selected from the respective pixels in the above manner are sequentially sent to the common horizontal signal line, and are connected to the output f path of the horizontal signal I (four)-end to become a signal output. 7 200803484 During the storage period of the signal charge of the conventional CMOS image sensor, as shown in FIG. 30(b), it is understood that the pixel corresponding to the n scan lines (i~n) constituting one frame respectively During storage, the time difference is sequentially generated along with the scanning time points of the respective scanning lines. The reason is that in the CM〇s image sensor, unlike the CCD image sensor, there is a vertical register (vertical ccD). Therefore, if the signal charge of each pixel is reset, the signal charge will be changed. There is a difference in the timing at which it is transmitted to the corresponding line signal line. Thus, in the conventional CMOS image sensor, the storage period of the signal charge varies with the scan line, and there is a difficulty in the simultaneous storage of the signal charge (in other words, simultaneous exposure). Photographing a subject to be moved at a high speed has a problem of distorting the acquired image. For example, if you want to shoot a blade that rotates at a high speed, it will produce a distorted image like Figure 34(b). In contrast, if a CCD image sensor capable of simultaneously storing the charge (simultaneous exposure) is used for photography, in this case, the image of the day will be as shown in FIG. 34(a), and the obtained image will not be obtained. Distortion occurs (Fig. 34, based on the basis and application of the above rCCD/CM〇s image sensor) (page 180). The second problem with the CMOS w-like sensor that is driven is that the light-receiving area that is effective compared to the pixel area is narrower, in other words, there is a problem that the aperture ratio (10) factor of the pixel is low. The reason will be described below with reference to Figs. 31 and 32. A schematic circuit diagram of a conventional CMOS image sensor is shown in Fig. 32. Fig. 32 is a cross-sectional view showing the main part of the schematic device structure. The circuit configuration of Figure 3 is a CM〇S image sensor with a 4-crystal type pixel. In addition to the photodiode in one pixel, 8 200803484 still contains 4 transistors (transfer gate). The pole, the reset transistor, the amplifying transistor, and the four MOS transistors used to select the gate). The transistor ' is formed and placed on the p-type substrate as shown in the device configuration of Fig. 32. Further, the Vcc-based power supply voltage and the Vrst-based reset voltage are shown in Fig. 31. The pixel of the jth row (i, j} (where Bu is a positive integer) is used to illustrate that the transmission gate is applied with a voltage pulse pTi ^ 吏 & through the read control line of the i-th column, 纟The signal charge stored in the photodiode is transmitted to the node connecting the transfer gate, the reset transistor, and the amplifying transistor at a predetermined timing. The transistor is reset, and a voltage is applied through the reset line of the first column. The pulse is turned into a conducting state, and passes through the transmitting idle electrode that has become the conductive state, and resets the signal charge stored in the photodiode at a predetermined timing (adding a predetermined resetting voltage Iu to the photodiode). The amplifying transistor connected to the node is configured as a source follower (so muscle), and has a function of amplifying the signal charge sent to the node. The gate is selected by the first brother. Column selection line (not shown) to apply a voltage pulse For the s SEU to become the V-pass state, and at the same time point, the amplified signal charge is transmitted to the opposite line of Ding Ying's line of the J line. Further, the CSN connected with the 4 lang point indicates the section# Z is the parasitic capacitance generated by black. The CMOS image sensor has a circuit structure of pixels, and there are also three transistor types. In the three transistor types, the pixels are excluded from the photodiode. It also contains three transistors (Panyu + „ electric Japanese body, amplifying transistor, MOS transistor for gate selection). That is, , , , , , , , , , , , , , , , , , , , , , The circuit configuration of Fig. 31 can be in the form shown in Fig. 32. Also, in the surface area of the P-type Si (si) substrate, it is divided into plural numbers by the element isolation insulating film. In the device region, a photodiode, a transfer interpole, a reset transistor, an amplifying transistor, and a closed cell are respectively formed to form four nanocrystals. In a device configuration of a conventional CMOS image sensor It can be understood from the main section of the figure, whether it is 4 transistor type or 3 In the crystal type, four or three MOS transistors occupy most of the pixel area, and the area ratio (i.e., "opening ratio") occupied by the photodiode (the opening portion) in the pixel area is relatively small. The aperture ratio of the conventional CM〇s image sensor is generally as low as about 3〇%. Therefore, there is a problem of low sensitivity. If the problem of low sensitivity is to be removed, then the large pixel area (pixel size) must be However, this is inconsistent with the need for miniaturization, and is not an ideal practice. The CMOS sensor for solving the first problem is disclosed in the patent document ι (Japanese Patent Laid-Open Publication No. Hei. No. 4-266957). The second of the device can achieve simultaneous exposure of all the pixels. 胄cm〇S image sensing: characterized by: having a light-receiving element in the pixel; for transmitting the signal charge generated by the buffer to the i-th segment of the next segment a storage unit; a storage unit that stores an output of the first transport mechanism; an initialization mechanism for performing charge initialization of the first portion; a connected lightning communication mechanism; and a second transfer mechanism from the second transport mechanism :,,,Voltage a charge detection unit that reads externally; it is for all

1 冢 , , 一起 一起 一起 一起 一起 一起 一起 一起 一起 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第Item 1). The effect of the invention of the 200303484 α is that "in the CMOS image sensor, an electronic exposure operation that enables all pixels to be simultaneously initialized, 1. The pixel circuit can also be simplistic in a simple process. Also, in the pixel Zoom in to achieve low noise (see paragraph 0036). On the other hand, in recent years, a semiconductor device in which a plurality of semiconductor wafers are laminated to form a three-dimensional structure has been proposed. For example, in the "1999 IEDM Technical Digest" published by Kino et al. in 1999, "a smart image sensor chip having a three-dimensional structure" has been proposed (see Non-Patent Document 1). The image sensor wafer has a four-layer structure, a processor array and an output circuit are disposed on the i-th semiconductor circuit layer, and a data flash lock circuit and a shield circuit are disposed on the second semiconductor circuit layer. An analog/digital converter; an image sensor array is disposed on the fourth semiconductor circuit layer. At the top of the image sensor array is covered with a layer of quartz glass containing a microlens array formed on the surface of the quartz glass layer. In each of the image sensors in the image sensor array, a photodiode as a semiconductor light receiving element is formed. Between the semiconductor circuit layers constituting the four-layer structure, an adhesive is used to form a mechanical connection, and the buried wirings using the conductive plugs and the microbump electrodes that are in contact with the buried δ and the wiring are formed to form each other. Electrical connections. In addition, in "The Japanese Society of Applied Physics" issued by Lee et al. in April 2000, the "Development of 3D Layering Technology for Highly Parallel Image Processing Wafers" is proposed. An image processing wafer is proposed, which includes The image sensor is the same as the solid-state image sensor proposed by Kino et al. (Ref. 11 200803484, Non-Patent Document 2). The image processing wafer of Lee et al. has substantially the same structure as the solid-state image sensor proposed by Kino et al. in the above paper. The conventional image sensor wafer and image processing wafer disclosed in Non-Patent Documents 1 and 2 are a plurality of semiconductor wafers (hereinafter also referred to as wafers) having a desired semiconductor circuit therein. After laminating and fixing each other, the obtained wafer laminate is diced and divided into Φ plural wafer groups to be manufactured. In other words, the semiconductor wafer in which the semiconductor circuit is formed is stacked and integrated at a wafer level, and then formed into a two-dimensional laminated structure, and then divided to obtain an image sensing wafer. Or image processing wafers. Further, in the conventional image sensor wafer and image processing wafer, a plurality of semiconductor circuits stacked inside the wafer constitute a "semiconductor circuit layer". [Non-Patent Document 1] Kurino et al., "Intelligent Image Sensors with Three-Dimensional Structures", 1999 IEDM Technical Abstracts 36.4.1 ~ 36·4·4 (Η· Kurino et al·, "Intelligent Image Sensor Chip With Three Dimensional Structure,,, 1999 IEDM Technical Digest, pp. 36.4.1-36.4.4, 1999) [Non-Patent Document 2] Li et al., "Three-dimensional for highly parallel image processing wafers" Development of Integrated Technology", Journal of the Applied Physics Society of Japan, Vol. 39, p. 2473~2477, Part 1 4B, April 2004 (K. Lee et al., ''Development of Three-Dimensional Integration Technology for Highly 12 Parallel Image-Processing Chip'', Jpn. J. Appl. 12 200803484 phys. Vol. 39, pp. 2474-2477, April 2000) [Patent Document 1] JP-A-2004-266597 (Fig. 2) Figure 8, Figure 12, Figure 15) [Summary of the Invention] One, one ~ m ~ Wang) Peng image sensor, there is the possibility of simultaneous storage of all pixel signal charges (in other words, simultaneous exposure), and pixel openings Two problems with low rates.

In the conventional CMOS image sensor disclosed in Patent Document 1, simultaneous exposure of all pixels is achieved. However, in each pixel, in addition to the RGB member, it is necessary to provide the first transmission when the 笊=load generated by the light-receiving element is transmitted to the —1 transmission mechanism m of the lower segment. a storage unit for outputting the mechanism, an initialization mechanism for initializing the light receiving element and the charge of the stored material, and a transfer mechanism connected to the storage unit. Therefore, the CMOS image is connected to the 3-transistor type. The risk is added to the storage unit. Therefore, in the LM〇s image sensor, there is a problem that the aperture ratio of the pixel is low. In the image sensor wafer and the image processing wafer disclosed in the documents 1 and 2, only the contents of the three-dimensional laminated structure are laminated and fixed by the semiconductor wafer or the semiconductor wafer. The address designation type 丨, S knows the reference. The above two problems are not considered in the above points and the Λα ^ ^ ^ well y lies in, i, a sensor circuit and address finger ^ ^ ^ & like a sensor, for all the usual desks, how can it be essentially the same as the new ones (beautiful exposure on the babe), 13 200803484 and, compared to the conventional address-specific image sense The detector can achieve a higher pixel aperture ratio. Another object of the present invention is to provide a sensor circuit and an address finger j-type image sensor, which can avoid the occurrence of a conventional address-specific image sense/ Another object of the image distortion that can be seen in the high-speed moving object is to provide an address-specific image sensing so that the total area of the light-receiving area can be relative to the total area of the photographing area. The area is up to a high ratio. The other objects of the present invention will be apparent from the following description and the accompanying drawings. (1) The sensor circuit of the first aspect of the present invention has a plurality of pixels arranged in an array and is used for address designation. The address-specific image sensor of each of the pixels is characterized in that: a plurality of pixel blocks are formed by paralleling a plurality of the pixels in a predetermined number in total and nodes; resetting the transistor, connecting And the common node of each of the pixel blocks is configured to reset a plurality of pixels in the pixel block; and the amplifying transistor is connected to each of the plurality of common nodes of the pixel block for amplifying the pixel block a signal sent by a plurality of pixels in the pixel block; in the pixel block, each pixel includes: a photoelectric conversion element that generates a signal charge corresponding to the illumination light; and a gate element that is disposed in the photoelectric conversion element and the pixel area A sensor scale circuit between the common nodes of the block. (7) The sensor circuit of the first aspect of the present invention has a plurality of pixel blocks, and the plurality of pixel blocks are a plurality of pixels in a predetermined number. In the example, each of the pixels includes: a photoelectric conversion element corresponding to a t-signal charge; and a 帛1 idler element, which is disposed in the photoelectric conversion 疋 200 803 803 803 803 803 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 a path between the device and the common node of the pixel block. X, in which the common node of the image is connected with a reset transistor and an amplifying transistor... This 'shares the reset transistor in each pixel block' And the amplification means that the reset transistor and the amplification 琶 crystal are not provided inside the pixel. In the sensor circuit, the signal charge generation, storage, and even signal output operation are performed as follows. First, the reset transistor provided in each of the pixel blocks is used to reset (initialize) (total reset) all of the pixels, so that the common block is set to be: The established reset voltage. At this time, the first gate state of the photoelectric conversion element is set. Χ ^

Then, the first gate element is turned off, and then the light is emitted, and all of the pixels (photoelectric conversion elements) are generated and stored in the entirety of the pixels. Then, in each of the pixel blocks, the first gate element is turned on in time, thereby, the signal corresponding to the signal charge stored in the pixel in the pixel block is timed. The common node reads. This action is performed simultaneously in a plurality of blocks. At this time, from the beginning of the signal reading of one pixel in the pixel block until the sfl number of the other pixel is read, the reset transistor 15 200803484 must be used to reset the common node during this period. . The reason is that if the common node is not reset, it may be affected by the residual signal that is read first, and the subsequent air number changes. The signals read in the above manner in each of the pixel blocks are sequentially or simultaneously amplified by the amplified transistor, and then outputted from the output terminals thereof. That is, when the output end of the amplifying transistor is one, the signals sequentially sent from the plurality of pixels in the pixel block are sequentially outputted from the output terminal after being amplified by the amplifying electric crystal. Output. On the other hand, if the total number of output terminals of the amplifying transistor is equal to the total number of pixels in the pixel block, a plurality of output terminals of the amplifying transistor are output in parallel. At present, the fast exposure speed (that is, the shortest signal charge storage period) is (1/8000) seconds (=125//sec), so the signal of 疋η for all the pixels is set as follows. The storage (exposure) of the charge can be performed substantially simultaneously, that is, the time required for the _ reset operation of the common node by the reset transistor to reach the necessary number of times [for example, (η-1) times (total weight) Set the time), and the sum of the time required for the signal charge of the pixel in each pixel block to be amplified by the corresponding amplifying transistor (total amplification time) must be far from the shortest signal charge storage period (=125) //sensor). In other words, by using the sense as a circuit, the signal charge of all of the pixels can be stored substantially simultaneously (substantially simultaneously exposed). Further, since the image can be simultaneously exposed by the above-described method, the image distortion of the conventional address-based image sensor does not occur, and the object to be moved at a high speed can be photographed. 16 200803484 In the sensor circuit of the first aspect of the present invention, for each of the pixel blocks, the reset transistor and the amplifying transistor are disposed outside the pixel block, and therefore, the pixel is only It suffices to include one photoelectric conversion element and one first gate element (usually a MOS transistor). Therefore, if the sensor circuit is used, a higher pixel opening can be realized compared to a conventional address-specific image sensor that includes two or four MOS transistors in addition to the photoelectric conversion elements in the pixel. rate. (3) A preferred embodiment of the sensor circuit of the third aspect of the present invention is such that the amplifying transistor has a single output terminal. The advantage of this situation is that a section of wiring that is connected to the output of the amplifying transistor tends to be simple. Preferably, in this embodiment, the storage capacitor element connected to the output end of the amplifying transistor and the output transistor for controlling the output of the signal stored in the capacitor element are further provided. This is advantageous in that the signal stored in the capacitive element can be output at a different timing from the opening and closing of the first gate element by using the output electrode. In another preferred embodiment of the sensor circuit of the first aspect of the present invention, the amplifying transistor has an output of an equal number of pixels in the pixel block corresponding to the amplifying transistor, and is outputted at the same The second gate element is connected to the terminal. In this case, each of the second gate elements can be opened and closed in synchronization with the corresponding first gate element, whereby signals from a plurality of pixels in the pixel block can be outputted by the plurality of outputs. The result is output in parallel and in parallel, and has the advantage that the signal processing of the next segment can be performed quickly. In this example, it is preferable to further comprise: a plurality of storage capacitor elements respectively connected to the plurality of output ends of the amplifying transistor; and a plurality of outputs for controlling the output of the signals stored by the capacitors of the 200803484 system Transistor. The advantage of this moon shape is that by using a plurality of the output transistors, the signals stored in the plurality of capacitor elements can be output at a different timing than the opening and closing of the second gate elements. Another preferred embodiment of the sensor circuit of the first aspect of the present invention is to reset all of the pixels using all of the reset transistors before all of the pixels are generated and stored as signal charges. The pixel block, the signal corresponding to the signal charge stored by the pixel, is read by the corresponding common node in time series, and then transmitted to the corresponding amplifying transistor. The advantage of this situation is that it is easy to achieve substantially simultaneous exposure. (4) A sensor circuit according to a second aspect of the present invention, comprising: a plurality of pixels arranged in an array, and an address specifying image sensor for selecting each of the pixels by address designation, wherein And having: a plurality of pixel blocks, wherein the plurality of pixels are connected in parallel to each common node by a predetermined number; and an amplifying transistor connected to each of the plurality of common nodes of the pixel block for amplifying the pixel a plurality of signals sent by the pixel in the block; in each pixel block ten, each of the pixels includes: a photoelectric conversion element that generates a signal charge corresponding to the illumination light; and a second gate element disposed on the photoelectric conversion element And a path between the common node of the pixel block; and resetting a connection point of the transistor to the photoelectric conversion element to perform resetting of the pixel. (7) A sensor circuit according to a second aspect of the present invention, comprising a plurality of pixel blocks 'the plurality of pixel blocks' is a plurality of pixels in an amount of money (Example 18 200803484 = n, η is an integer of 2 or more ) is constructed in parallel with a common node. Each pixel in each of the pixel blocks includes, in addition to a photoelectric conversion element, which is corresponding to the illumination light to generate a signal charge, and a path between the common node of the photoelectric conversion element and the pixel region. In addition to the gate element, a reset transistor is further included, which is connected to the connection point of the photoelectric conversion element and the (4) 1 gate element to reset the pixel. χ, a common transistor is connected to each of the pixel blocks, and an amplifying transistor is connected. Therefore, in each of the pixel blocks, the enlarged packets can be shared. In the sensor circuit in which the second aspect of the pixel is not provided in the inside of the pixel, the configuration of the reset transistor is different from the sensor circuit of the first aspect of the present invention. :ρ π In the sensor circuit of the viewpoint of the 帛 υ i, the reset electro-crystal system is disposed in each of the pixel blocks (also resetting the electro-crystal system in each of the main sides) The sensor of the second aspect of the present invention: = 杳 the reset transistor, for each pixel block to which the plural = pixel is set: (that is, the reset transistor system is disposed in each pixel ). Therefore, the following methods are used to carry out the action of generating, storing, and even outputting signal charges. First, for each of the pixel blocks, the reset transistor is placed, and all of the pixel blocks are heavily wf (initialized) (overall reset) for all the pixels. The block will recognize the common node - τ and the wind resets the voltage. At this time, the photoelectric conversion element is set to the state. The first gate element is turned on. Next, the first gate is used. When the element is kept in the off state, the first gate element of the 19 200803484 is turned off, and light is applied to all of the pixels (photoelectric conversion elements), so that the signal charges can be generated and stored as a whole.

Then, in each of the pixel blocks, the third gate element is sequentially turned on according to the timing, whereby the signal corresponding to the chirp charge stored by the pixel in the pixel block is time-dependent. The corresponding common node is read sequentially. This action is performed simultaneously in a plurality of blocks. At this time, from the beginning of reading a signal in the pixel block, until the signal is read from another pixel, the first gate element needs to be temporarily turned on to use the weight. A transistor is placed to reset the common node. The reason is that if the common node is not reset, it is feared that the residual influence of the signal read first will cause the subsequent signal to change. In each of the pixel blocks, the signals read in the above manner are sequentially or simultaneously amplified by corresponding (4) amplifying the transistors, and are outputted from the output terminals thereof after the absence. Also _, when the amplifying transistor has an output terminal, the plurality of images of the huigui block are sent in pure order (4), and the output is terminated by the output terminal in the time of the discharge. Output. The other Hd is the total number of output terminals of the amplifying transistor, and is equal to the sum of the pixel blocks, and is rotated by a plurality of output terminals of the amplifying transistor. This point and the sensor of the present invention, the fastest exposure speed in practice (that is, the shortest, therefore, the quality of the signal charge storage (exposure) of all the pixels is solidified by the following method, Keeping, that is, resetting the transistor to reset the common node up to 20 200803484 2 times (for example, (four times) times) (total reset, the signal charge of the pixel in each of the prime blocks Corresponding amplification: The sum of the time required for volume amplification (total amplification time) must be much less than the shortest:

During the storage period (=12w, in other words, by using the sensation benefit circuit, the signal charge of all the pixels can be simultaneously simultaneously exposed on J). Shell does not happen to be known to move at high speed

Further, since the image of the address-specified image sensor can be simultaneously exposed in the above manner, the object to be photographed is photographed. Furthermore, in the sensor circuit of the second aspect of the present invention, for each of the pixel blocks, the amplifying transistor is disposed outside the pixel block. Therefore, in the pixel, only one pixel is included. A photoelectric conversion element, a first gate element (usually a Mos transistor), and a reset transistor (pass 4 is a MOS transistor). Therefore, by using the sensor circuit, the phase car: in addition to the photoelectric conversion element in the pixel, there are three or four (four) purchases of the electric body of the known address & stereo image sensor, can be achieved High pixel aperture ratio. (6) A preferred embodiment of the sensor circuit of the second aspect of the present invention is such that the amplifying electrode body has a single wheel #. The advantage of this situation is that the wiring of the section below the output of the amplifying electric day body tends to be simple. In a preferred embodiment of the present invention, the storage capacitor element connected to the output end of the amplifying transistor and the wheel-out transistor for controlling the output of the capacitor are stored. The advantage of this case is that the signal stored in the capacitive element by the use of the 4-output transistor can be output at a point when the 21 200803484 is different from the opening and closing of the first gate element. Another preferred embodiment of the sensor circuit of the second aspect of the present invention is that the amplifying transistor has an equal number of rounds of the total number of pixels in the pixel block corresponding to the amplifying transistor, and the output is at the outputs The second gate element is connected to the terminal. In this case, each of the 帛2 gate elements can correspond to the first! The inter-pole element is synchronously opened and closed. Thereby, the signals from the plurality of pixels in the pixel block can be output in parallel by a plurality of the output terminals. The result 'has the advantage of being able to perform the signal processing of the next-stage quickly. In this example, the #乂' system further includes: a plurality of storage capacitor elements respectively connected to the plurality of output ends of the amplifying transistor; and a plurality of output electrodes for controlling the output of the signals stored by the "etc. Crystal. An advantage of this is that by using a plurality of the output transistors, the signals stored in the plurality of capacitive elements can be output at a different timing than when the first gate elements are opened and closed. Another preferred embodiment of the sensor circuit of the second aspect of the present invention is to reset all of the pixels as a whole by using all of the reset transistors before all of the pixels are generated and stored. Each of the pixel blocks, the signal corresponding to the signal charge stored in the pixel is read by the corresponding common node in time series, and then transmitted to the corresponding amplifying transistor. The advantage of this situation is that it is easy to achieve substantially simultaneous exposure. (7) The address specifying image sensor of the third aspect of the present invention has a plurality of pixels arranged in an array, and selects a pixel by address designation, and is characterized in that: a pixel block, wherein a plurality of the pixels are connected in parallel with a predetermined number 22 200803484 to a common node; a reset transistor is connected to a common node of each pixel block for resetting a plurality of pixels in the pixel block a pixel; and an amplifying transistor connected to a plurality of common nodes of the pixel block,

Amplifying a signal sent by a plurality of the pixels in the pixel block; in each of the pixel blocks, each pixel includes: a photoelectric conversion element that generates a signal charge corresponding to the illumination light; and a first gate element, a path between the photoelectric conversion element and a common node of the pixel block; at least the photoelectric conversion element is formed in the first semiconductor circuit layer constituting the three-dimensional laminated structure, and the first gate element is reset The transistor and the amplifying electric body are formed in the semiconductor circuit layer constituting the second or third of the three-dimensional laminated structure. (8) The third embodiment of the present invention is characterized in that the address sensor type image sensor of the present invention is equivalent to the sensor circuit of the above aspect of the present invention, and at least a plurality of the photoelectric devices are used. The conversion element is formed in the three-dimensional structure conductor circuit layer, and the gate electrode element, the reset transistor, and the germanium-magnification transistor are formed in the subsequent memory layer structure in the semiconductor circuit layer. Or the third reason therefore, based on the same reason as the present hair, the simultaneous exposure of all the pixels of the pixel 11 circuit, and the relative private storage of the electricity can be substantially simultaneously stored (substantially higher) Pixel On:: A well-known address-specific image sensor, in which the image sensor does not have a known address specification for photography. The distortion shape can be used for two-speed movement. The subject 23 200803484 Furthermore, since the conventional address-specified image sensor has a high pixel aperture ratio, the ratio of the total area of the light-receiving area to the total area of the photographing area can be increased.

(9) In a preferred embodiment of the address specifying image sensor of the third aspect of the present invention, in addition to the plurality of the photoelectric conversion elements, a plurality of the first plurality are also provided! The gate element is formed in the second semiconductor circuit layer, and a plurality of the amplifying transistors and a plurality of the resetting transistors are formed in the second or third semiconductor circuit layer. In this case, among the plurality of semiconductor circuit layers, a plurality of the third gate electrodes 70 are stored in addition to the plurality of the photoelectric conversion elements. However, in each pixel, in addition to the photoelectric conversion elements, It is only necessary to include one transistor constituting the first gate element, and therefore, conventional address-based image sensing is performed in comparison with the photoelectric conversion element including four transistors or three transistors in each pixel. The pixel aperture ratio can be increased. According to another preferred embodiment of the address specifying image sensor of the third aspect of the present invention, in addition to the plurality of the photoelectric conversion elements, the plurality of the first gate elements and the plurality of reset transistors are formed. In the second semiconductor circuit layer, a plurality of the amplifying transistors are formed in the second or third conductor circuit layer. In this case, 'This is the case! In the semiconductor circuit layer, a plurality of the first interpole elements and a plurality of reset transistors are included in addition to the plurality of the photoelectric conversion elements. However, in each of the pixels, only the photoelectric conversion elements are included. One transistor of the first gate element, again, the number (1/n). Therefore, one transistor or three transistors can increase the number of pixels of each pixel to open the total number of reset transistors as long as the total pixel is compared with the conventional address-specific image sensing including 4 in addition to the photoelectric conversion element. , a further preferred example of the address specifying image sensor of the third aspect of the present invention, wherein the amplifying transistor has a total number of pixels in the pixel block corresponding to the amplifying transistor An equal number of outputs are connected to the second gate elements (selective transistors) at the outputs. Further, in addition to the plurality of the photoelectric conversion elements, a plurality of the second gate elements, a plurality of the reset transistors, and a plurality of the amplifying transistors are formed on the second semiconductor

In the circuit layer, a plurality of the second gate elements (selective transistors) are formed in the second or third semiconductor circuit layer. In this case, in the semiconductor circuit layer, a plurality of the first gate elements, a plurality of the reset transistors, and a plurality of the amplifying transistors are present in addition to the plurality of the photoelectric conversion elements. However, in addition to the photoelectric conversion element, each pixel includes only one transistor constituting the first gate element, and the total number of the reset transistor and the amplifying transistor is only (10) of the total number of pixels. Just fine. Therefore, the conventional address of four transistors or three transistors other than the photoelectric conversion element means that the image sensor can increase the pixel aperture ratio of each pixel. Another preferred example of the address-specific image sensor of the non-inventive 3 view is that only a plurality of the photoelectric conversion elements are formed in the semiconductor circuit layer, and the plurality of the fi gate elements and the plurality of The reset transistor and a plurality of the amplifying transistors are formed in the second or third semiconductor circuit layer. In this case, in the first ^ A thousand conductor circuit layer, only a plurality of the photoelectric conversion elements are formed, and the respective boundaries Ιτ are completely free of the electric crystal. Therefore, the pixel aperture ratio of each pixel can be improved as compared with the conventional address-based image sensor including four transistors or 25 200803484 three transistors in addition to the photoelectric conversion element. In particular, the pixel aperture ratio is maximized. A preferred embodiment of the address specifying image sensor of the third aspect of the present invention is such that each of the amplifying transistors has a single output terminal. The advantage of this situation is that the wiring of the section below the output of the amplifying transistor tends to be simple. Preferably, in the second or third semiconductor circuit layer, the storage capacitor element connected to the output end of the amplifying transistor and the output of the signal stored by the capacitor element are further provided. The output transistor. The advantage of this case is that by using the output transistor, the signal stored in the capacitive element can be output at a different timing than the opening and closing of the first gate element. Another preferred embodiment of the address specifying image sensor of the third aspect of the present invention is that each of the amplifying transistors has an output of an equal number of pixels in the pixel block corresponding to the amplifying transistor. And connected to the second gate element at the output terminals. In this case, each of the second gate elements can be opened and closed in synchronization with the corresponding first gate element, whereby signals from a plurality of pixels in the pixel block can be used by a plurality of the output terminals. Two p mode output. As a result, there is an advantage that the signal processing of the next segment can be performed quickly.

The semiconductor circuit layers of 2 or 3 are respectively connected to the plurality of output terminals of the amplifying transistor, and a plurality of output transistors for controlling the capacitive elements thereof. The advantage of this case is that in 26 200803484, a plurality of the round-out transistors are used, and a plurality of the capacitor elements can be output at a different timing from the opening and closing of the first gate element. In the third aspect of the present & month, the address-specific image sensor is further characterized in that all of the pixels are collectively weighted with all of the reset transistors before all of the pixels are generated and stored. The signal corresponding to the signal charge stored in the pixel in each of the pixel blocks is read by the corresponding common node in time series, and then transmitted to the amplifying transistor of the phase. The advantage of this situation is that it is easy to achieve substantial simultaneous exposure. (10) The address specifying image sensor of the fourth aspect of the present invention, comprising: a plurality of pixels arranged in an array, and selecting each of the pixels by address designation, wherein: ??? a plurality of j pixel regions &, wherein a plurality of the pixels are connected in parallel to the common node by a predetermined number; and an amplifying transistor connected to the plurality of common nodes of the pixel block for amplifying the pixel a plurality of signals sent by the pixel in the block; in each of the pixel blocks, each of the pixels includes: a photoelectric conversion element that generates a signal charge corresponding to the illumination light; and a first gate element disposed on the photoelectric conversion element a path between the common node of the pixel block; and a reset transistor connected to the connection point of the photoelectric conversion element and the second gate element to perform resetting of the pixel; at least forming the photoelectric conversion element in the composition In the i-th semiconductor circuit layer of the three-dimensional laminated structure, the i-th gate element, the reset transistor, and the amplifying transistor are formed in the second constituting the three-dimensional laminated structure. 00803484 or in the semiconductor circuit layer after the third. (11) The first aspect of the present invention is to use the above-mentioned point of view of the present invention: the address specifying image is a plurality of the photoelectric conversion elements: the sensor circuit of the cow=, 2 viewpoint, at least in the semiconductor circuit layer, and The pre-fabricated structure, the younger brother i, and the amplifying transistor 1 are formed in the first interpole element, the reset transistor, and the semiconductor circuit layer after 3. ^ 戍 同 同 与 与 与 与 所述 所述 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感The address specifies the type of shadow "Bei II achieves a higher pixel aperture ratio. χ, the well-known address finger image sensor does not occur in the image of the living object of the high-speed moving object in the case of the sci-fi ancient & ^ 像 ~ image distortion. In addition, the higher the pixel aperture ratio 'by*', which has a higher pixel aperture ratio than the known address, can increase the ratio of the total area of the light-receiving area to the total area of the image-receiving area. (12) The address specifying image sensor of the fourth aspect of the present invention is the same as the above-described address specifying image sensor of the third aspect of the present invention. The only difference between the two is that in the address-specific image sensor of the third aspect of the present invention, the reset electro-crystal system is disposed in each of the regions (ie, the reset electro-crystal system is disposed at On the other hand, in the address specifying image sensor of the fourth aspect of the present invention, the reset crystal system is provided in a plurality of photoelectric conversion elements to which each of the blocks belongs. In other words, in the preferred embodiment of the address specifying image sensor of the fourth aspect of the present invention, in addition to the plurality of the photoelectric conversion elements, a plurality of the first gate elements are formed on the second semiconductor. In the circuit layer, a plurality of the amplifying transistors and a plurality of reset transistors are formed in the second or third semiconductor circuit layer. In this case, in the first semiconductor circuit layer, a plurality of the third gate elements are stored in addition to the plurality of the photoelectric conversion elements. However, in addition to the photoelectric conversion elements, It is only necessary to include one transistor constituting the first gate element, and therefore, compared with the conventional address-specific image sense in which the photoelectric conversion element includes four transistors or three transistors in each φ pixel The detector can increase the pixel aperture ratio. Another preferred example of the address specifying image sensor of the fourth aspect of the present invention is that, in addition to the plurality of read photoelectric conversion elements, the plurality of the first gate elements and the plurality of reset transistors are also Formed in the ith semiconductor circuit layer, a plurality of the amplifying transistors are formed in the second or third conductor circuit layer. In this case, in the germanium conductor circuit layer, except for a plurality of the photoelectric conversion elements, a plurality of the third gate elements and a plurality of reset transistors are included, but in each pixel, In addition to the photoelectric conversion 70, only the transistor constituting the first gate element and the reset transistor are included, and therefore, four transistors or three transistors are included in addition to the photoelectric conversion element. The conventional address-specific image sensing type of image can increase the pixel aperture ratio of each pixel. In another preferred embodiment of the address specifying image sensor of the fourth aspect of the present invention, the amplifying transistor has an output of an equal number of pixels in the pixel block corresponding to the amplifying transistor, and A second gate element (selective transistor) is connected to each of the output terminals. In addition to the plurality of light 29 200803484 private conversion elements, a plurality of the first gate elements, a plurality of the reset germanium crystals, and a plurality of the amplifying transistors are formed in the first semiconductor circuit layer. Further, a plurality of the second gate elements (selective transistors) are formed in the second or third semiconductor circuit layer. In this case, in the first half body wrap layer, in addition to the plurality of the photoelectric conversion elements, there are a plurality of the first gate elements, a plurality of the reset transistors, and a plurality of turns Amplifying the transistor, however, except for the photoelectric conversion element in each pixel, including the transistor constituting the first gate element and the reset transistor, and the total number of the amplified transistors only needs pixels The total number of (l/n) ports is a conventional address-based image sensor that includes four transistors or three transistors in addition to the photoelectric conversion elements, thereby increasing the pixel aperture ratio of each pixel. In the conductor circuit layer. In this shape, a || transistor is formed in the 篦1". H crystal or 3 and each pixel is whitened. Another preferred example of the address specifying image sensor of the fourth aspect of the present invention is that only a plurality of the photoelectric conversion elements are formed in the second semiconductor circuit layer, and the plurality of the first gate elements and the plurality of the first gate elements The reset transistor, and a plurality of the amplifying transistors are formed in the second or third semiconductor circuit layer

30 200803484 has the advantage that the wiring of the section below the output of the amplifying transistor tends to be simple. Preferably, in the second or third semiconductor circuit layer, the storage capacitor element connected to the output end of the amplifying transistor and the signal for storing the capacitor element are preferably provided. Output output transistor. The advantage of this case is that by using the output transistor, the signal stored in the capacitive element can be output at a different timing than the opening and closing of the first gate element. Another example of the address specifying image sensor of the fourth aspect of the present invention is that each of the amplifying transistors has an output of an equal number of pixels in the pixel block corresponding to the amplifying transistor. And connected to the second gate element at the output terminals. In this case, each of the second gate elements can be opened and closed synchronously with the corresponding first gate element, whereby signals from a plurality of pixels in the pixel block can be multiplied by the plurality of outputs Parallel output. As a result, there is an advantage that the signal processing of the next segment can be performed quickly. In this example, it is preferable that the plurality of storage capacitor elements connected to the plurality of output terminals of the amplifying transistor are further advanced in the second or third semiconductor circuit layer, and are used for controlling A plurality of output transistors of the output of the signals stored by the capacitive elements. The advantage of this case is that by using a plurality of the output transistors, the signals stored in the plurality of capacitor elements can be output at a different timing than the opening and closing of the ith gate (4). Another preferred example of the address-based image sensor of the fourth aspect of the present invention is that before the (four) pixel is generated and stored as a signal charge, 31 200803484 all of the reset transistors are used for all of the pixels. The reset is performed as a whole, and the signal corresponding to the signal charge stored in the pixel block is read by the corresponding common node according to the timing, and then transmitted to the corresponding-high-amplifier Carcass. The advantage of this situation is that the stomach is exposed to the stomach. (13) In the sensor circuit according to the first and second aspects of the present invention, and the address-based image sensor of the third and fourth aspects of the present invention, the "photoelectric_switching element" is performed. An element capable of generating electric charges corresponding to the irradiation of light. The "photoelectric conversion element" is preferably a photodiode of a semiconductor element. However, the present invention is not limited thereto as long as the element has a function of generating electric charges corresponding to irradiation light, and any of the inventions can be used. Type. The "first pole member" refers to a member having a gate function for opening and closing a plurality of connection paths of the photoelectric conversion element and a common node corresponding thereto. It is preferable to use a MOS transistor, but the present invention is not limited thereto. "Reset the transistor", as long as the function in the transistor can be used to reset the signal charge generated by the plurality of pixels (the photoelectric conversion element) to which the block belongs, any transistor can be used. The M〇s transistor is suitably used as a "reset transistor", but the present invention is not limited thereto. "Amplifying the transistor" as long as the function of the transistor has a function, the corresponding 5fL number of the signal charge generated by the plurality of pixels (the photoelectric conversion element) to which the pixel block belongs can be amplified according to the timing to generate an output signal. , can use any transistor. The MOS transistor is suitably used as an "amplifying transistor", but the present invention is not limited thereto. The "first semiconductor circuit layer" and the "second or third semiconductor 32 200803484 circuit layer layered semiconductor circuit" respectively represent a layer of a semiconductor circuit, in other words, in the form of a semiconductor substrate, The mold is not formed by "components" and "wiring" formed on the inside or the surface of the semiconductor substrate, but is not limited thereto. The material of the "semiconductor substrate" is not limited, and it is only required to form a desired semiconductor element or circuit, and may be a compound of Si Shi, a compound semiconductor or another semiconductor. The structure of the "semiconductor substrate" is not limited, and may be a single substrate made of a semiconductor, or may be a so-called φ S〇I (silicon On lnsuiat0r) substrate. + "First semiconductor circuit layer" and "Second or third semiconductor layer" can be used as needed (for example, 'The semiconductor circuit layer and the second or third semiconductor circuit layer cannot be obtained. When it is rigid, it is fixed to the "support substrate" which is sufficient to read it. The material of the "support substrate" is not limited. That is, it may be a semiconductor, a glass, or another material. It may also be a semiconductor substrate in which a circuit is formed, that is, a so-called LSI wafer or LSI wafer. _ ""Embedded wiring" means a wiring or conductor for electrical connection in the direction of lamination in the "the second semiconductor circuit layer" or the semiconductor circuit layer of the second or third semiconductor. In general, the "embedded wiring" is an "insulating film" that covers the entire inner wall surface of a "ditch" or a "through hole" formed in a semiconductor substrate, and is filled in (embedded in) the inner space of the insulating film. Conductive material". However, the constitution thereof is not limited to this. Here, the channel or the through hole is not limited as long as it has a desired depth and can be used as a conductive material for embedding wiring. The depth, opening shape, opening size of the "ditch" or "through hole", 33 200803484 cross-sectional shape, etc., can be set as needed. The method of forming the "ditch" or the "through hole" may be formed by selectively removing it from the surface side of the semiconductor substrate, and any method may be used. For example, an anisotropic etching method using a mask is quite suitable. The "insulating film" covering the inner wall surface of the "ditch" or "through hole" may be electrically insulated from the semiconductor substrate and the "conductive material" filled in the "ditch" or "through hole". Any absolute film can be used. For example, cerium oxide (SiOJ, lanthanum nitride (SiNx), etc. is quite suitable. The method of forming the "insulating film" is not limited. The "conductive material" filled in the "ditch" or "through hole" is required. Any material may be used as the buried wiring (for example, a conductive plug). For example, a semiconductor such as polyfluorene, a metal such as tungsten (w), copper (Cu), or aluminum (A1) is suitable. Any method can be used as long as the "conductive material" is filled into the "ditch" or the "through hole" on one side of the semiconductor substrate which can be used. The sensor circuit according to the present invention, The following effects can be obtained: (a) the signal charge for all pixels can be stored substantially simultaneously (substantially simultaneously exposed) and has a higher pixel aperture ratio than conventional address-specific image sensors. (b) The image distortion in the conventional address-based image sensor does not occur, and the object to be photographed at high speed can be photographed. According to the address-specific image sensor of the present invention, The following effects: (a) The signal charge for all pixels can be exposed at the same time at substantially the same time, and the image sensor has a higher pixel aperture ratio than the conventional address-based image sensor. (b) The conventional address-specific image does not occur ^ 34 200803484 Image distortion in the detector; (C) The total height of the light-receiving area is 0, which can accumulate the object to be moved at high speed. Ratio of total area in the photographic area [Embodiment] The following Illustrated® is used to describe the preferred embodiment of the present invention. (Embodiment 1 embodiment) Fig. 2 is a view showing a configuration of a sensor circuit of the i-th embodiment of the present invention. Figure! The functional block diagram ' indicates the overall configuration of the address specifying image sensor (hereinafter also referred to as (10) image sensor) using the sensing circuit 1. The sensor circuit i corresponds to the sensor circuit of the first aspect of the present invention. The overall configuration of the image sensor of FIG. 1 is substantially the same as the conventional CMOS (address-specified type) image sensor shown in FIG. 3(a), and has a (kM) column m仃(k, n). And m is an array shape of 2 or more integers, and the parent n") xm pixels u are arranged (hereinafter, the array formed by the pixels n is also referred to as a "pixel array"). The difference between the conventional CM〇s image sensor is that the pixel 11 of the pixel is divided into (kxm) pixel blocks 12; and the reset transistor is not included in each pixel u. Amplify the transistor. That is, in each of the pixel blocks 12, the pixels 11 belonging to the same row are connected in parallel to the common node in units of n (not shown in FIG. 1. Corresponding to the common node 13 in FIG. 2) The pixel blocks 12 constituting the pixel blocks (parameters, 0 2) are also arranged in an array shape. The reset transistor TrRsT and the amplifying transistor TrAMp are disposed outside the pixel block 12 and correspond to the respective pixel blocks 12. In other words, the reset transistor TrRST and the amplification 35 200803484 transistor Τγαμρ ' are shared by the n pixels 11 in each pixel block 12, respectively. Therefore, the total number of reset transistors TrRST is (kxm), and the total number of amplified transistors TrAMP is also (kxm). In the vicinity of each pixel block 12, there are respectively m reset lines 3 1 ' extending along respective rows of the pixel array. Since one reset transistor TrRsT is provided for each pixel block 12, k reset transistors TrRsT are connected to the respective reset lines 31. At each of the output terminals of the reset transistor TrRST, an amplifying transistor TrAMp is connected. Each reset line 31 is used to reset the signal charge stored in the pixel n (i.e., the pixel 11 in the k pixel blocks 12 to which the row belongs). The application of the reset voltage for its pixel i i is controlled using the corresponding reset transistor TrRsT. (Amplifying the transistor Tr when resetting the signal charge of the pixel 1 1

The gate of the AMP is also reset. Each of the amplifying transistors TrAMp is for amplifying signals read by the pixels 11 in the corresponding pixel block 12. The signal amplified by each of the amplifying transistors TrAMP is sequentially sent to the corresponding line signal line 37 through the output terminal of the amplifying transistor A1amp. In the vicinity of each pixel block 12, (kxn) read control lines 32 are further formed, which respectively extend along corresponding columns of the pixel array. Specifically, the setting of the control line 32 is set to n for each of the m pixel blocks 12 to which the same column belongs, for reading signals from the n pixels 11 in each of the pixel blocks 12. In Fig. 1, the n read control lines 3 2 provided for the m pixel blocks 12 to which the same column belongs are integrated and illustrated by a line segment. In the vicinity of the left end of the pixel array, there are provided a vertical scanning material 34 extending along the row of the pixel array 36 200803484. The vertical scanning circuit 34 sequentially scans the (kxn) strips to read the control lines 32 and selects them according to the sequence. At this time, in each of the read control lines 32, the selection signals of the n pixels u respectively included in the pixel arrays 12 to which the corresponding columns belong are sequentially outputted (with the transfer gate control signal $T1 of FIG. 2). ~P τη corresponds). In the vicinity of the lower end of the pixel array, a horizontal signal line 33 extending along the column of the pixel array, a horizontal scanning circuit 35, and m CDS circuits 36 for removing noise are provided. The horizontal scanning circuit 35 selects the CDS circuit 36 by timing according to the timing selection signal 38. The m CDS circuits 36 are respectively connected in parallel with the k line signal lines 37, and the k line signal lines 37 are respectively connected to the output terminals of the k magnifying electric crystals TrAMP to which the row belongs. Therefore, the k amplification transistors TrAMP to which the same column belongs, the k output signals are input in parallel to the corresponding CDS circuit 36. The output terminals of the m CDS circuits 36 are respectively connected to the horizontal signal lines 33, so that the output signals of the CDS circuits 36 are sequentially output to the outside of the image sensor through the horizontal signal lines 33. Next, the sensor circuit 1 for the first embodiment, that is, the sensor circuit 1 for the address specifying image sensor having the above configuration, will be described below with reference to Fig. 2 . 2 is a circuit configuration of two pixel blocks 12 belonging to the jth row (where j$m) of the pixel array. The upper pixel block 12 is tethered to the i-th item from the top (wherein the lower pixel block 12' is tied to the (i+丨) item from the top. Therefore, as needed, above The pixel block 12 is represented by 12 (i, j); the lower pixel block 37 200803484 12 is represented by 12 (i + l, j). The upper pixel block 12 (i, j) is included The pixel 1 1 is located in the [nχ(Μ)+1] column to the (nxi)th column of the jth row. The pixel 11 included in the lower pixel block I2(i+1, j) is Is the [nxi+l] column to the [nx (i+1)] column in the jth row. Since the above two pixel blocks 12(i,j) have the same as 12(i+l,j) In the following description, the pixel block 12 (ij) is mainly described above. _ In the pixel block 12 (ij), n pixels 11 are included, and each pixel 1 1 includes a photodiode And a transfer gate. Therefore, each pixel includes n photodiodes PD^PDn and n transfer gates TG^TGn. Each of the transfer gates TGi to TGn is composed of a MOS transistor. The anodes of the diode PD^PDn are connected to the transfer gate TG^TGn One of the source is connected to the source and the drain region, and the cathode is a terminal or region that is commonly connected to a predetermined potential (usually a ground potential). The other source and drain regions of each of the transfer gates TG^TGn are common. Connected to the common node 13 of _ in the pixel block 12 (ie, 』), that is, n pixels n in the pixel block 12 (i, j) are connected in parallel to the common node i 3. Pixel block 12 ( The common node 13 of i, j) is connected to the source and the drain region of the common reset transistor TrRST provided in correspondence with the pixel block 12 (i, j) by the node 14. And a gate of the common amplifying transistor AMP disposed in correspondence with the pixel block 12...D. The reset transistor TrRST and the amplifying transistor TrAMp are both disposed in the pixel block, The outer side of j). The other source and the drain region of the transistor TrRST are reset and connected to the reset voltage source (reset voltage =, τ). Amplifying power 38 200803484 ^One source and drain region of TrAMP, and DC power supply (supply voltage=(four) material, another-source, (four) region (output side), and the output block of this pixel block, ^ That is, the corresponding line signal line 37) is connected. The wheel end of the electric field TrAMp (the source side and the non-polar area of the output side) is amplified, and the predetermined potential (usually the ground potential) is transmitted through the resistor ' The terminal or region is connected to form an amplifier in the form of a source follower. The capacitor csn connected to the node 系 is the parasitic capacitance generated by the node 14. The node 14 transmits a parasitic capacitance Csn with a predetermined potential (usually grounded) The terminal or region of the potential is connected. The output terminal of the transistor TrAMP is amplified (the source and the non-polar region on the output side are connected to the corresponding signal line 37 as shown in Fig. 1, and the moon b is used to amplify the transistor. The output signal of TrAMp, that is, the timing of the photodiode PD wide PDn (10), is transmitted to the corresponding CDS circuit 36 through the corresponding line signal line 37. From, (10) circuit 36 is Sent to the horizontal signal line for 33 days, The line signal line 3 is selected by the m row selection signal 38 by the scanning of the horizontal scanning circuit %, and the timing output signal is transmitted to the horizontal signal line ^. Thereafter, the _ is in the undone condition line 33. One end of the image sensing source (not shown) is transmitted at one end (at the right end of Fig. 1). All pixel blocks 12 other than the pixel block 12 (1, j) are associated with the pixel area A (' J ^) has the same composition, therefore, in the same way as above, the photo-diode called ~ timing output signal is transmitted to the image sensing person's round of the total;, so 'can do the object to be taken Next, (4) 'The operation of the address-specific image sensor with the sensor circuit 1 (that is, the circuit with the above-mentioned configuration 39 200803484) (from the generation and storage of the signal charge until the signal output) ).

ι All pixels (all photodiodes) are reset as a whole. First, the logic state of each pulse signal (transmitting the gate control signal) p T1~p Τη applied to the gate of the MOS transistor becomes High. And all the transfer gates TG1 to TGn are turned on, and the M〇s transistors are used to form the transfer gates TG TGn of the photodiodes PA to PR which are δ and are placed in all the pixels, that is, The transistor of the ith gate element). Next, the transfer gates TGi to TGn of all the pixels u are kept in the on state, and the logic state of the gate t pulse signal (reset pulse signal) applied to the reset transistor TrRsT is made H, so that all the weights are made Placement transistor

TrRST is turned on as a whole, and the TrRST is set in all the pixel blocks (1) of each transistor. As a result, the predetermined reset voltage..., through the node 14, the common blackout "3, and the transmission call is called ~ call" and simultaneously applied to all the pixels 丨丨 < 冤 冤 极 p p p 苴. , applied to all the pixels U η t J, especially the voltage of the PD of the polar body PD, which is approximately equal to the reset voltage VRST, η t is replaced by a, and all the images like the Xin 11 氺 Φ diode PD ^ PDn are heavy Thus, ', is reset, that is, the "overall reset" is performed. The pixel 11 is integrated as a whole while 2 · exposure (charge storage). Next, the transfer gate control signal φ k gate applied to all the pixels u is applied. TG Guang Ding Gn w Τ 1 Ρ τ η logical makeup energy, & τ τ all transmission gate TG ^ TG A & ~, become Low (L), so that the logic state of the reset control signal ^; At the same time, make 4 L, all reset transistors 40 200803484

TrRST has also become disconnected as a whole. Thereafter, in this state, light is applied to the photodiodes PD1 to PDn of all the pixels u, and all of the photodiodes PDi to pDn are generated and stored as a signal charge. The irradiation time generally reaches hundreds (four) c or even several faces c, which is very long. At the same time as the generation and storage of the signal charge, the logic state of the reset control signal p RST is again turned on, and all the reset transistors ^.R. S ΤΓ are turned on as a whole, and the predetermined time (for example, i # s, so that the logic state of the reset control signal P RST becomes L again and all the reset transistors TrRST are turned off. Thus, the reset voltage can be applied to all nodes i 4 (ie, all amplifications) The gate of the transistor T r a (10) is set to set the gate voltage of all the amplifying transistors TrAMp to a predetermined reference voltage. 3 · The f f f f buy and its amplification in the above manner in all photodiodes pDi~pDn The charge and charge generated and stored are read by the pixel 11 in the form of a voltage by the following method, and then amplified. That is, first, the vertical scanning circuit 34 and the horizontal scanning circuit 35 are used. After the pixel block 12 is selected, the logic states of the n transfer gate control signals ρ Τ1 ρ Τ η in the pixel block 12 are sequentially changed from L to Η, and the transfer gate TG TGn is sequentially changed. Turn-on state. Again, at After the conduction state is maintained for a predetermined time (for example, 〇1//sec), the evasive state is sequentially returned to L. Thus, all the photodiodes PDcPDn from the pixel block 12 are obtained. The signal is read at node 14 according to the timing. During the period of 2008 2008484, all reset transistors Tr ϋ ^ ^ Μ里罝弘日日股lfRST is kept in the off state. Form and the board is destroyed, that is, the connection transistor is connected by 4

Since the gate of the TrAMP' is connected to the node 14, the voltage signal read at the node 14 is immediately amplified by the amplifying transistor I. Further, after the amplified signal, the source and the non-polar region on the output terminal side of the amplified thunder crystal _Tr, amp are outputted to the signal line 37.

When the signal is read from the n pixels u (ie, the photodiode PD^PDn) in the pixel block 12, the signal from the read image _..., for example, the optical package PD1) The end of the operation of the amplification is started until the next image fn is started (for example, during the period of reading the signal of the photodiode p(6), the pixel block 12 must be reset to the transistor TrRST. The state is to temporarily apply the reset voltage VRST to the node 14, and set all of the nodes 14 (the gate of the amplifying transistor TrAMP) to the reference potential (reset). The reason is that if this is not the case, the previous pixel 11 is feared ( For example, the residual influence of the signal of the photodiode PDi) causes a signal error condition in subsequent pixels (for example, the photodiode pD2). Since there are n photodiodes PD] PDn in the pixel block 12, The reading operation is performed by transmitting the gate control signals ρ η to ph, the number of times is n times; the amplification operation by the amplifying transistor TrAMP is performed n times; the resetting action of the amplifying transistor TrAMp is common (η- I) times. Specific and &, for example First, the first transmission idle pole TGI of the pixel block 12 is initially turned into a conducting state, and the voltage signal proportional to the signal charge (that is, the signal charge stored in the i-th optical book PDI) is at a node. 14 42 200803484 Read. The voltage signal is immediately amplified by the amplified transistor TrAMp, and then the obtained amplified signal is transmitted to the signal line 37. Then, the reset electric body TrRST is temporarily turned on, and the amplified power is amplified. The gate of the crystal (node 14) is reset to the reference potential. Thereafter, the voltage signal equal to the signal charge stored by the second photodiode PD2 is read by the node 14. The voltage signal is immediately amplified by the transistor. The TrAMP is amplified, and then it will be received: the signal is transmitted to the signal line 37. Secondly, the reset transistor is temporarily suspended.

The gate of the amplifying transistor TrAMP (node j 4) is reset to the reference voltage by the V-shaped center. Then, the same operation as described above is repeated for the third photodiode Pd3, the fourth photo-electrode 胄pd4, and the like. Finally, the reading operation and the amplification operation are performed on the photoelectrode body PDn, and then the processing of the pixel block 12 is ended. In the image sensor of FIG. 1, the output terminal of the amplifying transistor TrAMP corresponding to the pixel block 12 is one, and therefore, all photodiodes ΡΓ| ^ _ to PD in the pixel block 12 The n signals obtained by the PDn are from the rim # 2 A of the amplifying transistor TrAMP, and the source and drain regions on the side of the dice are rotated to the signal line 3 7 in time series. Also, gp, mountain-P is a signal outputted by the pixel block 12, and is connected to n pulse waveforms in a manner corresponding to a predetermined interval, for reflecting the signal charge amount of the photodiode PD ρ 1 . Timing signal (the amount of illumination). In the above image sensor, the combined w ^ ^ σ leaves have (kxm) pixel blocks 12, and therefore, the above-mentioned actions are repeated (kxm) times during the period 4 of scanning all the pixels. The signal that is rotated by the pixel block 12 is a time-series signal that connects the signal pulses with a predetermined interval, and is sent to 43 200803484. Sample and Hold circuits or analog, digital (A/D) conversion circuits for scheduled signal processing. The fastest exposure speed (ie, the shortest signal charge storage period) is now (1/8000) seconds (=125//sec). Therefore, for (kxm) pixel blocks 12, if the n value (the total number of pixels 11 in each pixel block 12) can be set in the following manner, the pixels to which all the pixel blocks 12 belong can be made (light) The signal charge storage (exposure) of the electrode bodies PDi PDD) can be performed substantially simultaneously, that is, the reset operation of the node 14 (the gate of the amplifying transistor TrAMP) by the reset transistor TrRsT is determined to be a predetermined number of times [also That is, the time required for (n··) times (total reset time) is the same as that of all the pixels η(10) in the pixel block 12, which are corresponding to the signal sent by the photo-polar body PD wide PDj. The sum of the time required for amplification (total amplification time), and then the (kxm) times of the sum is much less than the shortest signal charge storage period (1). The signal charge of all pixels 11 can be stored substantially simultaneously. On the same day, it was exposed.) 独 独 = = (rm) output timing signals, from the other pixel block 12 separate J independent output, therefore, for the 1 type to enter the rod 1 I,, output the day-to-day signal CM that can enter (four) ratio, digital (A/D) conversion, etc. in parallel OS Image Sensors Phase-reduction vehicles are known to benefit from the data processing of ^ 4 that is simultaneously exposed. This point can also be understood by the above action. If the timing output from the prime block 12 is output (4) in the frame to observe 'the end of each image, the closer to the scan time charge is compared to the fa1_a^ in the sweeping period. The longer the storage period (although the phase is produced, the output is the same, the phase of the field is 罝). Therefore, if you want to obtain more accurate image data, or a well-known circuit, you can correct it according to the number. Thereby, it is possible to suppress or avoid the influence. With a large 11 value, it can also be changed during the storage of the latter stage of charge to avoid the change during charge storage. 'There is no known that the south speed movement is due to the fact that it can be simultaneously exposed simultaneously in the above manner. The image distortion of the CMOS image sensor allows the subject to take pictures.

Furthermore, the common reset transistor TrRST and the common amplifying transistor TrAMP are disposed outside the pixel block 12 in a manner corresponding to each pixel block 12, and therefore, in the pixel block 12 Each pixel u, ^, includes a photodiode and a gate element (MOS transistor). Therefore, a higher pixel aperture ratio (for example, about 60%) can be achieved compared to a conventional CM〇s image sensor in which one photodiode still contains three or four MOS f crystals in one pixel. . Furthermore, in the conventional CMOS image sensor, the signal processing is performed in time series according to the number of scanning lines, and a high-speed a/d conversion circuit is required, but the sensor of the first embodiment is used. In the image sensor of the circuit, the η value is set to be smaller than the number of scanning lines, and the parallel connection degree can be improved, because the processing speed of the slower timing output signals can be allowed. Therefore, it is possible to use an a/d conversion circuit which is simpler in construction, and this is also an effect. Further, n output signals from the n photodiodes PD wide PDn are outputted in series by the respective amplifying transistors Tq·, and therefore, wirings of a section below the output terminals of the respective amplifying transistors TrAMp are connected. The trend of 45 200803484 is simple, and this is also the effect. (Second Embodiment) Fig. 3 is a circuit configuration diagram of a sensor circuit 1a according to a second embodiment of the present invention. The address specifying image sensor using the sensor circuit 丨A has the same overall configuration as that shown in the figure, and therefore its description will be omitted. The sensor circuit 1A corresponds to the sensor circuit of the first aspect of the present invention.

The circuit configuration of the sensor circuit 1A shown in FIG. 3 is substantially the same as that of the sensor circuit i (see FIG. 2) of the second embodiment, and only the phase is in the respective pixel regions. In addition, the storage capacitive element c and the output transistor Tr〇UT are added to the output side of the amplifying transistor TrAMp corresponding to the set relationship. Therefore, the same reference numerals are given to the same components as those of the sensor circuit of the second embodiment, and the description thereof is omitted. Kezi uses the amplified cell Tr gas 对应 AMP amplified signal corresponding to the capacitive element, one of the terminals, the amplified transistor + Λ, 4 ^ other - terminal, column - Γ ^ source, (four) area connection And connected. ! And the 疋 potential (usually the grounding phantom terminal or area capacitor #CST signal, (4) (four), / temporarily stored in the storage 37' its output side of the source, no pole area,:: to the corresponding line The signal line output terminal (line signal line 37) is connected. The output control signal of the 5th pixel block 12 is connected to the middle. The second: Luo: Crystal: Tr, if applied to the state, if Γ 〇 UT, t state In other words, the J is turned off. Therefore, when the signal temporarily stored in the memory 46 200803484 battery element cST is output to the line signal line 37, the output transistor is output.

The opening and closing time of the Tr0UT can be different from the opening and closing time of the transmission gate TG^TGn in the pixel block 12. In the image sensing sensor using the sensor circuit 1 of the first embodiment, the timing output signals from the n photodiodes PD1 to pDn in the corresponding pixel block 12 are amplified in the amplifying transistor TrAMP. Immediately, it is output to the order line 37. On the other hand, in the image sensor using the sense φ measured as the circuit 1A of the second embodiment, the timing output signals from the n photodiodes PDcPDn in the pixel block 12 are passed through the amplified transistor D(10). After being amplified, it is temporarily stored in the storage capacitive element Cst. Therefore, by outputting the control signal ρ 〇υτ, the timing of outputting the forward signal line 37 and the time of opening and closing of the transmission idle 亟 TG1 TG TGn can be performed. (ie, used to read the signals from the photodiodes PR to PD) are staggered from each other. In the image sensor of the sensor circuit ία of the second embodiment having the above-described configuration, φ can store the signal charges of all the pixels 11 substantially simultaneously for the same reason as in the case of the third embodiment ( In fact, since the exposure can be simultaneously performed in the above manner, the image distortion of the conventional CMOS image sensor does not occur, and the object to be moved at a high speed can be photographed. The common reset transistor TrRST and the common amplifying transistor T^MP are disposed outside the pixel region 12 in a manner corresponding to each pixel block 12, and therefore, each pixel 11 of the pixel block 12 It only needs to have one photodiode and one gate element (M〇s transistor). Therefore, compared with the photoelectric diode in one pixel, there are three or four 47.03484 MOS transistor The known cM〇s image sensor can achieve a higher pixel aperture rate. In addition, by outputting the control signal p 〇υτ, the signal is sent to the line of signal line 37 and the target point can be matched with the pixel block. Transfer gate TG wide TGn Since the guard points on the opening and closing day are shifted from each other, it is possible to perform high-speed photography more easily than the obstacle shape using the sensor circuit 1 of the first embodiment. (Embodiment 3) 4 is a circuit configuration diagram of a sensor circuit according to a third embodiment of the present invention. The address specifying image sensing 3' using the sensor circuit 1B is the same as that shown in FIG. Therefore, the description of the sensor circuit 1B corresponds to the sensor circuit of the first aspect of the present invention. The circuit configuration of the sensor circuit 丨b shown in FIG. 4 and the sense of the first embodiment The circuit configuration of the detector circuit 1 (see FIG. 2) is substantially the same, and the only difference is that the large-transistor TrAMP is disposed in correspondence with each pixel block 12, and the source and drain electrodes on the output side thereof. The region is further provided with n selection transistors TrsELi~TrsELn (second gate elements) connected in parallel thereto, and the output signals from the amplified n photodiodes PDi to PDa are transmitted through the selection transistors TrSEL1 to TrsELn. Parallel output to line signal line 37. Select transistor TrSEL1~T rsELn, if the logic state of the output selection signal P SEL wide P SELn applied to its gate is Η, each is turned on, and if it is L, it is turned off. Therefore, it is the same as the sensor circuit of FIG. The same reference numerals are given to the same elements, and the description thereof is omitted. When reading the corresponding signals of the signal charge (i.e., the number of charges generated by n photodiodes pDi~pDn 48 200803484), n are amplified. The transistors TrSEL1 to TrSELn are selected to be turned on and off in a substantially synchronized manner with the transfer gate TG TGn in the corresponding pixel block 12. That is, for example, the signal is read by the photodiode PD! In the case of amplification, the transfer gate TGi is turned on (becomes in an on state), and the selected transistor is also turned on (becomes in an on state). Therefore, the signal charge to be read is amplified by the amplified transistor TrAMP. Immediately thereafter, it is output to the signal line 37 by selecting the transistor 0 TrSELi. In the image sensor including the sensor circuit 1b of the third embodiment having the above-described configuration, the signal charges of all the pixels 11 can be substantially simultaneously stored for the same reason as in the case of the first embodiment (essentially Exposure at the same time). Further, since the simultaneous exposure can be substantially performed in the above manner, the image distortion of the conventional CMOS image sensor does not occur, and the object to be moved at a high speed can be photographed. Further, a common reset body TrRST and a common amplifying transistor TrAMP are disposed outside the pixel block 12 in a manner corresponding to each pixel block 12, and therefore, the pixel block 12 For each pixel, it is only necessary to have one photodiode and one gate element (M〇s transistor). Therefore, a higher pixel aperture ratio can be achieved than a conventional CMOS image sensor in which one or four MOS transistors are included in the photodiode in one pixel. Furthermore, the output signals from the amplified n photodiodes pDi to pD are outputted through the corresponding n-selected electro-optical cells ^sELi-TrSELn and are connected to the adjacent signal line 37. It also has the effect of being able to quickly perform the signal processing of the next paragraph of 2008 2008484. (Fourth Embodiment) Fig. 5 is an electric diagram of a sensor circuit (1) according to a fourth embodiment of the present invention. The address designation type image sensing using the sensor circuit 4 1C is the same as that shown in the first embodiment, and thus the description thereof will be omitted. The sensor circuit 1C is the same as the present invention! The sensor circuit phase of the present invention is substantially the same as the circuit configuration of the sensor circuit 1 (refer to _ 4) of the third embodiment, and is different from each pixel region. 12 is added to the output side of the amplifying transistor TW corresponding to the setting relationship η in addition to the n-th selectable transistors TrSEL1 to ΤΓςρτ (the output side of the ^^~TrSELn) is added, and #n storage capacitors CST1 to CSTn are added. And n output transistors ~. Therefore, the sensor circuit lc of FIG. 4 is omitted and the description thereof is omitted. The four-gate element is given the same symbol, and the storage capacitive element C ~ Γ λα is (1) ST1 STn The purpose is to temporarily store the amplified photodiode TrAMP after amplification of a photodiode called ~ heart, which is the terminal, respectively, and phase η

The source and drain regions of the output side of TrSEL1 to TrSELn are connected to each other, and the body is connected to a terminal or region of a predetermined potential (through f is a ground potential). The purpose of outputting the transistors Tr〇UT1 to T is to store the corresponding capacitive signal line 37 in the storage capacitive element, and to transmit the source and the drain of the bean to the source and drain regions of the phase wheel side. 50 200803484 The pixel block 12 is given φ # 7. _ output dice (line signal line 37) is connected. The output transistor τΓ〇υτι~τΓ〇υΤη, if applied to its gate, the output control signal 〇 UT11〇UTJ logic state is Η, then it is in conduction state, if it is L, it is open state. In the temporary storage, it is stored in the storage capacitors CST1~cSTn, and the amplification δίΐ is stored in parallel. When the rock/one type is output to the squall line 37, the output transistor

The opening and closing timing of the Tr〇uT wide Tr0UTn can be shifted from each other at the time of opening and closing of the transfer gate TGcTGn in the pixel block 12.

In the image sensing of the sensor circuit 1B using the third embodiment, the n output signals from the n photodiodes PDcPDn in the corresponding pixel block 12 are amplified by a transistor, The "amplified" is immediately output in parallel to the signal line 37. On the other hand, in the image sensor using the sensor circuit 丨c of the fourth embodiment, the output signals from the n photodiodes PDcPDn in the pixel block 12 are amplified by the amplified transistor ΤΓαμρ. After that, they are temporarily stored in the storage power components CST1 to CSTn, and therefore, by the output control number φ 0UT1 〜 p 〇 UTn, the timing is output to the line signal line 37 in parallel, and the transmission gate TG can be transmitted. The point at which the wide TGn is opened and closed (i.e., the point at which the signal is read from the photodiode PD wide PDn) is staggered from each other. In the image sensor including the sensor circuit 1C of the fourth embodiment configured as described above, the signal charges of all the pixels 11 can be substantially simultaneously stored (substantially simultaneously) for the same reason as in the case of the first embodiment. Exposure). Further, since the simultaneous exposure can be performed in the above manner, the image distortion of the conventional CMOS image sensor does not occur, and the object to be moved at a high speed can be photographed. 51 200803484 Further, the 'common reset transistor TrRST and the common amplifying transistor TrAMP' are disposed outside the pixel block 12 so as to correspond to the respective pixel blocks 12, and therefore, each of the pixel blocks 12 The pixel 11 only needs to have one photodiode and one gate element (M〇s transistor). Therefore, a higher pixel aperture ratio can be achieved than a conventional CM〇s image sensor in which one pixel or three MOS transistors are included in a single pixel. φ By outputting the control signals P OUT1 P POUTn, the time point when the signal is outputted to the signal line 3 7 can be shifted from the opening and closing of the transfer gate TG^TGn in the pixel block 12, and therefore, the phase is shifted. Compared with the case where the sensor circuit 1B is used in the third embodiment, it is possible to have a higher speed of photographing, and the effect is also obtained. (Fifth Embodiment) Fig. 6 is a circuit diagram showing a circuit configuration of a main part of the address specifying image sensor 2 according to the fifth embodiment of the present invention; and Fig. 8 is a main part of the actual call structure of the image sensor 2. Sectional view. In the image sensor 2, the sensor circuit 1B (refer to W 4) of the third embodiment is used, and the upper semiconductor circuit layer 21 and the lower semiconductor circuit layer 22 are laminated to form a two-dimensional three-layer laminated structure. . This image sensor 2 corresponds to the image sensor of the third aspect of the present invention. The overall configuration and operation of the image sensor 2 are the same as those shown in FIG. 1, and the description thereof will be omitted. Further, the circuit configuration of 'w 6' is the same as that of the sensor circuit 1B of the third embodiment shown in FIG. 4 (the n selection transistors Trs are connected to the output ends of the respective amplification transistor TrAMPs, and are not 52 200803484) The storage capacitor element is the same as the output transistor, and the same reference numerals are given to the same elements, and the description thereof is omitted. However, in the image sensor 2, as described above, a well-known buried wiring line 23' is used to make the common node 13 of each pixel block 12 formed in the upper semiconductor circuit layer 21, and the node μ (formed on The connection point between the reset transistor TrRST and the amplifying transistor TrAMp in the lower semiconductor circuit layer 22 is electrically connected. Therefore, in FIG. 6, the buried wiring 23 and the parasitic resistance generated by the disposed wiring 23 are added. The parasitic capacitance u (: 2. The buried wiring 23 is provided for each pixel block i2 (that is, n pixels 11). Next, the actual configuration of the image sensor 2 will be described with reference to Fig. 8. As can be seen from FIG. 8, the image sensor 2 uses a buried wiring" and a fine bump electrode (for example, a laminate of germanium (In) and gold (Au) or tungsten (f), etc.) 90 and an electrically insulating adhesive. (For example, polyimine 1 forms a mechanical and electrical connection between the upper semiconductor circuit layer 21 and the lower semiconductor circuit layer 22. Further, a method for forming the buried wiring 23 and the bump electrode 9A, and an adhesive 91 are used. And the upper semiconductor circuit layer 21 and the lower semiconductor are electrically The method of mechanically connecting the layers 22 is known to those skilled in the art, and the description thereof is omitted. In the upper half V body fast layer 21, (kxm) pixel blocks Η are formed, that is, (kxn) xm pixels n. Therefore, the upper semiconductor circuit layer 2! includes (kxn) xm photodiodes (that is, the photodiode group PD wide PDn of the (four) group); and (kxn) xm The transfer gates (that is, the transfer dummy groups TGi to TGJ of the (four) group are formed. Further, (kxm) buried wirings 23 are formed in the upper semiconductor circuit layer η 53 200803484. In the lower semiconductor circuit layer 22, : (kxm) reset transistors TrRST; (kxm) amplifying transistors TrAMP; and (kxn) xm selecting transistors (that is, having (kxm) groups of selected transistor groups TrsELi to TrsELn).

In the upper semiconductor circuit layer 21, in the surface region of the p-type single crystal germanium (si) substrate 4, the element isolation insulating film 4 is formed in a predetermined pattern, thereby (kxn) xm pixels 11 The regions are connected in parallel in an array, as shown in the layout of Figure 1. The component areas thereof are corresponding to one pixel 11, respectively. The configuration of the pixel block 12 is the same, and thus is described here by one pixel block 12 (i, j). Inside the element region corresponding to the pixel block 12 (i, j), n photodiodes PDi to PDn and n transfer gates TGi are formed, for example, as shown in FIG. 8, the photodiode pDi It is composed of a ^-type region 42 formed on the p-type substrate (10) (that is, a photodiode ρ〇ι-based p_n junction type photodiode). The transfer gate TGi is formed by an M〇s transistor, and includes a gate 44 and a gate W3 interposed therebetween. The gate TGi is transferred, and since the n-type region 42 of the photodiode is shared, a source and a non-polar region ' of the transfer gate TGi are electrically connected to the anode of the photodiode (4) PDi. An extremely insulating film exists between the interpole 44 and the surface of the substrate 40, which is omitted in FIG. 8 (the presence of a gate insulating film between the gate 44 and the surface of the substrate 40, the phase # is clear, The description of the closing of the insulating film is omitted in the description of m. The gate 44 is electrically connected to the corresponding read control line u 54 200803484 through the wiring formed in the wiring structure of the substrate 4: d 47 . Here, the wiring structure 47 includes a wiring conductor formed on the surface of the substrate 4A and an insulator including the same, and does not include a gate insulating film and a gate existing on the surface of the substrate 40. (This point is the same in the following embodiment.) As for the other photodiodes ρΓ^~ρΕ)η and the transfer gates TG2 to TGn, they are the same as the photodiode pDi and the transfer gate T (Ji). Composition.

Inside the wiring structure 47, a wiring film 46 is formed which is formed in a predetermined pattern; and n conductive contact plugs 45 are provided for n-type n +-type regions 43 of the transfer closed electrodes TG 〜 TGn This wiring film 46 forms an electrical connection. The n transfer gates TGi TG TG, n in the pixel block 12 (i, j) are electrically connected to the wiring film 46 by their contact plugs 45, thereby making the transfer gate TGcTGn parallel to the common node 13. In the substrate 4, the element isolation insulating film 41 and the substrate 40 are formed to penetrate in the vertical direction (the direction orthogonal to the main surface of the substrate 4A) (kx (4) through holes, and the formation positions thereof are located, and the transfer gates are formed. The overlapping position of the element isolation insulating film 41 adjacent to the n + -type region (source, drain region) 43 of the TG TG TGn is in the through hole, which is in contact with the inner wall of the dam portion of the substrate 40, and is covered by the insulating film 24. In the inside of the through hole (the inside of the insulating film 24 and the inside of the element isolation insulating film 41), a conductive material such as a pulverized material is filled, and the embedded wiring 23 is formed by the hopper. The upper end of the wiring ^ is exposed by the surface of the substrate 4 (the element isolation insulating film 41), and is connected to the lower end of the conductive contact plug formed inside the wiring structure 47. X conductive|± the upper end of the contact interposer 23a, The wiring layer 23 is electrically connected to the corresponding wiring film 46 through the conductive contact 55 200803484 plug 23a. As a result, the pixel block 12 (i, j) n transfer gate TG^TGni n+ type area (Source, drain region) 43 is electrically connected to the corresponding buried wiring 23 as shown in the circuit configuration of Fig. 6. The lower surface of each buried wiring 23 is exposed from the inner surface of the substrate 40. Mechanically and electrically connected to the bump electrode 90 corresponding to the lower end thereof. In the lower semiconductor circuit layer 22, the element isolation insulating film 61 is formed in a predetermined pattern in the surface region of the p-type single crystal germanium substrate 60_. Thereby, a predetermined number of element regions for resetting the transistor TrRST, a predetermined number of element regions for the amplifying transistor TrAMP, and a component region for a predetermined number of the selection transistors TrSEL1 to TrSELn are formed. A corresponding configuration of a pixel block 12 (i, j) is illustrated. As shown in FIG. 8, the reset transistor TrRsT is composed of an M〇s transistor, which includes a gate 63 and is interposed between the gates. 63 is formed on one side of the pair of n + -type regions (source, drain region) 62. The gate 63 is a wiring that is transmitted through the wiring structure 74 formed on the surface of the substrate 6A, and corresponds to The reset line 31 forms an electrical connection. The wiring structure 74 includes a wiring conductor formed on the surface of the substrate 60 and an insulator including the same, and the gate insulating film and the gate which are present on the surface of the substrate 60 are not included (this point is also in the following embodiment) The same is true. An n + -type region 62 (source, drain region) passes through the conductive contact plugs 68 formed in the wiring structure 74, the wiring film 72, the conductive contact plugs 74a, and the wiring film 75, and The corresponding bump electrodes 90 form an electrical connection. As a result, a source and a drain region of the reset transistor TrRsT are transmitted through the corresponding buried wiring 23, and a common node corresponding to the upper portion 56 200803484 semiconductor circuit layer 21 13 (Pixel block 丨叩, Sichuan forms an electrical connection (refer to Figure 6). The other n + type region 62 (source, no-pole region) is applied with a reset voltage through a wiring (not shown).

The amplifying transistor TrAMp is composed of a MOS transistor, and includes a gate 65 and a pair of n + -type regions (source, drain regions) 64 formed on both sides with the gate 65 interposed therebetween. The gate 65 is electrically connected to the corresponding bump electrode 透过 through the conductive contact plug 7 i formed in the wiring structure 74, the wiring film u, the conductive contact plug ^a, and the wiring film 75. The gate of the amplifying electrode ΤΓαμρ is electrically connected to the common node 13 (pixel block 12(i, j)) corresponding to the upper semiconductor circuit layer 21 through the corresponding buried wiring ( (refer to the figure). 6). Further, the other γ-type region 64 (source and drain region) is electrically connected to the wiring film 73 formed inside the wiring structure 透过 through the conductive contact plug 69 formed inside the wiring structure 74. In the other n + -type region 64 (source, drain region), the supply voltage Vcc is applied through a wiring (not shown). η selected transistors TrSEL1 Tr TrSELn, each consisting of a MOS transistor, including a gate 67, and a pair of n+-type regions (source, drain) formed on both sides with the gate 67 interposed therebetween Area) 66. An n + -type region (source, drain region) 66 passes through the conductive contact plug 70 formed in the wiring structure 74, the wiring film 73, and the conductive contact plug 69, and the corresponding amplifying transistor TrAMP One type of region (source, drain region) 64 forms a book gas connection. The other n+ type region (source, no-pole region) 66 is connected to the corresponding output terminal of the image sensor 2. The gate 67 is electrically connected to the output selection line 39 via the wiring formed in the wiring structure 74, 57 200803484. In each of the gates π of the selected transistors ΤΓ_~τ, the application of the predetermined (four) selection signals 9 SEL1 ～ 9 SELn is transmitted through the (four) appropriate wheel line selection 39 #. In the survey 2, as shown in Fig. 8, TrSEL1 and TrSEL2 are formed to minimize the occupied area. In the fifth embodiment, the two selected transistors are adjacent to each other, for example, in the same element region. This is for

In the element region <, "three types of regions (source, drain region) 66 are formed side by side with a predetermined distance, and the central n + type region μ is composed of two selection transistors TrsELi and Thu Share. Further, the common ^-type region 66 is electrically connected to one of the corresponding Δ-type regions 64 of the amplifying transistor TrAMp. The unshared n+ type regions 66 are respectively connected to corresponding output terminals. The type region 43 in the upper semiconductor circuit layer 21 and the n + type region 62 in the lower semiconductor circuit layer 22 (which are electrically connected to each other through the buried wiring 23) have a function of an FD (floating diffusion) region, in other words, The function is to convert the signal charge amount stored in the photodiode PD^PDn into a voltage signal by photoelectric conversion. Further, the method of forming the internal structure of the upper semiconductor circuit layer 21 and the lower semiconductor circuit layer 22 is well known to those skilled in the art, and the description thereof will be omitted. As described above, in the image sensor 2 of the fifth embodiment shown in FIGS. 6 and 8, the sensor circuit ι of the third embodiment shown in FIG. 4 is used, which is (kxm) pixel blocks. 12 (block 12 includes n pixels jj respectively) and (kxm) buried wirings 23 are formed in the upper semiconductor circuit layer 21, 58 200803484 and (kxm) reset transistors TrRsT and (kxm) are enlarged The transistor TrAMP and the (kxm) group of selected transistors are formed in the lower semiconductor circuit layer 22, and further penetrate the buried wiring 23 and the bump electrode 90 to make the pixel block in the upper semiconductor circuit layer 21. 12. The reset transistor TrRsT and the amplifying transistor TrAMP corresponding to the lower semiconductor circuit layer 22 are electrically connected to each other. Further, the main surface (surface of the wiring structure 74) above the lower semiconductor circuit layer 22 is formed by the bump electrode 9 and the adhesive 9 丨, and the lower surface of the upper semiconductor circuit f 21 (substrate 4) Since the inner surface of the crucible is electrically and mechanically connected, the two circuit layers 21 and 22 constitute a two-stage semiconductor laminate structure (three-dimensional structure). Therefore, based on the same reason as in the case of the sensor circuit 1B of the third embodiment described above, the signal charge for all the pixels 1 1 can be substantially the same on the same day. Exposure), and the image distortion of a conventional CMOS image sensor does not occur 'can be performed on a moving object to be moved at a high speed

X Α , Eight and Dale an optical pole and an interpole component (Cong transistor), therefore, compared to the photoelectric in the pixel, there are three or four M 〇 image sensors in the body. It can achieve a higher image, and the size of the pixel itself can be reduced. The German: 'Because of the pixel aperture ratio of 4 compared to the conventional CMOS image sensor, because of the body, the surface of the upper semiconductor 21 is exposed by the photodiode. The ratio of the total area of the heart area to the photographic area of this 59 200803484 can be improved. (Embodiment 6) FIG. 7 is a circuit diagram showing a configuration of a main part circuit of an address specifying type image sensor 2A according to a sixth embodiment of the present invention; and FIG. 9 is a main part of the internal structure of the image sensor 2a. Sectional view. The image sensor 2 A is a circuit 1 c (see FIG. 5) that senses the fourth semiconductor device, and the upper semiconductor circuit layer 21 and the lower semiconductor circuit layer 22 are laminated. Duan Zhi

Two-dimensional laminated structure. The image sensor 2 A corresponds to the image sensor of the third aspect of the present invention. The overall composition and operation of the image sensing type 2 A are the same as those shown in the figure. Therefore, the description about them and the like is omitted. Further, the circuit configuration of Fig. 7 is the same as that of the sensor circuit lc of the fourth embodiment shown in Fig. 5 (the selection transistors τ SEL SEL A ISELn 5 are connected to the output terminals of the respective amplification transistors TrAMP. The output side of the return-to-be-original body TrSEL1 to TrSELn is the same as the storage capacitor element Cst wide CSTn and the output transistor Tr〇im to Tr〇uTn. Therefore, the same reference numerals will be given to the same elements, and the description thereof will be omitted. However, in the image sensor 2A, as will be described later, the well-known buried wiring 23 is used so that the common node 13 of each pixel block 12 formed in the upper semiconductor circuit layer 21 and the node 14 (the node 14 The electrical connection is formed between the reset transistor η of the lower semiconductor electric layer 22 and the connection point of the amplifying transistor D. Therefore, in FIG. 7, the buried wiring 23 is added, and the wiring 23 is provided. The resulting parasitic resistance r❹ and parasitic capacitances Ci and c. 2. The buried wiring 23 is provided for each pixel block 12 (i.e., n images 1 is provided.) 200803484 Next, the actual structure of the image sensor 2A will be described with reference to FIG. As can be understood from FIG. 9, the image sensor 2A uses the buried wiring 23 and the fine bump electrode 90 and an electrically insulating adhesive (for example, polyimide) 91 to make the upper semiconductor circuit layer 21 and the lower semiconductor circuit layer 22 , forming mechanical and electrical connections.

The upper semiconductor circuit layer 21 has the same configuration as that of the image sensor 2 (see FIG. 8) of the fifth embodiment, and has (kxm) pixel blocks 12, that is, (kxn) x m pixels. 11, and (kxm) embedded wirings 23. The internal structure of the upper semiconductor circuit layer 21 is the same as that of the image sensor 2 of the fifth embodiment. Therefore, the same reference numerals are given to the fifth embodiment, and the detailed description thereof will be omitted. The lower semiconductor circuit layer 22 has substantially the same configuration as the lower semiconductor circuit layer 22 of the image sensor 2 (see FIG. 8) of the fifth embodiment, but the difference is that the storage capacitive element cst is added. Wide CsTn and output transistor Tr〇UT1~丁r〇UTn. That is, in the lower semiconductor circuit layer 22', in addition to the (kxm) reset electrical body Τ^τ, (kxm) amplification transistors TrAMp, and (kxm) group of selected transistor groups commits ~ Further, the storage capacitor element group Cst wide CsTn of the (kxm) group and the output transistor group Tr〇UT1 to Tr〇uTn of the group of xni) are additionally formed. In the lower semiconductor circuit layer 22, the element isolation is formed in a predetermined pattern in the surface region of the P-type single crystal chopped substrate 60, thereby forming a predetermined number of element regions, a predetermined number for the reset transistor TrRST. The component region for amplifying the transistor TrAMP, the predetermined number of selected transistors TrSEL1 to TTrSELn, the storage capacitor element (1), and the output region of the output transistor 61 200803484 body TrOUT1 Tr〇UTn. Here, the description will be made by the corresponding configuration of one pixel block 12 (1, j). The configuration of the reset 曰a body TrRST is the same as that of the image sensor 2 (see FIG. 8) of the fifth embodiment described above, and is composed of an M 〇s transistor, which includes a gate 63 and is interposed therebetween. The gate 63 is formed between the two

The pair of 11-type regions (source, and pole regions) 62. The electrical connection of the reset transistor TrRsT is also the same as in the case of the image sensor 2 (see Fig. 8) of the fifth embodiment. The configuration of the amplifying transistor TrAMP is also composed of an MOS transistor, which includes a gate 65 and a gate interposed therebetween, as in the case of the image sensing J and 2 (see FIG. 8) of the fifth embodiment. 65 is formed between the pair of n + type regions (source, drain region) 64 on both sides. The electrical connection of the amplifying transistor τ'· is also the same as that of the image sensor 2 (see Fig. 8) of the fifth embodiment. The configuration of the n selection transistors TrsELi to TrsELn is the same as that of the above-described image sensor 2 (see FIG. 8), and is composed of a m〇S transistor including a gate 67. And a pair of n + type regions (source and drain regions) formed on both sides of the gate 67 via the gate 67. Further, the storage capacitor element and the output transistor are formed by the circuit configuration shown in FIG. And connected to the MOS transistor. For example, in the case of the selective transistor TrsEL1, an n+ type region (source, drain region) 66 is transmitted through the conductive contact plugs 70 and 69 formed inside the wiring structure 74 and The wiring film 73 is electrically connected to an n + type region (source, drain region) 64 of the corresponding amplifying transistor ΤΓαμρ. The gate 67, 62 200803484 is transmitted through the wiring formed inside the wiring structure 74 and output. The line Μ is selected to form an electrical connection, and the output selection signal is applied. Another n+ type region (source, drain region) 66 of the transistor butyl rSEL1 is selected, along with the gate 67a as the axis on its opposite side. n+ type area 66&, constitutes storage The MOS capacitor functioning as the capacitive element CST1, the n+ type region 66a, together with the gate 67b, and the n+ type region 66a having the gate 67b as the axis on the opposite side of the n+ type region 66a, constitutes an output power The crystal H(10)η φ functions the M〇S transistor. The gate 67a is connected to a terminal or region of a predetermined potential (usually the power supply voltage Vcc). The gate 67b is electrically connected to the output control line 39a through a wiring (not shown). Connected, and there is an output control signal ο ο 施加 T 1 application. As shown, in one element region, a selective transistor τ IS IIL 1 and a storage capacitive element cST1 and an output transistor Tr〇uTi are formed. The same applies to the other transistors TrSEL2 to TrSELn. As described above, the image sensor 2' of the sixth embodiment shown in Figs. 7 and 9 uses the sensor circuit 1c shown in Fig. 5. The (kxm) pixel blocks 12 (including n pixels 11 respectively), the (kxm) group of transfer gate groups TG wide TGn, and (kxm) buried wirings 23 are formed on the upper semiconductor circuit layer 21 Medium, and will be (kxm) reset transistors TrRST, (kXm) amplification Crystal Tr*AMP, (k X m) group, selected transistor group TrsEL wide TrSELn, (kxm) group of storage capacitive element groups cST1 to CSTn, and (kxm) group of output transistor groups Tr〇UT1 to TrOUTn, Formed in the lower semiconductor circuit layer 22', and further transmitted through the buried wiring 23 and the bump electrode 90, the pixel block 12 in the upper semiconductor circuit layer 21 and the lower half 63 200803484 body circuit layer 22' The Thunder lion packs the day-to-day TrRsT and the magnifying transistor to form an electrical connection with each other. $ Uamp n &; for the same reason as in the case of the sensor circuit of the above-described 帛4 embodiment, as shown in Fig. 5), more than - the signal charge of all the pixels 11 can be simultaneously stored on the same (real, 皙, 守4, actinic), and the image of the CMOS image sensor and the image distortion phenomenon do not occur, and the object to be photographed at high speed can be photographed. τ photo

Moreover, each pixel 11 of the pixel block 12 only needs to have one photodiode and one gate element _s transistor, and therefore, in addition to the photo-polar body, there are three in the _ pixels. The CMOS image sensor of the white or four mqs transistors can achieve a higher pixel aperture ratio (about 60 / 例), and the size of the pixel can be reduced. Furthermore, since the CM 〇 image sensor has a higher pixel aperture ratio than the conventional CM 〇 image sensor, the total area of the light receiving region (the opening portion of each photodiode) on the surface of the upper semiconductor 21 is relatively The proportion of the total area of the photographing area can be increased. Further, by controlling the output transistors Tr0UT1 to Tr0UTn by outputting the control signals p 0UT1 to ¢) 0UTn, the signal is outputted to the signal line 37, and the gates TGi to TGn are transmitted in the pixel block 12. Further, when the opening and closing of the transistor group TirSEL wide TrSELn is selected, the positions can be shifted from each other. Therefore, compared with the image sensor 2 of the fifth embodiment, higher speed imaging can be performed, and the effect is also obtained. (Embodiment 7) FIG. 10 is a circuit diagram showing a configuration of a main circuit of an address specifying image sensor 64 200803484 2B according to a seventh embodiment of the present invention; and FIG. 9 is a main part of the actual structure of the image sensor π. Sectional view. In the image sensor 2B, the sensor circuit lc (see FIG. 5) of the fourth embodiment is used, and the upper semiconductor circuit layer 21A and the lower semiconductor circuit layer 22 are laminated to form a three-dimensional three-layer laminate. structure. The image sensor 2B corresponds to the image sensor of the present invention. Circuit shown in 砚1

The overall configuration and operation of the shirt image sensing Is 2B are the same as those in the figure. Therefore, the description of the same is omitted, and the other components are the same as those of the fourth embodiment of FIG. 5, and the sensor circuit 1C of the embodiment is the same except that the buried wiring 23 is added. The same symbols are used and the description thereof is omitted. As can be seen from FIG. 10 and FIG. 11, in the configuration of the image sensor 2β, the buried wiring 23, the fine bump electrode 9A, and the electrically insulating adhesive 91 are used to make the upper semiconductor circuit layer 21A and the lower position. The semiconductor circuit layers 22A' form a mechanical and electrical connection with each other. This configuration corresponds to shifting the (kxm) reset transistors TrRST formed in the lower semiconductor circuit layer 22' to the bit semiconductor in the image sensor 2A (see FIGS. 7 and 9) of the sixth embodiment. In the circuit layer 21. That is, (kxn) xm photodiodes are formed in the upper semiconductor circuit layer 2 (that is, (kx group 'photodiode group PD wide PDn); (kxn) xm transfer gates ( That is, the transfer gate group TG^TGJ of the (kcan) group; (kxm) reset transistor · 1 rRST; and (kxm) buried wiring 23. Photodiode pDi~PDn and transfer gate The configuration of TG to TGn is the same as that of the image sensor 2a of the sixth embodiment, and therefore the description thereof will be omitted. Month 65 200803484 The reset electric βθ body TrRST is as shown in FIG. The s transistor is configured to include a gate electrode 49 and an n-type region (source, no-pole region) 48 formed on one of the two sides via the gate electrode 49. The gate is transparently formed on the substrate 40. The wiring in the surface wiring structure 47 is electrically connected to the corresponding reset line 31. An n+ type region 48 (source, drain region) is transmitted through the conductive contact formed inside the wiring structure 47. The plug 5 〇, the wiring film 46, the conductive contact plug 23a, and the buried wiring 23 are electrically connected to the corresponding bump electrode 90. As a result, the source and drain regions of the reset transistor TrRST are electrically connected to the gate 65 of the corresponding amplifying transistor TrAMP of the lower semiconductor circuit layer 22A. Another n+ type of the reset transistor TrRST In the region 48 (source, drain region), the reset voltage vRST is applied through a wiring (not shown). In the lower semiconductor circuit layer 22A, (kxm) amplification transistors TrAMP are formed; (kxm) The group selects the transistor groups TrSEL1 to TrsELn; the (kxm) group of storage capacitor elements CST1 to CSTn; and the (kxm) group of output transistor groups Tr0UT1 to Tr0UTn. This configuration corresponds to the sixth embodiment. (Refer to Fig. 7 and Fig. 9) The lower semiconductor circuit layer 22 removes (kxm) reset transistors TrRST. The configuration of the amplified transistor TrAMP and the selection transistors TrSEL1 to TrSELn is the same as in the sixth embodiment. Therefore, the description will be omitted. As described above, in the image sensor 2B of the seventh embodiment shown in FIGS. 10 and 11, the sensor circuit 1c of the fourth embodiment is applied (see FIG. 5). ), which will be (kxm) pixel blocks 12 (each image) The block 12 includes n pixels 11), a (kxm) group of transfer gate groups TG^TGn, (kxm) resets 66 200803484, a packaged body TrRST, and (kxm) buried wirings 23, which are formed in the upper position. In the semiconductor circuit layer 21A, the (kxm) amplification transistor TrAMp, (kxm), and the remote selection transistor group Tr muscles i to Trs^, (kxm) are used for the storage capacitive element group cST1 to The output transistor groups Tr〇uTi to Tr〇uTn of the cSTn and (kxm) groups are formed in the lower semiconductor circuit layer 22, and further penetrate the buried wiring 23 and the bump electrode 90 to make the upper semiconductor circuit layer 2 1 The reset transistor TFrst is electrically connected to the lower semiconductor circuit layer 22A and the amplifying transistor TrAMP_. Further, the upper main surface (the surface of the wiring structure 74) of the lower semiconductor circuit layer 22A is formed by the bump electrode 90 and the adhesive 91, and the lower surface of the upper semiconductor circuit layer 21A (the substrate 40) Since the inner surface is electrically and mechanically connected, the two circuit layers 21A and 22 A' constitute a two-stage semiconductor laminated structure (three-dimensional structure). Therefore, based on the same reason as in the case of the sensor circuit 1 C of the fourth embodiment, the signal charge of all the pixels can be stored substantially simultaneously (the simultaneous exposure on the babe), and the conventional knowledge does not occur. The image distortion of the CMOS image sensor enables photography of objects to be moved at high speed. Moreover, each pixel 11 of the pixel block 12 only needs to have one photodiode and one gate element (M〇s transistor), and therefore, there are three in addition to the photodiode in one pixel. Or a conventional CMOS image sensor of four transistors, which can achieve a higher pixel aperture ratio (9) of about 60%, and the size of the pixel itself can be reduced. Furthermore, since the CMOS image sensor has a higher pixel aperture ratio of 67 200803484 than the conventional CMOS image sensor, the total area of the light receiving region of the upper semiconductor 21 (the π portion of each photodiode) is relatively The ratio of the total area of the photographing area can be increased. * In addition, by controlling the turn-out by outputting the control signal P 〇 claw 1 : the crystal Tr0UT is wide Tr0UTn, the signal is outputted to the signal line η by 4 points, and the pixel block 12 is transferred to the gate TG. Guangfan and the selection of the electric corpuscle group TrSEL wide TrSELn can be opened and closed at the same time, so the phase

The rut does not have a storage capacitor element ~c(1) and an output transistor

In the case of Tr〇uT1 to Tr0UTn, high-speed photography can be performed, which is also an effect. (Embodiment 8) FIG. 12 is a cross-sectional view of an essential part of an actual structure in which address-address-receiving type image sensing according to an eighth embodiment of the present invention is 2C. The image sensor 2C is obtained by removing the storage capacitive elements CST1 to CSTn and the output transistors ThUT1 to Tr0UTn in the image sensor 2B (see FIGS. 1A and 9) of the seventh embodiment. By. The image sensor 2C corresponds to the address specifying type image sensor of the third aspect of the present invention. As can be seen from Fig. 12, in the configuration of the image sensor 2C of the eighth embodiment, the embedded semiconductor wiring layer 23, the fine bump electrode 9A, and the electrically insulating adhesive 91 are used to make the upper semiconductor circuit layer 21A. Mechanical and electrical connection is made to the lower semiconductor circuit layer 22A. The configuration of the upper semiconductor circuit layer 21A is the same as that of the image sensor 2B of the seventh embodiment. The configuration of the lower semiconductor circuit layer 22A corresponds to the removal of the memory 68 200803484 ΤΓουτι to Tr0UTn from the lower semiconductor circuit layer 22A of the image sensor 2B of the seventh embodiment, and constitutes the power supply components C ς 〜 C rice a jr ST1 LSTn output transistor 0 to the sensor circuit 2C of the eighth embodiment, based on the same reason as the image sensor and 2B 4 t of the seventh embodiment, for all images, 11 The signal charge can be stored substantially simultaneously (substantially simultaneously exposed), and there is no known CMOS dan: W Γ 、 、 、 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一The subject to be photographed.

Moreover, each pixel U of the pixel area 12 is only required to have one photodiode and one idler element (M〇s transistor), and therefore, in addition to the photodiode in one pixel, A conventional CMOS image sensor including three or four m〇s electric cells can achieve a high pixel opening ratio (9) of about 60%, and the size of the pixel u itself can be reduced. Furthermore, since the CMOS image sensor has a higher pixel aperture ratio than the conventional CMOS image sensor, the total area of the light receiving area on the surface of the upper semiconductor 21A = (the opening portion of each photodiode) is relative to photography. The proportion of the total area of the area can be increased. (Embodiment 9) FIG. 13 is a circuit diagram showing a circuit configuration of a main part of an address specifying image sensor 2D according to a ninth embodiment of the present invention; and FIG. 14 is a view showing an actual structure in which image sensing is 2D. The image sensor 2d uses the sensor circuit 1c of the fourth embodiment (see FIG. 1 J' with the integrated layer upper semiconductor circuit layer 21B and the lower semiconductor circuit layer 22B, the second stage The three-dimensional laminated structure. The image sensor 2B corresponds to the image sensor of the third aspect of the present invention. 69 200803484 The overall configuration and operation of the image sensor 2D are the same as those shown in Fig. 1, and Fig. 13 The circuit configuration shown is the same as that of the sensor circuit c of the fourth embodiment of Fig. 5 except that the buried wiring 23 is added. The configuration of the image sensor 2D can be understood from Figs. 13 and 14 In the middle, the buried wiring 23, the fine bump electrode 90, and the electrically insulating adhesive 91 are used to mechanically and electrically connect the upper semiconductor circuit layer 21B and the lower semiconductor circuit layer '. Seventh embodiment The (kxm) amplifying transistors TrAMP formed in the lower semiconductor circuit layer 22A' in the image sensor 2B (refer to FIGS. 10 and 9) are transferred to the upper semiconductor circuit layer 21B. That is, in the upper semiconductor circuit The layer 21B is formed with: (kxn) xm photodiodes (that is, photodiode groups PDi to PDn of the (k X m) group); (kxn) xm transfer gates (ie, there are (kxm) group of transfer gate groups TG^TGJ; (kxm) reset transistors TrRST; (kxm) φ of amplified transistors Τγαμρ, and (kxm) buried wirings 23. Photodiodes PD^ The configuration of the PDn and the transfer gate TG wide TGn and the reset transistor TrRST is the same as that of the image sensor 2B of the seventh embodiment, and therefore the description thereof will be omitted. As shown in Fig. 14, the magnifying transistor is shown in Fig. 14. "(10) is composed of an M?s transistor, and includes a gate 53 and a pair of n + type regions (source, drain region) 52 formed on both sides with the gate 53 interposed therebetween. 53 is transmitted through the conductive contact plug 54 and the wiring film 46 formed inside the wiring structure 47, and the reset transistor TrRST and the transfer gate TGi to TG n forming electric 70 200803484 。. An n + type region 52 (source, drain region) passes through the conductive contact plug 55 formed in the wiring structure 47, the wiring film 56, the conductive contact plug 23a, and The wiring 23 is buried and electrically connected to the corresponding bump electrode 9A. As a result, the source and the gate region of the transistor LA· are amplified, and the selected transistor ThEL corresponding to the lower semiconductor circuit layer 22B is formed. An n+ type region 66 (source, drain region) of the wide TrSELn forms an electrical connection. When the other n + -type region 52 (source, drain region) of the transistor TrAMp is amplified, the supply voltage Vcc is applied through a wiring (not shown). In the lower semiconductor circuit layer 22B, a selection transistor group TrSEL1 to TrSELn of the (kxm) group; a storage capacitor element group cST wide cSTn of the (kxm) group; and an output transistor group Tr of the (kxm) group are formed. uT wide Tr〇m. This configuration corresponds to the removal of (kxm) amplification transistors TrAMp from the seventh embodiment (see FIG. 1 and the lower semiconductor circuit layer 22A). The transistors TrSEL1 to TrSELn and the storage capacitor elements are described. The configuration of cST1 to CSTn and the output transistor Tr0UT wide TrOUT is the same as that of the seventh embodiment, and thus the description thereof will be omitted. As described above, the image sensing of the ninth embodiment shown in Figs. 13 and 14 is performed. The sensor 2D' uses the sensor circuit 1c (see FIG. 5) of the fourth embodiment, which is (kxm) pixel blocks 12 (n pixels 各 in each pixel block 12), (kxm) The transfer gate groups TG1 to TGn, (kxm) reset transistors TrRST, (kxm) amplifier transistors TrAMP, and (kxm) buried wirings 23' are formed in the upper semiconductor circuit layer 21B, and (kxm) each of the selected transistor groups TrSELi to TrsE", the (kxm) group of storage capacitive element groups CST1 to CSTn, and the (kxm) group of output transistor groups Tr0UT1 to Tr0UTn, 71 200803484 are formed in the lower semiconductor circuit Layer 22B, medium, and further through buried wiring 23 The bump electrode 9A electrically connects the amplifying transistor TrAMp' in the upper semiconductor circuit layer 21b with the lower semiconductor circuit layer 22B, and the selection transistors TrSELi to TrSELn are electrically connected to each other. Further, 'on the lower semiconductor circuit layer 22B, The main surface (the surface of the wiring structure 74) is electrically and mechanically connected to the main surface (the inner surface of the substrate 4A) of the upper semiconductor circuit layer 21B by the bump electrode 90 and the adhesive 91. The circuit layers 21B and 22B constitute a two-stage semiconductor laminated structure (three-dimensional structure). Therefore, the signal charge for all the pixels 11 can be substantially simultaneously stored for the same reason as in the case of the sensor circuit 1C of the fourth embodiment. (Bebe on the same day, the exposure is exposed), and the conventional CM〇s image sensing Jay image distortion situation does not occur, and the high-speed moving object to be photographed can be photographed 0 and each pixel 11 of the pixel block 12, It only needs to have one photodiode and one gate element (de-embedded crystal), so it contains three or four transistors in addition to the photo-electrode in one pixel. The known CMOS image sensor can achieve a high pixel opening of about 60%, and the size of the pixel 11 itself can be reduced. Moreover, due to the pixel opening of the conventional CMOS image sensing device Therefore, the ratio of the total area of the opening portion of the upper semi-conducting electrode 21 to the area of the photographing area can be increased. 叼~ Furthermore, by outputting the control signal %υτιι〇υτη to control the round out 72 200803484 = 曰 Tr0UT wide Tr0UTn way, the signal to the line of signal line 37 rounded out of the point, and the pixel block 12 in the transmission gate TGi ~ and select electricity

The crystal group TrecT^Tr ΛΑ pa BB SEL1 SELn can be shifted from each other at the time of opening and closing, and therefore, compared with the CSTn and the output transistor which do not have the storage capacitive element CST

In the case of Tr〇UTi to TrOUTn, it is possible to perform high-speed photography, and this is also the effect. (10th embodiment) FIG. 15 is an actual structure in which the address specifying image sensing of the 10th embodiment of the present invention is 2E. A cross-sectional view of the main part. In the image sensor 2C (see FIGS. 3 and 14) of the ninth embodiment, the image sensor is removed from the storage f-capacity element Cst and the output transistors Tr0UT1 to Tr0UTn. . The image sensor 2E corresponds to the address specifying image sensor of the third aspect of the present invention. As can be seen from Fig. 15, in the configuration of the image sensor 2E of the tenth embodiment, the buried wiring 23, the fine bumps 9 and the electrically insulating adhesive 91 are used, and the upper semiconductor circuit layer is The lower semiconductor circuit layer 22B forms a mechanical and electrical connection. The configuration of the upper semiconductor circuit layer 21B is the same as that of the image sensor 2D of the ninth embodiment. The configuration of the lower semiconductor circuit layer 22B corresponds to the lower semiconductor circuit 22B of the image sensor 2D of the ninth embodiment, and the memory capacitors CsT1 to U are outputted to output the transistors TW1 to TrGUTn. As described above, in the sensor circuit 2E of the tenth embodiment, based on the same reason as in the case of the image sensor 2D of the ninth embodiment, the signal charge of the image 73 200803484 can be substantially simultaneously stored (substantially At the same time, the exposure is wide and the image distortion of the conventional CMOS image sensor occurs, and the object to be photographed in the south speed can be photographed. Moreover, each pixel 11 of the pixel block 12 only needs to have one photoelectric a diode and a gate element (M0S transistor), therefore, compared to a conventional CMOS image sensor that includes three or four M〇s transistors in addition to a photodiode in one pixel, It can achieve a higher pixel aperture ratio (for example, up to about 60%)' and the size of the pixel u itself can be reduced. Moreover, since the CM〇s image sensor has a higher pixel aperture ratio than the conventional one. Therefore, the ratio of the total area of the light-receiving area (the oblique portion of each photodiode) of the upper semiconductor 21B to the total area of the photographing area can be improved. (Department 1 embodiment) FIG. Address of the embodiment of the invention 11 A circuit diagram of a main circuit configuration of the fixed image sensor 2F; and a cross-sectional view showing an essential part of the actual structure of the image sensor 2F. The image sensor 2f is sensed using the fourth embodiment. The circuit ic (see FIG. 5) is a three-dimensional laminated structure of the two layers of the upper semiconductor circuit layer 21C and the lower semiconductor circuit layer 22c. The image sensor 2F and the image sensor of the third aspect of the present invention The overall configuration and operation of the image sensor 2F are the same as those shown in Fig. 16, and the circuit configuration shown in Fig. 16 is the same as that of the fourth embodiment of Fig. 5 except that the buried wiring is added. The sensor circuit 〖c is the same. It can be understood from Fig. 16 and Fig. 7 that the composition of the image sensor 2ρ, 74 200803484

The upper semiconductor circuit layer 21C and the lower semiconductor circuit layer 22C' are mechanically and electrically connected to each other by using the buried wiring 23, the fine bump electrode 90, and the electrically insulating adhesive 91. This configuration is equivalent to moving the (kxm) group transfer gate group TG^TG formed in the upper semiconductor circuit layer 21 in the image sensor 2A (see FIGS. 7 and 9) of the sixth embodiment. In the lower semiconductor circuit layer 221. Therefore, in the upper semiconductor circuit layer 21C, only (kxn) xm photodiodes (i.e., photodiode groups PD^PDn of the (kxm) group) and (kxm) buried wirings 23 are formed. The configuration of the photodiode PD^PDn is substantially the same as that of the image sensor 2A (see FIGS. 7 and 9) of the sixth embodiment, but differs in the respective element regions of the substrate 40. Form a photodiode. For example, in the case of the photodiode PD!, as shown in FIG. 17, one of a plurality of element regions formed in the surface region of the p-type substrate 40 by the element isolation insulating film 41 is used to span the entire surface. The n+ region Ο is formed in such a manner that the photodiode PDi is formed by the n+ region 42. In the substrate 4, an appropriate position for overlapping the element isolation insulating film 41 is formed in the vertical direction (the direction orthogonal to the main surface of the substrate 40) through the element isolation insulating layer 41 and the substrate 4" The portion of the through hole that is in contact with the base is covered with an insulating film 24 covering the entire surface of the inner wall. A conductive material is filled in the inside of the through hole (inside of the insulating film 24 and inside the element isolation insulating film 41), and the buried wiring 23 is formed of the conductive material. The upper end of the buried wiring is formed by the surface wiring structure 47 of the substrate 40 (element separation insulating film 41).

Within Trg7 μ. The underside of the wiring film 57 formed of ruthenium. The lower surface of the wiring film 57 is also connected to the surface of the corresponding „+ region 42 so that the η. region 75 200803484 field 42 is electrically connected to the buried wiring 23. The lower end of the buried wiring 23 is separated by the substrate 40 (component separation and insulation) The inner surface of the film 41) is exposed and mechanically and electrically connected to the corresponding bump electrode 90. In the lower semiconductor circuit layer 22C, the transfer gate groups TGi to TGn of the (kxm) group are formed; (kxm) Reset transistor TrRST; (kxm) amplification transistor TrAMP; (kxm) group of storage capacitor elements Csti~CsTn; and (kxm) group output transistor group ΤΓ〇υτι~ΤΓ〇υτη. Reset Transistor

The TrRST, the amplifying transistor TrAMP, the storage capacitive elements CST1 to csTn, and the output transistors TrOUT1 to Tr〇UTn have the same configuration as that of the image sensor 2A of the sixth embodiment (see FIGS. 7 and 9). Therefore, the same elements are denoted by the same reference numerals and their description will be omitted. Further, in Fig. 17, the storage capacitors cST1 to cSTn and the output transistors Tr〇uTi to Tr〇uTn have been omitted. . The transfer gate TG^TGn has the following configuration. For example, in the case of the transfer gate TG1, as shown in FIG. 17, it is composed of an M〇s transistor, 2 includes a gate 77, and a pair of η is formed on both sides with the gate 77 interposed therebetween. +-type region (source, drain region) 76. The gate 77 is provided with a transfer gate control signal through a wiring not shown. —n + type region 6 (source, drain region), through conductive contact plugs 78, 80, 82 formed inside wiring structure 74, and wiring films 79, 81 and 83, and corresponding bump electrodes 90 forms an electrical connection. As a result, the source and drain regions of the idle electrode are transferred, and the buried wiring 23 is electrically connected to the photodiode pDi corresponding to the upper semiconductor circuit layer 21C. The other n+ type region of the MOS transistor, the source and the drain region, penetrates through the conductive contact plug 78 formed in the wiring structure 74 and the wiring film (not shown), and corresponds to the weight. The transistor ΤΓμτ and the amplifying transistor TrAMP form an electrical connection. The transfer gate Τ (Ϊ2 to 叱2) has the same structure as the transfer gate. As shown, the lower semiconductor circuit layer 22C has a transfer gate TG TGn which is transmitted through the buried wiring 23 and is respectively connected to the upper semiconductor circuit layer. The photodiodes PDi to PDn in the 21C are electrically connected. As described above, the image sensing of the second embodiment shown in FIGS. 6 and 7 is 2F, and the sensor of the fourth embodiment is used. a circuit !c (refer to FIG. 5) in which (kxm) pixel blocks 12 (each pixel block 12 includes pixels 11) and (kxm) buried wirings 23 are formed in the upper semiconductor circuit layer 21C, Further, the transfer gate groups TGi to TGn, (kxm) reset transistors TrRST, (kxm) amplification transistors TrAMP, (kxm) group of selected transistor groups TrSELi to TrSELn, (kxm) The storage capacitor element groups CST1 to CSTn and the (kxm) group of output transistor groups Tr〇UT1 to Tr0UTn are formed in the lower semiconductor circuit layer 22C, and further through the buried wiring 23 and the bump electrode 90. , the pixel block 12 in the upper semiconductor circuit layer 2 1 c, and the lower semiconductor In the channel layer 22C, the transfer gates tGi to TGnrAMp are electrically connected to each other. Further, the upper main surface (the surface of the wiring structure 74) on the lower semiconductor circuit layer 22C is formed by the bump electrode 90 and the adhesive 91. Further, since the main surface (the inner surface of the substrate 40) below the upper semiconductor circuit layer 21C is electrically and mechanically connected, the two circuit layers 21C and 22C constitute a two-stage semiconductor laminated structure (three-dimensional structure). In the case of the sensor circuit 1 of the fourth embodiment (the same as the case of 77 200803484), the signal charge of the pixel 11 can be substantially simultaneously stored at the same time (the quality is simultaneously exposed and less, and does not occur). The conventional CMOS image sensing the image of Zhai is out of sight~ ^ 'The pixel 11 can be subjected to the high-speed moving object to be processed again. t. Each pixel 11 contains only one photodiode. Body, mouth, compared to a conventional CMOS image sensor that contains three or four VfOS devices in a single pixel, in addition to the photodiode, can achieve a better Pixel aperture ratio (彳丨

Sheep (for example, up to 60%), and the size of the pixel U itself can be reduced. In particular, it can be smaller than in the fifth embodiment to the first embodiment. Furthermore, since the CMOS image sensor has a higher pixel aperture ratio than that of the CMOS image sensor, the light-receiving area of the surface of the upper surface of the bovine V body 21C (the opening portion of the electro-polar body) The ratio of the total area to the total area of the photographing area can be increased. In particular, it can be higher than the above-described first embodiment to the tenth embodiment. Furthermore, by controlling the output transistors Τ ir ir0 UT1 to Tr0UTn by outputting the control signal p(10) Τη, the signal is outputted to the line signal line 37 at 4 o'clock and the transmission gate TG^TGn in the pixel block 12 and When the opening and closing of the electret groups TrSEL1 to TrSELn are selected, the points can be shifted from each other, and therefore, compared with the non-storage capacitive element Cst and the output transistor

In the case of Tr0UT1 to Tr〇UTn, high-speed photography can be performed, which is also an effect. (Embodiment of the Twelfth Embodiment) Fig. 1 is an image of a specific configuration of the sensor 2G according to the address specification of the twelfth embodiment of the present invention. In the image sensor 2G (see FIGS. 16 and 17), the image sensor 2F (see FIGS. 16 and 17) of the eleventh embodiment holds the lower semiconductor circuit layer 22C as it is, and the substrate in the upper semiconductor circuit layer 21C is replaced. 40 will be up and down. The image sensor 2G corresponds to the address specifying image sensor of the third aspect of the present invention. According to the image sensor 2G of the twelfth embodiment, as shown in Fig. 18, the fine bump electrode 90 and the electrically insulating adhesive 91 are used to electrically connect the upper semiconductor circuit layer 21D and the lower semiconductor circuit layer 22D. And mechanical connection. The configuration of the lower semiconductor circuit layer 21D is the same as that of the lower semiconductor circuit layer 2 1C of the image sensor 2F of the U-th embodiment. The image sensor 2G is different from the above-described fifth to eleventh embodiments in that the buried wiring 23 is not used. The substrate 40 in the upper semiconductor circuit layer 21D is reversed from the upper semiconductor circuit layer 2 1C of the image sensor 2F of the eleventh embodiment, and the wiring structure 47 is positioned on the lower side, and the substrate 40 is positioned on the upper side. Since the external light passes through the substrate 40 and is irradiated to the photodiodes PDi to PDn, the thickness of the substrate 4 is thinner than that of the image sensor 2F of the eleventh embodiment. Inside the wiring structure 47, conductive contact plugs 5 8 are formed, which are respectively electrically and mechanically connected to a plurality of n + -type regions 42 (each of which forms a photodiode PD ^ PDJ); and a plurality of The wiring film 59' is electrically and mechanically connected to the conductive contact plugs 58. The wiring film 59 is disposed in the vicinity of the surface of the wiring structure 47, and is electrically and mechanically connected to the corresponding bump electrode 90. As shown, the light 79 200803484 electric diode PD wide PDn is electrically connected to the corresponding transfer gates TG1 to TGn in the lower semiconductor circuit layer 22D' through the corresponding bump electrodes 90. The image sensor 2G of the twelfth embodiment has the same configuration as described above, and has the same effects as those described in the image sensor 2F of the eleventh embodiment. (Thirteenth embodiment) FIG. A circuit diagram of a main circuit configuration of the sensor circuit 3 according to the thirteenth embodiment of the present invention is shown in Fig. 19. Fig. 19 is a functional block diagram showing the overall configuration of an address specifying image sensor of the sensor circuit 3. Electric 3. Corresponding to the sensor circuit of the second aspect of the present invention. The overall configuration of the image sensor of Fig. 19 differs from the address-specific image sensor shown in Fig. 1 in that the setting is There is a reset line 31 that can penetrate through the k pixel blocks 12a to which the same row belongs. That is, there are (kxn) xm pixels Ua arranged in an array of (kxn) columns m rows. In Fig. 12a, the n pixels 11a belonging to the same row are merged and connected in parallel to the common node 19 (not shown in Fig. 19. Corresponding to the common node 13a in Fig. 2A). In the block 12a, m reset lines 31 are formed which extend along corresponding rows of the pixel array and penetrate the pixel block 12a to which the row belongs. Each pixel Ua in each reset line 31 And respectively connected to a reset transistor. In other words, for the n $pixel Ua to which the pixel block 12a belongs, reset transistors TrRST1 TrTrRSTn are respectively provided. The amplified NMOS body TrAMp is for each pixel block 12a. Set one. n reset powers 200803484 曰曰fRSTl~TrRSTn, respectively configured in the corresponding The inside of the n pixels 1 la in the pixel block i2a, and the amplifying transistor TrAMP are disposed outside the corresponding pixel block 12a. Each reset line 3 1 is used to reset the k corresponding to the corresponding row. The signal charge of the pixel 11a in the pixel block i2a is applied to the reset voltage Vrst of the pixel 11a, and the corresponding reset transistors TrRST1 to TrRSTn are used. The signal read from the pixel 11a in the pixel block 12a corresponding to φ is amplified and then sent to the corresponding line signal line 37. The signal ' amplified by each of the amplifying transistors TrAMp is sequentially sent to the corresponding line signal line 37. The configuration of the pixel 11a and the pixel block 12a and the configuration of the reset line 3! are the same as those of Fig. 1, and the description thereof will be omitted. Hereinafter, a sensor private circuit 3 of the thirteenth embodiment, that is, a sensor circuit for configuring an image sensor as shown in Fig. 19 will be described with reference to Fig. 20 . Figure 20 is a circuit configuration of two pixel blocks 12a(i,j)_ and 12a(i+l,j) to which the jth row belongs. The pixel block 12 (i, j) located above includes pixels 11 belonging to the [nχ(i-1)+l] column to the (nxi)th column of the jth row. The pixel block n(i+1, j) located below includes the pixel n belonging to the [nxi+l]th column to the [nxG+l)th column of the jth row. The above two pixel blocks 12 (i, j) have the same configuration as 12 (i + 1, j), and therefore, in the following description, mainly the upper pixel block 12 (i, j) will be explained. In the pixel block 12a(i, j), |1 pixels 14 are included. In other words, it includes: n photodiodes PD wide PDn, n transfer gates TG^TGn, 81 200803484 and n reset transistors TrRST wide TrRSTn. Each pixel & includes a photo-polar body, a transfer closed-pole, and a reset transistor. The transmission TG TG TGn is composed of M〇s electric eclipse and electric Japanese body respectively. Reset transistor

TrRST1~TrRSTn' 构成M纟s transistors are respectively formed. The anodes of the photodiodes PD1 to PDn are connected to the node 'point 15 (node '15), which is one of the source and the gateless region of the corresponding one of the transfer gates TG TGn, and the reset transistor TrRST1 The connection point of one of the source and the drain region of the corresponding one of the TrRSTn is located, and the cathode is connected to the terminal or region of the predetermined potential (usually the ground potential). The other source and drain regions of the reset transistor are connected to the reset voltage source (reset voltage = Vrst). The other source and drain regions of the respective gates TG TGn are connected to the common node 13a. As shown, the n pixels na in the pixel block 12a (i, j} are connected in parallel to the common node 1 3 a in the pixel 11 a. The common node i3a of the pixel block 12a (i, j) is connected a gate of the corresponding amplifying transistor TrAMP. The amplifying transistor TrAMp is disposed outside the pixel block 12a(i, j), a source, a drain region of the transistor ΤΓαμρ, and a DC power source (power source) Voltage=Vcc) is connected, and the other source and drain regions (output side) are connected to the output terminal of the pixel block 12(i,j) (that is, the corresponding line signal line 37). The output terminal of the TrAMp (source and gate region on the output side) is connected to a terminal of a predetermined potential (usually a ground potential) through a resistor R, and constitutes an amplifier in the form of a source follower. The parasitic capacitance is generated, but is omitted in Fig. 20. The source and the non-polar region on the output side of the amplifying transistor TrAMP are connected to the corresponding line signal line 37. Therefore, the output of the transistor TrAMp is amplified 82 200803484, That is, the serial output of η photodiodes PDi~PDn The signal 'sequence is sent to the corresponding CDS circuit 36. When the CDS circuit 36 is sent to the horizontal signal line 33, the row is selected by the m row selection signal 38 by scanning the horizontal scanning circuit %. The signal line 37, thereby transmitting the timing output signal to the horizontal signal line 33. Thereafter, it is transmitted to the image sensor of β and at one end of the horizontal ring line 33 (located at the right end of FIG. 9) Output terminal (not shown). All of the pixel blocks 12a other than the pixel block 12a (i, j) have the same configuration as the pixel block 12a (i, j), and therefore, the same as the above, n photodiodes The timing output signals of the bodies PD1 to PDn are transmitted to the wheel terminal of the image sensor, whereby the image of the object to be photographed can be taken. Secondly, the image sensor for the sensor circuit 3 having the above configuration is provided. The action (from the generation and storage of the signal charge until the output of the signal) is as follows: I reset the overall reset of all the pixels (all photodiodes) firstly 'make each transfer gate applied to the gate of the MOS transistor Pole control signal ρτ1 ΦΦτ The logic state of η becomes H (high), and all the transfer gates TGfTGn are turned on (the M〇s transistors have n, and the system #曰 is used to constitute the photodiode PD1~ disposed in all the pixels i Each of the transfer gates TGi to TGn, that is, the transistor of the first gate element. Next, in this state, the logic state of the reset control signal p applied to the gates of the reset transistors TrMT1 to TrRSTn becomes "Making all of the reset transistors TrRsTi to TrRsTn into an on state (the reset crystals TrRST1 to TrRSTn refer to an image 83 in the respective pixel block 12a).

Each reset transistor of RST element 11a). As a result, a predetermined reset voltage, the gate of the gate passes through the node 15, and is applied to all of the pixel photodiodes PD wide PDn of the whole pixel simultaneously. As shown, all pixels na are reset as a whole, that is, an overall reset. At this time, the voltages of all the amplifying transistors Tr are also reset. 2. Exposure (charge storage)

Next, the logic states of the transfer gate control signals pT1 to pTn applied to the transfer gates TG1 to TGn are LOW (L), and all of the transfer gates TGi to TGn are turned off. At the same time, the logic state of the reset control signal hST is set to L, and all the reset transistors ΤΓ_~υ are turned off. Π After that, the polar body PD1 is very long, and in this state, light is applied to the photodiodes PDDN of all the pixels 11a, and all the photodiodes ΡΕ>1 to p〇n are generated and stored as a whole. The irradiation time generally reaches several hundred sec or even several msec. At the same time as the generation and storage of the signal charge, the logic state of the reset control signal p RST is made Η so that all the reset transistors TrRST TrRSTn are turned on as a whole, and the transfer gate control signal Ρ τ ι φ Tn is made. The logic sorrow becomes η and all the transmission gates TG are widely turned on. After a predetermined time (for example, ^(4)), the logic state of the reset control Λ唬p RST is again L, so that all the reset transistors TrRST1 to TrRSTn are turned off as a whole, and at the same time, all the transfer gates are made. The logic state of the control signal width φτη is again L and all the transfer gates TGi to TGn are turned off. Thus, the reset voltage 84 200803484 is temporarily applied to all the common nodes 13a (that is, the gates of all the amplifying transistors TrAMp). 'To set (reset) the gate voltage of all the amplifying transistors TrAMp to a predetermined reference voltage. 3. The reading of the signal and its amplification are generated and stored in all the photodiode PDs in the above manner. The amount of charge is read by the pixel 11a in the form of a voltage in the following manner, and is amplified.

That is, after first selecting a pixel block 12a by the vertical scanning circuit 34 and the horizontal scanning circuit 35, the logical states of the n transfer gate control signals ρ Τ 1 〜 0 Τ n in the pixel block 12a are sequentially ordered by L. It becomes Η, and the transmission gate TG TGn is sequentially turned on. Further, after keeping the v-like grievance for a predetermined time (for example, 01 # sec), the logical state of the continuation is returned to L in order. Thus, the signals from all of the photodiodes PDi to PDn in the pixel block Ua are read at the node 遂 according to the timing. During this time, all reset transistors TrRsTi~ are kept in a disconnected state

The amplifying transistor TrAMP connected to the node 13a in the form of a source follower is connected to the node by its gate, so that the voltage signal read to (4) (1) is immediately amplified by the amplifying transistor TrAMp. Further, the signal "after the big" is outputted from the source and the non-polar region of the amplifier transistor I to the line signal line 37. Body: = n pixels 11a in the block 12a (that is, the photodiode = 1; when the signal is amplified, the signal is read from the - pixel, the first electrode - the current M PD1) and The amplified 85 200803484 is different until the start of the signal period of the next pixel 11a (for example, photodiode pE > 2), as described above, the reset transistor TrRST1 must be used for the pixel 1 ia In the on state, the reset voltage vRST is temporarily applied to the node 13a, and all of the nodes 13a (the gate of the amplifying transistor TrAMp) are set (reset) at the reference potential. The reason is that if this is not the case, it is feared that the residual influence of the signal of the previous pixel 11a (e.g., photodiode pDi) causes a signal error condition with the subsequent pixel 11a (e.g., photodiode Pd2). Since there are n pixels na (n photodiodes PD1 to PDn) in the pixel block 12a, the read operation of the transfer gate control signals ρ Τ1 to φ τη is performed n times. The amplification operation by the amplifying transistor TrAMp has a total of n times; the resetting operation of the amplifying transistor (4) has a total of (n-1) times. Specifically, for example, the signal transfer gate TG! of the pixel block 12a is initially turned into a conduction state, and the signal charge (that is, the signal charge stored in the second photodiode PDi) is proportional to the signal. Read on the node, take. The signal is immediately amplified by the amplifying transistor TrAMp, and the amplified signal is then transmitted to the signal line 37. Next, the reset transistor TrRsTi connected to the photodiode PD is temporarily turned on, the reset voltage VRST is temporarily applied to the node 13a, and the gates (nodes 14) of all the amplifying transistors TrAMp are reset. At the reference potential. Thereafter, the second transfer gate tG2 in the pixel block 12a is temporarily turned on, and the node 13a reads a signal proportional to the signal charge (i.e., the signal charge stored in the second photodiode PD2). The signal is immediately amplified by the amplification transistor TrAMP, and the resulting amplified signal is transmitted to the line 86 200803484 line 3 7 . And a ^ _ person's the waiter and the photodiode ρε> 2 connected to reset the crystal... RST2 is temporarily turned on, and the gate of the amplified transistor TrAMP (卽 14) is re-signed n; Bit. Next, the same operation as described above is repeated for the third photodiode ΡΕ ΡΕ > Ί 4 photodiode 叩 4 and the like. The most " ten pairs of n-th photodiodes pDn perform the reading operation and the amplifying operation, and the processing of the pixel block 12a is ended. In the image sensor of FIG. 1, the output terminal of the magnifying package TrAMp corresponding to the pixel block 12a is i, and therefore, the pixel block has a photo-electrode PD1~PDn. The obtained n signals are outputted from the source and drain regions on the output terminal side of the large electric beta body TrAMp to the row number line 37. That is, the timing signal that the n-pulse waveforms are connected by the pixel block 1 to reflect the signal charge amount (the amount of the illumination light) of the photodiodes PDi to pDn are separated by a predetermined interval. . The image sensor (see FIG. 19) has a total of (kxm) pixel blocks 12a. Therefore, during the scanning of all the pixels Ua, the above-mentioned operation is repeated (kxm) times and outputted by the pixel block 12a. The signal, that is, a timing signal in which n pulses are connected at a predetermined interval, is sent to a well-known sample and hold circuit or A/D conversion circuit for predetermined signal processing. The fastest exposure speed in practice (ie, the shortest signal charge storage period) is (1/8000) seconds, 125#sec). Therefore, for (kxm) pixel blocks 12a, if the n value (the total number of 87 200803484 pixels 11a in each pixel block 12&) can be set in the following manner, the pixels to which all the pixel blocks 12a belong can be made. The signal charge storage (exposure) of 11 a (photodiode PDcPDn) can be performed substantially simultaneously, that is, the weight of the node 13 3 a (the gate of the amplifying transistor TrAMP) by the reset transistors TrRST1 to TrRSTn is obtained. Between k (total reset time) required for the required number of times (ie, n times), all the pixels 11a in the pixel block 12a (the signals sent by the photodiode PD^PDJ are corresponding) The sum of the time (total amplification time) required to amplify the transistor TrAMP is amplified, and then the (kxm) times of the sum is much less than the shortest signal charge storage period (=125# sec). In other words, all The signal charge of Pixel Mountain can be stored substantially simultaneously (substantially simultaneously exposed). ~ η ·~I匪 are respectively output separately, so for their output timing signals, analogy and digits can be performed in parallel (A/ D) conversion and other processing. Compared with the conventional (10)S image sensor, it can have higher speed data processing. This point also has the effect of substantially simultaneous exposure. + F broadcast the above actions can be understood, if viewed in a frame, The end of the timing output output by each pixel block 12a is longer (although quite a slight amount) compared to when the # is closer to the scan time than during the initial charge storage period during the learning period. More accurate image data, or for the purpose of having a large mouth/in order to obtain a well-known circuit, the η value of 徂4 /, can also be used in the back-end circuit for the gate according to the charge storage period, / No. Correction. In this way, the influence of the child is affected. It is expected that the variation of the μ charge storage _ can be substantially simultaneously exposed by the above-mentioned method. The conventional image distortion of the CMOS image sensor of 200803484 can be used to photograph a high-speed moving object.

Further, the common amplifying transistor Τγαμρ is disposed outside the pixel block 丨2a so as to correspond to each pixel block 12a. Therefore, each pixel 11a in the pixel block 12a need only include A photodiode with a gate element (MOS transistor) and a reset transistor (M〇s transistor). Therefore, a higher pixel aperture ratio (for example, about 6〇%) can be achieved compared to a conventional CM〇s image sensor in which one photodiode still includes three or four MOS transistors in one pixel. ). The pixel aperture ratio is compared with the image sensor using the sensor circuit 第 of the first embodiment (that is, the one including only one photodiode and one gate element) (refer to the figure and the image illusion, Because there is a reset transistor, it is correspondingly reduced. Furthermore, in the conventional CMOS image sensor, the signal processing is performed in accordance with the number of scanning lines, and a high-speed a/d conversion circuit is necessary. However, the number of scanning lines set by the U η value in the image sensor using the sensor circuit 3 of the thirteenth embodiment is small, and the degree of parallel connection can be increased, thereby allowing each of the amplifying transistors 1 to be slow. The processing speed of the timing output signal. Therefore, it is possible to use an A/D conversion circuit which is simpler in construction, and this is also the effect. Also, 'n output signals from n photodiodes pD are wide. In the form of a series connection, the output transistors TrAMp are outputted. Therefore, the wiring of the next section connected to the output terminal of each of the two electric B bodies TrAMp tends to be simple, which is also the effect thereof. ) 89 200803484

Fig. 21 is a circuit diagram showing the configuration of the main circuit of the address specifying image sensor 4 according to the fourteenth embodiment of the present invention. Fig. 23 is a cross-sectional view showing the essential part of the actual structure of the image sensor 4. The sensing circuit used in the image sensor 4 is an amplifying transistor TrAMP of the sensor circuit 3 (see FIG. 20) of the thirteenth embodiment (the amplifying transistor TrAMp is associated with each pixel block). The source and drain regions on the output side of 12a are provided in a corresponding manner, and n selection transistors TrsELi to TrsELn (second gate elements) are connected so that the amplified photodiodes PDi to PDni n are amplified. The output signals are output in parallel by selecting the transistors TrSEL1 to TrrELn, and the upper semiconductor circuit layer 21E and the lower semiconductor circuit layer 22E are laminated to form a three-dimensional laminated structure. The image sensor 4 corresponds to the image sensor of the fourth aspect of the present invention, and the sensor circuit used therein corresponds to the sensor circuit of the second aspect of the present invention. The overall configuration and operation of the image sensor 4 are the same as those shown in Fig. 19, and the description thereof will be omitted. Further, in the circuit configuration of w 21, in the sensor circuit 3 of the thirteenth embodiment of FIG. 20, n selection transistors TrSEL wide TrSELn (second gate elements) are added (there are no storage capacitor elements and The transistor is output, and therefore the same reference numerals are given to the same components as those of FIG. 2Q, and the description thereof is omitted. Wherein, in the image sensor 4, in the upper semiconductor circuit layer 21E, the common ray point 13 a of each of the pixel blocks i 2a or the pixel block i 2a is formed. @ , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , "Electrical connection" Therefore, π w zi is dried on φ in Fig. 21, and the buried wiring 23, the buried wiring generated by the buried wiring 23, and the parasitic capacitance (: 01 and C〇2 ο 90) are added. 200803484 The wiring 23 is embedded, and a pixel is provided for each pixel block 12a (that is, n pixels Ua). Next, the actual configuration of the image sensor 4 will be described. As can be seen from FIG. 23, the image sensor 4 uses the buried wiring 23 The fine bump electrode 90 and the electrically insulating adhesive 91 form the upper semiconductor circuit layer 21E and the lower semiconductor circuit layer 22E in mechanical and electrical connection.

In the upper half of the body circuit layer 21E, (kxm) pixel blocks 12a are formed, that is, there are (kxn) xm pixels 1 ia. Therefore, in the upper semiconductor circuit layer 21E, the photodiode group PD of the group of (kxn) xm photodiodes (that is, the singularity) is included; (kxn) xm transfer gates (also That is, there are (kxm) groups of transmission gate groups TG TGJ; and (kXn) Xm reset transistors (that is, there are (kxm) groups of reset transistor groups TrRsTi~TrRsTj. In the upper semiconductor circuit layer 21E Further, (kxm) buried wirings 23 are formed. In the lower semiconductor circuit layer 22E, (kxm) amplification transistors TrAMP are formed; and (kxn) xm selection transistors (that is, there are (kxm) groups selected The transistor group TrSEL1 to TrSELn). In the upper semiconductor circuit layer 21E, the element isolation insulating film 41 is formed in a predetermined pattern in the surface area of the 一 _ 口 , , , , , , , , , , , , , , , , , , , , , , , , , , , The element regions are formed in an array of side by side, as shown in the layout of Fig. a. The element regions are respectively corresponding to one pixel Ha. 'There are n photodiodes 12a (i' j in the pixel block) ) corresponding to the inside of the component region, forming PD wide PDn; n transfer gates TGi to TGn; and e 91 20080348 4

Reset the electric b body TrRST wide TrRSTn. The photodiode pDi is formed, for example, as shown in Fig. 23, by forming a p-type substrate 4 () @ n + type region ^ (i.e., a p-n junction photodiode). The transfer gate TG! is formed by an M?S transistor, and includes a gate 44 and a m region 43 interposed therebetween with the gate region 44 interposed therebetween. Since the n + -type region 42 of the photodiode PDi is shared, the source and drain regions of the gate tGi are transferred to form an electrical connection with the anode of the photodiode ρ〇. The electrode insulating film existing between the gate 44 and the surface of the substrate 4 () is omitted in Fig. 23. The gate 44 is electrically connected to the corresponding read control line 32 by wiring of the wiring structure 47 formed on the surface of the substrate 4, and the wiring of the second and second γ. The reset transistor TrRST1 is formed of a MOS transistor and includes: a gate 49; and a region 43a between which the gate 49 is opposed to the meander region 42. The transistor is reset, and the n + -type region 42 of the photodiode PD is electrically connected to the anode of the photodiode PDi by a source and a non-polar region of the common 'reset transistor Tr'. In the n-type region 43a (source, drain region), the reset voltage VRST is applied through a wiring (not shown). The other photodiodes PR to PDn, the transfer gate tg, and the reset transistor TrRST TrRSTn have the same characteristics as the photodiode pDi, the transfer gate TG!, and the reset transistor TrRsTi, respectively. Composition. Inside the wiring structure 47, a wiring film 46 formed in a predetermined pattern; and n conductive layers for electrically connecting the n + -type regions 43 of the transfer gates to the wiring film 46 are formed. Contact plug 92 200803484 The n transfer gates tg in the pixel block 12a (i, j} are electrically connected to the wiring film 46 by the contact plugs 45, respectively. The pole TG wide TGn is connected in parallel to the common node (1). The n+ type region Ο in the upper semiconductor circuit layer 21E has a function of an FD (floating diffusion) region, that is, a function system, by photoelectric conversion

In other words, it will be stored in the photoelectric diode to P pressure signal. " body one signal charge amount converted into electricity

In the substrate 4A, a substrate is formed so that the element is separated from the insulating film 41. The substrate: (iv) m through holes penetrated in the up and down direction (the direction orthogonal to the main surface of the substrate 4A). The n+ of the idle electrode tGi to tg, the element isolation insulating film of the region (source, drain region) 43: the portion of the overlapping hole that is in contact with the substrate 4G is covered by the insulating film = == comprehensive. A conductive material is filled in the inside of the through hole (the inside of the insulating film 24 and the element: "the inside of the edge film 41"), and the conductive substrate 40 is embedded in the conductive substrate 40. The upper end of the buried wiring 23 is exposed to the lower end of the wiring contact plug. This conductivity is electrically connected from the wiring port 46 corresponding to the conductive contact plug 23a via the 1" embedded wiring 23 which is connected to the wiring film disk formed in the wiring structure 47 by the upper end. As a result, the n transfer terminals of the pixel block are extremely large, and the polar regions are 4; 3, as shown by the circuit configuration of the source 1 and the drain line 23 having the pass-through. The lower end of the inner and second buried wirings 23 of the corresponding embedded board is formed by the base/in, the lower jaw and the corresponding bump electrode 90. The mechanical and electrical connection is made in the lower semiconductor circuit layer 22E. The element isolation insulating film 6 is formed in a predetermined pattern on the surface region of the p-type single crystal germanium substrate 6?

The component area for TrAMP and the component area for SELn. Here, a predetermined number of the selection transistors TrSEL1 to Tr are formed to correspond to the configuration of one pixel block i2a(i, j). The amplifying transistor TrAMP is composed of a MOS transistor and includes

The gate 65 and a pair of γ-type regions (source, drain regions) 64 are formed on both sides with the gate 65 interposed therebetween. The gate electrode 65 is formed by the conductive contact plug 71, the wiring film 72, the conductive contact plug 4a, and the wiring film 75 which are opened in the wiring structure 74, and the corresponding bump electrode 9 is provided. 〇 form an electrical connection. As a result, the gate of the amplifying transistor TrAMp is electrically connected to the common node 13a (pixel block i2a(i, j)) corresponding to the upper semiconductor circuit layer 2 through the corresponding buried wiring 23 (refer to 21) Further, an n-type region 64 (source, drain region) is electrically connected to the wiring film 73 formed inside the wiring structure 74 through the conductive contact plug 69 formed inside the wiring structure 74. . The other n + -type region 64 (source, drain region) is supplied with a power supply voltage Vcc through a wiring (not shown). Each of the n far-selective transistors TrSEL1 to TrSELn, which is constituted by a MOS transistor, includes a gate 67 and a pair of n+-type regions (sources, drains) formed on the sides thereof via the gate 67 Area) 66. An n + -type region (source, drain region) 66 is formed by transmitting a conductive contact interposer 70 and a wiring film 73 formed inside the wiring structure 74 to an n + type of a corresponding amplifying transistor Tr 94 200803484 The regions (source, drain regions) 64 form an electrical connection. The gate 67 is electrically connected to the output selection line 39 through the wiring formed inside the wiring structure 74. The gates 67' of the selection transistors TrSEL1 to TrSELn are transmitted through the corresponding output selection lines 39, respectively, with the application of the predetermined output enable signals φSEL1 to φSELn. As described above, in the image sensor 4' of the fourteenth embodiment shown in Fig. 23, the sensor circuit shown in Fig. 21 is used, which is a group of photodiodes PD of (kxm) group, PDn, (kxm) The transfer gate group tg wide TGn, the reset transistor group dRST1 to TrRSTn of the (kxm) group, and the (kxm) buried wiring 23 are formed in the upper semiconductor circuit layer 21E, and (kxm) The selection transistor groups TrAMP1 and TrSELn of the amplification transistor TrAMP and the (kxm) group are formed in the lower semiconductor circuit layer 22E, and pass through the buried wiring 23 and the bump electrode 90 to cause the pixel block transfer gate in the upper semiconductor circuit layer 21E. The pole groups TG1 to TGn) and the amplifying transistors TrAMP in the lower semiconductor circuit layer 22E are electrically connected to each other. Further, the main surface (the surface of the wiring structure 74) above the lower semiconductor circuit layer 22E is mainly the lower surface of the upper semiconductor circuit layer 21E (the inner surface of the substrate 40) by the bump electrode 90 and the adhesive 91. Since the electrical and mechanical connections are made, the two circuit layers 21E and 22E constitute a two-stage semiconductor laminated structure (three-dimensional structure). Based on the same reason as the sensor circuit 3 of the thirteenth embodiment described above, the signal charge of all the pixels 能a can be stored substantially simultaneously (the same as the exposure on the same day), and does not occur. The image of the conventional image sensor is out of shape. It can take a picture of the object to be moved at the same speed. 95 200803484 Shadow 0 In addition, each pixel Ua of the pixel block 12a contains only one photodiode. , with an inter-pole device _s transistor) and a reset transistor (MOS transistor) 'so' compared to two or four M〇s in addition to the photodiode in one pixel The conventional cm〇s image sensor of the crystal can achieve a higher pixel aperture ratio (for example, up to about 6〇%), and the size of the pixel 11a itself can also be reduced. _ Furthermore, since the CMOS image sensor has a higher pixel aperture ratio than the conventional CMOS image sensor, the total area of the light receiving region (the opening portion of each light pack body) of the surface of the upper semiconductor 21e is relatively The proportion of the total area of the photographing area can be increased. (Embodiment 15) FIG. 22 is a circuit diagram showing the configuration of the main circuit of the address specifying type image sensing benefit 4A according to the fifteenth embodiment of the present invention; and FIG. 24 is a view showing the actual configuration of the image sensor 4A. A cross-sectional view of the main part. The image sensors 4A and φ are connected to the respective output sides of the n selection transistors τ AASEL η in the sensing state circuit (see FIG. 21) used in the image sensor circuit 4 of the above-described fourteenth embodiment. Further, the storage capacitive elements CST1 to C^n and the output private crystals TrOUT1 to Tr〇UTn are formed, and the upper semiconductor circuit layer 21e and the lower semiconductor circuit layer 22E are stacked to form a two-dimensional three-layer laminated structure. This image sensor 4A corresponds to the image sensor of the fourth aspect of the present invention. As can be seen from FIG. 24, the image sensor 4A uses the buried wiring 23, the fine bump electrode 9A, and the electrically insulating adhesive 91 to form the upper semiconductor circuit layer 21E and the lower semiconductor circuit layer 22E. Electricity 96 200803484 gas connection. The upper semiconductor circuit layer 21E has the same configuration as that of the video sensor 4 (see Fig. 23) of the above-described fourteenth embodiment. Therefore, the same reference numerals are given to the fourteenth embodiment, and the detailed description thereof will be omitted. The lower semiconductor circuit layer 22E has substantially the same configuration as the lower semiconductor circuit layer 22E of the image sensor 4 of the above-described fourteenth embodiment, but the only difference is that the storage capacitive element CST丨 is additionally formed. CSTn, and output transistor Tr〇UT丨~Tr〇UTn. That is, in the lower semiconductor circuit layer 22E, in addition to (kxm) amplifying transistors TrAMp, and (b) groups of selected transistors, such as ~η·, a storage capacitor of the group (4) is also formed. The output transistor groups ΤΓουτι to Tr0UTn of the element groups cST1 to cSTn and (kxm). As shown in FIG. 24, in the lower semiconductor circuit layer 22, the element isolation insulating film 61 is formed in a predetermined pattern on the surface region of the substrate 60, thereby forming an element region for a predetermined number of the amplification transistor TrAMp, In the case of a plurality of transistors, the structure of the transistor θ 〜 丁 — 、 、 、 、 、 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 。 。 。 。 。 。 The image sensor 4 (see FIG. 23) of the fourteenth embodiment is the same as that of the m〇s transistor, and includes a gate 65 and a gate 65 interposed therebetween.

A pair of 11-type regions (source, drain regions) 64 are formed. The electrical connection of the amplifying transistor TrAMP is also the same as that of the image sensor 4 (see Fig. 21) of the fourteenth embodiment. The n selective transistor transistors TrsEL1 to TrSELn have the same composition as the above-described 14th embodiment 97 200803484' by the image sensor 4 of the MOS transistor form.

The body includes a storage capacitor element C: a gate 67 formed on both sides, and an n+-type region (source, drain region) 66 interposed therebetween via the gate 67. Further, st wide CSTn and output transistors ΤΓ〇υτι to Tr〇uTn are connected to the MOS transistor in the circuit configuration shown in FIG.

For example, in the case of selecting a transistor, a type region (source, drain region) 66 is transmitted through the conductive contact plugs 70, 69 and the wiring M 73 formed inside the wiring structure 74, and corresponding thereto. An n+ type region (source, drain region) 64 of the amplifying transistor TrAMP forms an electrical connection. The gate 67 is electrically connected to the output selection line 39 through the wiring formed inside the wiring structure 74, and the output selection signal ^(1) is applied. Another n+-type region (source, drain region) 66 of the transistor TrSEL1 is selected, together with the n+-type region 66& on the opposite side of the gate 67a, constituting the M having the function of the storage capacitive element Csti 〇s capacitor. The type region 66a, together with the gate 67b, and the n+ type region 66a which is located on the opposite side of the n+ type region 66a when the gate electrode is used, constitutes a function of the Tr〇UT1 function as the input & f day Then Ο S transistor. The gate 6 7 a is connected to a terminal of a predetermined potential (passing $ is the ground potential). The gate 67b is electrically connected to the output control line 39a via a wiring (not shown), and has an output control of the application of the WL hole number W OUT1. As shown, in one element region, a selection transistor TrSEL1, a storage capacitance element Csti, and an output transistor Tr〇un are formed. This point is also the same for other selection transistors Tqel2~TrsELn. As described above, the image sensor of the fifteenth embodiment shown in FIG. 24 is 200803484

4. Using the sensor circuit shown in FIG. 22, the phototransistor group PD wide PDn of the (kxm) group, and the transfer gate groups TGI TG TGn and (kxm) of the (kxm) group are reset. The transistor groups TrRST1 to TrRSTn and (kxm) buried wirings 23 are formed in the upper semiconductor circuit layer 21E, and the (kxm) amplification transistors TrAMP and (kxm) groups are selected from the group of transistors. ^, the (kxm) group of the storage trough component groups CST1 to cSTn, and the (kxm) group of output transistor groups Tr0UT1 to Tr0UT1 are formed in the lower semiconductor circuit layer 22E, and through the sigh wiring 23 and the convex The bulk electrode 9A electrically connects the transfer gate group TG^TGn in the upper semiconductor circuit layer 2iE and the lower semiconductor circuit layer 22A to the amplifying transistors TrAMP. Further, the upper main surface (the surface of the wiring structure 在) of the lower semiconductor circuit layer 22E is mainly the lower surface of the upper semiconductor circuit layer 21E by the bump electrode % and the adhesive 91 (substrate 4 〇 The inner surface is electrically and mechanically connected. Therefore, the rain and thunder soft circuit layers 21E and 22E constitute a two-stage semiconductor laminate structure (three-dimensional structure). The y port is based on the same reason as the sensor circuit 3 of the thirteenth embodiment described above. The signal charge of all the pixel mountains can be substantially simultaneous: the sub-mass is simultaneously exposed, and the habit does not occur. Known CMOS image = image distortion of the detector, which can be used to take a high-speed moving object to be touched t ~ 廿丨豕 Ha, containing only one photodiode β _, /, a gate element (] ^ 〇 , # ^电曰曰体) and a reset transistor outside the H-containing photodiode or _ transistor in a pixel of the conventional CMOS image Wei 99 200803484 measured, can be compared The pixel opening ratio is high (for example, up to about 60%), and the size of the pixel 11a itself can be reduced. Furthermore, since the CMOS image sensor has a higher pixel aperture ratio than the conventional CMOS image sensor, the total area of the light receiving region (the opening portion of each photo-electrode body) on the surface of the upper semiconductor 2ie is relative to the photographing region. The ratio of the total area can be increased. , " again, by controlling the output = 曰 Tr0UT Width Tr0UTn by outputting the control signal φ 〇υ τ ι φ η η, the signal is outputted to the signal line 37 = time point, and the pixel block 12a When the transmission gate tg is wide and the selection of the electric body groups dSELi to Trseln can be shifted from each other, the image sensor of the fourteenth embodiment is more capable of performing high-speed photography. The effect is. (Embodiment 1) The address specifying image sensors 2 to 2A of the fifth to twelfth embodiments and the address specifying type image sensor 4 of the fourteenth and fifteenth embodiments

/V is a layered structure in which two semiconductor circuit layers of the upper and lower layers are laminated. However, the image sensor of the present invention is not limited to the second embodiment. It is also possible to form a semiconductor circuit layer of three or more layers by using a spear layer. An illustrative example is given below, which is composed of a semiconductor circuit layer of two layers of upper, middle, and lower layers. Fig. 28 is a schematic diagram showing the configuration of a main part circuit in which the address specifying image of the sixteenth embodiment of the present invention is sensed as 2H, and Fig. 29 is a cross-sectional view of the essential part of the actual structure of the same image sensor 2H. In the image sensor 2h, the sensor circuit 1B (see FIG. 4) of the third embodiment is used, and the three-dimensional three-dimensional embodiment of the embodiment of the sensor/program circuit 1B is used for 100 200803484. The image sensor 2 (see FIGS. 6 and 8 ) having a laminated structure has substantially the same configuration, but differs in that the upper semiconductor circuit layer 21F, the intermediate semiconductor circuit layer 22Fa, and the lower semiconductor are provided. The circuit layer 22Fb is laminated to form a three-dimensional three-layer laminated structure. The image sensor 2H corresponds to the image sensor of the second aspect of the present invention. The configuration of the upper semiconductor circuit layer 2 1F is the same as that of the upper semiconductor circuit layer 21 (see Fig. 8) of the image sensor 2 of the fifth embodiment. The (kx m) group of reset transistors TrRsTi to TrRsTn and (kxm) amplification transistors TrAMP' formed in the lower semiconductor circuit layer 22 in the image sensor 2 are formed in the intermediate semiconductor circuit layer 22Fa. Each of the pixel blocks 12 in the upper semiconductor circuit layer 21F and the reset transistors Τγ_TrTrsTn and the amplifying transistor TrA· corresponding to the intermediate semiconductor circuit layer 22Fa are formed in the upper semiconductor circuit layer 2 1F. The corresponding buried wirings 23 are electrically connected to each other. The 遥 遥 遥 电 于 于 于 于 下 下 下 下 下 下 下 下 下 下 下 下 下 下 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Tr 。 。 。 The selected interconnect transistors TrSEL1 to TrSELn corresponding to the lower semiconductor circuit layer 22Fb are electrically connected to each other through the corresponding buried wirings 23 formed in the intermediate semiconductor circuit layer 22Fa. The actual structure of the image sensor 2H will be described with reference to Fig. 29. The configuration of the upper semiconductor circuit layer 21F is the same as that of the upper semiconductor circuit layer 21 (see Fig. 8) of the image sensor 2 of the fifth embodiment 101200803484. The same is given to the corresponding elements and the description thereof is omitted.

The intermediate semiconductor circuit layer 22Fa is similar to the structure of the lower semiconductor package layer 22 of the image sensor 2 (refer to FIG. 8), and is formed in a predetermined pattern in the surface region of the P-type single crystal germanium substrate 6A. The film 61 thereby forms an element region for a predetermined number of reset transistors TrRST and an element region for amplifying the transistor TrAMP. As shown in FIG. 29, the IGBT is formed of a MOS transistor, which includes a gate 63 and a pair of n+-type regions (sources) formed on both sides with the gate 63 interposed therebetween. , bungee area) 62. The gate 63 is electrically connected to the corresponding reset line 31 by passing through the wiring formed in the wiring structure 74 on the surface of the substrate 60. The -n+ type region 62 (source, drain region) is transmitted through the conductive contact plug 68 formed in the wiring structure 74, the wiring film 72, the conductive contact plug 74a, and the wiring film 75. The bump electrodes 90 form an electrical connection. As a result, resetting the transistor

One of the source and drain regions of TrRST is electrically connected to the common node 13 (pixel block 12(i, j)) corresponding to the upper semiconductor circuit layer 21F through the corresponding buried wiring 23 (refer to the figure). 6). The other γ-type region 62 (source, drain region) is applied with a reset voltage 'π through a wiring (not shown). The amplifying transistor TrAMP is composed of a MOS transistor and includes a gate 65 and a pair of n-type regions (source, drain regions) 64 formed on both sides with the gate 65 interposed therebetween. The gate 65 is electrically connected to the corresponding bump electrode 9 through the conductive contact plug 7A, the wiring film 72, the conductive contact plug 74a, and the wiring film 75 formed inside the wiring 102 200803484 structure 74. connection. As a result, the gate of the amplifying transistor TrAMp is electrically connected to the common node 13 (pixel block 12) corresponding to the upper semiconductor circuit layer 21 through the corresponding buried wiring 23 (refer to the figure). 6) The 11-type region 64 (source, drain region) is formed by the conductive contact plug 69 formed in the wiring structure 74, the wiring film 73, and the conductive contact plug base 23a. The conductive interposer 23 of the lower semiconductor circuit layer 22fb is electrically connected, and the other n+ type region 64 (source, drain region) is applied with a power supply voltage Vcc through a wiring (not shown). Lower semiconductor circuit layer 22Fb The element isolation insulating film 61 is formed in a predetermined pattern on the surface region of the p-type single crystal germanium substrate 60, thereby forming an element region for the selection transistors TrsEu to TrsEh of the number of cells. The transistor TrSEL1 is selected. Each of TrSELn is composed of a M 〇s transistor, and includes a gate 67 and a pair of _ regions (source, drain regions) 66 formed on both sides with the gate 67 interposed therebetween. Area (source, bungee area) 66, The conductive contact plugs 7A, the wiring film 72a, the V electrical contact plugs 74ai, and the wiring film 75 formed inside the wiring structure 74 are electrically connected to the corresponding bump electrodes 90. Therefore, the n + -type region (source, drain region) 66 passes through the bump electrode 9 〇, and the conductive plug 23 in the intermediate semiconductor circuit layer 22Fa, and the corresponding amplifying transistor TrAMP An n+ type region (source, drain region) 64 forms an electrical connection. Another n-type region (source, drain region) 66 is connected to a corresponding output terminal of the image sensor 2A. Gate 67 The electrical connection is made to the output selection line 39 through the wiring ' formed inside the wiring structure 74, 103200803484. The gates 67 of the k-selective bodies TrSEL1 to TrsELn are respectively transmitted through the corresponding output materials 39. There is a predetermined output selection signal ^. The image sensor 2H of the 16th embodiment has the actual structure described above, but the operation and effect thereof are the same as the image sensing benefit 2 of the fifth embodiment. Mai Zhao is the same as in Figure 6 and _ 8). For example, the configuration of the storage capacitor element is shown in Fig. 25 to Fig. 27, and is a configuration example of the storage capacitor element used in the above embodiment. The storage capacitor element csT1 is provided between the selection transistor TrSEL1 and the output transistor Tr^, 餸ΓΓουτι. The storage capacitor element CST of Fig. 25(4) is internally connected to the p-type shi 基板 substrate 6 , The n+ region on the side of the element Cs" forms the germanium region 66b formed to form the selective transistor Tr, ^^^^SEL1, and the n+ region 66a on the side of the capacitive element CST1 (which is used to form the output transistor Tr_). The right bias is applied between the substrate 6 〇 and the n + region & complement to generate a p-n junction capacitance, and thus can be used as the storage capacitor element CST1. The storage capacitor element CST1 of Fig. 5 (= is formed in the selective transistor region 66 and the n+ region 66a forming the output transistor Tr〇UTi ... has a transmission gate insulating film (not shown) on the p-type germanium substrate 6〇 can be:: the gate 67'. If the power supply voltage Vcc is applied to the gate 67a, the surface of the substrate 60 can be erected & a or an inverted layer L of the n-type or n+ type can be generated, so that This is used as the storage capacitor MCST1. This is a typical deletion 104 200803484. "The user is in the above-described embodiments. The opening is the side of the capacitive element of the gate 67 of the gate electrode. The portion is placed above the gate 67 & through an insulating film (not shown). Similarly, the end portion of the gate 6% of the CST1 side of the gate 6% of the output transistor Tr〇Un is formed. The opposite side of the gate 67 is placed above the gate 67a through an insulating film (not shown). The storage capacitive element %' of Fig. 26(4) is formed in the region 66 where the selective transistor ku is formed and forms an output. The n+ region of the crystal has a transparent insulating film (not shown) and is formed on the p-type substrate. The square-formed gate 67a. Inside the substrate 6G, the n+ region 66 of the capacitive element Csti side for forming the selection transistor TrSEL1 and the n+ region 66a of the capacitive element CST1 side for forming the output transistor 已 have been removed. .

When the power supply voltage Vcc is applied to the gate electrode 67a, an inversion layer of an n-type or an n+ type is formed in the surface region of the substrate 60 as in the case of FIG. 25(b), and this is used as a storage capacitor element. Cm to use. At this time, the end portion of the reverse layer on the side of the idle electrode 67 functions as an η, region or n-type region for selecting the transistor TrSEL1. Further, the end portion of the inversion layer on the gate 67b side functions as an n-type region or an n+-type region for outputting the transistor ΤΓ〇υτι. This is a modification of the MOS capacitor. The storage capacitor element Csn of FIG. 26(b) has a pass-through 纟 缘 缘 ( (not shown) between the gate 67 of the transistor and the gate 67b of the output transistor Troim. A gate 67a is formed above the substrate 6A. Inside the substrate 6A, the n+ region 66 for forming the capacitance element Csti side of the selection transistor TrsEL1 and the n+ region 66a for forming the output element 105 200803484 crystal Tr〇UT1 on the capacitive element cST1 side have been removed. The '^ portion of the gate 67a passes through the insulating cavity; the soil, the film (not shown) is placed over the gate 67 for forming the selective transistor TrSEL1; the other end is transmitted through the insulating film. (not shown) is carried over the gate 67b for forming the wheel-out transistor. The power supply voltage Vce is applied to the gate 67a to the right. As in the case of FIG. 25(b), an inversion layer of an n-type or an n+ type is formed in the surface region of the substrate 60, so that it can be used as a storage capacitor element. . At this time, the end portion of the reverse layer on the gate 67 side functions as an n-type region or an n-type region for selecting the transistor Tr muscle 1. X, the inversion layer is on the side of the gate 67b and functions as an n-type region or an n+-type region for the output transistor TrOUT1. This is also a modification of the MOS capacitor. The storage capacitor element of Fig. 27 is inside the substrate 6A, the n+ region 66 for forming the capacitor element side of the selective transistor, and the n+ region of the capacitor element in side for forming the output transistor Tr(10)n are removed. 66a. Instead, a type region 66b is formed between the gate 67 of the transistor TrsEu and the gate 6 of the output transistor ΤΓ〇υτι. The gate 67 of the transistor TrsELi is selected to be disposed between the γ-type region 66 and the n+-type region 66b; and the gate 6 of the output transistor is disposed between the n+-type region 66a and the n+-type region 66b. On the gate electrodes 67 and 67b, a capacitor element 67 having a τ-type cross-sectional structure is formed through a gate insulating film (not shown). The core of the capacitor element 67 has a CST1 function of the capacitor element, and includes a lower electrode-shaped lower electrode 67aal in cross section, a 10610603484 edge film 67aa2 formed above the lower electrode 67aai, and an insulating film 67aa2. The upper electrode 67aa3 is formed above. The lower end of the lower electrode 67aal is in contact with the surface of the n + -type region 66b by extending downward between the gates 67 and 67b. The upper electrode 67aa3 has an appropriate gate voltage vc (0 to Vc). As shown, the storage capacitor element Csti can have various configurations. (Modification) The first to the sixteenth embodiments are The present invention is not limited to the embodiments, and various modifications can of course be made without departing from the gist of the invention. For example, most of the 1 bar of the above embodiment are used separately. The bump electrode and the buried wiring form an electrical connection between the upper semiconductor circuit layer and the lower semiconductor circuit layer, or electrically connect the upper semiconductor circuit layer and the intermediate semiconductor circuit layer, the intermediate semiconductor circuit layer and the lower semiconductor circuit layer to each other However, the present invention is not limited thereto. The bump electrode and the wiring film are used to electrically connect the upper semiconductor circuit layer and the lower semiconductor circuit layer φ to each other as described in the twelfth embodiment. It is a structure in which an upper semiconductor circuit layer and a lower semiconductor circuit layer can be electrically connected to each other, and can be used. Any of the above embodiments is a two-layer laminated structure composed of a higher semiconductor circuit layer and a lower semiconductor circuit layer, which is a peripheral circuit of a pixel array (vertical scanning circuit 34, horizontal scanning). The circuit 35 or the like is formed on the upper semiconductor circuit layer or the lower semiconductor circuit layer, but the present invention is not limited thereto. The peripheral circuit of the pixel array may be formed inside other semiconductor circuit layers, and then the semiconductor circuit layer is connected to the lower layer. Half 107 200803484 The inner surface of the conductor circuit layer. This point is also applicable to a three-layer laminated structure composed of an upper semiconductor circuit layer, a neutral semiconductor circuit layer, and a lower semiconductor circuit layer, or a laminated structure of four or more layers. In the embodiment, each of the pixel blocks having a plurality of pixels is provided with one buried wiring. However, the present invention is not limited thereto. Of course, one buried wiring may be provided for one pixel. For example, if This can be achieved by the right rear side (or one side) of each buried wiring. The upper semiconductor circuit layer And the lower semiconductor circuit layer may also be formed by a single semiconductor wafer, or may be formed by a plurality of semiconductor wafers, in other words, the circuit element formed in the semiconductor circuit layer may be integrally formed on a single semiconductor wafer. The inside of the semiconductor wafer can be divided and formed in a plurality of semiconductor wafers. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram of a pixel type image sensor using a sensor circuit according to an i-th embodiment of the present invention. Fig. 2 is a circuit diagram showing the principal part of the sensor circuit of the first embodiment of the present invention, which shows the circuit configuration of the two pixel blocks to which the jth row belongs. Fig. 3 is the second embodiment of the present invention. FIG. 4 is a view showing the configuration of the main part of the sensor circuit according to the third embodiment of the present invention (the same as FIG. 2). Fig. 5 is a road configuration diagram of the sensor circuit according to the fourth embodiment of the present invention (the same diagram as Fig. 2). 1 is a circuit diagram showing a configuration of an address P-type circuit of a port according to a fifth embodiment of the present invention. Fig. 7 is a circuit diagram showing a circuit configuration of a main part of an address specifying type image sensor according to a sixth embodiment of the present invention. Fig. 8 is a cross-sectional view of an essential part of an actual structure of an address-based image sensor of the fifth embodiment of the present invention. Fig. 9 is a cross-sectional view of the essential part of the internal structure in which the address specifying image is sensed in the sixth embodiment of the present invention. Fig. 1 is a circuit diagram showing a configuration of a main port P circuit of an address specifying type image sensing port according to a seventh embodiment of the present invention. Figure 11 is a cross-sectional view of an essential part of an actual structure in which an address specifying image is sensed in a seventh embodiment of the present invention. Fig. 1 is a cross-sectional view of an essential part of a cross structure in which an address specifying image of the eighth embodiment of the present invention is sensed. Fig. 13 is a circuit diagram showing a circuit configuration of a main part of an address specifying image sensor according to a ninth embodiment of the present invention. Figure 14 is a cross-sectional view of an essential part of a cross-sectional structure in which an address specifying image is detected in a ninth embodiment of the present invention. Fig. 15 is a cross-sectional view of an essential part of an actual configuration of an address specifying type image sensor according to a third embodiment of the present invention. Fig. 16 is a circuit diagram showing the configuration of the main circuit of the address specifying image sensor of the uth embodiment of the present invention. Figure 17 is a cross-sectional view of an essential part of an actual structure of an address specifying image sensor according to an eleventh embodiment of the present invention. Fig. 18 is a cross-sectional view of an essential part of the actual structure of the sensor according to the address specification type image sensor of the twelfth embodiment of the present invention. Fig. 19 is a functional block diagram showing the overall configuration of an address specifying image sensor using a sensor circuit according to a thirteenth embodiment of the present invention. Fig. 20 is a circuit diagram showing the main part of the sensor circuit of the thirteenth embodiment of the present invention, showing the circuit configuration of two pixel blocks to which the jth row belongs. Fig. 21 is a circuit diagram showing the configuration of the main circuit of the address specifying type image sensing according to the fourteenth embodiment of the present invention. Fig. 22 is a circuit diagram showing the configuration of the main circuit of the address specifying type image sensing according to the fifteenth embodiment of the present invention. Figure 23 is a cross-sectional view of an essential part of an actual structure of an address specifying type image sensor according to a fourth embodiment of the present invention. Fig. 24 is a cross-sectional view of an essential part of an actual configuration of an address specifying type image sensor according to a fifth embodiment of the present invention. 25(a) and (b) are cross-sectional views of essential parts of a configuration of a storage capacitor element used in the address specifying image sensor of the present invention. 26 (a) and (b) are cross-sectional views of essential parts of another configuration example of the storage capacitor element used in the address specifying image sensor of the present invention. Fig. 27 is a cross-sectional view of an essential part of another configuration example of the storage grid τ of the address specifying image sensor of the present invention. Figure 28 is a circuit diagram showing the configuration of a main circuit of an address specifying image sensor of a sixteenth embodiment of the present invention. Fig. 29 is a cross-sectional view of the principal part of the actual structure of the address specifying type image sensor of the sixteenth embodiment of the present invention. Figure 30 (a) is a conceptual diagram of a circuit configuration of a conventional CMOS (address-specific) image sensor, and a circuit diagram of the signal charge of the image sensor; . Fig. 31 is a circuit diagram showing a circuit configuration of a main part of a conventional CMOS (address-designated) image sensor. Figure 32 is a cross-sectional view of an essential part of a practical configuration of a conventional CMOS (address-specified type) image sensor. Fig. 33(a) is a conceptual diagram showing a general configuration of a conventional CCD (charge transfer type) image sensor; (b) is a conceptual diagram of a storage period of a signal charge of the image sensor. Figure 34 (4) is a conceptual diagram of an image obtained by photographing a blade of a high-speed suspected blade with a CCD (charge-transfer type) image sensor; (b) a conventional CMOS (address-specific) image sensor A conceptual diagram of the image obtained when photographing the same leaf. [Main component symbol description] 1, 1A, IB, ic: sensor circuit 2, 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H: address specifying type image sensor 3: sensor circuit 4, 4A: address-specific image sensor 11, 11 a : pixel 12, 12a: pixel block 13, 13a: common node 14, 15: node 21, 21A, 21B, 21C, 21D, 21E, 21F Upper semiconductor circuit layer 22Fa: Intermediate semiconductor circuit layer 111 200803484 22, 22, 22A, 22A, 22B, 22B, 22C, 22C, 22D1, 22E, 22E', 22Fb: Lower semiconductor circuit layers 23, 23 '··embedded wirings 23a, 23a': conductive contact plugs 24, 24': insulating film 31: reset line 32: read control line 3 3: horizontal signal line 34: vertical scanning circuit 3 5: horizontal scanning circuit 36: CDS circuit 37: line signal line 3 8: line selection signal 39: output selection line 39a: output control line 39a: output control line 40: p-type 矽 substrate 41: element isolation insulating film 42, 43: n+ type region 44 : gate 45 · conductive contact plug 46 : wiring film 47 : wiring member 48 : n + type region 112 200803484 49 · • gate 50 : Conductive contact plug 52 : n + type region 53 : gate 54 , 55 : conductive contact plug 56 , 57 : wiring film 58 : conductive contact plug 59 : wiring film

60, 60': p-type germanium substrate 61, 61': element isolation insulating film 62, 64, 66, 66a, 66b · n + type region 63, 65, 67, 67a, 67b: gate 67aa: capacitive element 68, 69, 70, 71: conductive contact plugs 72, 72a, 73: wiring films 74, 74' · wiring structures 74a, 74af: conductive contact plugs 75, 75': wiring film 76: n + region 77: gate Pole 78, 80, 82 · Conductive contact plugs 79, 81, 83: wiring film 90, 90f: bump electrodes 91, 91': electrically insulating adhesive 113 200803484 PD^PDn: photodiode TG TGn: transmission gate

TrRST, TrRST1~TrRSTn · Reset transistor T r A Μ P · Amplify the transistor

TrSEL1~TrSELn ·Select transistor R:Resistor

Cst, CsTl~CsTn · Storage capacitive element R. : parasitic resistance

Csn, Cd, cq2: parasitic capacitance

114

Claims (1)

200803484 X. Patent application scope: 1 · A sensor circuit with a plurality of pixels unconfigured in an array, and used for hunting address designation to select the address sense of each pixel of the poor pixel a detector, comprising: a plurality of pixel blocks, wherein a plurality of the pixels are connected in parallel to a common node by a predetermined number; and a reset transistor is connected to a common node of each pixel to reset the a plurality of the pixels in the pixel block; and the amplifying transistor 'connected to each of the plurality of common nodes of the pixel block for amplifying the signal sent by the plurality of pixels in the pixel block; In the pixel block, each of the pixels includes: a photoelectric conversion element that generates a signal charge corresponding to the illumination light; and a first gate element that is disposed between the photoelectric conversion element and a common node of the pixel block. 2. The sensor circuit of claim i, wherein the amplification transistor has a single output. 3. The sensor circuit of claim 1, further comprising: a storage capacitor element connected to an output end of the amplifying transistor; and an output transistor for controlling an output of the signal stored by the capacitor element . 4. The sensor circuit of claim 1, wherein the amplifying transistor has an output of an equal number of pixels in the pixel block corresponding to the amplifying transistor, and respectively at the output terminals Connect the second gate element. 5. The sensor circuit of claim 4, further comprising a plurality of storages 115 200803484 ==: respectively connected to the plurality of output ends of the amplifying transistor, and for controlling the capacitive elements A hard number of output transistors from which the signal is stored. The sensor circuit of any of the first to fifth patent ranges, such as the towel, ^ before all the pixels generate and store the signal charge, use the reset circuit to reset all of the pixels as a whole. In each pixel 2 blocks, the signal corresponding to the signal charge stored in the pixel is taken through the corresponding common "point" sequence (four), and then corresponding to the corresponding Crystal. The electric sensor S has a plurality of pixels arranged in an array, and is used for selecting an address-specific image sensor of each pixel by address designation, and is characterized in that a plurality of pixel blocks, wherein the plurality of pixels are connected in parallel to the common node by a predetermined number; and the amplifying transistor is connected to each of the plurality of common nodes of the pixel block for amplifying the pixel block a plurality of signals sent by the pixel; in each of the pixel blocks, each of the pixels includes: a photoelectric conversion element that generates a signal charge corresponding to the illumination light; and a second gate element disposed in the photoelectric conversion element and the pixel area a path between the common nodes of the block; and a reset transistor connected to a connection point of the photoelectric conversion element and the second gate element to perform resetting of the pixel. 8. The sensor circuit of claim 7, wherein the amplification transistor has a single output. 9_ The sensor circuit of claim 7, further comprising a storage capacitor element connected to the output end of the amplifying transistor, and 116 200803484 for controlling the output of the signal stored by the capacitor element. Transistor. 10. The sensor circuit of claim 7, wherein the amplifying transistor has an output of an equal number of pixels in the pixel block corresponding to the amplifying transistor, and is respectively connected at the output terminals The second gate element. 11. The sensor circuit of claim 10, further comprising a plurality of storage capacitor elements respectively connected to the plurality of output ends of the amplifying transistor, and for controlling signals stored in the capacitor elements The output of a plurality of output transistors. 12. The sensor circuit of any one of claims 7 to 5, wherein all of the pixels are reset using all of the reset transistors before all of the pixels are generated and stored in signal charge. In each of the pixel blocks, a signal corresponding to the signal charge stored in the pixel is read by the corresponding common node in time series, and then transmitted to the corresponding amplifying transistor. 13 - an address-specific image sensor having a three-dimensional layered structure, having a plurality of pixels arranged in an array, and selecting each of the pixels by address designation, characterized in that: a plurality of pixel regions are provided Block, the plurality of pixels are connected in parallel to the common node by a predetermined number; a reset transistor is connected to a common node of each pixel block for resetting a plurality of the pixels in the pixel block; and amplifying the electricity The crystal is connected to a plurality of common nodes of the pixel block for amplifying signals sent by a plurality of the pixels in the pixel block; 117 200803484 In each of the pixel blocks, each pixel includes: photoelectric conversion Components, corresponding to the makeup light to produce the nickname charge; and 帛! a gate element disposed between the photoelectric conversion element and a common node of the pixel block; at least the photoelectric conversion element is formed in the first semiconductor circuit layer constituting the three-dimensional laminated structure, and the first gate is formed The element, the reset transistor, and the amplifying transistor 'are formed in the second or third semiconductor circuit layer constituting the three-dimensional laminated structure. 14. The address-specific image sensor of claim 13, wherein, in addition to the plurality of the photoelectric conversion elements, a plurality of the first gate members are formed in the ith semiconductor circuit layer. A plurality of the amplifying transistors and a plurality of reset transistors are formed in the second or third semiconductor circuit layer. 1 5 · The address-specific image sensing benefit of the thirteenth application of the patent scope is in which, in addition to the plurality of the photoelectric conversion elements, a plurality of the first gate elements and a plurality of reset transistors are formed In the second semiconductor circuit layer, a plurality of the amplifying transistors are formed in the second or third semiconductor circuit layer. 16. The address specifying image sensor of claim 13, wherein the amplifying transistor has an output of an equal number of pixels in the pixel block corresponding to the amplifying transistor, and The output terminals are respectively connected to the second gate element (selecting the transistor); in addition to the plurality of the photoelectric conversion elements, the plurality of the first gate elements, the plurality of the reset transistors, and the plurality of the amplifying electrodes are also A crystal is formed in the first semiconductor circuit layer, and a plurality of the second gate elements (selection 118 200803484 electrification crystal) are formed in the second or third semiconductor circuit layer. [7] The address specifying type image sensor of claim 13, wherein only a plurality of the photoelectric conversion elements are formed in the first semiconductor circuit layer, and the plurality of the first gate elements A plurality of the reset transistors and a plurality of the amplifying transistors are formed in the second or third semiconductor circuit layer. 18. The address-specific image sensor of claim 13 wherein the amplifying transistor has a single output. 19. The address specification type image sensor of the invention, wherein the second or third semiconductor circuit layer further includes a storage device connected to the output end of the amplifying transistor. a capacitive element and an output transistor for controlling an output of the signal stored by the capacitive element. 20. The address specifying image sensor of claim 8, wherein each of the amplifying transistors has an output of an equal number of pixels in the pixel block corresponding to the amplifying transistor, and The second gate elements are connected to the output_ terminals, respectively. 21. The address specifying image sensor of the second aspect of the patent application, wherein the 'in the second or third semiconductor circuit layer is further provided and connected to the plurality of output terminals of the amplifying transistor respectively a plurality of storage capacitor elements and an output transistor for controlling the output of the signals stored in the capacitor elements. 22. The address-specified plastic image sensor of any one of claims 13 to 21, wherein all of the reset transistor pairs are used before all of the pixels are generated and stored with signal 119 200803484. All of the pixels are collectively reset in each of the 5 megapixel blocks, and the lanthanum corresponding to the signal charge stored in the pixel is read by the corresponding common node in time series, and then transmitted to the corresponding amplifying transistor. . An address-specified image sensor having a three-dimensional layered structure, having a plurality of pixels arranged in an array, and selecting each pixel by address designation is characterized by: The plurality of pixel blocks are formed by paralleling a plurality of the pixels in a predetermined number in parallel with the common node; and the amplifying transistor is connected to each of the plurality of common nodes of the pixel block for amplifying by the pixel block a plurality of signals sent by the pixel; each of the pixels in the pixel block includes: a photoelectric conversion element that generates a signal charge corresponding to the illumination light; and a first gate element disposed in the photoelectric conversion 7G device and the pixel region a path between the common nodes of the block; and a reset transistor connected to the connection point of the photoelectric conversion element and the 闸i gate element to perform resetting of the pixel; the three-dimensional laminated structure element, the reset electro-crystal In the three-dimensional laminated structure, at least the photoelectric conversion element is formed in the first semiconductor circuit layer, and the first gate body and the amplifying transistor are formed in the second or third semiconductor circuit layer. in. 24. The address-specific image sensor of the 23rd item of the patent application scope, wherein, in addition to the plurality of light shovel shovel-transfer 70 pieces, a plurality of the first gate elements are also formed. In the first semi-guided basket, the plurality of the magnifying electric Japanese body and the plurality of reset electro-technics are formed in the second or third after 120 200803484. In the semiconductor circuit layer. That is, 25. The address-specific image sensing of the second and third items of the patent application scope: wherein, in addition to the plurality of the photoelectric conversion elements, the first one of the first dragging members and the plurality of resetting transistors are also The first semiconductor circuit is formed to have a thickness Φ, and a plurality of the amplifying transistors are formed in the second or third semiconductor circuit layer. 26. If the address-specified image sensing of claim 23 of the patent application scope, the magnifying transistor has an output of an equal number of the total number of pixels in the pixel block corresponding to the amplifying transistor, and Connecting a second gate element (selecting a transistor) to the output terminals; and in addition to the plurality of the photoelectric conversion elements, a plurality of the first gate elements, a plurality of the reset transistors, and the plurality of The amplifying transistor is formed in the first semiconductor circuit layer, and a plurality of the second gate elements (selective transistors) are formed in the second or third semiconductor circuit layer. 27. The address-specified image sensor of claim 23, wherein only a plurality of the photoelectric conversion elements are formed in the first half of the circuit layer, and the plurality of the first gate elements A plurality of the reset transistors and a plurality of the amplifying transistors are formed in the second or third semiconductor circuit layer. 28. The address-specific image sensor of claim 23, wherein each of the amplifying transistors has a single output. 29. The address-specific image sensing of claim 28 is 'where' is further provided in the second or third semiconductor circuit layer: a storage capacitor connected to an output end of the amplifying transistor Component, 121 200803484, and an output transistor for controlling the output of the signal stored in the capacitive element. 30. The address-specific image sensor of claim 23, wherein each of the amplifying transistors has The amplifying transistor corresponds to an equal number of outputs of the total number of pixels in the pixel block, and the second gate elements are respectively connected to the output terminals. 31. The address-specific image sensing method of claim 30, wherein the second or third semiconductor circuit layer further comprises: respectively connected to a plurality of output terminals of the amplifying transistor The plurality of storage t-capacitors < cattle, and an output transistor for controlling the output of the signals stored in the capacitive elements. Address specification (4) of any of the patent scopes 23 to 31: a sensor that uses all of the reset transistors for all of the pixels to generate and store signals. The pixel is entirely reset in each of the money blocks, and the call corresponding to the signal charge stored in the pixel is read by the corresponding common node in time series, and then transmitted to the corresponding amplifying transistor. Η * —, round: as the next page 122