JP2002033965A - Drive circuit for solid-state image pickup element, and solid-state image sensing element having drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a drive circuit for slid-state image pickup elements that can adjust an input signal value by associating the value with characteristics for each solid-state image pickup element. SOLUTION: An input terminal, where a voltage Va is inputted, an output terminal for outputting an output voltage Vb to the solid-state image pickup element, a source/drain or a pair of nonvolatile memory elements, and a plurality of nonvolatile memory devices which include each terminal of accumulation gates are included, and an output voltage adjustment circuit for adjusting the output voltage Vb are included. The output voltage adjustment circuit adjusts the output voltage Vb, by making the storage state of the nonvolatile memory devices change, according to the characteristics of the solid-state image pickup device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for a solid-state image pickup device and a solid-state image pickup device provided with the same, and more particularly, to outputting an output signal suitable for operating characteristics of the solid-state image pickup device by adjusting the value of an input signal. About the technology that can be

[0002]

2. Description of the Related Art FIG. 11 is a functional block diagram showing an overall configuration of a CCD sensor including a solid-state image sensor.

As shown in FIG. 11, a CCD sensor including a solid-state image sensor includes a solid-state image sensor 51 and a solid-state image sensor 5.
1, a drive signal generation circuit 52 for generating one drive signal, an output signal processing circuit 53 for processing an output signal of the solid-state imaging device 51, a storage circuit 54 for storing the output signal, and a display for displaying the output signal as an image. 55.

FIG. 12 shows a general interline type CCD.
1 shows a plan view of a solid-state imaging device.

[0005] The solid-state imaging device 51 is formed on a semiconductor substrate 61 such as silicon. Pixel 63, vertical charge transfer path 65, horizontal charge transfer path 67, output amplifier 71
Are formed on the semiconductor substrate 61, and one CC as a whole is formed.
The D solid-state imaging device is configured.

The plurality of pixels 63 are arranged on the semiconductor substrate 61 in the vertical and horizontal directions.

[0007] The pixel 63 includes a photodiode (photoelectric conversion element) 63a and a transfer gate 63b.
The photodiode 63a converts the received light into electric charges and stores the charges. The transfer gate 63b reads out the charges stored in the photodiode 63a to the vertical charge transfer path 65.

[0008] One vertical charge transfer path 65 is arranged between each pixel column in which a plurality of pixels 63, 63, 63 are arranged in a vertical direction, corresponding to one pixel column. . The vertical charge transfer path 65 includes, for example, an n
Mold conductive layer. At the lower end of the vertical charge transfer path 65, a horizontal charge transfer path 67 is provided. Horizontal charge transfer path 67
An output amplifier 71 for amplifying and outputting the charge signal transferred from the horizontal charge transfer path 67 is provided at one end.

The output signal from the output amplifier 71 is shown in FIG.
Are processed by the output signal processing circuit 53 shown in FIG. The output of the output signal processing circuit 53 is output to a storage device (circuit) 54 such as a storage card and / or a display device (device) 55 such as a liquid crystal display device. The storage device 54 is configured to be able to write and read information by using a storage card such as a smart media or a compact flash card. The display device 55 can also display a moving image and monitor an image to be shot.

[0010]

By the way, actually,
The characteristics of the solid-state imaging device vary among individual devices.

In order to cope with the variation in the characteristics of the solid-state imaging device, the output signal from the drive signal generator 52 is changed to cope with the variation in the characteristics of the solid-state imaging device and to obtain a stable output. Need to be

Up to now, the driving signal generator 52 has
An adjustment circuit for generating a signal corresponding to the variation in the characteristics of the solid-state imaging device is incorporated, and the adjustment is performed in accordance with the characteristics of each solid-state imaging device.

However, in this method, adjustment is performed as a camera incorporating a solid-state imaging device, and a camera assembly operator performs the operation while viewing an image, which is complicated.

An object of the present invention is to provide a tester which evaluates the characteristics of a solid-state image sensor by associating input signal values with characteristics of each solid-state image sensor by incorporating a conventional adjustment circuit in the same chip as a solid-state image sensor. An object of the present invention is to provide a solid-state imaging device that can be adjusted to a minimum.

[0015]

According to one aspect of the present invention, an input terminal to which a voltage Va is input, an output terminal to output an output voltage Vb to a solid-state imaging device, and a pair of nonvolatile memory elements A driving circuit for a solid-state imaging device, comprising: a plurality of non-volatile memory elements each having a source / drain and a storage gate; and an output voltage adjusting circuit capable of adjusting the output voltage Vb.

The output voltage adjustment circuit includes a first wiring connecting the input terminal and the output terminal, a first resistor provided in the middle of the first wiring, A second wiring branched from the first wiring and grounded at the other end between the first wiring and the output terminal; a second resistor provided in the middle of the second wiring; A plurality of non-volatile memories including n-1 nodes dividing the second resistor into n (n is a positive integer of 2 or more), and a pair of source / drain and storage gate terminals for non-volatile memory elements Each of the plurality of nonvolatile memory elements has one of the source / drain terminals for the nonvolatile memory element connected to one of the plurality of nodes and the other connected in common. Is preferred.

The output voltage adjusting circuit includes a first wire connecting the input terminal and the output terminal, a first resistor provided in the middle of the first wire, and a first resistor. A second wiring branched from the first wiring and grounded on the other end side between the first wiring and the output terminal; a second resistor provided in the middle of the second wiring; Or n-1 nodes that divide the second resistor into n (n is a positive integer of 2 or more), and a non-volatile memory element source /
A plurality of non-volatile memory elements including terminals of a drain and a storage gate, wherein one of two adjacent nodes among the plurality of nodes has the source / drain terminal for the non-volatile memory element, and the other has the source / drain terminal. It is preferable that the drain / source terminal for the nonvolatile memory element is connected.

According to still another aspect of the present invention, a substrate of a first conductivity type, a well layer of a second conductivity type formed on the surface of the substrate, and a surface layer of the substrate formed in the well layer Are arranged in the vertical and horizontal directions at
A first first-conductivity-type semiconductor layer forming a photoelectric conversion element together with the second-conductivity-type well layer; and a first semiconductor layer disposed close to the photoelectric conversion element and extending vertically to form a vertical charge transfer path. A first conductive type semiconductor layer, an input terminal to which a voltage Va is input, an output terminal to output an output voltage Vb, a first wiring connecting the input terminal and the output terminal, A first resistor provided in the middle of the first wire, a second wire branched from the first wire and grounded at the other end between the first resistor and the output terminal; The second resistor provided in the middle of the wiring of the above and the first resistor or the second resistor is n (n is 2
The above-mentioned positive integer) includes n-1 nodes to be divided, and a plurality of nonvolatile memory elements each including a source / drain and a storage gate terminal for a nonvolatile memory element. Each of the solid-state imaging device driving devices, wherein the non-volatile memory element source / drain terminals are connected to any of the plurality of nodes, and the non-volatile memory element drain / source terminals are commonly connected. A solid-state imaging device including a circuit, wherein the output terminal and the ground are connected to the substrate and the well layer.

According to another aspect of the present invention, a substrate of a first conductivity type, a well layer of a second conductivity type formed on a surface of the substrate, and a well layer formed in the well layer, A first first-conductivity-type semiconductor layer that is arranged in the vertical and horizontal directions and forms a photoelectric conversion element together with the second-conductivity-type well layer; A first first conductivity type semiconductor layer extending in the vertical direction to form a vertical charge transfer path, an input terminal to which a voltage Va is input, an output terminal to output an output voltage Vb, and the input terminal and the output terminal. A first wiring to be connected; a first resistor provided in the middle of the first wiring;
A second wiring branched from the first wiring and grounded on the other end side between the first wiring and the output terminal; a second resistor provided in the middle of the second wiring; 1
Or n-1 nodes that divide the second resistor into n (n is a positive integer of 2 or more), and a plurality of non-volatile elements including terminals of a source / drain and a storage gate for a non-volatile memory element. A non-volatile memory element source / drain terminal is connected to one of two adjacent nodes among the plurality of nodes, and the other is connected to the non-volatile memory element drain / source terminal. And a driving circuit for the solid-state imaging device, wherein the output terminal and the ground are connected to the substrate and the well layer.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In this specification, terminals of a transistor including a nonvolatile transistor are referred to as a source / drain terminal, a (storage) gate terminal, and a drain / source terminal.

In this case, the source / drain terminal and the drain / source terminal refer to terminals provided on opposite sides of the storage gate. This means that operation is possible even if both terminals are exchanged. For example, n
In the channel transistor, a terminal from which electrons exit is referred to as a source / drain terminal, and a terminal from which electrons collect is referred to as a drain / source terminal. The channel transistor operates even when the voltage applied between both terminals is changed.

The term "resistor" in the present specification is not limited to ordinary resistors. For example, a two-terminal element (generally called a diode) in which a gate and a source of a transistor (FET) are short-circuited is also included in the “resistance” in this specification. That is, as long as a predetermined voltage drop occurs when a predetermined voltage is applied between the elements, such an element is also included in the category of “resistance”.

Hereinafter, a solid-state imaging device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1A shows a CCD including a solid-state image sensor.
It is a functional block diagram of a sensor.

As shown in FIG. 1A, the CCD sensor includes a solid-state image sensor A, a drive signal generating circuit W for generating a drive signal for driving the solid-state image sensor A, and an output of the solid-state image sensor A. An output signal processing circuit X for processing a signal;
It includes a storage circuit Y for storing an output signal and a display Z for displaying the output signal as an image.

The solid-state image pickup device A includes a first solid-state image pickup circuit A1 for performing a normal image pickup process and a second solid-state image pickup circuit A2 for internally processing a part of input signals applied to the first solid-state image pickup circuit. And The detailed configuration of the first solid-state imaging circuit A1 and the second solid-state imaging circuit A2 will be described later.

The drive signal generation circuit W generates a drive signal S1 for driving the solid-state imaging device A, and the drive signal S1
1 is output to the solid-state imaging device A.

The driving signal S1 is classified into a first driving signal S11 and a second driving signal S12. The first drive signal S11 is a drive signal directly input from the drive signal generation circuit W to the first solid-state imaging circuit A1. For example, a drive signal for a vertical charge transfer path for transferring charges in a vertical charge transfer path, and a drive signal for a horizontal charge transfer path for transferring charges in a horizontal charge transfer path.

The second drive signal S12 is not directly input to the first solid-state imaging circuit A1, but is supplied to the second solid-state imaging circuit A2.
Is input to Then, signal processing is performed in the solid-state imaging circuit A2. After signal processing is performed by the second solid-state imaging circuit A2, the signal is input to the first solid-state imaging circuit A1 as a third drive signal S13. The third drive signal S13 is, for example, a substrate bias signal applied to the solid-state imaging device.

The output signal S from the first solid-state imaging circuit A1
2 is processed by the output signal processing circuit X. The output signal S3 of the output signal processing circuit X is output to a storage circuit Y including a storage card or the like. Similarly, an output signal S4 of the output signal processing circuit X is output to a display Z such as a liquid crystal display device.

The storage circuit is connected to an interface for a storage card such as a smart media or a compact flash card, and is configured to exchange storage information with the storage card. The display unit Z is, for example, a liquid crystal display device, and can display a moving image and monitor an image to be captured.

Next, the structure of the solid-state imaging device A will be described.

FIG. 1B is a plan view showing the entire structure of the CCD solid-state imaging device A, and FIG. 2 is a diagram showing the structure of a pixel constituting the solid-state imaging device shown in FIG. is there.
2 (a) is a plan view, and FIG. 2 (b) is IIb in FIG. 2 (a).
FIG. 2C is a cross-sectional view taken along the line IIb ′ of FIG.
It is c-IIc 'sectional drawing.

As shown in FIG. 1A, the CCD solid-state imaging device A includes a first solid-state imaging circuit A1 and a second solid-state imaging circuit A2.

The first solid-state imaging circuit A1 includes a plurality of pixels 3 arranged in rows and columns on a semiconductor substrate 1 forming a two-dimensional plane, and a plurality of pixels 3 arranged in the vicinity of the pixels 3. A pixel array section B including a vertical charge transfer path 5 extending in the vertical direction, and a row scan arranged adjacent to the pixel array section B and generating a drive signal for driving charges in the vertical charge transfer path 5. A circuit C; a horizontal charge transfer path 7 disposed adjacent to the lower end of the pixel array section B for transferring charges transferred from the vertical charge transfer path 5 in the horizontal direction;
Output amplifier 1 that amplifies and outputs the charge transferred by the
1 is included. In addition to the row scanning circuit C1, a horizontal charge transfer path driving circuit C2 for generating a drive pulse for driving the horizontal charge transfer path 7 is provided separately. Each pixel includes a photoelectric conversion element 3a and a readout gate 3b.

FIG. 2A shows a structure for two pixels.

As shown in FIG. 2A, a pixel 3 formed on the semiconductor substrate 1 includes a photoelectric conversion element 3a such as a photodiode, a photoelectric conversion element 3a, and a vertical charge A read gate 3b formed between the vertical charge transfer path 5 and the transfer path 5 for transferring signal charges accumulated in the photoelectric conversion element 3a to the vertical charge transfer path 5;

On the semiconductor substrate 1, a first layer of polysilicon (hereinafter referred to as "1 poly") electrode 21 provided in a region avoiding the photoelectric conversion element 3a and extending in the horizontal direction, and a first layer Photoelectric conversion element 3 as well as polysilicon electrode 21
A second-layer polysilicon (hereinafter, referred to as “two-poly”) electrode 23 is provided in a region other than a and extends in the horizontal direction.

The 1-poly electrode 21 and the 2-poly electrode 23 are formed substantially symmetrically with respect to a straight line dividing the pixel 3 into substantially half in the horizontal direction, and cover the vertical charge transfer path 5 to form a charge transfer stage. Form.

FIG. 2B is a cross-sectional view taken along the line IIb-II in FIG.
It is a cross section along the line b ′.

A p-well layer 31 formed in the n-type silicon semiconductor substrate 1, an interlayer insulating film (flattening film) 33 formed on the p-well layer 31, and incident light formed on the interlayer insulating film 33 And a microlens ML formed on the color filter CF for condensing light in the photoelectric conversion element 3a.

In a surface region in the p-well layer 31, a vertical charge transfer path 5 formed by an n-type semiconductor layer and an n-type semiconductor region 35 forming a photoelectric conversion element (photodiode) together with the p-well layer 31 are formed. Are formed.

As shown in FIG. 2C, a first insulating film 22 is formed on the surface of the semiconductor substrate 1. First
The one-poly electrode 21 is formed on the insulating film 22 of the layer.

The first insulating film 22c includes, for example, an insulating film 22a made of silicon oxide, an insulating film 22b made of silicon nitride formed thereon, and an insulating film 22c made of silicon oxide formed thereon. Is formed by the three-layer structure. This three-layer structure can be used also as a gate oxide film which also serves as a charge storage layer of a nonvolatile transistor described later.

Another insulating film is formed on one poly electrode 21, and a two poly electrode 22 is formed thereon.

An interlayer insulating film 33 is formed on the above structure. In the interlayer insulating film 33, the one-poly electrode 21
And at least the photoelectric conversion element 3 a
A light-shielding film SF having an opening in a region is formed. The light shielding film SF prevents incident light from entering the vertical charge transfer path 5.

The light incident from the front side of the microlens ML is condensed by the microlens ML, color information is given by the color filter CF, and the photoelectric conversion element 3
a.

When a high positive voltage is applied to the one-poly electrode 21 shown in FIG. 2A, the potential of the n-type semiconductor layer forming the vertical charge transfer path 5 with respect to the charge storage region of the photodiode decreases. . The signal charge stored in the photoelectric conversion element 3a is transferred into the vertical charge transfer path 5 through the read gate 3b.

The signal charge transferred into the vertical charge transfer path 5 is transferred in the direction of the horizontal charge transfer path 7 in the vertical charge transfer path 5 by sequentially applying a voltage to the 1-poly electrode and the 2-poly electrode. You.

When light is irradiated on the photoelectric conversion element, electron-hole pairs are generated, and electrons are accumulated in the n-type region formed in the pn junction. If the intensity of the irradiated light is too high, the excess charge exceeds the charge storage capacity of the n-type region and surplus charges enter the surrounding pixels or the vertical charge transfer path. For this reason, a so-called blooming phenomenon occurs in which a bright region expands to a portion not irradiated with light.

Therefore, a substrate bias (reverse bias) Vb is applied between the p-well layer and the n-type semiconductor substrate,
The well layer is almost completely depleted.

When the photoelectric conversion element is irradiated with intense light, generated electrons accumulate in the n region, and the potential for the electrons in the n region increases. The potential well for electrons becomes shallower. As a result, the excess charge is discarded toward the substrate through the n ⁺ -pn path. This structure is called a vertical overflow drain structure. In the vertical overflow drain structure, the amount of accumulated charge that becomes a threshold at which charge is discarded to the substrate side can be adjusted by a substrate bias voltage applied between the substrate and the p-well. Therefore, the set value of the substrate bias voltage Vb becomes important.

FIG. 3 is a circuit diagram of a driving circuit for a solid-state imaging device included in the second solid-state imaging circuit A2 for controlling the substrate bias voltage Vb applied to the first solid-state imaging circuit A1.

As shown in FIG. 3, the driving circuit for the solid-state imaging device includes an input terminal Ta, an output terminal Tb, and an output voltage adjusting circuit for adjusting a voltage between both terminals. The output voltage adjustment circuit CC1 indicated by a region surrounded by a broken line is, for example,
It includes four transistors T1 to T4 and two non-volatile memory elements T5 and T6 having a floating gate.

An input terminal Ta for inputting an input voltage Va and an output terminal T for extracting a bias voltage Vb to the substrate.
b between the first wiring L1 and the first wiring L1.
The first resistor R1 is formed in the middle of the process. The first resistor R1 is formed between the input terminal Ta and the node a '.

The second wiring L2 is branched from the node a '. The second wiring L2 is grounded at a first ground point G1. A second point between the node a 'and the first ground point G1
Is provided.

More specifically, the second resistor R2 is connected to the node a '
It has a node h and a node i in order from the direction. That is, the second resistor R2 is divided into three series resistors by the nodes i and h. The resistance between the first ground point G1 and the node i is Ri, and the resistance between the contact point i and the node h is Rh.
And A resistor R2-Rh is provided between the contact point h and the contact point a '.
-Ri is connected.

A third line L3 is provided between the node i and the second ground point G2. In the middle of the third wiring L3, two transistors T1 and T2 are connected in series. A fourth wiring L4 is provided between the node h and the second ground point G2. In the middle of the fourth wiring L4, 2
Two transistors T3 and T4 are connected in series.

A fifth wiring L5 extends from the gate of the transistor T1, and one end of the fifth wiring L5 is connected to the terminal Tc. A sixth wiring L6 extends from the gate of the transistor T2, and one end thereof is connected to the terminal Td.

The gate of the transistor T3 and the fifth wiring L
5 are connected. The gate of the transistor T4 and the sixth wiring L6 are connected.

A node j is formed between the transistor T1 and the transistor T2 in the third wiring L3.

A seventh line L7 is provided branched from the node j of the third line L3, and is connected at one end to the terminal Tg. The nonvolatile memory element T6 is connected in series in the middle of the seventh wiring L7. The gate of the nonvolatile memory element T6 is connected to the terminal Tf.

A node k is formed between the transistor T3 and the transistor T4 of the fourth wiring L4, and an eighth wiring L8 branches from the node k. One end of the eighth wiring L8 is connected to the seventh wiring L7 at the node o, and is connected to the terminal Tg.

In the middle of the eighth wiring L8, a nonvolatile memory element T5 is connected in series. The gate of the nonvolatile memory element T5 is connected to the terminal Te.

FIG. 4 shows an example of a sectional structure of the nonvolatile memory elements T5 and T6.

As shown in FIG. 4, a p-type well layer 31 is formed in an n-type silicon semiconductor substrate 1. This structure is similar to the structure of the pixel portion of the solid-state imaging device shown in FIG.

On the surface of p well layer 31, a first oxide film 40 is deposited, for example, to a thickness of about 50 nm. On the first oxide film 40, a first nitride film 41 is deposited with a thickness of, for example, about 100 nm. On the first nitride film 41, a second oxide film 43 is deposited with a thickness of, for example, about 100 nm. On the second oxide film 43, a gate electrode 45 made of, for example, Al and having a thickness of about 100 nm is formed.

As described above, the first oxide film 40 is the oxide film 22a shown in FIG. 2C, the first nitride film 41 is the nitride film 22b shown in FIG. Oxide film 43
Is formed as the oxide film 22c shown in FIG. 2C, the pixel portion of the solid-state imaging device and the nonvolatile memory device can be formed by the same process. The manufacturing process for monolithically forming the CCD solid-state imaging device and the nonvolatile memory device can be simplified. Since it has the same structure as the CCD sensor, the above-mentioned nonvolatile memory element can be formed in the CCD solid-state imaging device. In order to secure the reliability of the nonvolatile memory element, particularly to lengthen the data retention time, it is desirable to provide a light-shielding film on the nonvolatile memory element.

The above-described first oxide film 40 and first nitride film 4
The stacked structure of the first and second oxide films 43 and the gate electrode 45 is processed into an island shape to form a storage gate SG for storing storage information.

In the p-well layer 31 on both sides of the storage gate SG, the source region 51 and the drain region 5 of the n-type semiconductor region are provided.
3 are formed.

Next, the operation of the nonvolatile memory element T5 (T6) will be described.

The nonvolatile memory elements T5 and T6 have the same structure, and have the same electrical characteristics such as threshold voltage. In a state where no charge is stored in the storage gate SG, the p-well layers 31 of the nonvolatile memory elements T5 and T6
Electrons are accumulated between the first oxide film 40 and the first oxide film 40 to form a channel layer.

The source / drain region 53 (source / drain electrode) of the nonvolatile memory element T5 is grounded, and a high voltage, for example, a voltage of 15 V is applied to the drain / source region 51 (source electrode) and the gate electrode 45. Then, avalanche breakdown occurs near the drain / source region 51. The electrons obtain high kinetic energy and become hot electrons, so-called hot electrons.

When a gate voltage is applied so as to have the same potential as that of the drain / source, the hot electrons are attracted in the direction of the gate which is almost at the same potential as the drain / source region 51. Some of the hot electrons are trapped and accumulated at the interface between the first oxide film 40 and the first nitride film 41 to form a charge accumulation region. If a polycrystalline silicon layer is used instead of the first nitride film 41, electrons can be trapped in the polycrystalline silicon layer.

When electrons are trapped in the charge storage region,
Due to the negative charge of the electrons, the p-well layer 31 and the first oxide film 4 of the nonvolatile memory element T5 (T6)
The channel layer formed at the interface with 0 is depleted. When the channel layer is depleted, the nonvolatile memory element T
5 (T6) is turned off.

The charges (electrons) stored in the charge storage region are semi-permanently stored in the storage gate, and the non-volatile memory element is kept off.

Next, the operation of the driving circuit for the solid-state imaging device will be described.

FIG. 5 shows an example of a signal waveform of the driving circuit for the solid-state image sensor. FIG. 6 shows a simple equivalent circuit when the circuit shown in FIG. 3 is operated.

In the initial state, no charge is stored in the storage gates SG of the nonvolatile memory elements T5 and T6. The nonvolatile memory elements T5 and T6 are in an on state in an initial state.

A high voltage signal, for example, 5
When a voltage of V is applied, the transistors T1 and T3 are turned on. The circuit shown in FIG. 3 in this state is represented by an equivalent circuit shown in FIG. When a short circuit occurs between the nodes h and i and a ground potential is applied to the terminal Tg, the potential of the node h also becomes the ground potential.

Accordingly, the voltage Vb at the terminal Tb becomes a voltage represented by the following equation (1).

Vb = (R2-Rh) Va / (R2-Rh + Ri) (1) Here, Rh is a resistance value from the contact point h to the ground point G1.

Next, a procedure for changing the potential of the terminal Tb will be described. First, as shown in FIG. 5, the following voltages are applied as initial setting values.

When a voltage of 0 V is applied to the terminal Tc, the transistors T1 and T3 are turned off (time t ₀ ).

At time t ₁ , when Vd (about 5 V) is applied to the terminal Td, the transistors T2 and T4 are turned on.

At time t ₂ , voltage Vg is applied to terminal Tg.
(About 15 V). At time t ₃ in this state, a voltage Ve (about 15 V) is applied to the terminal Te.
A voltage of 0 V is applied to the terminal Tf.

In this state, the nonvolatile memory element T
The gate voltage of No. 6 is 0V. Therefore, even if a high electric field exists between the source / drain and the drain / source and electrons become hot electrons, the hot electrons do not travel in the gate direction.

Therefore, electrons are not accumulated in the charge accumulation region (interface between the oxide film and the nitride film) of the nonvolatile memory element T6, and the nonvolatile memory element T6 is kept on.

In the nonvolatile memory element T5, a high voltage (about 15 V) is applied between the gate and the drain / source. Since the source / drain is almost 0V,
Electrons are accelerated by a large electric field generated from the source / drain to the drain / source, and become hot electrons.

Since a voltage of 15 V is also applied to the gate, some of the hot electrons are trapped in the charge storage region of the gate. If the accumulated amount of electrons becomes a certain value or more, the non-volatile memory element T5 is turned off if the channel layer is depleted.

As described above, by performing the step shown in FIG. 5A, T of the nonvolatile memory elements T5 and T6
Only 5 changes to the off state.

At time t ₄ , the voltage applied to the terminal Te is changed from 15 V to 0 V, and at time t ₅ , the terminal T
Even if the voltage applied to g is changed from Vg to 0 V, the on-off state of the nonvolatile memory elements T5 and T6 does not change.

When the voltage applied to the terminal Td is set to 0 V at time t ₆ and the voltage applied to the terminal Tc is set to 5 V at time t ₇ , the circuit shown in FIG. 3 can be represented by an equivalent circuit shown in FIG. State. When a ground potential is applied to the terminal Tg,
The potential of the contact i is also grounded. The short circuit between the contacts i and h is eliminated.

The potential Vb of the terminal Tb changes to a voltage represented by the following equation (2).

Vb = (R2-Ri) Va / ((R2-Ri) + R1) (2) Here, Ri is a resistance value from the contact point i to the ground point G1.

As described above, in the circuit shown in FIG.
By changing the storage state of the nonvolatile memories T5 and T6, the substrate bias voltage V connected to the terminal Tb is changed.
b can be varied.

The nonvolatile memories T5 and T6 have terminals Te,
Unless a high voltage is applied to Tf, the stored state is maintained semi-permanently. The off state of the transistor T5 can be maintained, and the substrate bias voltage Vb based on the equation (2) can be obtained.
Can be continuously applied to the substrate.

FIG. 7 illustrates a first modification of the solid-state imaging device according to the first embodiment, with reference to the drawings. FIG. 7A is a circuit diagram, and FIG. 7B is a cross-sectional view of a transistor.

FIG. 7A shows a modification of the solid-state image sensor driving circuit for controlling the substrate bias signal applied to the solid-state image sensor shown in FIG.

As shown in FIG. 7A, the output voltage adjustment circuit CC2 included in the drive circuit for the solid-state imaging device according to the modification and surrounded by a broken line includes the nonvolatile memory elements T5 and T6.
Is connected to a transistor T7 (drain terminal).

The source terminal of the transistor T7 is grounded (G
ND). A signal is input from the gate terminal K of the transistor T7.

The transistor T7 is connected to the source terminals of the nonvolatile memory elements T5 and T6, and is provided for protecting the gates of the nonvolatile memory elements T5 and T6.

FIG. 7B is a sectional view of the transistor T7. The transistor T7 shown in FIG. 7B has substantially the same structure as the transistors T1 to T4 shown in FIG. 4, but has a so-called offset drain structure in which an offset portion OF is provided between the drain 53 and the gate 45. Transistor.

By connecting the high voltage transistor T7 having an offset drain structure, the output voltage adjusting circuit can be protected, for example, when a high voltage is applied due to the influence of static electricity or the like.

FIGS. 8A and 8B are a cross-sectional view showing a structure of a nonvolatile memory element used in a solid-state imaging device according to a second modification of the present invention, and a leakage current characteristic of the nonvolatile memory element. .

The non-volatile memory element shown in FIG.
This is a so-called accumulated charge localized type nonvolatile memory element in which charges are locally accumulated on the source region side or the drain region side of the gate region. The structure, characteristics, and the like of this accumulated charge localization type nonvolatile memory element are disclosed in, for example, U.S. Pat. No. 5,768,192 in the column of Examples.

The storage charge localized type nonvolatile memory element shown in FIG. 8A has substantially the same structure as the nonvolatile memory element shown in FIG. The operation of the nonvolatile memory element will be described.

First, a write operation for forming the charge storage layer CSR in which electrons are stored near the source / drain will be described.

The source / drain 53 (terminal J) is grounded, and a positive high voltage, for example, 15 V is applied between the drain / source 51 (terminal G) and the gate 45 (terminal E).

Electrons travel from the source / drain 53 toward the drain / source 51 due to the electric field formed in the channel layer. The electrons receive a large amount of energy before reaching the channel layer near the drain / source 51,
What is called hot electrons. Hot electrons have high energy, and some of them travel in the gate direction beyond the potential barrier formed by the first insulating film 40. On the way, it is accumulated at the interface between the first insulating film (SiO ₂ ) 40 and the second insulating film (Si ₃ N ₄ ) 41 near the drain / source region 51.

When an appropriate amount of electrons are stored in the charge storage region CSR near the source, the charge causes the channel layer below the charge storage region CSR to be depleted.

In this state, a case where a stored information is read by applying a voltage between the source and the drain will be considered.

First, consider the case where the source / drain 53 is grounded and a voltage of, for example, 2 V is applied to the drain / source 51. Although the channel layer extends from the source / drain 53 to the vicinity of the charge storage region CSR on the drain / source 51 side, since the source / drain 53 is originally grounded, the channel layer extends near the charge storage region CSR on the drain / source 51 side. The channel layer keeps a potential of almost 0V. Since the voltage applied to the drain / source 5 is 2 V, a potential difference of 2 V occurs between the charge storage region CSR and the drain / source 51 in the vicinity thereof.

On the other hand, consider the case where the drain / source 51 is grounded and a voltage of, for example, 2 V is applied to the source / drain 53. The channel layer extends from the source / drain 53 to the vicinity of the charge storage region CSR on the drain / source 51 side. Charge storage region CSR on the drain / source 51 side
The channel layer in the vicinity is affected by a voltage drop of about 1 V, for example. Accordingly, the potential of the channel layer in the vicinity of the charge storage region CSR on the drain / source 51 side is about 1 V. Since the drain / source 51 is grounded,
Only a voltage of about 1 V is applied to the channel layer formed below the charge storage region CSR.

As described above, when the source / drain 53 is grounded and a voltage of, for example, 2 V is applied to the drain / source 53 to read stored information, the voltage across the charge storage region CSR is 2 V, and the read operation is performed. The transfer of the charge from the charge storage region CSR to the channel (so-called leak current) during the operation is increased.

On the other hand, when the stored information is read by applying a voltage of, for example, 2 V to the source / drain 53 while the drain / source 51 is grounded, the voltage across the charge storage region CSR is about 1 V. As shown in FIG. 8B, the movement of charges (so-called leak current I _L ) from the charge storage region CSR to the channel layer during the read operation is reduced.

Therefore, when the drain / source 51 is grounded and a read operation is performed by applying a voltage of, for example, 2 V to the source / drain 53, the retention time of the stored information in the nonvolatile memory element is shortened (due to the leak current). ) Can be greatly reduced.

FIG. 9 shows a solid-state image sensor driving circuit for a solid-state image sensor according to a second embodiment of the present invention.

Also in the solid-state imaging device driving circuit shown in FIG. 9, an output voltage adjusting circuit CC3 for controlling a substrate bias signal applied to the solid-state imaging device is provided in a region surrounded by a broken line as in FIG. Is provided.

As shown in FIG. 9, the solid-state imaging device driving circuit includes, for example, an input terminal Ta to which an input voltage Va2 is input.
2 and an output voltage adjustment circuit CC3. A first resistor R11 is formed between the output voltage adjusting circuit CC3 and an output terminal Tb2 for extracting the substrate bias voltage Vb2. The first resistor R11 has a node h, a node i, a node j, and a node o in order from the input terminal Ta2 side to the output terminal Tb2 side.

The second line L12 branches from the node o and is connected to the second ground GND12. The second resistor R2 is formed in the middle of the wiring L12.

Between the node h and the first ground point GND11, two transistors T11 and T17 are connected in series. A node k is formed between the two transistors T11 and T17.

The transistor T12 and the transistor T18 are connected in series between the node i and the terminal Tg2. A node l exists between the transistor T12 and the transistor T18.

A transistor T16 and a transistor T19 are connected in series between the node i and the ground point GND11. The transistors T11 and T17 and the transistors T13 and T19 are connected in parallel. A node m exists between the transistors T13 and T19.

The transistor T14 and the transistor T20 are connected in series between the node j and the terminal Tg2. A node n exists between the transistor T14 and the transistor T20.

The source / drain and the drain / source of the nonvolatile memory element T15 are connected between the nodes k and l, respectively. Non-volatile memory element T15
Is connected to the terminal Te2.

The source / drain and the drain / source of the nonvolatile memory element T16 are connected between the nodes m and n, respectively. Non-volatile memory element T16
Is connected to the terminal Tf2.

The gates of the four transistors T11 to T14 are commonly connected and connected to the terminal Tc2.

The gates of the four transistors T17 to T20 are commonly connected and connected to the terminal Td2.

Two nonvolatile memory elements T15 and T16
An element having a structure similar to that of the nonvolatile memory element described in the first embodiment can be used.

The first resistor R11 is formed so as to be able to be divided into three series resistors at the contact points h and i. That is, the first divided resistance Rij, between the node i and the node j,
Between the node h and the node i, a second dividing resistor Rhi, a terminal T
a3 and a third dividing resistor R1- (Rhi +
Rij).

In the output voltage adjusting circuit CC3, between the nodes h and i, and between the nodes i and j,
One each, a total of two nonvolatile memory elements T15, T1
6 to adjust the input signal value.

FIG. 10 shows operation waveforms of the driving circuit for the solid-state imaging device shown in FIG.

The non-volatile memory elements T15 and T16 are initially on.

A high voltage, for example, 5 V is applied to the terminal Tc2.
Are applied, the transistors T11 to T14
Turns on. The first resistor R11 is short-circuited between the node h and the node j, so that R11− (Rhi + Ri
j).

Therefore, the voltage Vb applied to the terminal Tb2
2 is represented by the following equation (3).

Vb = (R12) Va / (R12 + R11− (Rhi + Rij)) (3) where Rhi is a resistance value from the node h to the node i, and Rij is a resistance value from the node i to the node j. It is.

When the signal shown in FIG. 10 is applied as the initial set value, the solid-state drive circuit operates as follows.

1) The terminal Tc2 is set to 0 V to turn off the transistors T11 to T14.

2) At time t11, the terminal Td2 is set to V
d2 (about 15 V), and transistors T17 to T2
Turn on to 0.

3) At time t12, V is applied to terminal Tg2.
A voltage of g2 (about 15 V) is applied.

4) At time t13, a voltage of about 15 V is applied to terminal Te2. Note that a voltage of 0 V is applied to the terminal Tf2.

As a result of applying the above voltage, the solid-state imaging device driving circuit (output voltage adjusting circuit) shown in FIG.
Charge is stored only in the gate of the nonvolatile memory element T15. The non-volatile memory element T15 is turned off. In this state, the voltage applied to the terminal Te2 becomes 0 at time t14.
V, and does not change even if the voltage applied to the terminal Tf2 becomes 0 V at time t15.

As shown in FIG. 10, at time t16, 0 V is applied to terminal Td2, and at time t17, the voltage at terminal Tc2 is set to 5V. The short circuit between the node h and the node i is released, and the value of the first resistor R1 changes to R1-Rij.

The voltage Vb output from the terminal Tb2 is expressed by the following equation (4).

Vb = (R12) / ((R12) + (R1-Rij)) (4) As described above, the substrate bias Vb can be changed between the initial state and the operating state. Non-volatile memory element T
Since the storage state of T15 and T16 can be maintained semipermanently, the substrate bias voltage Vb expressed by the equation (4) can be continuously applied to the substrate.

Since a high voltage is applied between the drain and the gate of the transistors T18 and T20, the value of the gate width (W) / gate length (L) is determined by the transistors T15 and T20.
It is necessary to have a value sufficiently larger than T16.
When the gate width is increased, the local concentration of the electric field can be prevented, and the possibility of deterioration of the element or the like is reduced even when a high voltage is applied.

Although the embodiments of the present invention have been described above, it will be apparent to those skilled in the art that various changes, improvements, combinations, and the like can be made.

For example, in the output voltage adjusting circuit for a solid-state imaging device according to the second embodiment, the first resistor R11
Is divided into three by the nodes h and i, but the first resistor R11 may be divided into four using the three nodes.

By dividing into n + 1 resistors by n nodes (n = 2, 3, 4,...), It is possible to finely set the resistance value of the first resistor R11.

In addition, the second resistor R12 can be similarly divided into n + 1 resistors by n nodes. In this case, the value of R12 changes in the equations (3) and (4) representing the substrate bias voltage.

In the embodiment, the drive circuit for the solid-state imaging device including the output voltage adjustment circuit for adjusting the substrate bias voltage Vb has been described as an example. Other input terminals, for example, the offset drain voltage value (fine adjustment for eliminating the offset) of the amplification factor (indicated by reference numeral 11 in FIG. 1B) of the solid-state imaging device and the horizontal charge transfer path (FIG. 1 (b)
(Shown by reference numeral 7) can be applied to the adjustment of the drive pulse voltage value (for optimizing the transfer efficiency and the power consumption).

It is preferable that the driving circuit for the solid-state imaging device including the output voltage adjusting circuit is formed on the same substrate as the solid-state imaging device.

The driving circuit for a solid-state image sensor can be applied to a CCD solid-state image sensor. In the above embodiment,
Although an area sensor is taken as an example, it is apparent that the present invention can be used for a CCD line sensor. That, CC
In addition to the D sensor, the present invention can be applied to a CMOS type area sensor or line sensor with the same configuration.

Therefore, it goes without saying that circuits for controlling these devices are also included in the scope of the present invention.

[0156]

The maximum value of the input signal value can be adjusted in accordance with the characteristics of each solid-state imaging device.

[Brief description of the drawings]

FIG. 1A is a functional block diagram of a CCD sensor including a driving circuit for a solid-state imaging device according to a first embodiment of the present invention. FIG. 1B is a schematic diagram of the solid-state imaging device. It is a top view which shows a structure.

FIG. 2 is a diagram showing a detailed structure of a pixel unit in the solid-state imaging device according to the first embodiment of the present invention. FIG.
2 (a) is a plan view, and FIG. 2 (b) is II in FIG. 2 (a).
FIG. 2C is a sectional view taken along the line b-IIb ′, and FIG.
FIG. 2A is a sectional view taken along line IIc-IIc ′ of FIG.

FIG. 3 is a circuit diagram including a driving circuit for a solid-state imaging device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a structure of a nonvolatile memory element used in the solid-state imaging device drive circuit according to the first embodiment of the present invention.

FIG. 5 is a timing chart showing the operation of the solid-state imaging device drive circuit according to the first embodiment of the present invention.

FIGS. 6A and 6B are simplified circuit diagrams for explaining the operation of the driving circuit for a solid-state imaging device according to the first embodiment of the present invention.

FIG. 7A is a circuit diagram of a first modification of the solid-state imaging device driving circuit according to the first embodiment of the present invention, and FIG. 7B is a solid-state imaging device driving circuit. FIG. 3 is a cross-sectional view illustrating a structure of a switching transistor used in an output voltage adjustment circuit included in the circuit.

FIG. 8A is a modification example of the structure of a volatile memory element used in an output voltage adjustment circuit of the solid-state imaging device drive circuit according to the first embodiment of the present invention;
FIG. 8B shows a non-volatile memory element of FIG.
FIG. 7 is a diagram illustrating a relationship between a voltage across a trapped charge and a leak current.

FIG. 9 is a circuit diagram of a driving circuit for a solid-state imaging device according to a second embodiment of the present invention.

FIG. 10 is a timing chart illustrating the operation of the solid-state imaging device drive circuit according to the second embodiment of the present invention.

FIG. 11 is a functional block diagram of a conventional CCD sensor.

FIG. 12 is a plan view of a conventional CCD solid-state imaging device.

[Explanation of symbols]

Reference Signs List A solid-state imaging device A1 first solid-state imaging circuit A2 second solid-state imaging circuit B display unit C horizontal row driving unit CC output voltage adjustment circuit CF color filter CSR charge storage area L wiring ML micro lens OF offset area R1, R11 1 resistance R2, R12 2nd resistance SF light shielding film T1 to T4, T7, T8, T11 to T14, T17 to T
Reference Signs List 20 transistor T5, T6, T15, T16 nonvolatile memory element Vb substrate bias voltage W drive signal processing circuit X output signal processing circuit Y storage circuit Z display 1 semiconductor substrate 3 pixel 3a photoelectric conversion element 3b read gate 5 vertical charge transfer path Reference Signs List 7 horizontal charge transfer path 11 output amplifier 21, 23 vertical charge transfer electrode 22 insulating film 31 p-well 33 flattening film 35 n-type semiconductor layer for photoelectric conversion element

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H01L 29/792 F-term (Reference) 4M118 AA10 AB01 BA13 DD09 FA06 FA13 FA50 GC07 GD04 5C024 AX01 BX01 BX04 CY16 CY47 GX03 GX07 GX16 GY05 GZ48 HX17 HX40 HX44 HX57 5F001 AA14 AC30 AD61 5F083 EP18 ER04

Claims (10)

[Claims] An input terminal to which a voltage Va is input, an output terminal to output an output voltage Vb to a solid-state imaging device, and a plurality of terminals including a pair of a source / drain for a nonvolatile memory element and a storage gate Including a nonvolatile memory element of
A drive circuit for a solid-state imaging device, comprising: an output voltage adjustment circuit capable of adjusting the output voltage Vb. 2. The solid-state imaging device according to claim 1, wherein the output voltage adjustment circuit adjusts the output voltage Vb by changing a storage state of the nonvolatile memory device according to characteristics of the solid-state imaging device. Drive circuit. 3. The output voltage adjustment circuit includes: a first wiring connecting the input terminal and the output terminal; a first resistor provided in the middle of the first wiring; The first between a resistor and the output terminal;
A second wire branched from the other wire and grounded at the other end, a second resistor provided in the middle of the second wire, and the first resistor or the second resistor as n (n is Each of the plurality of nonvolatile memory elements, wherein one of the source / drain terminals for the nonvolatile memory element is any one of the plurality of nodes. 3. The driving circuit for a solid-state imaging device according to claim 1, wherein the driving circuit is connected to the other end and the other is connected to the other. 4. The driving circuit for a solid-state imaging device according to claim 3, further comprising a transistor connected in series with the other of the source / drain terminals for the nonvolatile memory device. 5. The output voltage adjustment circuit, comprising: a first wiring connecting the input terminal and the output terminal; a first resistor provided in the middle of the first wiring; The first between a resistor and the output terminal;
A second wiring branched from the other wiring and grounded at the other end, a second resistor provided in the middle of the second wiring, and the first resistance or the second resistance as n (n Is a positive integer of 2 or more). N-1 nodes to be divided; one of two adjacent nodes among the plurality of nodes; the source / drain terminal for a nonvolatile memory element; 3. The driving circuit for a solid-state imaging device according to claim 1, wherein the drain / source terminal for the volatile memory device is connected. And a plurality of switching transistors each including a source, a gate, and a drain, wherein the plurality of switching transistors are provided between each of the non-volatile memory element source / drain and the one of the nodes. The non-volatile memory element is connected in series between the drain / source for the non-volatile memory element and the other node, and the gates of the plurality of switching transistors are commonly connected. Drive circuit for solid-state imaging device. 7. The nonvolatile memory device according to claim 1, wherein electrons are accumulated in one of the storage gate and one of the drain terminal and the source terminal for the nonvolatile memory device in an off state. 7. The driving circuit for a solid-state imaging device according to any one of 1 to 6. 8. A solid-state imaging device in which the solid-state imaging device driving circuit according to claim 1 and the solid-state imaging device are formed on the same substrate. 9. A substrate of a first conductivity type, a well layer of a second conductivity type formed on the surface of the substrate, and formed in the well layer, and are aligned vertically and horizontally on the surface of the substrate. A first conductive semiconductor layer forming a photoelectric conversion element together with the well layer of the second conductivity type; a vertical charge transfer path extending in the vertical direction and disposed in close proximity to the photoelectric conversion element; A first conductive-type semiconductor layer forming an input terminal, an input terminal to which a voltage Va is input, an output terminal to output an output voltage Vb, and a first wiring connecting the input terminal and the output terminal. A first resistor provided in the middle of the first wire, and a second wire branched from the first wire and grounded at the other end between the first resistor and the output terminal. A second resistor provided in the middle of the second wiring , N-1 nodes dividing the first resistor or the second resistor into n (n is a positive integer of 2 or more), and each terminal of a source / drain and a storage gate for a nonvolatile memory element. A plurality of non-volatile memory elements, each of the plurality of non-volatile memory elements having a source / drain terminal for the non-volatile memory element connected to one of the plurality of nodes, and Drain for element /
A solid-state imaging device comprising: a driving circuit for a solid-state imaging device to which a source terminal is commonly connected, wherein the output terminal and the ground are connected to the substrate and the well layer. 10. A substrate of a first conductivity type, a well layer of a second conductivity type formed on the surface of the substrate, and formed in the well layer, and are vertically and horizontally aligned on the surface of the substrate. A first conductive semiconductor layer forming a photoelectric conversion element together with the well layer of the second conductivity type; and a vertical charge transfer path extending in the vertical direction and disposed close to the photoelectric conversion element. A first conductive-type semiconductor layer that forms: an input terminal to which a voltage Va is input; an output terminal to output an output voltage Vb; a first wiring connecting the input terminal and the output terminal; A first resistor provided in the middle of the first wiring; and a first resistor provided between the first resistor and the output terminal.
A second wiring branched from the other wiring and grounded at the other end, a second resistor provided in the middle of the second wiring, and the first resistance or the second resistance as n (n Is a positive integer greater than or equal to 2) divided into n-1 nodes, and a plurality of non-volatile memory elements including respective terminals of a source / drain and a storage gate for the non-volatile memory element. A drive circuit for a solid-state imaging device in which one of the two adjacent nodes is connected to the source / drain terminal for the nonvolatile memory element and the other is connected to the drain / source terminal for the nonvolatile memory element; A solid-state imaging device in which an output terminal and the ground are connected to the substrate and the well layer.